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PCI IRC routing fix.
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1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25
26 //#define DEBUG_PCI
27
28 struct PCIBus {
29 int bus_num;
30 int devfn_min;
31 pci_set_irq_fn set_irq;
32 pci_map_irq_fn map_irq;
33 uint32_t config_reg; /* XXX: suppress */
34 /* low level pic */
35 SetIRQFunc *low_set_irq;
36 void *irq_opaque;
37 PCIDevice *devices[256];
38 PCIDevice *parent_dev;
39 PCIBus *next;
40 /* The bus IRQ state is the logical OR of the connected devices.
41 Keep a count of the number of devices with raised IRQs. */
42 int irq_count[];
43 };
44
45 static void pci_update_mappings(PCIDevice *d);
46
47 target_phys_addr_t pci_mem_base;
48 static int pci_irq_index;
49 static PCIBus *first_bus;
50
51 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
52 void *pic, int devfn_min, int nirq)
53 {
54 PCIBus *bus;
55 bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
56 bus->set_irq = set_irq;
57 bus->map_irq = map_irq;
58 bus->irq_opaque = pic;
59 bus->devfn_min = devfn_min;
60 first_bus = bus;
61 return bus;
62 }
63
64 PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
65 {
66 PCIBus *bus;
67 bus = qemu_mallocz(sizeof(PCIBus));
68 bus->map_irq = map_irq;
69 bus->parent_dev = dev;
70 bus->next = dev->bus->next;
71 dev->bus->next = bus;
72 return bus;
73 }
74
75 int pci_bus_num(PCIBus *s)
76 {
77 return s->bus_num;
78 }
79
80 void pci_device_save(PCIDevice *s, QEMUFile *f)
81 {
82 qemu_put_be32(f, 1); /* PCI device version */
83 qemu_put_buffer(f, s->config, 256);
84 }
85
86 int pci_device_load(PCIDevice *s, QEMUFile *f)
87 {
88 uint32_t version_id;
89 version_id = qemu_get_be32(f);
90 if (version_id != 1)
91 return -EINVAL;
92 qemu_get_buffer(f, s->config, 256);
93 pci_update_mappings(s);
94 return 0;
95 }
96
97 /* -1 for devfn means auto assign */
98 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
99 int instance_size, int devfn,
100 PCIConfigReadFunc *config_read,
101 PCIConfigWriteFunc *config_write)
102 {
103 PCIDevice *pci_dev;
104
105 if (pci_irq_index >= PCI_DEVICES_MAX)
106 return NULL;
107
108 if (devfn < 0) {
109 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
110 if (!bus->devices[devfn])
111 goto found;
112 }
113 return NULL;
114 found: ;
115 }
116 pci_dev = qemu_mallocz(instance_size);
117 if (!pci_dev)
118 return NULL;
119 pci_dev->bus = bus;
120 pci_dev->devfn = devfn;
121 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
122 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
123
124 if (!config_read)
125 config_read = pci_default_read_config;
126 if (!config_write)
127 config_write = pci_default_write_config;
128 pci_dev->config_read = config_read;
129 pci_dev->config_write = config_write;
130 pci_dev->irq_index = pci_irq_index++;
131 bus->devices[devfn] = pci_dev;
132 return pci_dev;
133 }
134
135 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
136 uint32_t size, int type,
137 PCIMapIORegionFunc *map_func)
138 {
139 PCIIORegion *r;
140 uint32_t addr;
141
142 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
143 return;
144 r = &pci_dev->io_regions[region_num];
145 r->addr = -1;
146 r->size = size;
147 r->type = type;
148 r->map_func = map_func;
149 if (region_num == PCI_ROM_SLOT) {
150 addr = 0x30;
151 } else {
152 addr = 0x10 + region_num * 4;
153 }
154 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
155 }
156
157 target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
158 {
159 return addr + pci_mem_base;
160 }
161
162 static void pci_update_mappings(PCIDevice *d)
163 {
164 PCIIORegion *r;
165 int cmd, i;
166 uint32_t last_addr, new_addr, config_ofs;
167
168 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
169 for(i = 0; i < PCI_NUM_REGIONS; i++) {
170 r = &d->io_regions[i];
171 if (i == PCI_ROM_SLOT) {
172 config_ofs = 0x30;
173 } else {
174 config_ofs = 0x10 + i * 4;
175 }
176 if (r->size != 0) {
177 if (r->type & PCI_ADDRESS_SPACE_IO) {
178 if (cmd & PCI_COMMAND_IO) {
179 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
180 config_ofs));
181 new_addr = new_addr & ~(r->size - 1);
182 last_addr = new_addr + r->size - 1;
183 /* NOTE: we have only 64K ioports on PC */
184 if (last_addr <= new_addr || new_addr == 0 ||
185 last_addr >= 0x10000) {
186 new_addr = -1;
187 }
188 } else {
189 new_addr = -1;
190 }
191 } else {
192 if (cmd & PCI_COMMAND_MEMORY) {
193 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
194 config_ofs));
195 /* the ROM slot has a specific enable bit */
196 if (i == PCI_ROM_SLOT && !(new_addr & 1))
197 goto no_mem_map;
198 new_addr = new_addr & ~(r->size - 1);
199 last_addr = new_addr + r->size - 1;
200 /* NOTE: we do not support wrapping */
201 /* XXX: as we cannot support really dynamic
202 mappings, we handle specific values as invalid
203 mappings. */
204 if (last_addr <= new_addr || new_addr == 0 ||
205 last_addr == -1) {
206 new_addr = -1;
207 }
208 } else {
209 no_mem_map:
210 new_addr = -1;
211 }
212 }
213 /* now do the real mapping */
214 if (new_addr != r->addr) {
215 if (r->addr != -1) {
216 if (r->type & PCI_ADDRESS_SPACE_IO) {
217 int class;
218 /* NOTE: specific hack for IDE in PC case:
219 only one byte must be mapped. */
220 class = d->config[0x0a] | (d->config[0x0b] << 8);
221 if (class == 0x0101 && r->size == 4) {
222 isa_unassign_ioport(r->addr + 2, 1);
223 } else {
224 isa_unassign_ioport(r->addr, r->size);
225 }
226 } else {
227 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
228 r->size,
229 IO_MEM_UNASSIGNED);
230 }
231 }
232 r->addr = new_addr;
233 if (r->addr != -1) {
234 r->map_func(d, i, r->addr, r->size, r->type);
235 }
236 }
237 }
238 }
239 }
240
241 uint32_t pci_default_read_config(PCIDevice *d,
242 uint32_t address, int len)
243 {
244 uint32_t val;
245 switch(len) {
246 case 1:
247 val = d->config[address];
248 break;
249 case 2:
250 val = le16_to_cpu(*(uint16_t *)(d->config + address));
251 break;
252 default:
253 case 4:
254 val = le32_to_cpu(*(uint32_t *)(d->config + address));
255 break;
256 }
257 return val;
258 }
259
260 void pci_default_write_config(PCIDevice *d,
261 uint32_t address, uint32_t val, int len)
262 {
263 int can_write, i;
264 uint32_t end, addr;
265
266 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
267 (address >= 0x30 && address < 0x34))) {
268 PCIIORegion *r;
269 int reg;
270
271 if ( address >= 0x30 ) {
272 reg = PCI_ROM_SLOT;
273 }else{
274 reg = (address - 0x10) >> 2;
275 }
276 r = &d->io_regions[reg];
277 if (r->size == 0)
278 goto default_config;
279 /* compute the stored value */
280 if (reg == PCI_ROM_SLOT) {
281 /* keep ROM enable bit */
282 val &= (~(r->size - 1)) | 1;
283 } else {
284 val &= ~(r->size - 1);
285 val |= r->type;
286 }
287 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
288 pci_update_mappings(d);
289 return;
290 }
291 default_config:
292 /* not efficient, but simple */
293 addr = address;
294 for(i = 0; i < len; i++) {
295 /* default read/write accesses */
296 switch(d->config[0x0e]) {
297 case 0x00:
298 case 0x80:
299 switch(addr) {
300 case 0x00:
301 case 0x01:
302 case 0x02:
303 case 0x03:
304 case 0x08:
305 case 0x09:
306 case 0x0a:
307 case 0x0b:
308 case 0x0e:
309 case 0x10 ... 0x27: /* base */
310 case 0x30 ... 0x33: /* rom */
311 case 0x3d:
312 can_write = 0;
313 break;
314 default:
315 can_write = 1;
316 break;
317 }
318 break;
319 default:
320 case 0x01:
321 switch(addr) {
322 case 0x00:
323 case 0x01:
324 case 0x02:
325 case 0x03:
326 case 0x08:
327 case 0x09:
328 case 0x0a:
329 case 0x0b:
330 case 0x0e:
331 case 0x38 ... 0x3b: /* rom */
332 case 0x3d:
333 can_write = 0;
334 break;
335 default:
336 can_write = 1;
337 break;
338 }
339 break;
340 }
341 if (can_write) {
342 d->config[addr] = val;
343 }
344 addr++;
345 val >>= 8;
346 }
347
348 end = address + len;
349 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
350 /* if the command register is modified, we must modify the mappings */
351 pci_update_mappings(d);
352 }
353 }
354
355 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
356 {
357 PCIBus *s = opaque;
358 PCIDevice *pci_dev;
359 int config_addr, bus_num;
360
361 #if defined(DEBUG_PCI) && 0
362 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
363 addr, val, len);
364 #endif
365 bus_num = (addr >> 16) & 0xff;
366 while (s && s->bus_num != bus_num)
367 s = s->next;
368 if (!s)
369 return;
370 pci_dev = s->devices[(addr >> 8) & 0xff];
371 if (!pci_dev)
372 return;
373 config_addr = addr & 0xff;
374 #if defined(DEBUG_PCI)
375 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
376 pci_dev->name, config_addr, val, len);
377 #endif
378 pci_dev->config_write(pci_dev, config_addr, val, len);
379 }
380
381 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
382 {
383 PCIBus *s = opaque;
384 PCIDevice *pci_dev;
385 int config_addr, bus_num;
386 uint32_t val;
387
388 bus_num = (addr >> 16) & 0xff;
389 while (s && s->bus_num != bus_num)
390 s= s->next;
391 if (!s)
392 goto fail;
393 pci_dev = s->devices[(addr >> 8) & 0xff];
394 if (!pci_dev) {
395 fail:
396 switch(len) {
397 case 1:
398 val = 0xff;
399 break;
400 case 2:
401 val = 0xffff;
402 break;
403 default:
404 case 4:
405 val = 0xffffffff;
406 break;
407 }
408 goto the_end;
409 }
410 config_addr = addr & 0xff;
411 val = pci_dev->config_read(pci_dev, config_addr, len);
412 #if defined(DEBUG_PCI)
413 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
414 pci_dev->name, config_addr, val, len);
415 #endif
416 the_end:
417 #if defined(DEBUG_PCI) && 0
418 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
419 addr, val, len);
420 #endif
421 return val;
422 }
423
424 /***********************************************************/
425 /* generic PCI irq support */
426
427 /* 0 <= irq_num <= 3. level must be 0 or 1 */
428 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
429 {
430 PCIBus *bus;
431 int change;
432
433 change = level - pci_dev->irq_state[irq_num];
434 if (!change)
435 return;
436
437 pci_dev->irq_state[irq_num] = level;
438 for (;;) {
439 bus = pci_dev->bus;
440 irq_num = bus->map_irq(pci_dev, irq_num);
441 if (bus->set_irq)
442 break;
443 pci_dev = bus->parent_dev;
444 }
445 bus->irq_count[irq_num] += change;
446 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
447 }
448
449 /***********************************************************/
450 /* monitor info on PCI */
451
452 typedef struct {
453 uint16_t class;
454 const char *desc;
455 } pci_class_desc;
456
457 static pci_class_desc pci_class_descriptions[] =
458 {
459 { 0x0100, "SCSI controller"},
460 { 0x0101, "IDE controller"},
461 { 0x0200, "Ethernet controller"},
462 { 0x0300, "VGA controller"},
463 { 0x0600, "Host bridge"},
464 { 0x0601, "ISA bridge"},
465 { 0x0604, "PCI bridge"},
466 { 0x0c03, "USB controller"},
467 { 0, NULL}
468 };
469
470 static void pci_info_device(PCIDevice *d)
471 {
472 int i, class;
473 PCIIORegion *r;
474 pci_class_desc *desc;
475
476 term_printf(" Bus %2d, device %3d, function %d:\n",
477 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
478 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
479 term_printf(" ");
480 desc = pci_class_descriptions;
481 while (desc->desc && class != desc->class)
482 desc++;
483 if (desc->desc) {
484 term_printf("%s", desc->desc);
485 } else {
486 term_printf("Class %04x", class);
487 }
488 term_printf(": PCI device %04x:%04x\n",
489 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
490 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
491
492 if (d->config[PCI_INTERRUPT_PIN] != 0) {
493 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
494 }
495 if (class == 0x0604) {
496 term_printf(" BUS %d.\n", d->config[0x19]);
497 }
498 for(i = 0;i < PCI_NUM_REGIONS; i++) {
499 r = &d->io_regions[i];
500 if (r->size != 0) {
501 term_printf(" BAR%d: ", i);
502 if (r->type & PCI_ADDRESS_SPACE_IO) {
503 term_printf("I/O at 0x%04x [0x%04x].\n",
504 r->addr, r->addr + r->size - 1);
505 } else {
506 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
507 r->addr, r->addr + r->size - 1);
508 }
509 }
510 }
511 if (class == 0x0604 && d->config[0x19] != 0) {
512 pci_for_each_device(d->config[0x19], pci_info_device);
513 }
514 }
515
516 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
517 {
518 PCIBus *bus = first_bus;
519 PCIDevice *d;
520 int devfn;
521
522 while (bus && bus->bus_num != bus_num)
523 bus = bus->next;
524 if (bus) {
525 for(devfn = 0; devfn < 256; devfn++) {
526 d = bus->devices[devfn];
527 if (d)
528 fn(d);
529 }
530 }
531 }
532
533 void pci_info(void)
534 {
535 pci_for_each_device(0, pci_info_device);
536 }
537
538 /* Initialize a PCI NIC. */
539 void pci_nic_init(PCIBus *bus, NICInfo *nd)
540 {
541 if (strcmp(nd->model, "ne2k_pci") == 0) {
542 pci_ne2000_init(bus, nd);
543 } else if (strcmp(nd->model, "rtl8139") == 0) {
544 pci_rtl8139_init(bus, nd);
545 } else if (strcmp(nd->model, "pcnet") == 0) {
546 pci_pcnet_init(bus, nd);
547 } else {
548 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
549 exit (1);
550 }
551 }
552
553 typedef struct {
554 PCIDevice dev;
555 PCIBus *bus;
556 } PCIBridge;
557
558 void pci_bridge_write_config(PCIDevice *d,
559 uint32_t address, uint32_t val, int len)
560 {
561 PCIBridge *s = (PCIBridge *)d;
562
563 if (address == 0x19 || (address == 0x18 && len > 1)) {
564 if (address == 0x19)
565 s->bus->bus_num = val & 0xff;
566 else
567 s->bus->bus_num = (val >> 8) & 0xff;
568 #if defined(DEBUG_PCI)
569 printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
570 #endif
571 }
572 pci_default_write_config(d, address, val, len);
573 }
574
575 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
576 pci_map_irq_fn map_irq, const char *name)
577 {
578 PCIBridge *s;
579 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
580 devfn, NULL, pci_bridge_write_config);
581 s->dev.config[0x00] = id >> 16;
582 s->dev.config[0x01] = id > 24;
583 s->dev.config[0x02] = id; // device_id
584 s->dev.config[0x03] = id >> 8;
585 s->dev.config[0x04] = 0x06; // command = bus master, pci mem
586 s->dev.config[0x05] = 0x00;
587 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
588 s->dev.config[0x07] = 0x00; // status = fast devsel
589 s->dev.config[0x08] = 0x00; // revision
590 s->dev.config[0x09] = 0x00; // programming i/f
591 s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
592 s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
593 s->dev.config[0x0D] = 0x10; // latency_timer
594 s->dev.config[0x0E] = 0x81; // header_type
595 s->dev.config[0x1E] = 0xa0; // secondary status
596
597 s->bus = pci_register_secondary_bus(&s->dev, map_irq);
598 return s->bus;
599 }