hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_PCI
  27
  28 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  29 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  30 #define PCI_COMMAND             0x04    /* 16 bits */
  31 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  32 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
  33 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
  34 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
  35 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
  36 #define PCI_MIN_GNT             0x3e    /* 8 bits */
  37 #define PCI_MAX_LAT             0x3f    /* 8 bits */
  38
  39 /* just used for simpler irq handling. */
  40 #define PCI_DEVICES_MAX 64
  41 #define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)
  42
  43 typedef struct PCIBridge {
  44     uint32_t config_reg;
  45     PCIDevice **pci_bus[256];
  46 } PCIBridge;
  47
  48 static PCIBridge pci_bridge;
  49 target_phys_addr_t pci_mem_base;
  50 static int pci_irq_index;
  51 static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
  52
  53 /* -1 for devfn means auto assign */
  54 PCIDevice *pci_register_device(const char *name, int instance_size,
  55                                int bus_num, int devfn,
  56                                PCIConfigReadFunc *config_read,
  57                                PCIConfigWriteFunc *config_write)
  58 {
  59     PCIBridge *s = &pci_bridge;
  60     PCIDevice *pci_dev, **bus;
  61
  62     if (pci_irq_index >= PCI_DEVICES_MAX)
  63         return NULL;
  64
  65     if (!s->pci_bus[bus_num]) {
  66         s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *));
  67         if (!s->pci_bus[bus_num])
  68             return NULL;
  69     }
  70     bus = s->pci_bus[bus_num];
  71     if (devfn < 0) {
  72         for(devfn = 0 ; devfn < 256; devfn += 8) {
  73             if (!bus[devfn])
  74                 goto found;
  75         }
  76         return NULL;
  77     found: ;
  78     }
  79     pci_dev = qemu_mallocz(instance_size);
  80     if (!pci_dev)
  81         return NULL;
  82     pci_dev->bus_num = bus_num;
  83     pci_dev->devfn = devfn;
  84     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
  85
  86     if (!config_read)
  87         config_read = pci_default_read_config;
  88     if (!config_write)
  89         config_write = pci_default_write_config;
  90     pci_dev->config_read = config_read;
  91     pci_dev->config_write = config_write;
  92     pci_dev->irq_index = pci_irq_index++;
  93     bus[devfn] = pci_dev;
  94     return pci_dev;
  95 }
  96
  97 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
  98                             uint32_t size, int type,
  99                             PCIMapIORegionFunc *map_func)
 100 {
 101     PCIIORegion *r;
 102
 103     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 104         return;
 105     r = &pci_dev->io_regions[region_num];
 106     r->addr = -1;
 107     r->size = size;
 108     r->type = type;
 109     r->map_func = map_func;
 110 }
 111
 112 static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
 113 {
 114     PCIBridge *s = opaque;
 115     s->config_reg = val;
 116 }
 117
 118 static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
 119 {
 120     PCIBridge *s = opaque;
 121     return s->config_reg;
 122 }
 123
 124 static void pci_update_mappings(PCIDevice *d)
 125 {
 126     PCIIORegion *r;
 127     int cmd, i;
 128     uint32_t last_addr, new_addr, config_ofs;
 129
 130     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 131     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 132         r = &d->io_regions[i];
 133         if (i == PCI_ROM_SLOT) {
 134             config_ofs = 0x30;
 135         } else {
 136             config_ofs = 0x10 + i * 4;
 137         }
 138         if (r->size != 0) {
 139             if (r->type & PCI_ADDRESS_SPACE_IO) {
 140                 if (cmd & PCI_COMMAND_IO) {
 141                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 142                                                          config_ofs));
 143                     new_addr = new_addr & ~(r->size - 1);
 144                     last_addr = new_addr + r->size - 1;
 145                     /* NOTE: we have only 64K ioports on PC */
 146                     if (last_addr <= new_addr || new_addr == 0 ||
 147                         last_addr >= 0x10000) {
 148                         new_addr = -1;
 149                     }
 150                 } else {
 151                     new_addr = -1;
 152                 }
 153             } else {
 154                 if (cmd & PCI_COMMAND_MEMORY) {
 155                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 156                                                          config_ofs));
 157                     /* the ROM slot has a specific enable bit */
 158                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 159                         goto no_mem_map;
 160                     new_addr = new_addr & ~(r->size - 1);
 161                     last_addr = new_addr + r->size - 1;
 162                     /* NOTE: we do not support wrapping */
 163                     /* XXX: as we cannot support really dynamic
 164                        mappings, we handle specific values as invalid
 165                        mappings. */
 166                     if (last_addr <= new_addr || new_addr == 0 ||
 167                         last_addr == -1) {
 168                         new_addr = -1;
 169                     }
 170                 } else {
 171                 no_mem_map:
 172                     new_addr = -1;
 173                 }
 174             }
 175             /* now do the real mapping */
 176             if (new_addr != r->addr) {
 177                 if (r->addr != -1) {
 178                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 179                         int class;
 180                         /* NOTE: specific hack for IDE in PC case:
 181                            only one byte must be mapped. */
 182                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 183                         if (class == 0x0101 && r->size == 4) {
 184                             isa_unassign_ioport(r->addr + 2, 1);
 185                         } else {
 186                             isa_unassign_ioport(r->addr, r->size);
 187                         }
 188                     } else {
 189                         cpu_register_physical_memory(r->addr + pci_mem_base,
 190                                                      r->size,
 191                                                      IO_MEM_UNASSIGNED);
 192                     }
 193                 }
 194                 r->addr = new_addr;
 195                 if (r->addr != -1) {
 196                     r->map_func(d, i, r->addr, r->size, r->type);
 197                 }
 198             }
 199         }
 200     }
 201 }
 202
 203 uint32_t pci_default_read_config(PCIDevice *d,
 204                                  uint32_t address, int len)
 205 {
 206     uint32_t val;
 207     switch(len) {
 208     case 1:
 209         val = d->config[address];
 210         break;
 211     case 2:
 212         val = le16_to_cpu(*(uint16_t *)(d->config + address));
 213         break;
 214     default:
 215     case 4:
 216         val = le32_to_cpu(*(uint32_t *)(d->config + address));
 217         break;
 218     }
 219     return val;
 220 }
 221
 222 void pci_default_write_config(PCIDevice *d,
 223                               uint32_t address, uint32_t val, int len)
 224 {
 225     int can_write, i;
 226     uint32_t end, addr;
 227
 228     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 229                      (address >= 0x30 && address < 0x34))) {
 230         PCIIORegion *r;
 231         int reg;
 232
 233         if ( address >= 0x30 ) {
 234             reg = PCI_ROM_SLOT;
 235         }else{
 236             reg = (address - 0x10) >> 2;
 237         }
 238         r = &d->io_regions[reg];
 239         if (r->size == 0)
 240             goto default_config;
 241         /* compute the stored value */
 242         if (reg == PCI_ROM_SLOT) {
 243             /* keep ROM enable bit */
 244             val &= (~(r->size - 1)) | 1;
 245         } else {
 246             val &= ~(r->size - 1);
 247             val |= r->type;
 248         }
 249         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 250         pci_update_mappings(d);
 251         return;
 252     }
 253  default_config:
 254     /* not efficient, but simple */
 255     addr = address;
 256     for(i = 0; i < len; i++) {
 257         /* default read/write accesses */
 258         switch(addr) {
 259         case 0x00:
 260         case 0x01:
 261         case 0x02:
 262         case 0x03:
 263         case 0x08:
 264         case 0x09:
 265         case 0x0a:
 266         case 0x0b:
 267         case 0x0e:
 268         case 0x3d:
 269             can_write = 0;
 270             break;
 271         default:
 272             can_write = 1;
 273             break;
 274         }
 275         if (can_write) {
 276             d->config[addr] = val;
 277         }
 278         addr++;
 279         val >>= 8;
 280     }
 281
 282     end = address + len;
 283     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 284         /* if the command register is modified, we must modify the mappings */
 285         pci_update_mappings(d);
 286     }
 287 }
 288
 289 static void pci_data_write(void *opaque, uint32_t addr,
 290                            uint32_t val, int len)
 291 {
 292     PCIBridge *s = opaque;
 293     PCIDevice **bus, *pci_dev;
 294     int config_addr;
 295
 296 #if defined(DEBUG_PCI) && 0
 297     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 298            s->config_reg, val, len);
 299 #endif
 300     if (!(s->config_reg & (1 << 31))) {
 301         return;
 302     }
 303     if ((s->config_reg & 0x3) != 0) {
 304         return;
 305     }
 306     bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
 307     if (!bus)
 308         return;
 309     pci_dev = bus[(s->config_reg >> 8) & 0xff];
 310     if (!pci_dev)
 311         return;
 312     config_addr = (s->config_reg & 0xfc) | (addr & 3);
 313 #if defined(DEBUG_PCI)
 314     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 315            pci_dev->name, config_addr, val, len);
 316 #endif
 317     pci_dev->config_write(pci_dev, config_addr, val, len);
 318 }
 319
 320 static uint32_t pci_data_read(void *opaque, uint32_t addr,
 321                               int len)
 322 {
 323     PCIBridge *s = opaque;
 324     PCIDevice **bus, *pci_dev;
 325     int config_addr;
 326     uint32_t val;
 327
 328     if (!(s->config_reg & (1 << 31)))
 329         goto fail;
 330     if ((s->config_reg & 0x3) != 0)
 331         goto fail;
 332     bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
 333     if (!bus)
 334         goto fail;
 335     pci_dev = bus[(s->config_reg >> 8) & 0xff];
 336     if (!pci_dev) {
 337     fail:
 338         switch(len) {
 339         case 1:
 340             val = 0xff;
 341             break;
 342         case 2:
 343             val = 0xffff;
 344             break;
 345         default:
 346         case 4:
 347             val = 0xffffffff;
 348             break;
 349         }
 350         goto the_end;
 351     }
 352     config_addr = (s->config_reg & 0xfc) | (addr & 3);
 353     val = pci_dev->config_read(pci_dev, config_addr, len);
 354 #if defined(DEBUG_PCI)
 355     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 356            pci_dev->name, config_addr, val, len);
 357 #endif
 358  the_end:
 359 #if defined(DEBUG_PCI) && 0
 360     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 361            s->config_reg, val, len);
 362 #endif
 363     return val;
 364 }
 365
 366 static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
 367 {
 368     pci_data_write(opaque, addr, val, 1);
 369 }
 370
 371 static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
 372 {
 373     pci_data_write(opaque, addr, val, 2);
 374 }
 375
 376 static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
 377 {
 378     pci_data_write(opaque, addr, val, 4);
 379 }
 380
 381 static uint32_t pci_data_readb(void* opaque, uint32_t addr)
 382 {
 383     return pci_data_read(opaque, addr, 1);
 384 }
 385
 386 static uint32_t pci_data_readw(void* opaque, uint32_t addr)
 387 {
 388     return pci_data_read(opaque, addr, 2);
 389 }
 390
 391 static uint32_t pci_data_readl(void* opaque, uint32_t addr)
 392 {
 393     return pci_data_read(opaque, addr, 4);
 394 }
 395
 396 /* i440FX PCI bridge */
 397
 398 void i440fx_init(void)
 399 {
 400     PCIBridge *s = &pci_bridge;
 401     PCIDevice *d;
 402
 403     register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
 404     register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
 405
 406     register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
 407     register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
 408     register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
 409     register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
 410     register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
 411     register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
 412
 413     d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0,
 414                             NULL, NULL);
 415
 416     d->config[0x00] = 0x86; // vendor_id
 417     d->config[0x01] = 0x80;
 418     d->config[0x02] = 0x37; // device_id
 419     d->config[0x03] = 0x12;
 420     d->config[0x08] = 0x02; // revision
 421     d->config[0x0a] = 0x04; // class_sub = pci2pci
 422     d->config[0x0b] = 0x06; // class_base = PCI_bridge
 423     d->config[0x0c] = 0x01; // line_size in 32 bit words
 424     d->config[0x0e] = 0x01; // header_type
 425 }
 426
 427 /* PIIX3 PCI to ISA bridge */
 428
 429 typedef struct PIIX3State {
 430     PCIDevice dev;
 431 } PIIX3State;
 432
 433 PIIX3State *piix3_state;
 434
 435 static void piix3_reset(PIIX3State *d)
 436 {
 437     uint8_t *pci_conf = d->dev.config;
 438
 439     pci_conf[0x04] = 0x07; // master, memory and I/O
 440     pci_conf[0x05] = 0x00;
 441     pci_conf[0x06] = 0x00;
 442     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 443     pci_conf[0x4c] = 0x4d;
 444     pci_conf[0x4e] = 0x03;
 445     pci_conf[0x4f] = 0x00;
 446     pci_conf[0x60] = 0x80;
 447     pci_conf[0x69] = 0x02;
 448     pci_conf[0x70] = 0x80;
 449     pci_conf[0x76] = 0x0c;
 450     pci_conf[0x77] = 0x0c;
 451     pci_conf[0x78] = 0x02;
 452     pci_conf[0x79] = 0x00;
 453     pci_conf[0x80] = 0x00;
 454     pci_conf[0x82] = 0x00;
 455     pci_conf[0xa0] = 0x08;
 456     pci_conf[0xa0] = 0x08;
 457     pci_conf[0xa2] = 0x00;
 458     pci_conf[0xa3] = 0x00;
 459     pci_conf[0xa4] = 0x00;
 460     pci_conf[0xa5] = 0x00;
 461     pci_conf[0xa6] = 0x00;
 462     pci_conf[0xa7] = 0x00;
 463     pci_conf[0xa8] = 0x0f;
 464     pci_conf[0xaa] = 0x00;
 465     pci_conf[0xab] = 0x00;
 466     pci_conf[0xac] = 0x00;
 467     pci_conf[0xae] = 0x00;
 468 }
 469
 470 void piix3_init(void)
 471 {
 472     PIIX3State *d;
 473     uint8_t *pci_conf;
 474
 475     d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State),
 476                                           0, -1,
 477                                           NULL, NULL);
 478     piix3_state = d;
 479     pci_conf = d->dev.config;
 480
 481     pci_conf[0x00] = 0x86; // Intel
 482     pci_conf[0x01] = 0x80;
 483     pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 484     pci_conf[0x03] = 0x70;
 485     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
 486     pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
 487     pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
 488
 489     piix3_reset(d);
 490 }
 491
 492 /* PREP pci init */
 493
 494 static inline void set_config(PCIBridge *s, target_phys_addr_t addr)
 495 {
 496     int devfn, i;
 497
 498     for(i = 0; i < 11; i++) {
 499         if ((addr & (1 << (11 + i))) != 0)
 500             break;
 501     }
 502     devfn = ((addr >> 8) & 7) | (i << 3);
 503     s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
 504 }
 505
 506 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
 507 {
 508     PCIBridge *s = opaque;
 509     set_config(s, addr);
 510     pci_data_write(s, addr, val, 1);
 511 }
 512
 513 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
 514 {
 515     PCIBridge *s = opaque;
 516     set_config(s, addr);
 517 #ifdef TARGET_WORDS_BIGENDIAN
 518     val = bswap16(val);
 519 #endif
 520     pci_data_write(s, addr, val, 2);
 521 }
 522
 523 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
 524 {
 525     PCIBridge *s = opaque;
 526     set_config(s, addr);
 527 #ifdef TARGET_WORDS_BIGENDIAN
 528     val = bswap32(val);
 529 #endif
 530     pci_data_write(s, addr, val, 4);
 531 }
 532
 533 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
 534 {
 535     PCIBridge *s = opaque;
 536     uint32_t val;
 537     set_config(s, addr);
 538     val = pci_data_read(s, addr, 1);
 539     return val;
 540 }
 541
 542 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
 543 {
 544     PCIBridge *s = opaque;
 545     uint32_t val;
 546     set_config(s, addr);
 547     val = pci_data_read(s, addr, 2);
 548 #ifdef TARGET_WORDS_BIGENDIAN
 549     val = bswap16(val);
 550 #endif
 551     return val;
 552 }
 553
 554 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
 555 {
 556     PCIBridge *s = opaque;
 557     uint32_t val;
 558     set_config(s, addr);
 559     val = pci_data_read(s, addr, 4);
 560 #ifdef TARGET_WORDS_BIGENDIAN
 561     val = bswap32(val);
 562 #endif
 563     return val;
 564 }
 565
 566 static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
 567     &PPC_PCIIO_writeb,
 568     &PPC_PCIIO_writew,
 569     &PPC_PCIIO_writel,
 570 };
 571
 572 static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
 573     &PPC_PCIIO_readb,
 574     &PPC_PCIIO_readw,
 575     &PPC_PCIIO_readl,
 576 };
 577
 578 void pci_prep_init(void)
 579 {
 580     PCIBridge *s = &pci_bridge;
 581     PCIDevice *d;
 582     int PPC_io_memory;
 583
 584     PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
 585                                            PPC_PCIIO_write, s);
 586     cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
 587
 588     d = pci_register_device("PREP PCI Bridge", sizeof(PCIDevice), 0, 0,
 589                             NULL, NULL);
 590
 591     /* XXX: put correct IDs */
 592     d->config[0x00] = 0x11; // vendor_id
 593     d->config[0x01] = 0x10;
 594     d->config[0x02] = 0x26; // device_id
 595     d->config[0x03] = 0x00;
 596     d->config[0x08] = 0x02; // revision
 597     d->config[0x0a] = 0x04; // class_sub = pci2pci
 598     d->config[0x0b] = 0x06; // class_base = PCI_bridge
 599     d->config[0x0e] = 0x01; // header_type
 600 }
 601
 602
 603 /* pmac pci init */
 604
 605 static void pci_pmac_config_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
 606 {
 607     PCIBridge *s = opaque;
 608 #ifdef TARGET_WORDS_BIGENDIAN
 609     val = bswap32(val);
 610 #endif
 611     s->config_reg = val;
 612 }
 613
 614 static uint32_t pci_pmac_config_readl (void *opaque, target_phys_addr_t addr)
 615 {
 616     PCIBridge *s = opaque;
 617     uint32_t val;
 618
 619     val = s->config_reg;
 620 #ifdef TARGET_WORDS_BIGENDIAN
 621     val = bswap32(val);
 622 #endif
 623     return val;
 624 }
 625
 626 static CPUWriteMemoryFunc *pci_pmac_config_write[] = {
 627     &pci_pmac_config_writel,
 628     &pci_pmac_config_writel,
 629     &pci_pmac_config_writel,
 630 };
 631
 632 static CPUReadMemoryFunc *pci_pmac_config_read[] = {
 633     &pci_pmac_config_readl,
 634     &pci_pmac_config_readl,
 635     &pci_pmac_config_readl,
 636 };
 637
 638 static void pci_pmac_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
 639 {
 640     PCIBridge *s = opaque;
 641     pci_data_write(s, addr, val, 1);
 642 }
 643
 644 static void pci_pmac_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
 645 {
 646     PCIBridge *s = opaque;
 647 #ifdef TARGET_WORDS_BIGENDIAN
 648     val = bswap16(val);
 649 #endif
 650     pci_data_write(s, addr, val, 2);
 651 }
 652
 653 static void pci_pmac_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
 654 {
 655     PCIBridge *s = opaque;
 656 #ifdef TARGET_WORDS_BIGENDIAN
 657     val = bswap32(val);
 658 #endif
 659     pci_data_write(s, addr, val, 4);
 660 }
 661
 662 static uint32_t pci_pmac_readb (void *opaque, target_phys_addr_t addr)
 663 {
 664     PCIBridge *s = opaque;
 665     uint32_t val;
 666     val = pci_data_read(s, addr, 1);
 667     return val;
 668 }
 669
 670 static uint32_t pci_pmac_readw (void *opaque, target_phys_addr_t addr)
 671 {
 672     PCIBridge *s = opaque;
 673     uint32_t val;
 674     val = pci_data_read(s, addr, 2);
 675 #ifdef TARGET_WORDS_BIGENDIAN
 676     val = bswap16(val);
 677 #endif
 678     return val;
 679 }
 680
 681 static uint32_t pci_pmac_readl (void *opaque, target_phys_addr_t addr)
 682 {
 683     PCIBridge *s = opaque;
 684     uint32_t val;
 685
 686     val = pci_data_read(s, addr, 4);
 687 #ifdef TARGET_WORDS_BIGENDIAN
 688     val = bswap32(val);
 689 #endif
 690     return val;
 691 }
 692
 693 static CPUWriteMemoryFunc *pci_pmac_write[] = {
 694     &pci_pmac_writeb,
 695     &pci_pmac_writew,
 696     &pci_pmac_writel,
 697 };
 698
 699 static CPUReadMemoryFunc *pci_pmac_read[] = {
 700     &pci_pmac_readb,
 701     &pci_pmac_readw,
 702     &pci_pmac_readl,
 703 };
 704
 705 void pci_pmac_init(void)
 706 {
 707     PCIBridge *s = &pci_bridge;
 708     PCIDevice *d;
 709     int pci_mem_config, pci_mem_data;
 710
 711     pci_mem_config = cpu_register_io_memory(0, pci_pmac_config_read,
 712                                             pci_pmac_config_write, s);
 713     pci_mem_data = cpu_register_io_memory(0, pci_pmac_read, pci_pmac_write, s);
 714
 715     cpu_register_physical_memory(0xfec00000, 0x1000, pci_mem_config);
 716     cpu_register_physical_memory(0xfee00000, 0x1000, pci_mem_data);
 717
 718     d = pci_register_device("MPC106", sizeof(PCIDevice), 0, 0,
 719                             NULL, NULL);
 720
 721     /* same values as PearPC - check this */
 722     d->config[0x00] = 0x11; // vendor_id
 723     d->config[0x01] = 0x10;
 724     d->config[0x02] = 0x26; // device_id
 725     d->config[0x03] = 0x00;
 726     d->config[0x08] = 0x02; // revision
 727     d->config[0x0a] = 0x04; // class_sub = pci2pci
 728     d->config[0x0b] = 0x06; // class_base = PCI_bridge
 729     d->config[0x0e] = 0x01; // header_type
 730
 731     d->config[0x18] = 0x0;  // primary_bus
 732     d->config[0x19] = 0x1;  // secondary_bus
 733     d->config[0x1a] = 0x1;  // subordinate_bus
 734     d->config[0x1c] = 0x10; // io_base
 735     d->config[0x1d] = 0x20; // io_limit
 736
 737     d->config[0x20] = 0x80; // memory_base
 738     d->config[0x21] = 0x80;
 739     d->config[0x22] = 0x90; // memory_limit
 740     d->config[0x23] = 0x80;
 741
 742     d->config[0x24] = 0x00; // prefetchable_memory_base
 743     d->config[0x25] = 0x84;
 744     d->config[0x26] = 0x00; // prefetchable_memory_limit
 745     d->config[0x27] = 0x85;
 746 }
 747
 748 /***********************************************************/
 749 /* generic PCI irq support */
 750
 751 /* return the global irq number corresponding to a given device irq
 752    pin. We could also use the bus number to have a more precise
 753    mapping. */
 754 static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
 755 {
 756     int slot_addend;
 757     slot_addend = (pci_dev->devfn >> 3);
 758     return (irq_num + slot_addend) & 3;
 759 }
 760
 761 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 762 #ifdef TARGET_PPC
 763 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
 764 {
 765 }
 766 #else
 767 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
 768 {
 769     int irq_index, shift, pic_irq, pic_level;
 770     uint32_t *p;
 771
 772     irq_num = pci_slot_get_pirq(pci_dev, irq_num);
 773     irq_index = pci_dev->irq_index;
 774     p = &pci_irq_levels[irq_num][irq_index >> 5];
 775     shift = (irq_index & 0x1f);
 776     *p = (*p & ~(1 << shift)) | (level << shift);
 777
 778     /* now we change the pic irq level according to the piix irq mappings */
 779     pic_irq = piix3_state->dev.config[0x60 + irq_num];
 780     if (pic_irq < 16) {
 781         /* the pic level is the logical OR of all the PCI irqs mapped
 782            to it */
 783         pic_level = 0;
 784 #if (PCI_IRQ_WORDS == 2)
 785         pic_level = ((pci_irq_levels[irq_num][0] |
 786                       pci_irq_levels[irq_num][1]) != 0);
 787 #else
 788         {
 789             int i;
 790             pic_level = 0;
 791             for(i = 0; i < PCI_IRQ_WORDS; i++) {
 792                 if (pci_irq_levels[irq_num][i]) {
 793                     pic_level = 1;
 794                     break;
 795                 }
 796             }
 797         }
 798 #endif
 799         pic_set_irq(pic_irq, pic_level);
 800     }
 801 }
 802 #endif
 803
 804 /***********************************************************/
 805 /* monitor info on PCI */
 806
 807 static void pci_info_device(PCIDevice *d)
 808 {
 809     int i, class;
 810     PCIIORegion *r;
 811
 812     printf("  Bus %2d, device %3d, function %d:\n",
 813            d->bus_num, d->devfn >> 3, d->devfn & 7);
 814     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 815     printf("    ");
 816     switch(class) {
 817     case 0x0101:
 818         printf("IDE controller");
 819         break;
 820     case 0x0200:
 821         printf("Ethernet controller");
 822         break;
 823     case 0x0300:
 824         printf("VGA controller");
 825         break;
 826     default:
 827         printf("Class %04x", class);
 828         break;
 829     }
 830     printf(": PCI device %04x:%04x\n",
 831            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 832            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 833
 834     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 835         printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
 836     }
 837     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 838         r = &d->io_regions[i];
 839         if (r->size != 0) {
 840             printf("      BAR%d: ", i);
 841             if (r->type & PCI_ADDRESS_SPACE_IO) {
 842                 printf("I/O at 0x%04x [0x%04x].\n",
 843                        r->addr, r->addr + r->size - 1);
 844             } else {
 845                 printf("32 bit memory at 0x%08x [0x%08x].\n",
 846                        r->addr, r->addr + r->size - 1);
 847             }
 848         }
 849     }
 850 }
 851
 852 void pci_info(void)
 853 {
 854     PCIBridge *s = &pci_bridge;
 855     PCIDevice **bus;
 856     int bus_num, devfn;
 857
 858     for(bus_num = 0; bus_num < 256; bus_num++) {
 859         bus = s->pci_bus[bus_num];
 860         if (bus) {
 861             for(devfn = 0; devfn < 256; devfn++) {
 862                 if (bus[devfn])
 863                     pci_info_device(bus[devfn]);
 864             }
 865         }
 866     }
 867 }
 868
 869 /***********************************************************/
 870 /* XXX: the following should be moved to the PC BIOS */
 871
 872 static uint32_t isa_inb(uint32_t addr)
 873 {
 874     return cpu_inb(cpu_single_env, addr);
 875 }
 876
 877 static void isa_outb(uint32_t val, uint32_t addr)
 878 {
 879     cpu_outb(cpu_single_env, addr, val);
 880 }
 881
 882 static uint32_t isa_inw(uint32_t addr)
 883 {
 884     return cpu_inw(cpu_single_env, addr);
 885 }
 886
 887 static void isa_outw(uint32_t val, uint32_t addr)
 888 {
 889     cpu_outw(cpu_single_env, addr, val);
 890 }
 891
 892 static uint32_t isa_inl(uint32_t addr)
 893 {
 894     return cpu_inl(cpu_single_env, addr);
 895 }
 896
 897 static void isa_outl(uint32_t val, uint32_t addr)
 898 {
 899     cpu_outl(cpu_single_env, addr, val);
 900 }
 901
 902 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
 903 {
 904     PCIBridge *s = &pci_bridge;
 905     s->config_reg = 0x80000000 | (d->bus_num << 16) |
 906         (d->devfn << 8) | addr;
 907     pci_data_write(s, 0, val, 4);
 908 }
 909
 910 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
 911 {
 912     PCIBridge *s = &pci_bridge;
 913     s->config_reg = 0x80000000 | (d->bus_num << 16) |
 914         (d->devfn << 8) | (addr & ~3);
 915     pci_data_write(s, addr & 3, val, 2);
 916 }
 917
 918 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
 919 {
 920     PCIBridge *s = &pci_bridge;
 921     s->config_reg = 0x80000000 | (d->bus_num << 16) |
 922         (d->devfn << 8) | (addr & ~3);
 923     pci_data_write(s, addr & 3, val, 1);
 924 }
 925
 926 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
 927 {
 928     PCIBridge *s = &pci_bridge;
 929     s->config_reg = 0x80000000 | (d->bus_num << 16) |
 930         (d->devfn << 8) | addr;
 931     return pci_data_read(s, 0, 4);
 932 }
 933
 934 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
 935 {
 936     PCIBridge *s = &pci_bridge;
 937     s->config_reg = 0x80000000 | (d->bus_num << 16) |
 938         (d->devfn << 8) | (addr & ~3);
 939     return pci_data_read(s, addr & 3, 2);
 940 }
 941
 942 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
 943 {
 944     PCIBridge *s = &pci_bridge;
 945     s->config_reg = 0x80000000 | (d->bus_num << 16) |
 946         (d->devfn << 8) | (addr & ~3);
 947     return pci_data_read(s, addr & 3, 1);
 948 }
 949
 950 static uint32_t pci_bios_io_addr;
 951 static uint32_t pci_bios_mem_addr;
 952 /* host irqs corresponding to PCI irqs A-D */
 953 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
 954
 955 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
 956 {
 957     PCIIORegion *r;
 958     uint16_t cmd;
 959     uint32_t ofs;
 960
 961     if ( region_num == PCI_ROM_SLOT ) {
 962         ofs = 0x30;
 963     }else{
 964         ofs = 0x10 + region_num * 4;
 965     }
 966
 967     pci_config_writel(d, ofs, addr);
 968     r = &d->io_regions[region_num];
 969
 970     /* enable memory mappings */
 971     cmd = pci_config_readw(d, PCI_COMMAND);
 972     if ( region_num == PCI_ROM_SLOT )
 973         cmd |= 2;
 974     else if (r->type & PCI_ADDRESS_SPACE_IO)
 975         cmd |= 1;
 976     else
 977         cmd |= 2;
 978     pci_config_writew(d, PCI_COMMAND, cmd);
 979 }
 980
 981 static void pci_bios_init_device(PCIDevice *d)
 982 {
 983     int class;
 984     PCIIORegion *r;
 985     uint32_t *paddr;
 986     int i, pin, pic_irq, vendor_id, device_id;
 987
 988     class = pci_config_readw(d, PCI_CLASS_DEVICE);
 989     switch(class) {
 990     case 0x0101:
 991         vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
 992         device_id = pci_config_readw(d, PCI_DEVICE_ID);
 993         if (vendor_id == 0x8086 && device_id == 0x7010) {
 994             /* PIIX3 IDE */
 995             pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO);
 996             pci_config_writew(d, 0x40, 0x8000); // enable IDE0
 997         } else {
 998             /* IDE: we map it as in ISA mode */
 999             pci_set_io_region_addr(d, 0, 0x1f0);
1000             pci_set_io_region_addr(d, 1, 0x3f4);
1001             pci_set_io_region_addr(d, 2, 0x170);
1002             pci_set_io_region_addr(d, 3, 0x374);
1003         }
1004         break;
1005     case 0x0300:
1006         /* VGA: map frame buffer to default Bochs VBE address */
1007         pci_set_io_region_addr(d, 0, 0xE0000000);
1008         break;
1009     default:
1010         /* default memory mappings */
1011         for(i = 0; i < PCI_NUM_REGIONS; i++) {
1012             r = &d->io_regions[i];
1013             if (r->size) {
1014                 if (r->type & PCI_ADDRESS_SPACE_IO)
1015                     paddr = &pci_bios_io_addr;
1016                 else
1017                     paddr = &pci_bios_mem_addr;
1018                 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
1019                 pci_set_io_region_addr(d, i, *paddr);
1020                 *paddr += r->size;
1021             }
1022         }
1023         break;
1024     }
1025
1026     /* map the interrupt */
1027     pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1028     if (pin != 0) {
1029         pin = pci_slot_get_pirq(d, pin - 1);
1030         pic_irq = pci_irqs[pin];
1031         pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1032     }
1033 }
1034
1035 /*
1036  * This function initializes the PCI devices as a normal PCI BIOS
1037  * would do. It is provided just in case the BIOS has no support for
1038  * PCI.
1039  */
1040 void pci_bios_init(void)
1041 {
1042     PCIBridge *s = &pci_bridge;
1043     PCIDevice **bus;
1044     int bus_num, devfn, i, irq;
1045     uint8_t elcr[2];
1046
1047     pci_bios_io_addr = 0xc000;
1048     pci_bios_mem_addr = 0xf0000000;
1049
1050     /* activate IRQ mappings */
1051     elcr[0] = 0x00;
1052     elcr[1] = 0x00;
1053     for(i = 0; i < 4; i++) {
1054         irq = pci_irqs[i];
1055         /* set to trigger level */
1056         elcr[irq >> 3] |= (1 << (irq & 7));
1057         /* activate irq remapping in PIIX */
1058         pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1059     }
1060     isa_outb(elcr[0], 0x4d0);
1061     isa_outb(elcr[1], 0x4d1);
1062
1063     for(bus_num = 0; bus_num < 256; bus_num++) {
1064         bus = s->pci_bus[bus_num];
1065         if (bus) {
1066             for(devfn = 0; devfn < 256; devfn++) {
1067                 if (bus[devfn])
1068                     pci_bios_init_device(bus[devfn]);
1069             }
1070         }
1071     }
1072 }
1073
1074 /*
1075  * This function initializes the PCI devices as a normal PCI BIOS
1076  * would do. It is provided just in case the BIOS has no support for
1077  * PCI.
1078  */
1079 void pci_ppc_bios_init(void)
1080 {
1081     PCIBridge *s = &pci_bridge;
1082     PCIDevice **bus;
1083     int bus_num, devfn, i, irq;
1084     uint8_t elcr[2];
1085
1086     pci_bios_io_addr = 0xc000;
1087     pci_bios_mem_addr = 0xc0000000;
1088
1089 #if 0
1090     /* activate IRQ mappings */
1091     elcr[0] = 0x00;
1092     elcr[1] = 0x00;
1093     for(i = 0; i < 4; i++) {
1094         irq = pci_irqs[i];
1095         /* set to trigger level */
1096         elcr[irq >> 3] |= (1 << (irq & 7));
1097         /* activate irq remapping in PIIX */
1098         pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1099     }
1100     isa_outb(elcr[0], 0x4d0);
1101     isa_outb(elcr[1], 0x4d1);
1102 #endif
1103
1104     for(bus_num = 0; bus_num < 256; bus_num++) {
1105         bus = s->pci_bus[bus_num];
1106         if (bus) {
1107             for(devfn = 0; devfn < 256; devfn++) {
1108                 if (bus[devfn])
1109                     pci_bios_init_device(bus[devfn]);
1110             }
1111         }
1112     }
1113 }