hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 /* PCI includes legacy ISA access.  */
  10 #include "isa.h"
  11
  12 /* PCI bus */
  13
  14 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  15 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  16 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  17 #define PCI_FUNC_MAX            8
  18
  19 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  20 #include "pci_ids.h"
  21
  22 /* QEMU-specific Vendor and Device ID definitions */
  23
  24 /* IBM (0x1014) */
  25 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  26 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  27
  28 /* Hitachi (0x1054) */
  29 #define PCI_VENDOR_ID_HITACHI            0x1054
  30 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  31
  32 /* Apple (0x106b) */
  33 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  35 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  37 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  38
  39 /* Realtek (0x10ec) */
  40 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  41
  42 /* Xilinx (0x10ee) */
  43 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  44
  45 /* Marvell (0x11ab) */
  46 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  47
  48 /* QEMU/Bochs VGA (0x1234) */
  49 #define PCI_VENDOR_ID_QEMU               0x1234
  50 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  51
  52 /* VMWare (0x15ad) */
  53 #define PCI_VENDOR_ID_VMWARE             0x15ad
  54 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  55 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  56 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  57 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  58 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  59
  60 /* Intel (0x8086) */
  61 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  62 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  63
  64 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  65 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  66 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  67 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  68
  69 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  70 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  71 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  72 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  73
  74 #define FMT_PCIBUS                      PRIx64
  75
  76 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  77                                 uint32_t address, uint32_t data, int len);
  78 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  79                                    uint32_t address, int len);
  80 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  81                                 pcibus_t addr, pcibus_t size, int type);
  82 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  83
  84 typedef struct PCIIORegion {
  85     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  86 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  87     pcibus_t size;
  88     pcibus_t filtered_size;
  89     uint8_t type;
  90     PCIMapIORegionFunc *map_func;
  91 } PCIIORegion;
  92
  93 #define PCI_ROM_SLOT 6
  94 #define PCI_NUM_REGIONS 7
  95
  96 #include "pci_regs.h"
  97
  98 /* PCI HEADER_TYPE */
  99 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 100
 101 /* Size of the standard PCI config header */
 102 #define PCI_CONFIG_HEADER_SIZE 0x40
 103 /* Size of the standard PCI config space */
 104 #define PCI_CONFIG_SPACE_SIZE 0x100
 105 /* Size of the standart PCIe config space: 4KB */
 106 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 107
 108 #define PCI_NUM_PINS 4 /* A-D */
 109
 110 /* Bits in cap_present field. */
 111 enum {
 112     QEMU_PCI_CAP_MSIX = 0x1,
 113     QEMU_PCI_CAP_EXPRESS = 0x2,
 114 };
 115
 116 struct PCIDevice {
 117     DeviceState qdev;
 118     /* PCI config space */
 119     uint8_t *config;
 120
 121     /* Used to enable config checks on load. Note that writeable bits are
 122      * never checked even if set in cmask. */
 123     uint8_t *cmask;
 124
 125     /* Used to implement R/W bytes */
 126     uint8_t *wmask;
 127
 128     /* Used to allocate config space for capabilities. */
 129     uint8_t *used;
 130
 131     /* the following fields are read only */
 132     PCIBus *bus;
 133     uint32_t devfn;
 134     char name[64];
 135     PCIIORegion io_regions[PCI_NUM_REGIONS];
 136
 137     /* do not access the following fields */
 138     PCIConfigReadFunc *config_read;
 139     PCIConfigWriteFunc *config_write;
 140
 141     /* IRQ objects for the INTA-INTD pins.  */
 142     qemu_irq *irq;
 143
 144     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 145     uint8_t irq_state;
 146
 147     /* Capability bits */
 148     uint32_t cap_present;
 149
 150     /* Offset of MSI-X capability in config space */
 151     uint8_t msix_cap;
 152
 153     /* MSI-X entries */
 154     int msix_entries_nr;
 155
 156     /* Space to store MSIX table */
 157     uint8_t *msix_table_page;
 158     /* MMIO index used to map MSIX table and pending bit entries. */
 159     int msix_mmio_index;
 160     /* Reference-count for entries actually in use by driver. */
 161     unsigned *msix_entry_used;
 162     /* Region including the MSI-X table */
 163     uint32_t msix_bar_size;
 164     /* Version id needed for VMState */
 165     int32_t version_id;
 166
 167     /* Location of option rom */
 168     char *romfile;
 169     ram_addr_t rom_offset;
 170     uint32_t rom_bar;
 171 };
 172
 173 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 174                                int instance_size, int devfn,
 175                                PCIConfigReadFunc *config_read,
 176                                PCIConfigWriteFunc *config_write);
 177
 178 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 179                             pcibus_t size, int type,
 180                             PCIMapIORegionFunc *map_func);
 181
 182 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 183 int pci_add_capability_at_offset(PCIDevice *pci_dev, uint8_t cap_id,
 184                                  uint8_t cap_offset, uint8_t cap_size);
 185
 186 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 187
 188 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 189
 190 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 191
 192
 193 uint32_t pci_default_read_config(PCIDevice *d,
 194                                  uint32_t address, int len);
 195 void pci_default_write_config(PCIDevice *d,
 196                               uint32_t address, uint32_t val, int len);
 197 void pci_device_save(PCIDevice *s, QEMUFile *f);
 198 int pci_device_load(PCIDevice *s, QEMUFile *f);
 199
 200 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 201 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 202 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
 203 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 204                          const char *name, int devfn_min);
 205 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 206 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 207                   void *irq_opaque, int nirq);
 208 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 209 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 210                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 211                          void *irq_opaque, int devfn_min, int nirq);
 212
 213 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 214
 215 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 216                         const char *default_devaddr);
 217 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 218                                const char *default_devaddr);
 219 int pci_bus_num(PCIBus *s);
 220 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 221 PCIBus *pci_find_root_bus(int domain);
 222 int pci_find_domain(const PCIBus *bus);
 223 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 224 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 225 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 226
 227 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 228                      unsigned *slotp);
 229
 230 void do_pci_info_print(Monitor *mon, const QObject *data);
 231 void do_pci_info(Monitor *mon, QObject **ret_data);
 232 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 233                         pci_map_irq_fn map_irq, const char *name);
 234 PCIDevice *pci_bridge_get_device(PCIBus *bus);
 235
 236 static inline void
 237 pci_set_byte(uint8_t *config, uint8_t val)
 238 {
 239     *config = val;
 240 }
 241
 242 static inline uint8_t
 243 pci_get_byte(const uint8_t *config)
 244 {
 245     return *config;
 246 }
 247
 248 static inline void
 249 pci_set_word(uint8_t *config, uint16_t val)
 250 {
 251     cpu_to_le16wu((uint16_t *)config, val);
 252 }
 253
 254 static inline uint16_t
 255 pci_get_word(const uint8_t *config)
 256 {
 257     return le16_to_cpupu((const uint16_t *)config);
 258 }
 259
 260 static inline void
 261 pci_set_long(uint8_t *config, uint32_t val)
 262 {
 263     cpu_to_le32wu((uint32_t *)config, val);
 264 }
 265
 266 static inline uint32_t
 267 pci_get_long(const uint8_t *config)
 268 {
 269     return le32_to_cpupu((const uint32_t *)config);
 270 }
 271
 272 static inline void
 273 pci_set_quad(uint8_t *config, uint64_t val)
 274 {
 275     cpu_to_le64w((uint64_t *)config, val);
 276 }
 277
 278 static inline uint64_t
 279 pci_get_quad(const uint8_t *config)
 280 {
 281     return le64_to_cpup((const uint64_t *)config);
 282 }
 283
 284 static inline void
 285 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 286 {
 287     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 288 }
 289
 290 static inline void
 291 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 292 {
 293     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 294 }
 295
 296 static inline void
 297 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 298 {
 299     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 300 }
 301
 302 static inline void
 303 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 304 {
 305     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 306 }
 307
 308 static inline void
 309 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 310 {
 311     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 312 }
 313
 314 static inline void
 315 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 316 {
 317     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 318 }
 319
 320 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 321 typedef struct {
 322     DeviceInfo qdev;
 323     pci_qdev_initfn init;
 324     PCIUnregisterFunc *exit;
 325     PCIConfigReadFunc *config_read;
 326     PCIConfigWriteFunc *config_write;
 327
 328     /*
 329      * pci-to-pci bridge or normal device.
 330      * This doesn't mean pci host switch.
 331      * When card bus bridge is supported, this would be enhanced.
 332      */
 333     int is_bridge;
 334
 335     /* pcie stuff */
 336     int is_express;   /* is this device pci express? */
 337
 338     /* rom bar */
 339     const char *romfile;
 340 } PCIDeviceInfo;
 341
 342 void pci_qdev_register(PCIDeviceInfo *info);
 343 void pci_qdev_register_many(PCIDeviceInfo *info);
 344
 345 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 346 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 347
 348 static inline int pci_is_express(const PCIDevice *d)
 349 {
 350     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 351 }
 352
 353 static inline uint32_t pci_config_size(const PCIDevice *d)
 354 {
 355     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 356 }
 357
 358 /* These are not pci specific. Should move into a separate header.
 359  * Only pci.c uses them, so keep them here for now.
 360  */
 361
 362 /* Get last byte of a range from offset + length.
 363  * Undefined for ranges that wrap around 0. */
 364 static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
 365 {
 366     return offset + len - 1;
 367 }
 368
 369 /* Check whether a given range covers a given byte. */
 370 static inline int range_covers_byte(uint64_t offset, uint64_t len,
 371                                     uint64_t byte)
 372 {
 373     return offset <= byte && byte <= range_get_last(offset, len);
 374 }
 375
 376 /* Check whether 2 given ranges overlap.
 377  * Undefined if ranges that wrap around 0. */
 378 static inline int ranges_overlap(uint64_t first1, uint64_t len1,
 379                                  uint64_t first2, uint64_t len2)
 380 {
 381     uint64_t last1 = range_get_last(first1, len1);
 382     uint64_t last2 = range_get_last(first2, len2);
 383
 384     return !(last2 < first1 || last1 < first2);
 385 }
 386
 387 #endif