4 /* PCI includes legacy ISA access. */
9 extern target_phys_addr_t pci_mem_base
;
11 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
12 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
13 #define PCI_FUNC(devfn) ((devfn) & 0x07)
15 /* Device classes and subclasses */
17 #define PCI_CLASS_STORAGE_SCSI 0x0100
18 #define PCI_CLASS_STORAGE_IDE 0x0101
19 #define PCI_CLASS_STORAGE_OTHER 0x0180
21 #define PCI_CLASS_NETWORK_ETHERNET 0x0200
23 #define PCI_CLASS_DISPLAY_VGA 0x0300
24 #define PCI_CLASS_DISPLAY_OTHER 0x0380
26 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
28 #define PCI_CLASS_MEMORY_RAM 0x0500
30 #define PCI_CLASS_SYSTEM_OTHER 0x0880
32 #define PCI_CLASS_SERIAL_USB 0x0c03
34 #define PCI_CLASS_BRIDGE_HOST 0x0600
35 #define PCI_CLASS_BRIDGE_ISA 0x0601
36 #define PCI_CLASS_BRIDGE_PCI 0x0604
37 #define PCI_CLASS_BRIDGE_OTHER 0x0680
39 #define PCI_CLASS_PROCESSOR_CO 0x0b40
41 #define PCI_CLASS_OTHERS 0xff
43 /* Vendors and devices. */
45 #define PCI_VENDOR_ID_LSI_LOGIC 0x1000
46 #define PCI_DEVICE_ID_LSI_53C895A 0x0012
48 #define PCI_VENDOR_ID_DEC 0x1011
49 #define PCI_DEVICE_ID_DEC_21154 0x0026
51 #define PCI_VENDOR_ID_CIRRUS 0x1013
53 #define PCI_VENDOR_ID_IBM 0x1014
54 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
56 #define PCI_VENDOR_ID_AMD 0x1022
57 #define PCI_DEVICE_ID_AMD_LANCE 0x2000
59 #define PCI_VENDOR_ID_HITACHI 0x1054
61 #define PCI_VENDOR_ID_MOTOROLA 0x1057
62 #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
63 #define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
65 #define PCI_VENDOR_ID_APPLE 0x106b
66 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
67 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
68 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
69 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020
70 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
72 #define PCI_VENDOR_ID_SUN 0x108e
73 #define PCI_DEVICE_ID_SUN_EBUS 0x1000
74 #define PCI_DEVICE_ID_SUN_SIMBA 0x5000
75 #define PCI_DEVICE_ID_SUN_SABRE 0xa000
77 #define PCI_VENDOR_ID_CMD 0x1095
78 #define PCI_DEVICE_ID_CMD_646 0x0646
80 #define PCI_VENDOR_ID_REALTEK 0x10ec
81 #define PCI_DEVICE_ID_REALTEK_RTL8029 0x8029
82 #define PCI_DEVICE_ID_REALTEK_8139 0x8139
84 #define PCI_VENDOR_ID_XILINX 0x10ee
86 #define PCI_VENDOR_ID_MARVELL 0x11ab
88 #define PCI_VENDOR_ID_QEMU 0x1234
89 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
91 #define PCI_VENDOR_ID_ENSONIQ 0x1274
92 #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000
94 #define PCI_VENDOR_ID_VMWARE 0x15ad
95 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
96 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
97 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
98 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
99 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
101 #define PCI_VENDOR_ID_INTEL 0x8086
102 #define PCI_DEVICE_ID_INTEL_82441 0x1237
103 #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
104 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
105 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
106 #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
107 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
108 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
109 #define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
110 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
112 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
113 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
114 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
115 #define PCI_SUBDEVICE_ID_QEMU 0x1100
117 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
118 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
119 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
120 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
122 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
123 uint32_t address
, uint32_t data
, int len
);
124 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
125 uint32_t address
, int len
);
126 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
127 uint32_t addr
, uint32_t size
, int type
);
128 typedef int PCIUnregisterFunc(PCIDevice
*pci_dev
);
130 #define PCI_ADDRESS_SPACE_MEM 0x00
131 #define PCI_ADDRESS_SPACE_IO 0x01
132 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
134 typedef struct PCIIORegion
{
135 uint32_t addr
; /* current PCI mapping address. -1 means not mapped */
138 PCIMapIORegionFunc
*map_func
;
141 #define PCI_ROM_SLOT 6
142 #define PCI_NUM_REGIONS 7
144 #define PCI_DEVICES_MAX 64
146 #define PCI_VENDOR_ID 0x00 /* 16 bits */
147 #define PCI_DEVICE_ID 0x02 /* 16 bits */
148 #define PCI_COMMAND 0x04 /* 16 bits */
149 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
150 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
151 #define PCI_REVISION 0x08
152 #define PCI_CLASS_DEVICE 0x0a /* Device class */
153 #define PCI_SUBVENDOR_ID 0x2c /* 16 bits */
154 #define PCI_SUBDEVICE_ID 0x2e /* 16 bits */
155 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
156 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
157 #define PCI_MIN_GNT 0x3e /* 8 bits */
158 #define PCI_MAX_LAT 0x3f /* 8 bits */
160 /* Bits in the PCI Status Register (PCI 2.3 spec) */
161 #define PCI_STATUS_RESERVED1 0x007
162 #define PCI_STATUS_INT_STATUS 0x008
163 #define PCI_STATUS_CAPABILITIES 0x010
164 #define PCI_STATUS_66MHZ 0x020
165 #define PCI_STATUS_RESERVED2 0x040
166 #define PCI_STATUS_FAST_BACK 0x080
167 #define PCI_STATUS_DEVSEL 0x600
169 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
170 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
171 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
173 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
175 /* Bits in the PCI Command Register (PCI 2.3 spec) */
176 #define PCI_COMMAND_RESERVED 0xf800
178 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
181 /* PCI config space */
184 /* the following fields are read only */
188 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
190 /* do not access the following fields */
191 PCIConfigReadFunc
*config_read
;
192 PCIConfigWriteFunc
*config_write
;
193 PCIUnregisterFunc
*unregister
;
194 /* ??? This is a PC-specific hack, and should be removed. */
197 /* IRQ objects for the INTA-INTD pins. */
200 /* Current IRQ levels. Used internally by the generic PCI code. */
204 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
205 int instance_size
, int devfn
,
206 PCIConfigReadFunc
*config_read
,
207 PCIConfigWriteFunc
*config_write
);
208 int pci_unregister_device(PCIDevice
*pci_dev
);
210 void pci_register_io_region(PCIDevice
*pci_dev
, int region_num
,
211 uint32_t size
, int type
,
212 PCIMapIORegionFunc
*map_func
);
214 uint32_t pci_default_read_config(PCIDevice
*d
,
215 uint32_t address
, int len
);
216 void pci_default_write_config(PCIDevice
*d
,
217 uint32_t address
, uint32_t val
, int len
);
218 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
219 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
221 typedef void (*pci_set_irq_fn
)(qemu_irq
*pic
, int irq_num
, int level
);
222 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
223 PCIBus
*pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
224 qemu_irq
*pic
, int devfn_min
, int nirq
);
226 PCIDevice
*pci_nic_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
,
227 const char *default_model
);
228 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
);
229 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
);
230 int pci_bus_num(PCIBus
*s
);
231 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
));
232 PCIBus
*pci_find_bus(int bus_num
);
233 PCIDevice
*pci_find_device(int bus_num
, int slot
, int function
);
235 int pci_read_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
);
236 int pci_assign_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
);
239 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
240 pci_map_irq_fn map_irq
, const char *name
);
243 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
245 cpu_to_le16wu((uint16_t *)&pci_config
[PCI_VENDOR_ID
], val
);
249 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
251 cpu_to_le16wu((uint16_t *)&pci_config
[PCI_DEVICE_ID
], val
);
255 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
257 cpu_to_le16wu((uint16_t *)&pci_config
[PCI_CLASS_DEVICE
], val
);
261 #define LSI_MAX_DEVS 7
262 void lsi_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
);
263 void *lsi_scsi_init(PCIBus
*bus
, int devfn
);
266 void pci_vmsvga_init(PCIBus
*bus
, uint8_t *vga_ram_base
,
267 unsigned long vga_ram_offset
, int vga_ram_size
);
270 void usb_uhci_piix3_init(PCIBus
*bus
, int devfn
);
271 void usb_uhci_piix4_init(PCIBus
*bus
, int devfn
);
274 void usb_ohci_init_pci(struct PCIBus
*bus
, int num_ports
, int devfn
);
278 PCIDevice
*pci_i82551_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
279 PCIDevice
*pci_i82557b_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
280 PCIDevice
*pci_i82559er_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
284 PCIDevice
*pci_ne2000_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
288 PCIDevice
*pci_rtl8139_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
291 PCIDevice
*pci_e1000_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
294 PCIDevice
*pci_pcnet_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
297 PCIBus
*pci_prep_init(qemu_irq
*pic
);
300 PCIBus
*pci_apb_init(target_phys_addr_t special_base
,
301 target_phys_addr_t mem_base
,
302 qemu_irq
*pic
, PCIBus
**bus2
, PCIBus
**bus3
);
305 PCIBus
*sh_pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
306 qemu_irq
*pic
, int devfn_min
, int nirq
);