hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8 #include "memory.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78
  79 #define FMT_PCIBUS                      PRIx64
  80
  81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  82                                 uint32_t address, uint32_t data, int len);
  83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  84                                    uint32_t address, int len);
  85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  86                                 pcibus_t addr, pcibus_t size, int type);
  87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  88
  89 typedef struct PCIIORegion {
  90     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  92     pcibus_t size;
  93     pcibus_t filtered_size;
  94     uint8_t type;
  95     PCIMapIORegionFunc *map_func;
  96     ram_addr_t ram_addr;
  97     MemoryRegion *memory;
  98     MemoryRegion *address_space;
  99 } PCIIORegion;
 100
 101 #define PCI_ROM_SLOT 6
 102 #define PCI_NUM_REGIONS 7
 103
 104 #include "pci_regs.h"
 105
 106 /* PCI HEADER_TYPE */
 107 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 108
 109 /* Size of the standard PCI config header */
 110 #define PCI_CONFIG_HEADER_SIZE 0x40
 111 /* Size of the standard PCI config space */
 112 #define PCI_CONFIG_SPACE_SIZE 0x100
 113 /* Size of the standart PCIe config space: 4KB */
 114 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 115
 116 #define PCI_NUM_PINS 4 /* A-D */
 117
 118 /* Bits in cap_present field. */
 119 enum {
 120     QEMU_PCI_CAP_MSI = 0x1,
 121     QEMU_PCI_CAP_MSIX = 0x2,
 122     QEMU_PCI_CAP_EXPRESS = 0x4,
 123
 124     /* multifunction capable device */
 125 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 126     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 127
 128     /* command register SERR bit enabled */
 129 #define QEMU_PCI_CAP_SERR_BITNR 4
 130     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 131 };
 132
 133 struct PCIDevice {
 134     DeviceState qdev;
 135     /* PCI config space */
 136     uint8_t *config;
 137
 138     /* Used to enable config checks on load. Note that writable bits are
 139      * never checked even if set in cmask. */
 140     uint8_t *cmask;
 141
 142     /* Used to implement R/W bytes */
 143     uint8_t *wmask;
 144
 145     /* Used to implement RW1C(Write 1 to Clear) bytes */
 146     uint8_t *w1cmask;
 147
 148     /* Used to allocate config space for capabilities. */
 149     uint8_t *used;
 150
 151     /* the following fields are read only */
 152     PCIBus *bus;
 153     uint32_t devfn;
 154     char name[64];
 155     PCIIORegion io_regions[PCI_NUM_REGIONS];
 156
 157     /* do not access the following fields */
 158     PCIConfigReadFunc *config_read;
 159     PCIConfigWriteFunc *config_write;
 160
 161     /* IRQ objects for the INTA-INTD pins.  */
 162     qemu_irq *irq;
 163
 164     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 165     uint8_t irq_state;
 166
 167     /* Capability bits */
 168     uint32_t cap_present;
 169
 170     /* Offset of MSI-X capability in config space */
 171     uint8_t msix_cap;
 172
 173     /* MSI-X entries */
 174     int msix_entries_nr;
 175
 176     /* Space to store MSIX table */
 177     uint8_t *msix_table_page;
 178     /* MMIO index used to map MSIX table and pending bit entries. */
 179     MemoryRegion msix_mmio;
 180     /* Reference-count for entries actually in use by driver. */
 181     unsigned *msix_entry_used;
 182     /* Region including the MSI-X table */
 183     uint32_t msix_bar_size;
 184     /* Version id needed for VMState */
 185     int32_t version_id;
 186
 187     /* Offset of MSI capability in config space */
 188     uint8_t msi_cap;
 189
 190     /* PCI Express */
 191     PCIExpressDevice exp;
 192
 193     /* Location of option rom */
 194     char *romfile;
 195     ram_addr_t rom_offset;
 196     uint32_t rom_bar;
 197 };
 198
 199 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 200                                int instance_size, int devfn,
 201                                PCIConfigReadFunc *config_read,
 202                                PCIConfigWriteFunc *config_write);
 203
 204 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 205                             pcibus_t size, uint8_t type,
 206                             PCIMapIORegionFunc *map_func);
 207 void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
 208                              pcibus_t size, uint8_t attr, ram_addr_t ram_addr);
 209 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
 210                              uint8_t attr, MemoryRegion *memory);
 211 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 212
 213 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 214                        uint8_t offset, uint8_t size);
 215
 216 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 217
 218 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 219
 220 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 221
 222
 223 uint32_t pci_default_read_config(PCIDevice *d,
 224                                  uint32_t address, int len);
 225 void pci_default_write_config(PCIDevice *d,
 226                               uint32_t address, uint32_t val, int len);
 227 void pci_device_save(PCIDevice *s, QEMUFile *f);
 228 int pci_device_load(PCIDevice *s, QEMUFile *f);
 229
 230 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 231 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 232
 233 typedef enum {
 234     PCI_HOTPLUG_DISABLED,
 235     PCI_HOTPLUG_ENABLED,
 236     PCI_COLDPLUG_ENABLED,
 237 } PCIHotplugState;
 238
 239 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 240                               PCIHotplugState state);
 241 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 242                          const char *name,
 243                          MemoryRegion *address_space_mem,
 244                          MemoryRegion *address_space_io,
 245                          uint8_t devfn_min);
 246 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 247                     MemoryRegion *address_space_mem,
 248                     MemoryRegion *address_space_io,
 249                     uint8_t devfn_min);
 250 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 251                   void *irq_opaque, int nirq);
 252 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 253 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 254 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 255                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 256                          void *irq_opaque,
 257                          MemoryRegion *address_space_mem,
 258                          MemoryRegion *address_space_io,
 259                          uint8_t devfn_min, int nirq);
 260 void pci_device_reset(PCIDevice *dev);
 261 void pci_bus_reset(PCIBus *bus);
 262
 263 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 264
 265 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 266                         const char *default_devaddr);
 267 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 268                                const char *default_devaddr);
 269 int pci_bus_num(PCIBus *s);
 270 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 271 PCIBus *pci_find_root_bus(int domain);
 272 int pci_find_domain(const PCIBus *bus);
 273 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 274 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 275 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 276 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 277
 278 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 279                       unsigned int *slotp, unsigned int *funcp);
 280 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 281                      unsigned *slotp);
 282
 283 void do_pci_info_print(Monitor *mon, const QObject *data);
 284 void do_pci_info(Monitor *mon, QObject **ret_data);
 285 void pci_bridge_update_mappings(PCIBus *b);
 286
 287 void pci_device_deassert_intx(PCIDevice *dev);
 288
 289 static inline void
 290 pci_set_byte(uint8_t *config, uint8_t val)
 291 {
 292     *config = val;
 293 }
 294
 295 static inline uint8_t
 296 pci_get_byte(const uint8_t *config)
 297 {
 298     return *config;
 299 }
 300
 301 static inline void
 302 pci_set_word(uint8_t *config, uint16_t val)
 303 {
 304     cpu_to_le16wu((uint16_t *)config, val);
 305 }
 306
 307 static inline uint16_t
 308 pci_get_word(const uint8_t *config)
 309 {
 310     return le16_to_cpupu((const uint16_t *)config);
 311 }
 312
 313 static inline void
 314 pci_set_long(uint8_t *config, uint32_t val)
 315 {
 316     cpu_to_le32wu((uint32_t *)config, val);
 317 }
 318
 319 static inline uint32_t
 320 pci_get_long(const uint8_t *config)
 321 {
 322     return le32_to_cpupu((const uint32_t *)config);
 323 }
 324
 325 static inline void
 326 pci_set_quad(uint8_t *config, uint64_t val)
 327 {
 328     cpu_to_le64w((uint64_t *)config, val);
 329 }
 330
 331 static inline uint64_t
 332 pci_get_quad(const uint8_t *config)
 333 {
 334     return le64_to_cpup((const uint64_t *)config);
 335 }
 336
 337 static inline void
 338 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 339 {
 340     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 341 }
 342
 343 static inline void
 344 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 345 {
 346     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 347 }
 348
 349 static inline void
 350 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 351 {
 352     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 353 }
 354
 355 static inline void
 356 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 357 {
 358     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 359 }
 360
 361 static inline void
 362 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 363 {
 364     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 365 }
 366
 367 static inline void
 368 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 369 {
 370     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 371 }
 372
 373 /*
 374  * helper functions to do bit mask operation on configuration space.
 375  * Just to set bit, use test-and-set and discard returned value.
 376  * Just to clear bit, use test-and-clear and discard returned value.
 377  * NOTE: They aren't atomic.
 378  */
 379 static inline uint8_t
 380 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 381 {
 382     uint8_t val = pci_get_byte(config);
 383     pci_set_byte(config, val & ~mask);
 384     return val & mask;
 385 }
 386
 387 static inline uint8_t
 388 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 389 {
 390     uint8_t val = pci_get_byte(config);
 391     pci_set_byte(config, val | mask);
 392     return val & mask;
 393 }
 394
 395 static inline uint16_t
 396 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 397 {
 398     uint16_t val = pci_get_word(config);
 399     pci_set_word(config, val & ~mask);
 400     return val & mask;
 401 }
 402
 403 static inline uint16_t
 404 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 405 {
 406     uint16_t val = pci_get_word(config);
 407     pci_set_word(config, val | mask);
 408     return val & mask;
 409 }
 410
 411 static inline uint32_t
 412 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 413 {
 414     uint32_t val = pci_get_long(config);
 415     pci_set_long(config, val & ~mask);
 416     return val & mask;
 417 }
 418
 419 static inline uint32_t
 420 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 421 {
 422     uint32_t val = pci_get_long(config);
 423     pci_set_long(config, val | mask);
 424     return val & mask;
 425 }
 426
 427 static inline uint64_t
 428 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 429 {
 430     uint64_t val = pci_get_quad(config);
 431     pci_set_quad(config, val & ~mask);
 432     return val & mask;
 433 }
 434
 435 static inline uint64_t
 436 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 437 {
 438     uint64_t val = pci_get_quad(config);
 439     pci_set_quad(config, val | mask);
 440     return val & mask;
 441 }
 442
 443 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 444 typedef struct {
 445     DeviceInfo qdev;
 446     pci_qdev_initfn init;
 447     PCIUnregisterFunc *exit;
 448     PCIConfigReadFunc *config_read;
 449     PCIConfigWriteFunc *config_write;
 450
 451     uint16_t vendor_id;
 452     uint16_t device_id;
 453     uint8_t revision;
 454     uint16_t class_id;
 455     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 456     uint16_t subsystem_id;              /* only for header type = 0 */
 457
 458     /*
 459      * pci-to-pci bridge or normal device.
 460      * This doesn't mean pci host switch.
 461      * When card bus bridge is supported, this would be enhanced.
 462      */
 463     int is_bridge;
 464
 465     /* pcie stuff */
 466     int is_express;   /* is this device pci express? */
 467
 468     /* device isn't hot-pluggable */
 469     int no_hotplug;
 470
 471     /* rom bar */
 472     const char *romfile;
 473 } PCIDeviceInfo;
 474
 475 void pci_qdev_register(PCIDeviceInfo *info);
 476 void pci_qdev_register_many(PCIDeviceInfo *info);
 477
 478 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 479                                     const char *name);
 480 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 481                                            bool multifunction,
 482                                            const char *name);
 483 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
 484                                         bool multifunction,
 485                                         const char *name);
 486 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 487 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 488 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
 489
 490 static inline int pci_is_express(const PCIDevice *d)
 491 {
 492     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 493 }
 494
 495 static inline uint32_t pci_config_size(const PCIDevice *d)
 496 {
 497     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 498 }
 499
 500 #endif