hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "isa.h"
  10
  11 /* PCI bus */
  12
  13 extern target_phys_addr_t pci_mem_base;
  14
  15 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  16 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  17 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  18
  19 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  20 #include "pci_ids.h"
  21
  22 /* QEMU-specific Vendor and Device ID definitions */
  23
  24 /* IBM (0x1014) */
  25 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  26 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  27
  28 /* Hitachi (0x1054) */
  29 #define PCI_VENDOR_ID_HITACHI            0x1054
  30 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  31
  32 /* Apple (0x106b) */
  33 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  35 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  37 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  38
  39 /* Realtek (0x10ec) */
  40 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  41
  42 /* Xilinx (0x10ee) */
  43 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  44
  45 /* Marvell (0x11ab) */
  46 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  47
  48 /* QEMU/Bochs VGA (0x1234) */
  49 #define PCI_VENDOR_ID_QEMU               0x1234
  50 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  51
  52 /* VMWare (0x15ad) */
  53 #define PCI_VENDOR_ID_VMWARE             0x15ad
  54 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  55 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  56 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  57 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  58 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  59
  60 /* Intel (0x8086) */
  61 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  62 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  63
  64 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  65 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  66 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  67 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  68
  69 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  70 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  71 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  72 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  73
  74 typedef uint32_t pcibus_t;
  75
  76 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  77                                 uint32_t address, uint32_t data, int len);
  78 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  79                                    uint32_t address, int len);
  80 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  81                                 pcibus_t addr, pcibus_t size, int type);
  82 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  83
  84 typedef struct PCIIORegion {
  85     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  86 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  87     pcibus_t size;
  88     uint8_t type;
  89     PCIMapIORegionFunc *map_func;
  90 } PCIIORegion;
  91
  92 #define PCI_ROM_SLOT 6
  93 #define PCI_NUM_REGIONS 7
  94
  95 /* Declarations from linux/pci_regs.h */
  96 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  97 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  98 #define PCI_COMMAND             0x04    /* 16 bits */
  99 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 100 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 101 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus master */
 102 #define PCI_STATUS              0x06    /* 16 bits */
 103 #define PCI_REVISION_ID         0x08    /* 8 bits  */
 104 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
 105 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 106 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
 107 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
 108 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
 109 #define  PCI_HEADER_TYPE_NORMAL         0
 110 #define  PCI_HEADER_TYPE_BRIDGE         1
 111 #define  PCI_HEADER_TYPE_CARDBUS        2
 112 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 113 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
 114 #define  PCI_BASE_ADDRESS_SPACE_IO      0x01
 115 #define  PCI_BASE_ADDRESS_SPACE_MEMORY  0x00
 116 #define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
 117 #define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
 118 #define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
 119 #define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
 120 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
 121 #define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
 122 #define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
 123 #define  PCI_ROM_ADDRESS_ENABLE 0x01
 124 #define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
 125 #define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
 126 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 127 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 128 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 129 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 130
 131 /* Capability lists */
 132 #define PCI_CAP_LIST_ID         0       /* Capability ID */
 133 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 134
 135 #define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
 136 #define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
 137 #define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */
 138
 139 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 140 #define PCI_STATUS_RESERVED1    0x007
 141 #define PCI_STATUS_INT_STATUS   0x008
 142 #define PCI_STATUS_CAP_LIST     0x010
 143 #define PCI_STATUS_66MHZ        0x020
 144 #define PCI_STATUS_RESERVED2    0x040
 145 #define PCI_STATUS_FAST_BACK    0x080
 146 #define PCI_STATUS_DEVSEL       0x600
 147
 148 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 149                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 150                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 151
 152 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 153
 154 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 155 #define PCI_COMMAND_RESERVED    0xf800
 156
 157 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 158
 159 /* Size of the standard PCI config header */
 160 #define PCI_CONFIG_HEADER_SIZE 0x40
 161 /* Size of the standard PCI config space */
 162 #define PCI_CONFIG_SPACE_SIZE 0x100
 163
 164 #define PCI_NUM_PINS 4 /* A-D */
 165
 166 /* Bits in cap_present field. */
 167 enum {
 168     QEMU_PCI_CAP_MSIX = 0x1,
 169 };
 170
 171 struct PCIDevice {
 172     DeviceState qdev;
 173     /* PCI config space */
 174     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 175
 176     /* Used to enable config checks on load. Note that writeable bits are
 177      * never checked even if set in cmask. */
 178     uint8_t cmask[PCI_CONFIG_SPACE_SIZE];
 179
 180     /* Used to implement R/W bytes */
 181     uint8_t wmask[PCI_CONFIG_SPACE_SIZE];
 182
 183     /* Used to allocate config space for capabilities. */
 184     uint8_t used[PCI_CONFIG_SPACE_SIZE];
 185
 186     /* the following fields are read only */
 187     PCIBus *bus;
 188     uint32_t devfn;
 189     char name[64];
 190     PCIIORegion io_regions[PCI_NUM_REGIONS];
 191
 192     /* do not access the following fields */
 193     PCIConfigReadFunc *config_read;
 194     PCIConfigWriteFunc *config_write;
 195
 196     /* IRQ objects for the INTA-INTD pins.  */
 197     qemu_irq *irq;
 198
 199     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 200     int irq_state[PCI_NUM_PINS];
 201
 202     /* Capability bits */
 203     uint32_t cap_present;
 204
 205     /* Offset of MSI-X capability in config space */
 206     uint8_t msix_cap;
 207
 208     /* MSI-X entries */
 209     int msix_entries_nr;
 210
 211     /* Space to store MSIX table */
 212     uint8_t *msix_table_page;
 213     /* MMIO index used to map MSIX table and pending bit entries. */
 214     int msix_mmio_index;
 215     /* Reference-count for entries actually in use by driver. */
 216     unsigned *msix_entry_used;
 217     /* Region including the MSI-X table */
 218     uint32_t msix_bar_size;
 219     /* Version id needed for VMState */
 220     int32_t version_id;
 221 };
 222
 223 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 224                                int instance_size, int devfn,
 225                                PCIConfigReadFunc *config_read,
 226                                PCIConfigWriteFunc *config_write);
 227
 228 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 229                             pcibus_t size, int type,
 230                             PCIMapIORegionFunc *map_func);
 231
 232 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 233
 234 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 235
 236 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 237
 238 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 239
 240
 241 uint32_t pci_default_read_config(PCIDevice *d,
 242                                  uint32_t address, int len);
 243 void pci_default_write_config(PCIDevice *d,
 244                               uint32_t address, uint32_t val, int len);
 245 void pci_device_save(PCIDevice *s, QEMUFile *f);
 246 int pci_device_load(PCIDevice *s, QEMUFile *f);
 247
 248 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 249 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 250 typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state);
 251 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 252                          const char *name, int devfn_min);
 253 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 254 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 255                   void *irq_opaque, int nirq);
 256 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
 257 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 258                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 259                          void *irq_opaque, int devfn_min, int nirq);
 260
 261 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 262                         const char *default_devaddr);
 263 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 264                                const char *default_devaddr);
 265 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 266 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 267 int pci_bus_num(PCIBus *s);
 268 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 269 PCIBus *pci_find_bus(int bus_num);
 270 PCIDevice *pci_find_device(int bus_num, int slot, int function);
 271 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 272
 273 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 274                      unsigned *slotp);
 275
 276 void pci_info(Monitor *mon);
 277 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 278                         pci_map_irq_fn map_irq, const char *name);
 279
 280 static inline void
 281 pci_set_byte(uint8_t *config, uint8_t val)
 282 {
 283     *config = val;
 284 }
 285
 286 static inline uint8_t
 287 pci_get_byte(uint8_t *config)
 288 {
 289     return *config;
 290 }
 291
 292 static inline void
 293 pci_set_word(uint8_t *config, uint16_t val)
 294 {
 295     cpu_to_le16wu((uint16_t *)config, val);
 296 }
 297
 298 static inline uint16_t
 299 pci_get_word(uint8_t *config)
 300 {
 301     return le16_to_cpupu((uint16_t *)config);
 302 }
 303
 304 static inline void
 305 pci_set_long(uint8_t *config, uint32_t val)
 306 {
 307     cpu_to_le32wu((uint32_t *)config, val);
 308 }
 309
 310 static inline uint32_t
 311 pci_get_long(uint8_t *config)
 312 {
 313     return le32_to_cpupu((uint32_t *)config);
 314 }
 315
 316 static inline void
 317 pci_set_quad(uint8_t *config, uint64_t val)
 318 {
 319     cpu_to_le64w((uint64_t *)config, val);
 320 }
 321
 322 static inline uint64_t
 323 pci_get_quad(uint8_t *config)
 324 {
 325     return le64_to_cpup((uint64_t *)config);
 326 }
 327
 328 static inline void
 329 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 330 {
 331     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 332 }
 333
 334 static inline void
 335 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 336 {
 337     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 338 }
 339
 340 static inline void
 341 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 342 {
 343     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 344 }
 345
 346 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 347 typedef struct {
 348     DeviceInfo qdev;
 349     pci_qdev_initfn init;
 350     PCIUnregisterFunc *exit;
 351     PCIConfigReadFunc *config_read;
 352     PCIConfigWriteFunc *config_write;
 353 } PCIDeviceInfo;
 354
 355 void pci_qdev_register(PCIDeviceInfo *info);
 356 void pci_qdev_register_many(PCIDeviceInfo *info);
 357
 358 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 359 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 360
 361 /* lsi53c895a.c */
 362 #define LSI_MAX_DEVS 7
 363
 364 /* vmware_vga.c */
 365 void pci_vmsvga_init(PCIBus *bus);
 366
 367 /* usb-uhci.c */
 368 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 369 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 370
 371 /* usb-ohci.c */
 372 void usb_ohci_init_pci(struct PCIBus *bus, int devfn);
 373
 374 /* prep_pci.c */
 375 PCIBus *pci_prep_init(qemu_irq *pic);
 376
 377 /* apb_pci.c */
 378 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 379                      target_phys_addr_t mem_base,
 380                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 381
 382 /* sh_pci.c */
 383 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 384                             void *pic, int devfn_min, int nirq);
 385
 386 #endif