hw/pcie.c

   1 /*
   2  * pcie.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "sysemu.h"
  22 #include "range.h"
  23 #include "pci_bridge.h"
  24 #include "pcie.h"
  25 #include "msix.h"
  26 #include "msi.h"
  27 #include "pci_internals.h"
  28 #include "pcie_regs.h"
  29 #include "range.h"
  30
  31 //#define DEBUG_PCIE
  32 #ifdef DEBUG_PCIE
  33 # define PCIE_DPRINTF(fmt, ...)                                         \
  34     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  35 #else
  36 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
  37 #endif
  38 #define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  39     PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  40
  41
  42 /***************************************************************************
  43  * pci express capability helper functions
  44  */
  45 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
  46 {
  47     int pos;
  48     uint8_t *exp_cap;
  49
  50     assert(pci_is_express(dev));
  51
  52     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
  53                                  PCI_EXP_VER2_SIZEOF);
  54     if (pos < 0) {
  55         return pos;
  56     }
  57     dev->exp.exp_cap = pos;
  58     exp_cap = dev->config + pos;
  59
  60     /* capability register
  61        interrupt message number defaults to 0 */
  62     pci_set_word(exp_cap + PCI_EXP_FLAGS,
  63                  ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
  64                  PCI_EXP_FLAGS_VER2);
  65
  66     /* device capability register
  67      * table 7-12:
  68      * roll based error reporting bit must be set by all
  69      * Functions conforming to the ECN, PCI Express Base
  70      * Specification, Revision 1.1., or subsequent PCI Express Base
  71      * Specification revisions.
  72      */
  73     pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
  74
  75     pci_set_long(exp_cap + PCI_EXP_LNKCAP,
  76                  (port << PCI_EXP_LNKCAP_PN_SHIFT) |
  77                  PCI_EXP_LNKCAP_ASPMS_0S |
  78                  PCI_EXP_LNK_MLW_1 |
  79                  PCI_EXP_LNK_LS_25);
  80
  81     pci_set_word(exp_cap + PCI_EXP_LNKSTA,
  82                  PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
  83
  84     pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
  85                  PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
  86
  87     pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB);
  88     return pos;
  89 }
  90
  91 void pcie_cap_exit(PCIDevice *dev)
  92 {
  93     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
  94 }
  95
  96 uint8_t pcie_cap_get_type(const PCIDevice *dev)
  97 {
  98     uint32_t pos = dev->exp.exp_cap;
  99     assert(pos > 0);
 100     return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
 101             PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
 102 }
 103
 104 /* MSI/MSI-X */
 105 /* pci express interrupt message number */
 106 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
 107 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
 108 {
 109     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 110     assert(vector < 32);
 111     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
 112     pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
 113                                vector << PCI_EXP_FLAGS_IRQ_SHIFT);
 114 }
 115
 116 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
 117 {
 118     return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
 119             PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
 120 }
 121
 122 void pcie_cap_deverr_init(PCIDevice *dev)
 123 {
 124     uint32_t pos = dev->exp.exp_cap;
 125     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
 126                                PCI_EXP_DEVCAP_RBER);
 127     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
 128                                PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 129                                PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 130     pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
 131                                PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
 132                                PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD);
 133 }
 134
 135 void pcie_cap_deverr_reset(PCIDevice *dev)
 136 {
 137     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 138     pci_long_test_and_clear_mask(devctl,
 139                                  PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 140                                  PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 141 }
 142
 143 static void hotplug_event_update_event_status(PCIDevice *dev)
 144 {
 145     uint32_t pos = dev->exp.exp_cap;
 146     uint8_t *exp_cap = dev->config + pos;
 147     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 148     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 149
 150     dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 151         (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
 152 }
 153
 154 static void hotplug_event_notify(PCIDevice *dev)
 155 {
 156     bool prev = dev->exp.hpev_notified;
 157
 158     hotplug_event_update_event_status(dev);
 159
 160     if (prev == dev->exp.hpev_notified) {
 161         return;
 162     }
 163
 164     /* Note: the logic above does not take into account whether interrupts
 165      * are masked. The result is that interrupt will be sent when it is
 166      * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
 167      * The Port may optionally send an MSI when there are hot-plug events that
 168      * occur while interrupt generation is disabled, and interrupt generation is
 169      * subsequently enabled. */
 170     if (!pci_msi_enabled(dev)) {
 171         qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified);
 172     } else if (dev->exp.hpev_notified) {
 173         pci_msi_notify(dev, pcie_cap_flags_get_vector(dev));
 174     }
 175 }
 176
 177 /*
 178  * A PCI Express Hot-Plug Event has occured, so update slot status register
 179  * and notify OS of the event if necessary.
 180  *
 181  * 6.7.3 PCI Express Hot-Plug Events
 182  * 6.7.3.4 Software Notification of Hot-Plug Events
 183  */
 184 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
 185 {
 186     /* Minor optimization: if nothing changed - no event is needed. */
 187     if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
 188                                    PCI_EXP_SLTSTA, event)) {
 189         return;
 190     }
 191     hotplug_event_notify(dev);
 192 }
 193
 194 static int pcie_cap_slot_hotplug(DeviceState *qdev,
 195                                  PCIDevice *pci_dev, int state)
 196 {
 197     PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
 198     uint8_t *exp_cap = d->config + d->exp.exp_cap;
 199     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 200
 201     if (!pci_dev->qdev.hotplugged) {
 202         assert(state); /* this case only happens at machine creation. */
 203         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 204                                    PCI_EXP_SLTSTA_PDS);
 205         return 0;
 206     }
 207
 208     PCIE_DEV_PRINTF(pci_dev, "hotplug state: %d\n", state);
 209     if (sltsta & PCI_EXP_SLTSTA_EIS) {
 210         /* the slot is electromechanically locked.
 211          * This error is propagated up to qdev and then to HMP/QMP.
 212          */
 213         return -EBUSY;
 214     }
 215
 216     /* TODO: multifunction hot-plug.
 217      * Right now, only a device of function = 0 is allowed to be
 218      * hot plugged/unplugged.
 219      */
 220     assert(PCI_FUNC(pci_dev->devfn) == 0);
 221
 222     if (state) {
 223         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 224                                    PCI_EXP_SLTSTA_PDS);
 225         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 226     } else {
 227         qdev_free(&pci_dev->qdev);
 228         pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 229                                      PCI_EXP_SLTSTA_PDS);
 230         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 231     }
 232     return 0;
 233 }
 234
 235 /* pci express slot for pci express root/downstream port
 236    PCI express capability slot registers */
 237 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
 238 {
 239     uint32_t pos = dev->exp.exp_cap;
 240
 241     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
 242                                PCI_EXP_FLAGS_SLOT);
 243
 244     pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
 245                                  ~PCI_EXP_SLTCAP_PSN);
 246     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 247                                (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
 248                                PCI_EXP_SLTCAP_EIP |
 249                                PCI_EXP_SLTCAP_HPS |
 250                                PCI_EXP_SLTCAP_HPC |
 251                                PCI_EXP_SLTCAP_PIP |
 252                                PCI_EXP_SLTCAP_AIP |
 253                                PCI_EXP_SLTCAP_ABP);
 254
 255     pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 256                                  PCI_EXP_SLTCTL_PIC |
 257                                  PCI_EXP_SLTCTL_AIC);
 258     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
 259                                PCI_EXP_SLTCTL_PIC_OFF |
 260                                PCI_EXP_SLTCTL_AIC_OFF);
 261     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 262                                PCI_EXP_SLTCTL_PIC |
 263                                PCI_EXP_SLTCTL_AIC |
 264                                PCI_EXP_SLTCTL_HPIE |
 265                                PCI_EXP_SLTCTL_CCIE |
 266                                PCI_EXP_SLTCTL_PDCE |
 267                                PCI_EXP_SLTCTL_ABPE);
 268     /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
 269      * make the bit writable here in order to detect 1b is written.
 270      * pcie_cap_slot_write_config() test-and-clear the bit, so
 271      * this bit always returns 0 to the guest.
 272      */
 273     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 274                                PCI_EXP_SLTCTL_EIC);
 275
 276     pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
 277                                PCI_EXP_HP_EV_SUPPORTED);
 278
 279     dev->exp.hpev_notified = false;
 280
 281     pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)),
 282                     pcie_cap_slot_hotplug, &dev->qdev);
 283 }
 284
 285 void pcie_cap_slot_reset(PCIDevice *dev)
 286 {
 287     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 288
 289     PCIE_DEV_PRINTF(dev, "reset\n");
 290
 291     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 292                                  PCI_EXP_SLTCTL_EIC |
 293                                  PCI_EXP_SLTCTL_PIC |
 294                                  PCI_EXP_SLTCTL_AIC |
 295                                  PCI_EXP_SLTCTL_HPIE |
 296                                  PCI_EXP_SLTCTL_CCIE |
 297                                  PCI_EXP_SLTCTL_PDCE |
 298                                  PCI_EXP_SLTCTL_ABPE);
 299     pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 300                                PCI_EXP_SLTCTL_PIC_OFF |
 301                                PCI_EXP_SLTCTL_AIC_OFF);
 302
 303     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 304                                  PCI_EXP_SLTSTA_EIS |/* on reset,
 305                                                         the lock is released */
 306                                  PCI_EXP_SLTSTA_CC |
 307                                  PCI_EXP_SLTSTA_PDC |
 308                                  PCI_EXP_SLTSTA_ABP);
 309
 310     hotplug_event_update_event_status(dev);
 311 }
 312
 313 void pcie_cap_slot_write_config(PCIDevice *dev,
 314                                 uint32_t addr, uint32_t val, int len)
 315 {
 316     uint32_t pos = dev->exp.exp_cap;
 317     uint8_t *exp_cap = dev->config + pos;
 318     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 319
 320     if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
 321         return;
 322     }
 323
 324     if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 325                                      PCI_EXP_SLTCTL_EIC)) {
 326         sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
 327         pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
 328         PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
 329                         "sltsta -> 0x%02"PRIx16"\n",
 330                         sltsta);
 331     }
 332
 333     hotplug_event_notify(dev);
 334
 335     /*
 336      * 6.7.3.2 Command Completed Events
 337      *
 338      * Software issues a command to a hot-plug capable Downstream Port by
 339      * issuing a write transaction that targets any portion of the Port’s Slot
 340      * Control register. A single write to the Slot Control register is
 341      * considered to be a single command, even if the write affects more than
 342      * one field in the Slot Control register. In response to this transaction,
 343      * the Port must carry out the requested actions and then set the
 344      * associated status field for the command completed event. */
 345
 346     /* Real hardware might take a while to complete requested command because
 347      * physical movement would be involved like locking the electromechanical
 348      * lock.  However in our case, command is completed instantaneously above,
 349      * so send a command completion event right now.
 350      */
 351     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
 352 }
 353
 354 int pcie_cap_slot_post_load(void *opaque, int version_id)
 355 {
 356     PCIDevice *dev = opaque;
 357     hotplug_event_update_event_status(dev);
 358     return 0;
 359 }
 360
 361 void pcie_cap_slot_push_attention_button(PCIDevice *dev)
 362 {
 363     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
 364 }
 365
 366 /* root control/capabilities/status. PME isn't emulated for now */
 367 void pcie_cap_root_init(PCIDevice *dev)
 368 {
 369     pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
 370                  PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 371                  PCI_EXP_RTCTL_SEFEE);
 372 }
 373
 374 void pcie_cap_root_reset(PCIDevice *dev)
 375 {
 376     pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
 377 }
 378
 379 /*
 380  * TODO: implement FLR:
 381  * Right now sets the bit which indicates FLR is supported.
 382  */
 383 /* function level reset(FLR) */
 384 void pcie_cap_flr_init(PCIDevice *dev)
 385 {
 386     pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
 387                                PCI_EXP_DEVCAP_FLR);
 388
 389     /* Although reading BCR_FLR returns always 0,
 390      * the bit is made writable here in order to detect the 1b is written
 391      * pcie_cap_flr_write_config() test-and-clear the bit, so
 392      * this bit always returns 0 to the guest.
 393      */
 394     pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
 395                                PCI_EXP_DEVCTL_BCR_FLR);
 396 }
 397
 398 void pcie_cap_flr_write_config(PCIDevice *dev,
 399                                uint32_t addr, uint32_t val, int len)
 400 {
 401     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 402     if (pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR)) {
 403         /* TODO: implement FLR */
 404     }
 405 }
 406
 407 /* Alternative Routing-ID Interpretation (ARI) */
 408 /* ari forwarding support for down stream port */
 409 void pcie_cap_ari_init(PCIDevice *dev)
 410 {
 411     uint32_t pos = dev->exp.exp_cap;
 412     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
 413                                PCI_EXP_DEVCAP2_ARI);
 414     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
 415                                PCI_EXP_DEVCTL2_ARI);
 416 }
 417
 418 void pcie_cap_ari_reset(PCIDevice *dev)
 419 {
 420     uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
 421     pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
 422 }
 423
 424 bool pcie_cap_is_ari_enabled(const PCIDevice *dev)
 425 {
 426     if (!pci_is_express(dev)) {
 427         return false;
 428     }
 429     if (!dev->exp.exp_cap) {
 430         return false;
 431     }
 432
 433     return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 434         PCI_EXP_DEVCTL2_ARI;
 435 }
 436
 437 /**************************************************************************
 438  * pci express extended capability allocation functions
 439  * uint16_t ext_cap_id (16 bit)
 440  * uint8_t cap_ver (4 bit)
 441  * uint16_t cap_offset (12 bit)
 442  * uint16_t ext_cap_size
 443  */
 444
 445 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
 446                                           uint16_t *prev_p)
 447 {
 448     uint16_t prev = 0;
 449     uint16_t next;
 450     uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
 451
 452     if (!header) {
 453         /* no extended capability */
 454         next = 0;
 455         goto out;
 456     }
 457     for (next = PCI_CONFIG_SPACE_SIZE; next;
 458          prev = next, next = PCI_EXT_CAP_NEXT(header)) {
 459
 460         assert(next >= PCI_CONFIG_SPACE_SIZE);
 461         assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
 462
 463         header = pci_get_long(dev->config + next);
 464         if (PCI_EXT_CAP_ID(header) == cap_id) {
 465             break;
 466         }
 467     }
 468
 469 out:
 470     if (prev_p) {
 471         *prev_p = prev;
 472     }
 473     return next;
 474 }
 475
 476 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
 477 {
 478     return pcie_find_capability_list(dev, cap_id, NULL);
 479 }
 480
 481 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
 482 {
 483     uint16_t header = pci_get_long(dev->config + pos);
 484     assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
 485     header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
 486         ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
 487     pci_set_long(dev->config + pos, header);
 488 }
 489
 490 /*
 491  * caller must supply valid (offset, size) * such that the range shouldn't
 492  * overlap with other capability or other registers.
 493  * This function doesn't check it.
 494  */
 495 void pcie_add_capability(PCIDevice *dev,
 496                          uint16_t cap_id, uint8_t cap_ver,
 497                          uint16_t offset, uint16_t size)
 498 {
 499     uint32_t header;
 500     uint16_t next;
 501
 502     assert(offset >= PCI_CONFIG_SPACE_SIZE);
 503     assert(offset < offset + size);
 504     assert(offset + size < PCIE_CONFIG_SPACE_SIZE);
 505     assert(size >= 8);
 506     assert(pci_is_express(dev));
 507
 508     if (offset == PCI_CONFIG_SPACE_SIZE) {
 509         header = pci_get_long(dev->config + offset);
 510         next = PCI_EXT_CAP_NEXT(header);
 511     } else {
 512         uint16_t prev;
 513
 514         /* 0 is reserved cap id. use internally to find the last capability
 515            in the linked list */
 516         next = pcie_find_capability_list(dev, 0, &prev);
 517
 518         assert(prev >= PCI_CONFIG_SPACE_SIZE);
 519         assert(next == 0);
 520         pcie_ext_cap_set_next(dev, prev, offset);
 521     }
 522     pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
 523
 524     /* Make capability read-only by default */
 525     memset(dev->wmask + offset, 0, size);
 526     memset(dev->w1cmask + offset, 0, size);
 527     /* Check capability by default */
 528     memset(dev->cmask + offset, 0xFF, size);
 529 }
 530
 531 /**************************************************************************
 532  * pci express extended capability helper functions
 533  */
 534
 535 /* ARI */
 536 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
 537 {
 538     pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
 539                         offset, PCI_ARI_SIZEOF);
 540     pci_set_long(dev->config + offset + PCI_ARI_CAP, PCI_ARI_CAP_NFN(nextfn));
 541 }