hw/pcnet-pci.c

   1 /*
   2  * QEMU AMD PC-Net II (Am79C970A) PCI emulation
   3  *
   4  * Copyright (c) 2004 Antony T Curtis
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /* This software was written to be compatible with the specification:
  26  * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
  27  * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
  28  */
  29
  30 #include "pci.h"
  31 #include "net.h"
  32 #include "loader.h"
  33 #include "qemu-timer.h"
  34 #include "dma.h"
  35
  36 #include "pcnet.h"
  37
  38 //#define PCNET_DEBUG
  39 //#define PCNET_DEBUG_IO
  40 //#define PCNET_DEBUG_BCR
  41 //#define PCNET_DEBUG_CSR
  42 //#define PCNET_DEBUG_RMD
  43 //#define PCNET_DEBUG_TMD
  44 //#define PCNET_DEBUG_MATCH
  45
  46
  47 typedef struct {
  48     PCIDevice pci_dev;
  49     PCNetState state;
  50     MemoryRegion io_bar;
  51 } PCIPCNetState;
  52
  53 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
  54 {
  55     PCNetState *s = opaque;
  56 #ifdef PCNET_DEBUG
  57     printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
  58 #endif
  59     if (BCR_APROMWE(s)) {
  60         s->prom[addr & 15] = val;
  61     }
  62 }
  63
  64 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
  65 {
  66     PCNetState *s = opaque;
  67     uint32_t val = s->prom[addr & 15];
  68 #ifdef PCNET_DEBUG
  69     printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
  70 #endif
  71     return val;
  72 }
  73
  74 static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
  75                                   unsigned size)
  76 {
  77     PCNetState *d = opaque;
  78
  79     if (addr < 16 && size == 1) {
  80         return pcnet_aprom_readb(d, addr);
  81     } else if (addr >= 0x10 && addr < 0x20 && size == 2) {
  82         return pcnet_ioport_readw(d, addr);
  83     } else if (addr >= 0x10 && addr < 0x20 && size == 4) {
  84         return pcnet_ioport_readl(d, addr);
  85     }
  86     return ((uint64_t)1 << (size * 8)) - 1;
  87 }
  88
  89 static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
  90                                uint64_t data, unsigned size)
  91 {
  92     PCNetState *d = opaque;
  93
  94     if (addr < 16 && size == 1) {
  95         return pcnet_aprom_writeb(d, addr, data);
  96     } else if (addr >= 0x10 && addr < 0x20 && size == 2) {
  97         return pcnet_ioport_writew(d, addr, data);
  98     } else if (addr >= 0x10 && addr < 0x20 && size == 4) {
  99         return pcnet_ioport_writel(d, addr, data);
 100     }
 101 }
 102
 103 static const MemoryRegionOps pcnet_io_ops = {
 104     .read = pcnet_ioport_read,
 105     .write = pcnet_ioport_write,
 106     .endianness = DEVICE_NATIVE_ENDIAN,
 107 };
 108
 109 static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 110 {
 111     PCNetState *d = opaque;
 112 #ifdef PCNET_DEBUG_IO
 113     printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
 114            val);
 115 #endif
 116     if (!(addr & 0x10))
 117         pcnet_aprom_writeb(d, addr & 0x0f, val);
 118 }
 119
 120 static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
 121 {
 122     PCNetState *d = opaque;
 123     uint32_t val = -1;
 124     if (!(addr & 0x10))
 125         val = pcnet_aprom_readb(d, addr & 0x0f);
 126 #ifdef PCNET_DEBUG_IO
 127     printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
 128            val & 0xff);
 129 #endif
 130     return val;
 131 }
 132
 133 static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 134 {
 135     PCNetState *d = opaque;
 136 #ifdef PCNET_DEBUG_IO
 137     printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
 138            val);
 139 #endif
 140     if (addr & 0x10)
 141         pcnet_ioport_writew(d, addr & 0x0f, val);
 142     else {
 143         addr &= 0x0f;
 144         pcnet_aprom_writeb(d, addr, val & 0xff);
 145         pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
 146     }
 147 }
 148
 149 static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
 150 {
 151     PCNetState *d = opaque;
 152     uint32_t val = -1;
 153     if (addr & 0x10)
 154         val = pcnet_ioport_readw(d, addr & 0x0f);
 155     else {
 156         addr &= 0x0f;
 157         val = pcnet_aprom_readb(d, addr+1);
 158         val <<= 8;
 159         val |= pcnet_aprom_readb(d, addr);
 160     }
 161 #ifdef PCNET_DEBUG_IO
 162     printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
 163            val & 0xffff);
 164 #endif
 165     return val;
 166 }
 167
 168 static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 169 {
 170     PCNetState *d = opaque;
 171 #ifdef PCNET_DEBUG_IO
 172     printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
 173            val);
 174 #endif
 175     if (addr & 0x10)
 176         pcnet_ioport_writel(d, addr & 0x0f, val);
 177     else {
 178         addr &= 0x0f;
 179         pcnet_aprom_writeb(d, addr, val & 0xff);
 180         pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
 181         pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
 182         pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
 183     }
 184 }
 185
 186 static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
 187 {
 188     PCNetState *d = opaque;
 189     uint32_t val;
 190     if (addr & 0x10)
 191         val = pcnet_ioport_readl(d, addr & 0x0f);
 192     else {
 193         addr &= 0x0f;
 194         val = pcnet_aprom_readb(d, addr+3);
 195         val <<= 8;
 196         val |= pcnet_aprom_readb(d, addr+2);
 197         val <<= 8;
 198         val |= pcnet_aprom_readb(d, addr+1);
 199         val <<= 8;
 200         val |= pcnet_aprom_readb(d, addr);
 201     }
 202 #ifdef PCNET_DEBUG_IO
 203     printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
 204            val);
 205 #endif
 206     return val;
 207 }
 208
 209 static const VMStateDescription vmstate_pci_pcnet = {
 210     .name = "pcnet",
 211     .version_id = 3,
 212     .minimum_version_id = 2,
 213     .minimum_version_id_old = 2,
 214     .fields      = (VMStateField []) {
 215         VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState),
 216         VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
 217         VMSTATE_END_OF_LIST()
 218     }
 219 };
 220
 221 /* PCI interface */
 222
 223 static const MemoryRegionOps pcnet_mmio_ops = {
 224     .old_mmio = {
 225         .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
 226         .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
 227     },
 228     .endianness = DEVICE_NATIVE_ENDIAN,
 229 };
 230
 231 static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
 232                                       uint8_t *buf, int len, int do_bswap)
 233 {
 234     pci_dma_write(dma_opaque, addr, buf, len);
 235 }
 236
 237 static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
 238                                      uint8_t *buf, int len, int do_bswap)
 239 {
 240     pci_dma_read(dma_opaque, addr, buf, len);
 241 }
 242
 243 static void pci_pcnet_cleanup(VLANClientState *nc)
 244 {
 245     PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;
 246
 247     pcnet_common_cleanup(d);
 248 }
 249
 250 static int pci_pcnet_uninit(PCIDevice *dev)
 251 {
 252     PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev);
 253
 254     memory_region_destroy(&d->state.mmio);
 255     memory_region_destroy(&d->io_bar);
 256     qemu_del_timer(d->state.poll_timer);
 257     qemu_free_timer(d->state.poll_timer);
 258     qemu_del_vlan_client(&d->state.nic->nc);
 259     return 0;
 260 }
 261
 262 static NetClientInfo net_pci_pcnet_info = {
 263     .type = NET_CLIENT_TYPE_NIC,
 264     .size = sizeof(NICState),
 265     .can_receive = pcnet_can_receive,
 266     .receive = pcnet_receive,
 267     .cleanup = pci_pcnet_cleanup,
 268 };
 269
 270 static int pci_pcnet_init(PCIDevice *pci_dev)
 271 {
 272     PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
 273     PCNetState *s = &d->state;
 274     uint8_t *pci_conf;
 275
 276 #if 0
 277     printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
 278         sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
 279 #endif
 280
 281     pci_conf = pci_dev->config;
 282
 283     pci_set_word(pci_conf + PCI_STATUS,
 284                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
 285
 286     pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
 287     pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
 288
 289     pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
 290     pci_conf[PCI_MIN_GNT] = 0x06;
 291     pci_conf[PCI_MAX_LAT] = 0xff;
 292
 293     /* Handler for memory-mapped I/O */
 294     memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, s, "pcnet-mmio",
 295                           PCNET_PNPMMIO_SIZE);
 296
 297     memory_region_init_io(&d->io_bar, &pcnet_io_ops, s, "pcnet-io",
 298                           PCNET_IOPORT_SIZE);
 299     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
 300
 301     pci_register_bar(pci_dev, 1, 0, &s->mmio);
 302
 303     s->irq = pci_dev->irq[0];
 304     s->phys_mem_read = pci_physical_memory_read;
 305     s->phys_mem_write = pci_physical_memory_write;
 306     s->dma_opaque = pci_dev;
 307
 308     if (!pci_dev->qdev.hotplugged) {
 309         static int loaded = 0;
 310         if (!loaded) {
 311             rom_add_option("pxe-pcnet.rom", -1);
 312             loaded = 1;
 313         }
 314     }
 315
 316     return pcnet_common_init(&pci_dev->qdev, s, &net_pci_pcnet_info);
 317 }
 318
 319 static void pci_reset(DeviceState *dev)
 320 {
 321     PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev);
 322
 323     pcnet_h_reset(&d->state);
 324 }
 325
 326 static PCIDeviceInfo pcnet_info = {
 327     .qdev.name  = "pcnet",
 328     .qdev.size  = sizeof(PCIPCNetState),
 329     .qdev.reset = pci_reset,
 330     .qdev.vmsd  = &vmstate_pci_pcnet,
 331     .init       = pci_pcnet_init,
 332     .exit       = pci_pcnet_uninit,
 333     .vendor_id  = PCI_VENDOR_ID_AMD,
 334     .device_id  = PCI_DEVICE_ID_AMD_LANCE,
 335     .revision   = 0x10,
 336     .class_id   = PCI_CLASS_NETWORK_ETHERNET,
 337     .qdev.props = (Property[]) {
 338         DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
 339         DEFINE_PROP_END_OF_LIST(),
 340     }
 341 };
 342
 343 static void pci_pcnet_register_devices(void)
 344 {
 345     pci_qdev_register(&pcnet_info);
 346 }
 347
 348 device_init(pci_pcnet_register_devices)