hw/pflash_cfi01.c

   1 /*
   2  *  CFI parallel flash with Intel command set emulation
   3  *
   4  *  Copyright (c) 2006 Thorsten Zitterell
   5  *  Copyright (c) 2005 Jocelyn Mayer
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 /*
  22  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  23  * Supported commands/modes are:
  24  * - flash read
  25  * - flash write
  26  * - flash ID read
  27  * - sector erase
  28  * - CFI queries
  29  *
  30  * It does not support timings
  31  * It does not support flash interleaving
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  *
  36  * It does not implement much more ...
  37  */
  38
  39 #include "hw.h"
  40 #include "flash.h"
  41 #include "block/block.h"
  42 #include "qemu/timer.h"
  43 #include "exec/address-spaces.h"
  44 #include "qemu/host-utils.h"
  45 #include "sysbus.h"
  46
  47 #define PFLASH_BUG(fmt, ...) \
  48 do { \
  49     fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
  50     exit(1); \
  51 } while(0)
  52
  53 /* #define PFLASH_DEBUG */
  54 #ifdef PFLASH_DEBUG
  55 #define DPRINTF(fmt, ...)                                   \
  56 do {                                                        \
  57     fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__);       \
  58 } while (0)
  59 #else
  60 #define DPRINTF(fmt, ...) do { } while (0)
  61 #endif
  62
  63 struct pflash_t {
  64     SysBusDevice busdev;
  65     BlockDriverState *bs;
  66     uint32_t nb_blocs;
  67     uint64_t sector_len;
  68     uint8_t width;
  69     uint8_t be;
  70     int wcycle; /* if 0, the flash is read normally */
  71     int bypass;
  72     int ro;
  73     uint8_t cmd;
  74     uint8_t status;
  75     uint16_t ident0;
  76     uint16_t ident1;
  77     uint16_t ident2;
  78     uint16_t ident3;
  79     uint8_t cfi_len;
  80     uint8_t cfi_table[0x52];
  81     hwaddr counter;
  82     unsigned int writeblock_size;
  83     QEMUTimer *timer;
  84     MemoryRegion mem;
  85     char *name;
  86     void *storage;
  87 };
  88
  89 static void pflash_timer (void *opaque)
  90 {
  91     pflash_t *pfl = opaque;
  92
  93     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
  94     /* Reset flash */
  95     pfl->status ^= 0x80;
  96     if (pfl->bypass) {
  97         pfl->wcycle = 2;
  98     } else {
  99         memory_region_rom_device_set_readable(&pfl->mem, true);
 100         pfl->wcycle = 0;
 101     }
 102     pfl->cmd = 0;
 103 }
 104
 105 static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
 106                              int width, int be)
 107 {
 108     hwaddr boff;
 109     uint32_t ret;
 110     uint8_t *p;
 111
 112     ret = -1;
 113     boff = offset & 0xFF; /* why this here ?? */
 114
 115     if (pfl->width == 2)
 116         boff = boff >> 1;
 117     else if (pfl->width == 4)
 118         boff = boff >> 2;
 119
 120 #if 0
 121     DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
 122             __func__, offset, pfl->cmd, width);
 123 #endif
 124     switch (pfl->cmd) {
 125     case 0x00:
 126         /* Flash area read */
 127         p = pfl->storage;
 128         switch (width) {
 129         case 1:
 130             ret = p[offset];
 131             DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
 132                     __func__, offset, ret);
 133             break;
 134         case 2:
 135             if (be) {
 136                 ret = p[offset] << 8;
 137                 ret |= p[offset + 1];
 138             } else {
 139                 ret = p[offset];
 140                 ret |= p[offset + 1] << 8;
 141             }
 142             DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
 143                     __func__, offset, ret);
 144             break;
 145         case 4:
 146             if (be) {
 147                 ret = p[offset] << 24;
 148                 ret |= p[offset + 1] << 16;
 149                 ret |= p[offset + 2] << 8;
 150                 ret |= p[offset + 3];
 151             } else {
 152                 ret = p[offset];
 153                 ret |= p[offset + 1] << 8;
 154                 ret |= p[offset + 2] << 16;
 155                 ret |= p[offset + 3] << 24;
 156             }
 157             DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
 158                     __func__, offset, ret);
 159             break;
 160         default:
 161             DPRINTF("BUG in %s\n", __func__);
 162         }
 163
 164         break;
 165     case 0x10: /* Single byte program */
 166     case 0x20: /* Block erase */
 167     case 0x28: /* Block erase */
 168     case 0x40: /* single byte program */
 169     case 0x50: /* Clear status register */
 170     case 0x60: /* Block /un)lock */
 171     case 0x70: /* Status Register */
 172     case 0xe8: /* Write block */
 173         /* Status register read */
 174         ret = pfl->status;
 175         DPRINTF("%s: status %x\n", __func__, ret);
 176         break;
 177     case 0x90:
 178         switch (boff) {
 179         case 0:
 180             ret = pfl->ident0 << 8 | pfl->ident1;
 181             DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
 182             break;
 183         case 1:
 184             ret = pfl->ident2 << 8 | pfl->ident3;
 185             DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
 186             break;
 187         default:
 188             DPRINTF("%s: Read Device Information boff=%x\n", __func__,
 189                     (unsigned)boff);
 190             ret = 0;
 191             break;
 192         }
 193         break;
 194     case 0x98: /* Query mode */
 195         if (boff > pfl->cfi_len)
 196             ret = 0;
 197         else
 198             ret = pfl->cfi_table[boff];
 199         break;
 200     default:
 201         /* This should never happen : reset state & treat it as a read */
 202         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 203         pfl->wcycle = 0;
 204         pfl->cmd = 0;
 205     }
 206     return ret;
 207 }
 208
 209 /* update flash content on disk */
 210 static void pflash_update(pflash_t *pfl, int offset,
 211                           int size)
 212 {
 213     int offset_end;
 214     if (pfl->bs) {
 215         offset_end = offset + size;
 216         /* round to sectors */
 217         offset = offset >> 9;
 218         offset_end = (offset_end + 511) >> 9;
 219         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 220                    offset_end - offset);
 221     }
 222 }
 223
 224 static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
 225                                      uint32_t value, int width, int be)
 226 {
 227     uint8_t *p = pfl->storage;
 228
 229     DPRINTF("%s: block write offset " TARGET_FMT_plx
 230             " value %x counter " TARGET_FMT_plx "\n",
 231             __func__, offset, value, pfl->counter);
 232     switch (width) {
 233     case 1:
 234         p[offset] = value;
 235         break;
 236     case 2:
 237         if (be) {
 238             p[offset] = value >> 8;
 239             p[offset + 1] = value;
 240         } else {
 241             p[offset] = value;
 242             p[offset + 1] = value >> 8;
 243         }
 244         break;
 245     case 4:
 246         if (be) {
 247             p[offset] = value >> 24;
 248             p[offset + 1] = value >> 16;
 249             p[offset + 2] = value >> 8;
 250             p[offset + 3] = value;
 251         } else {
 252             p[offset] = value;
 253             p[offset + 1] = value >> 8;
 254             p[offset + 2] = value >> 16;
 255             p[offset + 3] = value >> 24;
 256         }
 257         break;
 258     }
 259
 260 }
 261
 262 static void pflash_write(pflash_t *pfl, hwaddr offset,
 263                          uint32_t value, int width, int be)
 264 {
 265     uint8_t *p;
 266     uint8_t cmd;
 267
 268     cmd = value;
 269
 270     DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
 271             __func__, offset, value, width, pfl->wcycle);
 272
 273     if (!pfl->wcycle) {
 274         /* Set the device in I/O access mode */
 275         memory_region_rom_device_set_readable(&pfl->mem, false);
 276     }
 277
 278     switch (pfl->wcycle) {
 279     case 0:
 280         /* read mode */
 281         switch (cmd) {
 282         case 0x00: /* ??? */
 283             goto reset_flash;
 284         case 0x10: /* Single Byte Program */
 285         case 0x40: /* Single Byte Program */
 286             DPRINTF("%s: Single Byte Program\n", __func__);
 287             break;
 288         case 0x20: /* Block erase */
 289             p = pfl->storage;
 290             offset &= ~(pfl->sector_len - 1);
 291
 292             DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n",
 293                     __func__, offset, (unsigned)pfl->sector_len);
 294
 295             if (!pfl->ro) {
 296                 memset(p + offset, 0xff, pfl->sector_len);
 297                 pflash_update(pfl, offset, pfl->sector_len);
 298             } else {
 299                 pfl->status |= 0x20; /* Block erase error */
 300             }
 301             pfl->status |= 0x80; /* Ready! */
 302             break;
 303         case 0x50: /* Clear status bits */
 304             DPRINTF("%s: Clear status bits\n", __func__);
 305             pfl->status = 0x0;
 306             goto reset_flash;
 307         case 0x60: /* Block (un)lock */
 308             DPRINTF("%s: Block unlock\n", __func__);
 309             break;
 310         case 0x70: /* Status Register */
 311             DPRINTF("%s: Read status register\n", __func__);
 312             pfl->cmd = cmd;
 313             return;
 314         case 0x90: /* Read Device ID */
 315             DPRINTF("%s: Read Device information\n", __func__);
 316             pfl->cmd = cmd;
 317             return;
 318         case 0x98: /* CFI query */
 319             DPRINTF("%s: CFI query\n", __func__);
 320             break;
 321         case 0xe8: /* Write to buffer */
 322             DPRINTF("%s: Write to buffer\n", __func__);
 323             pfl->status |= 0x80; /* Ready! */
 324             break;
 325         case 0xf0: /* Probe for AMD flash */
 326             DPRINTF("%s: Probe for AMD flash\n", __func__);
 327             goto reset_flash;
 328         case 0xff: /* Read array mode */
 329             DPRINTF("%s: Read array mode\n", __func__);
 330             goto reset_flash;
 331         default:
 332             goto error_flash;
 333         }
 334         pfl->wcycle++;
 335         pfl->cmd = cmd;
 336         break;
 337     case 1:
 338         switch (pfl->cmd) {
 339         case 0x10: /* Single Byte Program */
 340         case 0x40: /* Single Byte Program */
 341             DPRINTF("%s: Single Byte Program\n", __func__);
 342             if (!pfl->ro) {
 343                 pflash_data_write(pfl, offset, value, width, be);
 344                 pflash_update(pfl, offset, width);
 345             } else {
 346                 pfl->status |= 0x10; /* Programming error */
 347             }
 348             pfl->status |= 0x80; /* Ready! */
 349             pfl->wcycle = 0;
 350         break;
 351         case 0x20: /* Block erase */
 352         case 0x28:
 353             if (cmd == 0xd0) { /* confirm */
 354                 pfl->wcycle = 0;
 355                 pfl->status |= 0x80;
 356             } else if (cmd == 0xff) { /* read array mode */
 357                 goto reset_flash;
 358             } else
 359                 goto error_flash;
 360
 361             break;
 362         case 0xe8:
 363             DPRINTF("%s: block write of %x bytes\n", __func__, value);
 364             pfl->counter = value;
 365             pfl->wcycle++;
 366             break;
 367         case 0x60:
 368             if (cmd == 0xd0) {
 369                 pfl->wcycle = 0;
 370                 pfl->status |= 0x80;
 371             } else if (cmd == 0x01) {
 372                 pfl->wcycle = 0;
 373                 pfl->status |= 0x80;
 374             } else if (cmd == 0xff) {
 375                 goto reset_flash;
 376             } else {
 377                 DPRINTF("%s: Unknown (un)locking command\n", __func__);
 378                 goto reset_flash;
 379             }
 380             break;
 381         case 0x98:
 382             if (cmd == 0xff) {
 383                 goto reset_flash;
 384             } else {
 385                 DPRINTF("%s: leaving query mode\n", __func__);
 386             }
 387             break;
 388         default:
 389             goto error_flash;
 390         }
 391         break;
 392     case 2:
 393         switch (pfl->cmd) {
 394         case 0xe8: /* Block write */
 395             if (!pfl->ro) {
 396                 pflash_data_write(pfl, offset, value, width, be);
 397             } else {
 398                 pfl->status |= 0x10; /* Programming error */
 399             }
 400
 401             pfl->status |= 0x80;
 402
 403             if (!pfl->counter) {
 404                 hwaddr mask = pfl->writeblock_size - 1;
 405                 mask = ~mask;
 406
 407                 DPRINTF("%s: block write finished\n", __func__);
 408                 pfl->wcycle++;
 409                 if (!pfl->ro) {
 410                     /* Flush the entire write buffer onto backing storage.  */
 411                     pflash_update(pfl, offset & mask, pfl->writeblock_size);
 412                 } else {
 413                     pfl->status |= 0x10; /* Programming error */
 414                 }
 415             }
 416
 417             pfl->counter--;
 418             break;
 419         default:
 420             goto error_flash;
 421         }
 422         break;
 423     case 3: /* Confirm mode */
 424         switch (pfl->cmd) {
 425         case 0xe8: /* Block write */
 426             if (cmd == 0xd0) {
 427                 pfl->wcycle = 0;
 428                 pfl->status |= 0x80;
 429             } else {
 430                 DPRINTF("%s: unknown command for \"write block\"\n", __func__);
 431                 PFLASH_BUG("Write block confirm");
 432                 goto reset_flash;
 433             }
 434             break;
 435         default:
 436             goto error_flash;
 437         }
 438         break;
 439     default:
 440         /* Should never happen */
 441         DPRINTF("%s: invalid write state\n",  __func__);
 442         goto reset_flash;
 443     }
 444     return;
 445
 446  error_flash:
 447     qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
 448                   "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
 449                   "\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
 450
 451  reset_flash:
 452     memory_region_rom_device_set_readable(&pfl->mem, true);
 453
 454     pfl->bypass = 0;
 455     pfl->wcycle = 0;
 456     pfl->cmd = 0;
 457 }
 458
 459
 460 static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
 461 {
 462     return pflash_read(opaque, addr, 1, 1);
 463 }
 464
 465 static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
 466 {
 467     return pflash_read(opaque, addr, 1, 0);
 468 }
 469
 470 static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
 471 {
 472     pflash_t *pfl = opaque;
 473
 474     return pflash_read(pfl, addr, 2, 1);
 475 }
 476
 477 static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
 478 {
 479     pflash_t *pfl = opaque;
 480
 481     return pflash_read(pfl, addr, 2, 0);
 482 }
 483
 484 static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
 485 {
 486     pflash_t *pfl = opaque;
 487
 488     return pflash_read(pfl, addr, 4, 1);
 489 }
 490
 491 static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
 492 {
 493     pflash_t *pfl = opaque;
 494
 495     return pflash_read(pfl, addr, 4, 0);
 496 }
 497
 498 static void pflash_writeb_be(void *opaque, hwaddr addr,
 499                              uint32_t value)
 500 {
 501     pflash_write(opaque, addr, value, 1, 1);
 502 }
 503
 504 static void pflash_writeb_le(void *opaque, hwaddr addr,
 505                              uint32_t value)
 506 {
 507     pflash_write(opaque, addr, value, 1, 0);
 508 }
 509
 510 static void pflash_writew_be(void *opaque, hwaddr addr,
 511                              uint32_t value)
 512 {
 513     pflash_t *pfl = opaque;
 514
 515     pflash_write(pfl, addr, value, 2, 1);
 516 }
 517
 518 static void pflash_writew_le(void *opaque, hwaddr addr,
 519                              uint32_t value)
 520 {
 521     pflash_t *pfl = opaque;
 522
 523     pflash_write(pfl, addr, value, 2, 0);
 524 }
 525
 526 static void pflash_writel_be(void *opaque, hwaddr addr,
 527                              uint32_t value)
 528 {
 529     pflash_t *pfl = opaque;
 530
 531     pflash_write(pfl, addr, value, 4, 1);
 532 }
 533
 534 static void pflash_writel_le(void *opaque, hwaddr addr,
 535                              uint32_t value)
 536 {
 537     pflash_t *pfl = opaque;
 538
 539     pflash_write(pfl, addr, value, 4, 0);
 540 }
 541
 542 static const MemoryRegionOps pflash_cfi01_ops_be = {
 543     .old_mmio = {
 544         .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
 545         .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
 546     },
 547     .endianness = DEVICE_NATIVE_ENDIAN,
 548 };
 549
 550 static const MemoryRegionOps pflash_cfi01_ops_le = {
 551     .old_mmio = {
 552         .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
 553         .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
 554     },
 555     .endianness = DEVICE_NATIVE_ENDIAN,
 556 };
 557
 558 static int pflash_cfi01_init(SysBusDevice *dev)
 559 {
 560     pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev);
 561     uint64_t total_len;
 562     int ret;
 563
 564     total_len = pfl->sector_len * pfl->nb_blocs;
 565
 566     /* XXX: to be fixed */
 567 #if 0
 568     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 569         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 570         return NULL;
 571 #endif
 572
 573     memory_region_init_rom_device(
 574         &pfl->mem, pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
 575         pfl->name, total_len);
 576     vmstate_register_ram(&pfl->mem, DEVICE(pfl));
 577     pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
 578     sysbus_init_mmio(dev, &pfl->mem);
 579
 580     if (pfl->bs) {
 581         /* read the initial flash content */
 582         ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
 583
 584         if (ret < 0) {
 585             vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
 586             memory_region_destroy(&pfl->mem);
 587             return 1;
 588         }
 589     }
 590
 591     if (pfl->bs) {
 592         pfl->ro = bdrv_is_read_only(pfl->bs);
 593     } else {
 594         pfl->ro = 0;
 595     }
 596
 597     pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
 598     pfl->wcycle = 0;
 599     pfl->cmd = 0;
 600     pfl->status = 0;
 601     /* Hardcoded CFI table */
 602     pfl->cfi_len = 0x52;
 603     /* Standard "QRY" string */
 604     pfl->cfi_table[0x10] = 'Q';
 605     pfl->cfi_table[0x11] = 'R';
 606     pfl->cfi_table[0x12] = 'Y';
 607     /* Command set (Intel) */
 608     pfl->cfi_table[0x13] = 0x01;
 609     pfl->cfi_table[0x14] = 0x00;
 610     /* Primary extended table address (none) */
 611     pfl->cfi_table[0x15] = 0x31;
 612     pfl->cfi_table[0x16] = 0x00;
 613     /* Alternate command set (none) */
 614     pfl->cfi_table[0x17] = 0x00;
 615     pfl->cfi_table[0x18] = 0x00;
 616     /* Alternate extended table (none) */
 617     pfl->cfi_table[0x19] = 0x00;
 618     pfl->cfi_table[0x1A] = 0x00;
 619     /* Vcc min */
 620     pfl->cfi_table[0x1B] = 0x45;
 621     /* Vcc max */
 622     pfl->cfi_table[0x1C] = 0x55;
 623     /* Vpp min (no Vpp pin) */
 624     pfl->cfi_table[0x1D] = 0x00;
 625     /* Vpp max (no Vpp pin) */
 626     pfl->cfi_table[0x1E] = 0x00;
 627     /* Reserved */
 628     pfl->cfi_table[0x1F] = 0x07;
 629     /* Timeout for min size buffer write */
 630     pfl->cfi_table[0x20] = 0x07;
 631     /* Typical timeout for block erase */
 632     pfl->cfi_table[0x21] = 0x0a;
 633     /* Typical timeout for full chip erase (4096 ms) */
 634     pfl->cfi_table[0x22] = 0x00;
 635     /* Reserved */
 636     pfl->cfi_table[0x23] = 0x04;
 637     /* Max timeout for buffer write */
 638     pfl->cfi_table[0x24] = 0x04;
 639     /* Max timeout for block erase */
 640     pfl->cfi_table[0x25] = 0x04;
 641     /* Max timeout for chip erase */
 642     pfl->cfi_table[0x26] = 0x00;
 643     /* Device size */
 644     pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
 645     /* Flash device interface (8 & 16 bits) */
 646     pfl->cfi_table[0x28] = 0x02;
 647     pfl->cfi_table[0x29] = 0x00;
 648     /* Max number of bytes in multi-bytes write */
 649     if (pfl->width == 1) {
 650         pfl->cfi_table[0x2A] = 0x08;
 651     } else {
 652         pfl->cfi_table[0x2A] = 0x0B;
 653     }
 654     pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
 655
 656     pfl->cfi_table[0x2B] = 0x00;
 657     /* Number of erase block regions (uniform) */
 658     pfl->cfi_table[0x2C] = 0x01;
 659     /* Erase block region 1 */
 660     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
 661     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
 662     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
 663     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
 664
 665     /* Extended */
 666     pfl->cfi_table[0x31] = 'P';
 667     pfl->cfi_table[0x32] = 'R';
 668     pfl->cfi_table[0x33] = 'I';
 669
 670     pfl->cfi_table[0x34] = '1';
 671     pfl->cfi_table[0x35] = '0';
 672
 673     pfl->cfi_table[0x36] = 0x00;
 674     pfl->cfi_table[0x37] = 0x00;
 675     pfl->cfi_table[0x38] = 0x00;
 676     pfl->cfi_table[0x39] = 0x00;
 677
 678     pfl->cfi_table[0x3a] = 0x00;
 679
 680     pfl->cfi_table[0x3b] = 0x00;
 681     pfl->cfi_table[0x3c] = 0x00;
 682
 683     pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
 684
 685     return 0;
 686 }
 687
 688 static Property pflash_cfi01_properties[] = {
 689     DEFINE_PROP_DRIVE("drive", struct pflash_t, bs),
 690     DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
 691     DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0),
 692     DEFINE_PROP_UINT8("width", struct pflash_t, width, 0),
 693     DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0),
 694     DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
 695     DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
 696     DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),
 697     DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),
 698     DEFINE_PROP_STRING("name", struct pflash_t, name),
 699     DEFINE_PROP_END_OF_LIST(),
 700 };
 701
 702 static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
 703 {
 704     DeviceClass *dc = DEVICE_CLASS(klass);
 705     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 706
 707     k->init = pflash_cfi01_init;
 708     dc->props = pflash_cfi01_properties;
 709 }
 710
 711
 712 static const TypeInfo pflash_cfi01_info = {
 713     .name           = "cfi.pflash01",
 714     .parent         = TYPE_SYS_BUS_DEVICE,
 715     .instance_size  = sizeof(struct pflash_t),
 716     .class_init     = pflash_cfi01_class_init,
 717 };
 718
 719 static void pflash_cfi01_register_types(void)
 720 {
 721     type_register_static(&pflash_cfi01_info);
 722 }
 723
 724 type_init(pflash_cfi01_register_types)
 725
 726 pflash_t *pflash_cfi01_register(hwaddr base,
 727                                 DeviceState *qdev, const char *name,
 728                                 hwaddr size,
 729                                 BlockDriverState *bs,
 730                                 uint32_t sector_len, int nb_blocs, int width,
 731                                 uint16_t id0, uint16_t id1,
 732                                 uint16_t id2, uint16_t id3, int be)
 733 {
 734     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 735     SysBusDevice *busdev = SYS_BUS_DEVICE(dev);
 736     pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev),
 737                                                     "cfi.pflash01");
 738
 739     if (bs && qdev_prop_set_drive(dev, "drive", bs)) {
 740         abort();
 741     }
 742     qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
 743     qdev_prop_set_uint64(dev, "sector-length", sector_len);
 744     qdev_prop_set_uint8(dev, "width", width);
 745     qdev_prop_set_uint8(dev, "big-endian", !!be);
 746     qdev_prop_set_uint16(dev, "id0", id0);
 747     qdev_prop_set_uint16(dev, "id1", id1);
 748     qdev_prop_set_uint16(dev, "id2", id2);
 749     qdev_prop_set_uint16(dev, "id3", id3);
 750     qdev_prop_set_string(dev, "name", name);
 751     qdev_init_nofail(dev);
 752
 753     sysbus_mmio_map(busdev, 0, base);
 754     return pfl;
 755 }
 756
 757 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)
 758 {
 759     return &fl->mem;
 760 }