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git.proxmox.com Git - mirror_qemu.git/blob - hw/pflash_cfi02.c
2 * CFI parallel flash with AMD command set emulation
4 * Copyright (c) 2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
29 * - unlock bypass command
32 * It does not support flash interleaving.
33 * It does not implement boot blocs with reduced size
34 * It does not implement software data protection as found in many real chips
35 * It does not implement erase suspend/resume commands
36 * It does not implement multiple sectors erase
41 #include "qemu-timer.h"
44 //#define PFLASH_DEBUG
46 #define DPRINTF(fmt, args...) \
48 printf("PFLASH: " fmt , ##args); \
51 #define DPRINTF(fmt, args...) do { } while (0)
56 target_phys_addr_t base
;
61 int wcycle
; /* if 0, the flash is read normally */
67 uint16_t unlock_addr
[2];
69 uint8_t cfi_table
[0x52];
76 static void pflash_register_memory(pflash_t
*pfl
, int rom_mode
)
78 unsigned long phys_offset
= pfl
->fl_mem
;
82 phys_offset
|= pfl
->off
| IO_MEM_ROMD
;
84 for (i
= 0; i
< pfl
->mappings
; i
++)
85 cpu_register_physical_memory(pfl
->base
+ i
* pfl
->chip_len
,
86 pfl
->chip_len
, phys_offset
);
89 static void pflash_timer (void *opaque
)
91 pflash_t
*pfl
= opaque
;
93 DPRINTF("%s: command %02x done\n", __func__
, pfl
->cmd
);
99 pflash_register_memory(pfl
, 1);
105 static uint32_t pflash_read (pflash_t
*pfl
, uint32_t offset
, int width
)
111 DPRINTF("%s: offset " TARGET_FMT_lx
"\n", __func__
, offset
);
114 offset
&= pfl
->chip_len
- 1;
115 boff
= offset
& 0xFF;
118 else if (pfl
->width
== 4)
122 /* This should never happen : reset state & treat it as a read*/
123 DPRINTF("%s: unknown command state: %x\n", __func__
, pfl
->cmd
);
127 /* We accept reads during second unlock sequence... */
130 /* Flash area read */
135 // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
138 #if defined(TARGET_WORDS_BIGENDIAN)
139 ret
= p
[offset
] << 8;
140 ret
|= p
[offset
+ 1];
143 ret
|= p
[offset
+ 1] << 8;
145 // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
148 #if defined(TARGET_WORDS_BIGENDIAN)
149 ret
= p
[offset
] << 24;
150 ret
|= p
[offset
+ 1] << 16;
151 ret
|= p
[offset
+ 2] << 8;
152 ret
|= p
[offset
+ 3];
155 ret
|= p
[offset
+ 1] << 8;
156 ret
|= p
[offset
+ 2] << 16;
157 ret
|= p
[offset
+ 3] << 24;
159 // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
168 ret
= pfl
->ident
[boff
& 0x01];
171 ret
= 0x00; /* Pretend all sectors are unprotected */
175 if (pfl
->ident
[2 + (boff
& 0x01)] == (uint8_t)-1)
177 ret
= pfl
->ident
[2 + (boff
& 0x01)];
182 DPRINTF("%s: ID " TARGET_FMT_ld
" %x\n", __func__
, boff
, ret
);
187 /* Status register read */
189 DPRINTF("%s: status %x\n", __func__
, ret
);
195 if (boff
> pfl
->cfi_len
)
198 ret
= pfl
->cfi_table
[boff
];
205 /* update flash content on disk */
206 static void pflash_update(pflash_t
*pfl
, int offset
,
211 offset_end
= offset
+ size
;
212 /* round to sectors */
213 offset
= offset
>> 9;
214 offset_end
= (offset_end
+ 511) >> 9;
215 bdrv_write(pfl
->bs
, offset
, pfl
->storage
+ (offset
<< 9),
216 offset_end
- offset
);
220 static void pflash_write (pflash_t
*pfl
, uint32_t offset
, uint32_t value
,
227 /* WARNING: when the memory area is in ROMD mode, the offset is a
228 ram offset, not a physical address */
230 if (pfl
->cmd
!= 0xA0 && cmd
== 0xF0) {
232 DPRINTF("%s: flash reset asked (%02x %02x)\n",
233 __func__
, pfl
->cmd
, cmd
);
237 DPRINTF("%s: offset " TARGET_FMT_lx
" %08x %d %d\n", __func__
,
238 offset
, value
, width
, pfl
->wcycle
);
239 if (pfl
->wcycle
== 0)
240 offset
-= (uint32_t)(long)pfl
->storage
;
243 offset
&= pfl
->chip_len
- 1;
245 DPRINTF("%s: offset " TARGET_FMT_lx
" %08x %d\n", __func__
,
246 offset
, value
, width
);
247 boff
= offset
& (pfl
->sector_len
- 1);
250 else if (pfl
->width
== 4)
252 switch (pfl
->wcycle
) {
254 /* Set the device in I/O access mode */
255 pflash_register_memory(pfl
, 0);
256 /* We're in read mode */
258 if (boff
== 0x55 && cmd
== 0x98) {
260 /* Enter CFI query mode */
265 if (boff
!= pfl
->unlock_addr
[0] || cmd
!= 0xAA) {
266 DPRINTF("%s: unlock0 failed " TARGET_FMT_lx
" %02x %04x\n",
267 __func__
, boff
, cmd
, pfl
->unlock_addr
[0]);
270 DPRINTF("%s: unlock sequence started\n", __func__
);
273 /* We started an unlock sequence */
275 if (boff
!= pfl
->unlock_addr
[1] || cmd
!= 0x55) {
276 DPRINTF("%s: unlock1 failed " TARGET_FMT_lx
" %02x\n", __func__
,
280 DPRINTF("%s: unlock sequence done\n", __func__
);
283 /* We finished an unlock sequence */
284 if (!pfl
->bypass
&& boff
!= pfl
->unlock_addr
[0]) {
285 DPRINTF("%s: command failed " TARGET_FMT_lx
" %02x\n", __func__
,
297 DPRINTF("%s: starting command %02x\n", __func__
, cmd
);
300 DPRINTF("%s: unknown command %02x\n", __func__
, cmd
);
307 /* We need another unlock sequence */
310 DPRINTF("%s: write data offset " TARGET_FMT_lx
" %08x %d\n",
311 __func__
, offset
, value
, width
);
316 pflash_update(pfl
, offset
, 1);
319 #if defined(TARGET_WORDS_BIGENDIAN)
320 p
[offset
] &= value
>> 8;
321 p
[offset
+ 1] &= value
;
324 p
[offset
+ 1] &= value
>> 8;
326 pflash_update(pfl
, offset
, 2);
329 #if defined(TARGET_WORDS_BIGENDIAN)
330 p
[offset
] &= value
>> 24;
331 p
[offset
+ 1] &= value
>> 16;
332 p
[offset
+ 2] &= value
>> 8;
333 p
[offset
+ 3] &= value
;
336 p
[offset
+ 1] &= value
>> 8;
337 p
[offset
+ 2] &= value
>> 16;
338 p
[offset
+ 3] &= value
>> 24;
340 pflash_update(pfl
, offset
, 4);
343 pfl
->status
= 0x00 | ~(value
& 0x80);
344 /* Let's pretend write is immediate */
349 if (pfl
->bypass
&& cmd
== 0x00) {
350 /* Unlock bypass reset */
353 /* We can enter CFI query mode from autoselect mode */
354 if (boff
== 0x55 && cmd
== 0x98)
358 DPRINTF("%s: invalid write for command %02x\n",
365 /* Ignore writes while flash data write is occuring */
366 /* As we suppose write is immediate, this should never happen */
371 /* Should never happen */
372 DPRINTF("%s: invalid command state %02x (wc 4)\n",
380 if (boff
!= pfl
->unlock_addr
[0]) {
381 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx
"\n",
386 DPRINTF("%s: start chip erase\n", __func__
);
387 memset(pfl
->storage
, 0xFF, pfl
->chip_len
);
389 pflash_update(pfl
, 0, pfl
->chip_len
);
390 /* Let's wait 5 seconds before chip erase is done */
391 qemu_mod_timer(pfl
->timer
,
392 qemu_get_clock(vm_clock
) + (ticks_per_sec
* 5));
397 offset
&= ~(pfl
->sector_len
- 1);
398 DPRINTF("%s: start sector erase at " TARGET_FMT_lx
"\n", __func__
,
400 memset(p
+ offset
, 0xFF, pfl
->sector_len
);
401 pflash_update(pfl
, offset
, pfl
->sector_len
);
403 /* Let's wait 1/2 second before sector erase is done */
404 qemu_mod_timer(pfl
->timer
,
405 qemu_get_clock(vm_clock
) + (ticks_per_sec
/ 2));
408 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__
, cmd
);
416 /* Ignore writes during chip erase */
419 /* Ignore writes during sector erase */
422 /* Should never happen */
423 DPRINTF("%s: invalid command state %02x (wc 6)\n",
428 case 7: /* Special value for CFI queries */
429 DPRINTF("%s: invalid write in CFI query mode\n", __func__
);
432 /* Should never happen */
433 DPRINTF("%s: invalid write state (wc 7)\n", __func__
);
442 pflash_register_memory(pfl
, 1);
455 static uint32_t pflash_readb (void *opaque
, target_phys_addr_t addr
)
457 return pflash_read(opaque
, addr
, 1);
460 static uint32_t pflash_readw (void *opaque
, target_phys_addr_t addr
)
462 pflash_t
*pfl
= opaque
;
464 return pflash_read(pfl
, addr
, 2);
467 static uint32_t pflash_readl (void *opaque
, target_phys_addr_t addr
)
469 pflash_t
*pfl
= opaque
;
471 return pflash_read(pfl
, addr
, 4);
474 static void pflash_writeb (void *opaque
, target_phys_addr_t addr
,
477 pflash_write(opaque
, addr
, value
, 1);
480 static void pflash_writew (void *opaque
, target_phys_addr_t addr
,
483 pflash_t
*pfl
= opaque
;
485 pflash_write(pfl
, addr
, value
, 2);
488 static void pflash_writel (void *opaque
, target_phys_addr_t addr
,
491 pflash_t
*pfl
= opaque
;
493 pflash_write(pfl
, addr
, value
, 4);
496 static CPUWriteMemoryFunc
*pflash_write_ops
[] = {
502 static CPUReadMemoryFunc
*pflash_read_ops
[] = {
508 /* Count trailing zeroes of a 32 bits quantity */
509 static int ctz32 (uint32_t n
)
534 #if 0 /* This is not necessary as n is never 0 */
542 pflash_t
*pflash_cfi02_register(target_phys_addr_t base
, ram_addr_t off
,
543 BlockDriverState
*bs
, uint32_t sector_len
,
544 int nb_blocs
, int nb_mappings
, int width
,
545 uint16_t id0
, uint16_t id1
,
546 uint16_t id2
, uint16_t id3
,
547 uint16_t unlock_addr0
, uint16_t unlock_addr1
)
552 chip_len
= sector_len
* nb_blocs
;
553 /* XXX: to be fixed */
555 if (total_len
!= (8 * 1024 * 1024) && total_len
!= (16 * 1024 * 1024) &&
556 total_len
!= (32 * 1024 * 1024) && total_len
!= (64 * 1024 * 1024))
559 pfl
= qemu_mallocz(sizeof(pflash_t
));
562 pfl
->storage
= phys_ram_base
+ off
;
563 pfl
->fl_mem
= cpu_register_io_memory(0, pflash_read_ops
, pflash_write_ops
,
567 pfl
->chip_len
= chip_len
;
568 pfl
->mappings
= nb_mappings
;
569 pflash_register_memory(pfl
, 1);
572 /* read the initial flash content */
573 bdrv_read(pfl
->bs
, 0, pfl
->storage
, chip_len
>> 9);
575 #if 0 /* XXX: there should be a bit to set up read-only,
576 * the same way the hardware does (with WP pin).
582 pfl
->timer
= qemu_new_timer(vm_clock
, pflash_timer
, pfl
);
583 pfl
->sector_len
= sector_len
;
592 pfl
->unlock_addr
[0] = unlock_addr0
;
593 pfl
->unlock_addr
[1] = unlock_addr1
;
594 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
596 /* Standard "QRY" string */
597 pfl
->cfi_table
[0x10] = 'Q';
598 pfl
->cfi_table
[0x11] = 'R';
599 pfl
->cfi_table
[0x12] = 'Y';
600 /* Command set (AMD/Fujitsu) */
601 pfl
->cfi_table
[0x13] = 0x02;
602 pfl
->cfi_table
[0x14] = 0x00;
603 /* Primary extended table address (none) */
604 pfl
->cfi_table
[0x15] = 0x00;
605 pfl
->cfi_table
[0x16] = 0x00;
606 /* Alternate command set (none) */
607 pfl
->cfi_table
[0x17] = 0x00;
608 pfl
->cfi_table
[0x18] = 0x00;
609 /* Alternate extended table (none) */
610 pfl
->cfi_table
[0x19] = 0x00;
611 pfl
->cfi_table
[0x1A] = 0x00;
613 pfl
->cfi_table
[0x1B] = 0x27;
615 pfl
->cfi_table
[0x1C] = 0x36;
616 /* Vpp min (no Vpp pin) */
617 pfl
->cfi_table
[0x1D] = 0x00;
618 /* Vpp max (no Vpp pin) */
619 pfl
->cfi_table
[0x1E] = 0x00;
621 pfl
->cfi_table
[0x1F] = 0x07;
622 /* Timeout for min size buffer write (16 µs) */
623 pfl
->cfi_table
[0x20] = 0x04;
624 /* Typical timeout for block erase (512 ms) */
625 pfl
->cfi_table
[0x21] = 0x09;
626 /* Typical timeout for full chip erase (4096 ms) */
627 pfl
->cfi_table
[0x22] = 0x0C;
629 pfl
->cfi_table
[0x23] = 0x01;
630 /* Max timeout for buffer write */
631 pfl
->cfi_table
[0x24] = 0x04;
632 /* Max timeout for block erase */
633 pfl
->cfi_table
[0x25] = 0x0A;
634 /* Max timeout for chip erase */
635 pfl
->cfi_table
[0x26] = 0x0D;
637 pfl
->cfi_table
[0x27] = ctz32(chip_len
) + 1;
638 /* Flash device interface (8 & 16 bits) */
639 pfl
->cfi_table
[0x28] = 0x02;
640 pfl
->cfi_table
[0x29] = 0x00;
641 /* Max number of bytes in multi-bytes write */
642 /* XXX: disable buffered write as it's not supported */
643 // pfl->cfi_table[0x2A] = 0x05;
644 pfl
->cfi_table
[0x2A] = 0x00;
645 pfl
->cfi_table
[0x2B] = 0x00;
646 /* Number of erase block regions (uniform) */
647 pfl
->cfi_table
[0x2C] = 0x01;
648 /* Erase block region 1 */
649 pfl
->cfi_table
[0x2D] = nb_blocs
- 1;
650 pfl
->cfi_table
[0x2E] = (nb_blocs
- 1) >> 8;
651 pfl
->cfi_table
[0x2F] = sector_len
>> 8;
652 pfl
->cfi_table
[0x30] = sector_len
>> 16;