hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33
  34 /*
  35  * I440FX chipset data sheet.
  36  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  37  */
  38
  39 typedef PCIHostState I440FXState;
  40
  41 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  42 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  43 #define XEN_PIIX_NUM_PIRQS      128ULL
  44 #define PIIX_PIRQC              0x60
  45
  46 typedef struct PIIX3State {
  47     PCIDevice dev;
  48
  49     /*
  50      * bitmap to track pic levels.
  51      * The pic level is the logical OR of all the PCI irqs mapped to it
  52      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  53      *
  54      * PIRQ is mapped to PIC pins, we track it by
  55      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  56      * pic_irq * PIIX_NUM_PIRQS + pirq
  57      */
  58 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  59 #error "unable to encode pic state in 64bit in pic_levels."
  60 #endif
  61     uint64_t pic_levels;
  62
  63     qemu_irq *pic;
  64
  65     /* This member isn't used. Just for save/load compatibility */
  66     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  67 } PIIX3State;
  68
  69 typedef struct PAMMemoryRegion {
  70     MemoryRegion mem;
  71     bool initialized;
  72 } PAMMemoryRegion;
  73
  74 struct PCII440FXState {
  75     PCIDevice dev;
  76     MemoryRegion *system_memory;
  77     MemoryRegion *pci_address_space;
  78     MemoryRegion *ram_memory;
  79     MemoryRegion pci_hole;
  80     MemoryRegion pci_hole_64bit;
  81     PAMMemoryRegion pam_regions[13];
  82     MemoryRegion smram_region;
  83     uint8_t smm_enabled;
  84 };
  85
  86
  87 #define I440FX_PAM      0x59
  88 #define I440FX_PAM_SIZE 7
  89 #define I440FX_SMRAM    0x72
  90
  91 static void piix3_set_irq(void *opaque, int pirq, int level);
  92 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
  93 static void piix3_write_config_xen(PCIDevice *dev,
  94                                uint32_t address, uint32_t val, int len);
  95
  96 /* return the global irq number corresponding to a given device irq
  97    pin. We could also use the bus number to have a more precise
  98    mapping. */
  99 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 100 {
 101     int slot_addend;
 102     slot_addend = (pci_dev->devfn >> 3) - 1;
 103     return (pci_intx + slot_addend) & 3;
 104 }
 105
 106 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
 107                        PAMMemoryRegion *mem)
 108 {
 109     if (mem->initialized) {
 110         memory_region_del_subregion(d->system_memory, &mem->mem);
 111         memory_region_destroy(&mem->mem);
 112     }
 113
 114     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
 115     switch(r) {
 116     case 3:
 117         /* RAM */
 118         memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
 119                                  start, end - start);
 120         break;
 121     case 1:
 122         /* ROM (XXX: not quite correct) */
 123         memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
 124                                  start, end - start);
 125         memory_region_set_readonly(&mem->mem, true);
 126         break;
 127     case 2:
 128     case 0:
 129         /* XXX: should distinguish read/write cases */
 130         memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
 131                                  start, end - start);
 132         break;
 133     }
 134     memory_region_add_subregion_overlap(d->system_memory,
 135                                         start, &mem->mem, 1);
 136     mem->initialized = true;
 137 }
 138
 139 static void i440fx_update_memory_mappings(PCII440FXState *d)
 140 {
 141     int i, r;
 142     uint32_t smram;
 143     bool smram_enabled;
 144
 145     memory_region_transaction_begin();
 146     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
 147                &d->pam_regions[0]);
 148     for(i = 0; i < 12; i++) {
 149         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 150         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
 151                    &d->pam_regions[i+1]);
 152     }
 153     smram = d->dev.config[I440FX_SMRAM];
 154     smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
 155     memory_region_set_enabled(&d->smram_region, !smram_enabled);
 156     memory_region_transaction_commit();
 157 }
 158
 159 static void i440fx_set_smm(int val, void *arg)
 160 {
 161     PCII440FXState *d = arg;
 162
 163     val = (val != 0);
 164     if (d->smm_enabled != val) {
 165         d->smm_enabled = val;
 166         i440fx_update_memory_mappings(d);
 167     }
 168 }
 169
 170
 171 static void i440fx_write_config(PCIDevice *dev,
 172                                 uint32_t address, uint32_t val, int len)
 173 {
 174     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 175
 176     /* XXX: implement SMRAM.D_LOCK */
 177     pci_default_write_config(dev, address, val, len);
 178     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 179         range_covers_byte(address, len, I440FX_SMRAM)) {
 180         i440fx_update_memory_mappings(d);
 181     }
 182 }
 183
 184 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 185 {
 186     PCII440FXState *d = opaque;
 187     int ret, i;
 188
 189     ret = pci_device_load(&d->dev, f);
 190     if (ret < 0)
 191         return ret;
 192     i440fx_update_memory_mappings(d);
 193     qemu_get_8s(f, &d->smm_enabled);
 194
 195     if (version_id == 2) {
 196         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 197             qemu_get_be32(f); /* dummy load for compatibility */
 198         }
 199     }
 200
 201     return 0;
 202 }
 203
 204 static int i440fx_post_load(void *opaque, int version_id)
 205 {
 206     PCII440FXState *d = opaque;
 207
 208     i440fx_update_memory_mappings(d);
 209     return 0;
 210 }
 211
 212 static const VMStateDescription vmstate_i440fx = {
 213     .name = "I440FX",
 214     .version_id = 3,
 215     .minimum_version_id = 3,
 216     .minimum_version_id_old = 1,
 217     .load_state_old = i440fx_load_old,
 218     .post_load = i440fx_post_load,
 219     .fields      = (VMStateField []) {
 220         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 221         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 222         VMSTATE_END_OF_LIST()
 223     }
 224 };
 225
 226 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 227 {
 228     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 229
 230     memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
 231                           "pci-conf-idx", 4);
 232     sysbus_add_io(dev, 0xcf8, &s->conf_mem);
 233     sysbus_init_ioports(&s->busdev, 0xcf8, 4);
 234
 235     memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
 236                           "pci-conf-data", 4);
 237     sysbus_add_io(dev, 0xcfc, &s->data_mem);
 238     sysbus_init_ioports(&s->busdev, 0xcfc, 4);
 239
 240     return 0;
 241 }
 242
 243 static int i440fx_initfn(PCIDevice *dev)
 244 {
 245     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 246
 247     d->dev.config[I440FX_SMRAM] = 0x02;
 248
 249     cpu_smm_register(&i440fx_set_smm, d);
 250     return 0;
 251 }
 252
 253 static PCIBus *i440fx_common_init(const char *device_name,
 254                                   PCII440FXState **pi440fx_state,
 255                                   int *piix3_devfn,
 256                                   ISABus **isa_bus, qemu_irq *pic,
 257                                   MemoryRegion *address_space_mem,
 258                                   MemoryRegion *address_space_io,
 259                                   ram_addr_t ram_size,
 260                                   target_phys_addr_t pci_hole_start,
 261                                   target_phys_addr_t pci_hole_size,
 262                                   target_phys_addr_t pci_hole64_start,
 263                                   target_phys_addr_t pci_hole64_size,
 264                                   MemoryRegion *pci_address_space,
 265                                   MemoryRegion *ram_memory)
 266 {
 267     DeviceState *dev;
 268     PCIBus *b;
 269     PCIDevice *d;
 270     PCIHostState *s;
 271     PIIX3State *piix3;
 272     PCII440FXState *f;
 273
 274     dev = qdev_create(NULL, "i440FX-pcihost");
 275     s = PCI_HOST_BRIDGE(dev);
 276     s->address_space = address_space_mem;
 277     b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
 278                     address_space_io, 0);
 279     s->bus = b;
 280     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 281     qdev_init_nofail(dev);
 282
 283     d = pci_create_simple(b, 0, device_name);
 284     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 285     f = *pi440fx_state;
 286     f->system_memory = address_space_mem;
 287     f->pci_address_space = pci_address_space;
 288     f->ram_memory = ram_memory;
 289     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
 290                              pci_hole_start, pci_hole_size);
 291     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 292     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
 293                              f->pci_address_space,
 294                              pci_hole64_start, pci_hole64_size);
 295     if (pci_hole64_size) {
 296         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 297                                     &f->pci_hole_64bit);
 298     }
 299     memory_region_init_alias(&f->smram_region, "smram-region",
 300                              f->pci_address_space, 0xa0000, 0x20000);
 301     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 302                                         &f->smram_region, 1);
 303     memory_region_set_enabled(&f->smram_region, false);
 304
 305     /* Xen supports additional interrupt routes from the PCI devices to
 306      * the IOAPIC: the four pins of each PCI device on the bus are also
 307      * connected to the IOAPIC directly.
 308      * These additional routes can be discovered through ACPI. */
 309     if (xen_enabled()) {
 310         piix3 = DO_UPCAST(PIIX3State, dev,
 311                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 312         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 313                 piix3, XEN_PIIX_NUM_PIRQS);
 314     } else {
 315         piix3 = DO_UPCAST(PIIX3State, dev,
 316                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 317         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 318                 PIIX_NUM_PIRQS);
 319         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 320     }
 321     piix3->pic = pic;
 322     *isa_bus = DO_UPCAST(ISABus, qbus,
 323                          qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
 324
 325     *piix3_devfn = piix3->dev.devfn;
 326
 327     ram_size = ram_size / 8 / 1024 / 1024;
 328     if (ram_size > 255)
 329         ram_size = 255;
 330     (*pi440fx_state)->dev.config[0x57]=ram_size;
 331
 332     i440fx_update_memory_mappings(f);
 333
 334     return b;
 335 }
 336
 337 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 338                     ISABus **isa_bus, qemu_irq *pic,
 339                     MemoryRegion *address_space_mem,
 340                     MemoryRegion *address_space_io,
 341                     ram_addr_t ram_size,
 342                     target_phys_addr_t pci_hole_start,
 343                     target_phys_addr_t pci_hole_size,
 344                     target_phys_addr_t pci_hole64_start,
 345                     target_phys_addr_t pci_hole64_size,
 346                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 347
 348 {
 349     PCIBus *b;
 350
 351     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
 352                            address_space_mem, address_space_io, ram_size,
 353                            pci_hole_start, pci_hole_size,
 354                            pci_hole64_start, pci_hole64_size,
 355                            pci_memory, ram_memory);
 356     return b;
 357 }
 358
 359 /* PIIX3 PCI to ISA bridge */
 360 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 361 {
 362     qemu_set_irq(piix3->pic[pic_irq],
 363                  !!(piix3->pic_levels &
 364                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 365                      (pic_irq * PIIX_NUM_PIRQS))));
 366 }
 367
 368 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 369 {
 370     int pic_irq;
 371     uint64_t mask;
 372
 373     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 374     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 375         return;
 376     }
 377
 378     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 379     piix3->pic_levels &= ~mask;
 380     piix3->pic_levels |= mask * !!level;
 381
 382     piix3_set_irq_pic(piix3, pic_irq);
 383 }
 384
 385 static void piix3_set_irq(void *opaque, int pirq, int level)
 386 {
 387     PIIX3State *piix3 = opaque;
 388     piix3_set_irq_level(piix3, pirq, level);
 389 }
 390
 391 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 392 {
 393     PIIX3State *piix3 = opaque;
 394     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 395     PCIINTxRoute route;
 396
 397     if (irq < PIIX_NUM_PIC_IRQS) {
 398         route.mode = PCI_INTX_ENABLED;
 399         route.irq = irq;
 400     } else {
 401         route.mode = PCI_INTX_DISABLED;
 402         route.irq = -1;
 403     }
 404     return route;
 405 }
 406
 407 /* irq routing is changed. so rebuild bitmap */
 408 static void piix3_update_irq_levels(PIIX3State *piix3)
 409 {
 410     int pirq;
 411
 412     piix3->pic_levels = 0;
 413     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 414         piix3_set_irq_level(piix3, pirq,
 415                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 416     }
 417 }
 418
 419 static void piix3_write_config(PCIDevice *dev,
 420                                uint32_t address, uint32_t val, int len)
 421 {
 422     pci_default_write_config(dev, address, val, len);
 423     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 424         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 425         int pic_irq;
 426
 427         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 428         piix3_update_irq_levels(piix3);
 429         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 430             piix3_set_irq_pic(piix3, pic_irq);
 431         }
 432     }
 433 }
 434
 435 static void piix3_write_config_xen(PCIDevice *dev,
 436                                uint32_t address, uint32_t val, int len)
 437 {
 438     xen_piix_pci_write_config_client(address, val, len);
 439     piix3_write_config(dev, address, val, len);
 440 }
 441
 442 static void piix3_reset(void *opaque)
 443 {
 444     PIIX3State *d = opaque;
 445     uint8_t *pci_conf = d->dev.config;
 446
 447     pci_conf[0x04] = 0x07; // master, memory and I/O
 448     pci_conf[0x05] = 0x00;
 449     pci_conf[0x06] = 0x00;
 450     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 451     pci_conf[0x4c] = 0x4d;
 452     pci_conf[0x4e] = 0x03;
 453     pci_conf[0x4f] = 0x00;
 454     pci_conf[0x60] = 0x80;
 455     pci_conf[0x61] = 0x80;
 456     pci_conf[0x62] = 0x80;
 457     pci_conf[0x63] = 0x80;
 458     pci_conf[0x69] = 0x02;
 459     pci_conf[0x70] = 0x80;
 460     pci_conf[0x76] = 0x0c;
 461     pci_conf[0x77] = 0x0c;
 462     pci_conf[0x78] = 0x02;
 463     pci_conf[0x79] = 0x00;
 464     pci_conf[0x80] = 0x00;
 465     pci_conf[0x82] = 0x00;
 466     pci_conf[0xa0] = 0x08;
 467     pci_conf[0xa2] = 0x00;
 468     pci_conf[0xa3] = 0x00;
 469     pci_conf[0xa4] = 0x00;
 470     pci_conf[0xa5] = 0x00;
 471     pci_conf[0xa6] = 0x00;
 472     pci_conf[0xa7] = 0x00;
 473     pci_conf[0xa8] = 0x0f;
 474     pci_conf[0xaa] = 0x00;
 475     pci_conf[0xab] = 0x00;
 476     pci_conf[0xac] = 0x00;
 477     pci_conf[0xae] = 0x00;
 478
 479     d->pic_levels = 0;
 480 }
 481
 482 static int piix3_post_load(void *opaque, int version_id)
 483 {
 484     PIIX3State *piix3 = opaque;
 485     piix3_update_irq_levels(piix3);
 486     return 0;
 487 }
 488
 489 static void piix3_pre_save(void *opaque)
 490 {
 491     int i;
 492     PIIX3State *piix3 = opaque;
 493
 494     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 495         piix3->pci_irq_levels_vmstate[i] =
 496             pci_bus_get_irq_level(piix3->dev.bus, i);
 497     }
 498 }
 499
 500 static const VMStateDescription vmstate_piix3 = {
 501     .name = "PIIX3",
 502     .version_id = 3,
 503     .minimum_version_id = 2,
 504     .minimum_version_id_old = 2,
 505     .post_load = piix3_post_load,
 506     .pre_save = piix3_pre_save,
 507     .fields      = (VMStateField []) {
 508         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 509         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 510                               PIIX_NUM_PIRQS, 3),
 511         VMSTATE_END_OF_LIST()
 512     }
 513 };
 514
 515 static int piix3_initfn(PCIDevice *dev)
 516 {
 517     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 518
 519     isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
 520     qemu_register_reset(piix3_reset, d);
 521     return 0;
 522 }
 523
 524 static void piix3_class_init(ObjectClass *klass, void *data)
 525 {
 526     DeviceClass *dc = DEVICE_CLASS(klass);
 527     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 528
 529     dc->desc        = "ISA bridge";
 530     dc->vmsd        = &vmstate_piix3;
 531     dc->no_user     = 1,
 532     k->no_hotplug   = 1;
 533     k->init         = piix3_initfn;
 534     k->config_write = piix3_write_config;
 535     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 536     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 537     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 538 }
 539
 540 static const TypeInfo piix3_info = {
 541     .name          = "PIIX3",
 542     .parent        = TYPE_PCI_DEVICE,
 543     .instance_size = sizeof(PIIX3State),
 544     .class_init    = piix3_class_init,
 545 };
 546
 547 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 548 {
 549     DeviceClass *dc = DEVICE_CLASS(klass);
 550     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 551
 552     dc->desc        = "ISA bridge";
 553     dc->vmsd        = &vmstate_piix3;
 554     dc->no_user     = 1;
 555     k->no_hotplug   = 1;
 556     k->init         = piix3_initfn;
 557     k->config_write = piix3_write_config_xen;
 558     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 559     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 560     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 561 };
 562
 563 static const TypeInfo piix3_xen_info = {
 564     .name          = "PIIX3-xen",
 565     .parent        = TYPE_PCI_DEVICE,
 566     .instance_size = sizeof(PIIX3State),
 567     .class_init    = piix3_xen_class_init,
 568 };
 569
 570 static void i440fx_class_init(ObjectClass *klass, void *data)
 571 {
 572     DeviceClass *dc = DEVICE_CLASS(klass);
 573     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 574
 575     k->no_hotplug = 1;
 576     k->init = i440fx_initfn;
 577     k->config_write = i440fx_write_config;
 578     k->vendor_id = PCI_VENDOR_ID_INTEL;
 579     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 580     k->revision = 0x02;
 581     k->class_id = PCI_CLASS_BRIDGE_HOST;
 582     dc->desc = "Host bridge";
 583     dc->no_user = 1;
 584     dc->vmsd = &vmstate_i440fx;
 585 }
 586
 587 static const TypeInfo i440fx_info = {
 588     .name          = "i440FX",
 589     .parent        = TYPE_PCI_DEVICE,
 590     .instance_size = sizeof(PCII440FXState),
 591     .class_init    = i440fx_class_init,
 592 };
 593
 594 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 595 {
 596     DeviceClass *dc = DEVICE_CLASS(klass);
 597     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 598
 599     k->init = i440fx_pcihost_initfn;
 600     dc->fw_name = "pci";
 601     dc->no_user = 1;
 602 }
 603
 604 static const TypeInfo i440fx_pcihost_info = {
 605     .name          = "i440FX-pcihost",
 606     .parent        = TYPE_PCI_HOST_BRIDGE,
 607     .instance_size = sizeof(I440FXState),
 608     .class_init    = i440fx_pcihost_class_init,
 609 };
 610
 611 static void i440fx_register_types(void)
 612 {
 613     type_register_static(&i440fx_info);
 614     type_register_static(&piix3_info);
 615     type_register_static(&piix3_xen_info);
 616     type_register_static(&i440fx_pcihost_info);
 617 }
 618
 619 type_init(i440fx_register_types)