hw/pl061.c

   1 /*
   2  * Arm PrimeCell PL061 General Purpose IO with additional
   3  * Luminary Micro Stellaris bits.
   4  *
   5  * Copyright (c) 2007 CodeSourcery.
   6  * Written by Paul Brook
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "sysbus.h"
  12
  13 //#define DEBUG_PL061 1
  14
  15 #ifdef DEBUG_PL061
  16 #define DPRINTF(fmt, ...) \
  17 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
  18 #define BADF(fmt, ...) \
  19 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  20 #else
  21 #define DPRINTF(fmt, ...) do {} while(0)
  22 #define BADF(fmt, ...) \
  23 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
  24 #endif
  25
  26 static const uint8_t pl061_id[12] =
  27   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  28 static const uint8_t pl061_id_luminary[12] =
  29   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
  30
  31 typedef struct {
  32     SysBusDevice busdev;
  33     uint32_t locked;
  34     uint32_t data;
  35     uint32_t old_data;
  36     uint32_t dir;
  37     uint32_t isense;
  38     uint32_t ibe;
  39     uint32_t iev;
  40     uint32_t im;
  41     uint32_t istate;
  42     uint32_t afsel;
  43     uint32_t dr2r;
  44     uint32_t dr4r;
  45     uint32_t dr8r;
  46     uint32_t odr;
  47     uint32_t pur;
  48     uint32_t pdr;
  49     uint32_t slr;
  50     uint32_t den;
  51     uint32_t cr;
  52     uint32_t float_high;
  53     qemu_irq irq;
  54     qemu_irq out[8];
  55     const unsigned char *id;
  56 } pl061_state;
  57
  58 static const VMStateDescription vmstate_pl061 = {
  59     .name = "pl061",
  60     .version_id = 1,
  61     .minimum_version_id = 1,
  62     .fields = (VMStateField[]) {
  63         VMSTATE_UINT32(locked, pl061_state),
  64         VMSTATE_UINT32(data, pl061_state),
  65         VMSTATE_UINT32(old_data, pl061_state),
  66         VMSTATE_UINT32(dir, pl061_state),
  67         VMSTATE_UINT32(isense, pl061_state),
  68         VMSTATE_UINT32(ibe, pl061_state),
  69         VMSTATE_UINT32(iev, pl061_state),
  70         VMSTATE_UINT32(im, pl061_state),
  71         VMSTATE_UINT32(istate, pl061_state),
  72         VMSTATE_UINT32(afsel, pl061_state),
  73         VMSTATE_UINT32(dr2r, pl061_state),
  74         VMSTATE_UINT32(dr4r, pl061_state),
  75         VMSTATE_UINT32(dr8r, pl061_state),
  76         VMSTATE_UINT32(odr, pl061_state),
  77         VMSTATE_UINT32(pur, pl061_state),
  78         VMSTATE_UINT32(pdr, pl061_state),
  79         VMSTATE_UINT32(slr, pl061_state),
  80         VMSTATE_UINT32(den, pl061_state),
  81         VMSTATE_UINT32(cr, pl061_state),
  82         VMSTATE_UINT32(float_high, pl061_state),
  83         VMSTATE_END_OF_LIST()
  84     }
  85 };
  86
  87 static void pl061_update(pl061_state *s)
  88 {
  89     uint8_t changed;
  90     uint8_t mask;
  91     uint8_t out;
  92     int i;
  93
  94     /* Outputs float high.  */
  95     /* FIXME: This is board dependent.  */
  96     out = (s->data & s->dir) | ~s->dir;
  97     changed = s->old_data ^ out;
  98     if (!changed)
  99         return;
 100
 101     s->old_data = out;
 102     for (i = 0; i < 8; i++) {
 103         mask = 1 << i;
 104         if ((changed & mask) && s->out) {
 105             DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
 106             qemu_set_irq(s->out[i], (out & mask) != 0);
 107         }
 108     }
 109
 110     /* FIXME: Implement input interrupts.  */
 111 }
 112
 113 static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
 114 {
 115     pl061_state *s = (pl061_state *)opaque;
 116
 117     if (offset >= 0xfd0 && offset < 0x1000) {
 118         return s->id[(offset - 0xfd0) >> 2];
 119     }
 120     if (offset < 0x400) {
 121         return s->data & (offset >> 2);
 122     }
 123     switch (offset) {
 124     case 0x400: /* Direction */
 125         return s->dir;
 126     case 0x404: /* Interrupt sense */
 127         return s->isense;
 128     case 0x408: /* Interrupt both edges */
 129         return s->ibe;
 130     case 0x40c: /* Interrupt event */
 131         return s->iev;
 132     case 0x410: /* Interrupt mask */
 133         return s->im;
 134     case 0x414: /* Raw interrupt status */
 135         return s->istate;
 136     case 0x418: /* Masked interrupt status */
 137         return s->istate | s->im;
 138     case 0x420: /* Alternate function select */
 139         return s->afsel;
 140     case 0x500: /* 2mA drive */
 141         return s->dr2r;
 142     case 0x504: /* 4mA drive */
 143         return s->dr4r;
 144     case 0x508: /* 8mA drive */
 145         return s->dr8r;
 146     case 0x50c: /* Open drain */
 147         return s->odr;
 148     case 0x510: /* Pull-up */
 149         return s->pur;
 150     case 0x514: /* Pull-down */
 151         return s->pdr;
 152     case 0x518: /* Slew rate control */
 153         return s->slr;
 154     case 0x51c: /* Digital enable */
 155         return s->den;
 156     case 0x520: /* Lock */
 157         return s->locked;
 158     case 0x524: /* Commit */
 159         return s->cr;
 160     default:
 161         hw_error("pl061_read: Bad offset %x\n", (int)offset);
 162         return 0;
 163     }
 164 }
 165
 166 static void pl061_write(void *opaque, target_phys_addr_t offset,
 167                         uint32_t value)
 168 {
 169     pl061_state *s = (pl061_state *)opaque;
 170     uint8_t mask;
 171
 172     if (offset < 0x400) {
 173         mask = (offset >> 2) & s->dir;
 174         s->data = (s->data & ~mask) | (value & mask);
 175         pl061_update(s);
 176         return;
 177     }
 178     switch (offset) {
 179     case 0x400: /* Direction */
 180         s->dir = value & 0xff;
 181         break;
 182     case 0x404: /* Interrupt sense */
 183         s->isense = value & 0xff;
 184         break;
 185     case 0x408: /* Interrupt both edges */
 186         s->ibe = value & 0xff;
 187         break;
 188     case 0x40c: /* Interrupt event */
 189         s->iev = value & 0xff;
 190         break;
 191     case 0x410: /* Interrupt mask */
 192         s->im = value & 0xff;
 193         break;
 194     case 0x41c: /* Interrupt clear */
 195         s->istate &= ~value;
 196         break;
 197     case 0x420: /* Alternate function select */
 198         mask = s->cr;
 199         s->afsel = (s->afsel & ~mask) | (value & mask);
 200         break;
 201     case 0x500: /* 2mA drive */
 202         s->dr2r = value & 0xff;
 203         break;
 204     case 0x504: /* 4mA drive */
 205         s->dr4r = value & 0xff;
 206         break;
 207     case 0x508: /* 8mA drive */
 208         s->dr8r = value & 0xff;
 209         break;
 210     case 0x50c: /* Open drain */
 211         s->odr = value & 0xff;
 212         break;
 213     case 0x510: /* Pull-up */
 214         s->pur = value & 0xff;
 215         break;
 216     case 0x514: /* Pull-down */
 217         s->pdr = value & 0xff;
 218         break;
 219     case 0x518: /* Slew rate control */
 220         s->slr = value & 0xff;
 221         break;
 222     case 0x51c: /* Digital enable */
 223         s->den = value & 0xff;
 224         break;
 225     case 0x520: /* Lock */
 226         s->locked = (value != 0xacce551);
 227         break;
 228     case 0x524: /* Commit */
 229         if (!s->locked)
 230             s->cr = value & 0xff;
 231         break;
 232     default:
 233         hw_error("pl061_write: Bad offset %x\n", (int)offset);
 234     }
 235     pl061_update(s);
 236 }
 237
 238 static void pl061_reset(pl061_state *s)
 239 {
 240   s->locked = 1;
 241   s->cr = 0xff;
 242 }
 243
 244 static void pl061_set_irq(void * opaque, int irq, int level)
 245 {
 246     pl061_state *s = (pl061_state *)opaque;
 247     uint8_t mask;
 248
 249     mask = 1 << irq;
 250     if ((s->dir & mask) == 0) {
 251         s->data &= ~mask;
 252         if (level)
 253             s->data |= mask;
 254         pl061_update(s);
 255     }
 256 }
 257
 258 static CPUReadMemoryFunc * const pl061_readfn[] = {
 259    pl061_read,
 260    pl061_read,
 261    pl061_read
 262 };
 263
 264 static CPUWriteMemoryFunc * const pl061_writefn[] = {
 265    pl061_write,
 266    pl061_write,
 267    pl061_write
 268 };
 269
 270 static int pl061_init(SysBusDevice *dev, const unsigned char *id)
 271 {
 272     int iomemtype;
 273     pl061_state *s = FROM_SYSBUS(pl061_state, dev);
 274     s->id = id;
 275     iomemtype = cpu_register_io_memory(pl061_readfn,
 276                                        pl061_writefn, s,
 277                                        DEVICE_NATIVE_ENDIAN);
 278     sysbus_init_mmio(dev, 0x1000, iomemtype);
 279     sysbus_init_irq(dev, &s->irq);
 280     qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
 281     qdev_init_gpio_out(&dev->qdev, s->out, 8);
 282     pl061_reset(s);
 283     return 0;
 284 }
 285
 286 static int pl061_init_luminary(SysBusDevice *dev)
 287 {
 288     return pl061_init(dev, pl061_id_luminary);
 289 }
 290
 291 static int pl061_init_arm(SysBusDevice *dev)
 292 {
 293     return pl061_init(dev, pl061_id);
 294 }
 295
 296 static SysBusDeviceInfo pl061_info = {
 297     .init = pl061_init_arm,
 298     .qdev.name = "pl061",
 299     .qdev.size = sizeof(pl061_state),
 300     .qdev.vmsd = &vmstate_pl061,
 301 };
 302
 303 static SysBusDeviceInfo pl061_luminary_info = {
 304     .init = pl061_init_luminary,
 305     .qdev.name = "pl061_luminary",
 306     .qdev.size = sizeof(pl061_state),
 307     .qdev.vmsd = &vmstate_pl061,
 308 };
 309
 310 static void pl061_register_devices(void)
 311 {
 312     sysbus_register_withprop(&pl061_info);
 313     sysbus_register_withprop(&pl061_luminary_info);
 314 }
 315
 316 device_init(pl061_register_devices)