2 * QEMU PowerPC e500-based platforms
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
18 #include "qemu-common.h"
20 #include "e500-ccsr.h"
23 #include "hw/serial.h"
25 #include "hw/boards.h"
29 #include "device_tree.h"
30 #include "hw/openpic.h"
32 #include "hw/loader.h"
34 #include "hw/sysbus.h"
35 #include "exec-memory.h"
36 #include "host-utils.h"
38 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
39 #define UIMAGE_LOAD_BASE 0
40 #define DTC_LOAD_PAD 0x1800000
41 #define DTC_PAD_MASK 0xFFFFF
42 #define INITRD_LOAD_PAD 0x2000000
43 #define INITRD_PAD_MASK 0xFFFFFF
45 #define RAM_SIZES_ALIGN (64UL << 20)
47 /* TODO: parameterize */
48 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL
49 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
50 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
51 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
52 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
53 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
54 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
55 MPC8544_PCI_REGS_OFFSET)
56 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
57 #define MPC8544_PCI_IO 0xE1000000ULL
58 #define MPC8544_UTIL_OFFSET 0xe0000ULL
59 #define MPC8544_SPIN_BASE 0xEF000000ULL
68 static void pci_map_create(void *fdt
, uint32_t *pci_map
, uint32_t mpic
)
71 const uint32_t tmp
[] = {
72 /* IDSEL 0x11 J17 Slot 1 */
73 0x8800, 0x0, 0x0, 0x1, mpic
, 0x2, 0x1,
74 0x8800, 0x0, 0x0, 0x2, mpic
, 0x3, 0x1,
75 0x8800, 0x0, 0x0, 0x3, mpic
, 0x4, 0x1,
76 0x8800, 0x0, 0x0, 0x4, mpic
, 0x1, 0x1,
78 /* IDSEL 0x12 J16 Slot 2 */
79 0x9000, 0x0, 0x0, 0x1, mpic
, 0x3, 0x1,
80 0x9000, 0x0, 0x0, 0x2, mpic
, 0x4, 0x1,
81 0x9000, 0x0, 0x0, 0x3, mpic
, 0x2, 0x1,
82 0x9000, 0x0, 0x0, 0x4, mpic
, 0x1, 0x1,
84 for (i
= 0; i
< (7 * 8); i
++) {
85 pci_map
[i
] = cpu_to_be32(tmp
[i
]);
89 static void dt_serial_create(void *fdt
, unsigned long long offset
,
90 const char *soc
, const char *mpic
,
91 const char *alias
, int idx
, bool defcon
)
95 snprintf(ser
, sizeof(ser
), "%s/serial@%llx", soc
, offset
);
96 qemu_devtree_add_subnode(fdt
, ser
);
97 qemu_devtree_setprop_string(fdt
, ser
, "device_type", "serial");
98 qemu_devtree_setprop_string(fdt
, ser
, "compatible", "ns16550");
99 qemu_devtree_setprop_cells(fdt
, ser
, "reg", offset
, 0x100);
100 qemu_devtree_setprop_cell(fdt
, ser
, "cell-index", idx
);
101 qemu_devtree_setprop_cell(fdt
, ser
, "clock-frequency", 0);
102 qemu_devtree_setprop_cells(fdt
, ser
, "interrupts", 42, 2);
103 qemu_devtree_setprop_phandle(fdt
, ser
, "interrupt-parent", mpic
);
104 qemu_devtree_setprop_string(fdt
, "/aliases", alias
, ser
);
107 qemu_devtree_setprop_string(fdt
, "/chosen", "linux,stdout-path", ser
);
111 static int ppce500_load_device_tree(CPUPPCState
*env
,
112 PPCE500Params
*params
,
118 uint64_t mem_reg_property
[] = { 0, cpu_to_be64(params
->ram_size
) };
121 uint8_t hypercall
[16];
122 uint32_t clock_freq
= 400000000;
123 uint32_t tb_freq
= 400000000;
125 const char *toplevel_compat
= NULL
; /* user override */
126 char compatible_sb
[] = "fsl,mpc8544-immr\0simple-bus";
132 uint32_t pci_map
[7 * 8];
133 uint32_t pci_ranges
[14] =
135 0x2000000, 0x0, 0xc0000000,
143 QemuOpts
*machine_opts
;
144 const char *dtb_file
= NULL
;
146 machine_opts
= qemu_opts_find(qemu_find_opts("machine"), 0);
148 dtb_file
= qemu_opt_get(machine_opts
, "dtb");
149 toplevel_compat
= qemu_opt_get(machine_opts
, "dt_compatible");
154 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, dtb_file
);
159 fdt
= load_device_tree(filename
, &fdt_size
);
166 fdt
= create_device_tree(&fdt_size
);
171 /* Manipulate device tree in memory. */
172 qemu_devtree_setprop_cell(fdt
, "/", "#address-cells", 2);
173 qemu_devtree_setprop_cell(fdt
, "/", "#size-cells", 2);
175 qemu_devtree_add_subnode(fdt
, "/memory");
176 qemu_devtree_setprop_string(fdt
, "/memory", "device_type", "memory");
177 qemu_devtree_setprop(fdt
, "/memory", "reg", mem_reg_property
,
178 sizeof(mem_reg_property
));
180 qemu_devtree_add_subnode(fdt
, "/chosen");
182 ret
= qemu_devtree_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
185 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
188 ret
= qemu_devtree_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
189 (initrd_base
+ initrd_size
));
191 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
195 ret
= qemu_devtree_setprop_string(fdt
, "/chosen", "bootargs",
196 params
->kernel_cmdline
);
198 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
201 /* Read out host's frequencies */
202 clock_freq
= kvmppc_get_clockfreq();
203 tb_freq
= kvmppc_get_tbfreq();
205 /* indicate KVM hypercall interface */
206 qemu_devtree_add_subnode(fdt
, "/hypervisor");
207 qemu_devtree_setprop_string(fdt
, "/hypervisor", "compatible",
209 kvmppc_get_hypercall(env
, hypercall
, sizeof(hypercall
));
210 qemu_devtree_setprop(fdt
, "/hypervisor", "hcall-instructions",
211 hypercall
, sizeof(hypercall
));
214 /* Create CPU nodes */
215 qemu_devtree_add_subnode(fdt
, "/cpus");
216 qemu_devtree_setprop_cell(fdt
, "/cpus", "#address-cells", 1);
217 qemu_devtree_setprop_cell(fdt
, "/cpus", "#size-cells", 0);
219 /* We need to generate the cpu nodes in reverse order, so Linux can pick
220 the first node as boot node and be happy */
221 for (i
= smp_cpus
- 1; i
>= 0; i
--) {
223 uint64_t cpu_release_addr
= MPC8544_SPIN_BASE
+ (i
* 0x20);
225 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
226 if (env
->cpu_index
== i
) {
235 snprintf(cpu_name
, sizeof(cpu_name
), "/cpus/PowerPC,8544@%x", env
->cpu_index
);
236 qemu_devtree_add_subnode(fdt
, cpu_name
);
237 qemu_devtree_setprop_cell(fdt
, cpu_name
, "clock-frequency", clock_freq
);
238 qemu_devtree_setprop_cell(fdt
, cpu_name
, "timebase-frequency", tb_freq
);
239 qemu_devtree_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
240 qemu_devtree_setprop_cell(fdt
, cpu_name
, "reg", env
->cpu_index
);
241 qemu_devtree_setprop_cell(fdt
, cpu_name
, "d-cache-line-size",
242 env
->dcache_line_size
);
243 qemu_devtree_setprop_cell(fdt
, cpu_name
, "i-cache-line-size",
244 env
->icache_line_size
);
245 qemu_devtree_setprop_cell(fdt
, cpu_name
, "d-cache-size", 0x8000);
246 qemu_devtree_setprop_cell(fdt
, cpu_name
, "i-cache-size", 0x8000);
247 qemu_devtree_setprop_cell(fdt
, cpu_name
, "bus-frequency", 0);
248 if (env
->cpu_index
) {
249 qemu_devtree_setprop_string(fdt
, cpu_name
, "status", "disabled");
250 qemu_devtree_setprop_string(fdt
, cpu_name
, "enable-method", "spin-table");
251 qemu_devtree_setprop_u64(fdt
, cpu_name
, "cpu-release-addr",
254 qemu_devtree_setprop_string(fdt
, cpu_name
, "status", "okay");
258 qemu_devtree_add_subnode(fdt
, "/aliases");
259 /* XXX These should go into their respective devices' code */
260 snprintf(soc
, sizeof(soc
), "/soc@%llx", MPC8544_CCSRBAR_BASE
);
261 qemu_devtree_add_subnode(fdt
, soc
);
262 qemu_devtree_setprop_string(fdt
, soc
, "device_type", "soc");
263 qemu_devtree_setprop(fdt
, soc
, "compatible", compatible_sb
,
264 sizeof(compatible_sb
));
265 qemu_devtree_setprop_cell(fdt
, soc
, "#address-cells", 1);
266 qemu_devtree_setprop_cell(fdt
, soc
, "#size-cells", 1);
267 qemu_devtree_setprop_cells(fdt
, soc
, "ranges", 0x0,
268 MPC8544_CCSRBAR_BASE
>> 32, MPC8544_CCSRBAR_BASE
,
269 MPC8544_CCSRBAR_SIZE
);
270 /* XXX should contain a reasonable value */
271 qemu_devtree_setprop_cell(fdt
, soc
, "bus-frequency", 0);
273 snprintf(mpic
, sizeof(mpic
), "%s/pic@%llx", soc
, MPC8544_MPIC_REGS_OFFSET
);
274 qemu_devtree_add_subnode(fdt
, mpic
);
275 qemu_devtree_setprop_string(fdt
, mpic
, "device_type", "open-pic");
276 qemu_devtree_setprop_string(fdt
, mpic
, "compatible", "chrp,open-pic");
277 qemu_devtree_setprop_cells(fdt
, mpic
, "reg", MPC8544_MPIC_REGS_OFFSET
,
279 qemu_devtree_setprop_cell(fdt
, mpic
, "#address-cells", 0);
280 qemu_devtree_setprop_cell(fdt
, mpic
, "#interrupt-cells", 2);
281 mpic_ph
= qemu_devtree_alloc_phandle(fdt
);
282 qemu_devtree_setprop_cell(fdt
, mpic
, "phandle", mpic_ph
);
283 qemu_devtree_setprop_cell(fdt
, mpic
, "linux,phandle", mpic_ph
);
284 qemu_devtree_setprop(fdt
, mpic
, "interrupt-controller", NULL
, 0);
287 * We have to generate ser1 first, because Linux takes the first
288 * device it finds in the dt as serial output device. And we generate
289 * devices in reverse order to the dt.
291 dt_serial_create(fdt
, MPC8544_SERIAL1_REGS_OFFSET
,
292 soc
, mpic
, "serial1", 1, false);
293 dt_serial_create(fdt
, MPC8544_SERIAL0_REGS_OFFSET
,
294 soc
, mpic
, "serial0", 0, true);
296 snprintf(gutil
, sizeof(gutil
), "%s/global-utilities@%llx", soc
,
297 MPC8544_UTIL_OFFSET
);
298 qemu_devtree_add_subnode(fdt
, gutil
);
299 qemu_devtree_setprop_string(fdt
, gutil
, "compatible", "fsl,mpc8544-guts");
300 qemu_devtree_setprop_cells(fdt
, gutil
, "reg", MPC8544_UTIL_OFFSET
, 0x1000);
301 qemu_devtree_setprop(fdt
, gutil
, "fsl,has-rstcr", NULL
, 0);
303 snprintf(pci
, sizeof(pci
), "/pci@%llx", MPC8544_PCI_REGS_BASE
);
304 qemu_devtree_add_subnode(fdt
, pci
);
305 qemu_devtree_setprop_cell(fdt
, pci
, "cell-index", 0);
306 qemu_devtree_setprop_string(fdt
, pci
, "compatible", "fsl,mpc8540-pci");
307 qemu_devtree_setprop_string(fdt
, pci
, "device_type", "pci");
308 qemu_devtree_setprop_cells(fdt
, pci
, "interrupt-map-mask", 0xf800, 0x0,
310 pci_map_create(fdt
, pci_map
, qemu_devtree_get_phandle(fdt
, mpic
));
311 qemu_devtree_setprop(fdt
, pci
, "interrupt-map", pci_map
, sizeof(pci_map
));
312 qemu_devtree_setprop_phandle(fdt
, pci
, "interrupt-parent", mpic
);
313 qemu_devtree_setprop_cells(fdt
, pci
, "interrupts", 24, 2);
314 qemu_devtree_setprop_cells(fdt
, pci
, "bus-range", 0, 255);
315 for (i
= 0; i
< 14; i
++) {
316 pci_ranges
[i
] = cpu_to_be32(pci_ranges
[i
]);
318 qemu_devtree_setprop(fdt
, pci
, "ranges", pci_ranges
, sizeof(pci_ranges
));
319 qemu_devtree_setprop_cells(fdt
, pci
, "reg", MPC8544_PCI_REGS_BASE
>> 32,
320 MPC8544_PCI_REGS_BASE
, 0, 0x1000);
321 qemu_devtree_setprop_cell(fdt
, pci
, "clock-frequency", 66666666);
322 qemu_devtree_setprop_cell(fdt
, pci
, "#interrupt-cells", 1);
323 qemu_devtree_setprop_cell(fdt
, pci
, "#size-cells", 2);
324 qemu_devtree_setprop_cell(fdt
, pci
, "#address-cells", 3);
325 qemu_devtree_setprop_string(fdt
, "/aliases", "pci0", pci
);
327 params
->fixup_devtree(params
, fdt
);
329 if (toplevel_compat
) {
330 qemu_devtree_setprop(fdt
, "/", "compatible", toplevel_compat
,
331 strlen(toplevel_compat
) + 1);
335 qemu_devtree_dumpdtb(fdt
, fdt_size
);
336 ret
= rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE
, fdt
, fdt_size
, addr
);
348 /* Create -kernel TLB entries for BookE. */
349 static inline hwaddr
booke206_page_size_to_tlb(uint64_t size
)
351 return 63 - clz64(size
>> 10);
354 static void mmubooke_create_initial_mapping(CPUPPCState
*env
)
356 struct boot_info
*bi
= env
->load_info
;
357 ppcmas_tlb_t
*tlb
= booke206_get_tlbm(env
, 1, 0, 0);
361 /* Our initial TLB entry needs to cover everything from 0 to
362 the device tree top */
363 dt_end
= bi
->dt_base
+ bi
->dt_size
;
364 ps
= booke206_page_size_to_tlb(dt_end
) + 1;
366 /* e500v2 can only do even TLB size bits */
369 size
= (ps
<< MAS1_TSIZE_SHIFT
);
370 tlb
->mas1
= MAS1_VALID
| size
;
373 tlb
->mas7_3
|= MAS3_UR
| MAS3_UW
| MAS3_UX
| MAS3_SR
| MAS3_SW
| MAS3_SX
;
375 env
->tlb_dirty
= true;
378 static void ppce500_cpu_reset_sec(void *opaque
)
380 PowerPCCPU
*cpu
= opaque
;
381 CPUPPCState
*env
= &cpu
->env
;
385 /* Secondary CPU starts in halted state for now. Needs to change when
386 implementing non-kernel boot. */
388 env
->exception_index
= EXCP_HLT
;
391 static void ppce500_cpu_reset(void *opaque
)
393 PowerPCCPU
*cpu
= opaque
;
394 CPUPPCState
*env
= &cpu
->env
;
395 struct boot_info
*bi
= env
->load_info
;
399 /* Set initial guest state. */
401 env
->gpr
[1] = (16<<20) - 8;
402 env
->gpr
[3] = bi
->dt_base
;
403 env
->nip
= bi
->entry
;
404 mmubooke_create_initial_mapping(env
);
407 void ppce500_init(PPCE500Params
*params
)
409 MemoryRegion
*address_space_mem
= get_system_memory();
410 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
412 CPUPPCState
*env
= NULL
;
414 uint64_t elf_lowaddr
;
416 hwaddr loadaddr
=UIMAGE_LOAD_BASE
;
417 target_long kernel_size
=0;
418 target_ulong dt_base
= 0;
419 target_ulong initrd_base
= 0;
420 target_long initrd_size
=0;
422 unsigned int pci_irq_nrs
[4] = {1, 2, 3, 4};
423 qemu_irq
**irqs
, *mpic
;
425 CPUPPCState
*firstenv
= NULL
;
426 MemoryRegion
*ccsr_addr_space
;
428 PPCE500CCSRState
*ccsr
;
431 if (params
->cpu_model
== NULL
) {
432 params
->cpu_model
= "e500v2_v30";
435 irqs
= g_malloc0(smp_cpus
* sizeof(qemu_irq
*));
436 irqs
[0] = g_malloc0(smp_cpus
* sizeof(qemu_irq
) * OPENPIC_OUTPUT_NB
);
437 for (i
= 0; i
< smp_cpus
; i
++) {
441 cpu
= cpu_ppc_init(params
->cpu_model
);
443 fprintf(stderr
, "Unable to initialize CPU!\n");
452 irqs
[i
] = irqs
[0] + (i
* OPENPIC_OUTPUT_NB
);
453 input
= (qemu_irq
*)env
->irq_inputs
;
454 irqs
[i
][OPENPIC_OUTPUT_INT
] = input
[PPCE500_INPUT_INT
];
455 irqs
[i
][OPENPIC_OUTPUT_CINT
] = input
[PPCE500_INPUT_CINT
];
456 env
->spr
[SPR_BOOKE_PIR
] = env
->cpu_index
= i
;
457 env
->mpic_cpu_base
= MPC8544_CCSRBAR_BASE
+
458 MPC8544_MPIC_REGS_OFFSET
+ 0x20000;
460 ppc_booke_timers_init(env
, 400000000, PPC_TIMER_E500
);
462 /* Register reset handler */
465 struct boot_info
*boot_info
;
466 boot_info
= g_malloc0(sizeof(struct boot_info
));
467 qemu_register_reset(ppce500_cpu_reset
, cpu
);
468 env
->load_info
= boot_info
;
471 qemu_register_reset(ppce500_cpu_reset_sec
, cpu
);
477 /* Fixup Memory size on a alignment boundary */
478 ram_size
&= ~(RAM_SIZES_ALIGN
- 1);
480 /* Register Memory */
481 memory_region_init_ram(ram
, "mpc8544ds.ram", ram_size
);
482 vmstate_register_ram_global(ram
);
483 memory_region_add_subregion(address_space_mem
, 0, ram
);
485 dev
= qdev_create(NULL
, "e500-ccsr");
486 object_property_add_child(qdev_get_machine(), "e500-ccsr",
488 qdev_init_nofail(dev
);
490 ccsr_addr_space
= &ccsr
->ccsr_space
;
491 memory_region_add_subregion(address_space_mem
, MPC8544_CCSRBAR_BASE
,
495 mpic
= g_new(qemu_irq
, 256);
496 dev
= qdev_create(NULL
, "openpic");
497 qdev_prop_set_uint32(dev
, "nb_cpus", smp_cpus
);
498 qdev_prop_set_uint32(dev
, "model", OPENPIC_MODEL_FSL_MPIC_20
);
499 qdev_init_nofail(dev
);
500 s
= sysbus_from_qdev(dev
);
503 for (i
= 0; i
< smp_cpus
; i
++) {
504 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
505 sysbus_connect_irq(s
, k
++, irqs
[i
][j
]);
509 for (i
= 0; i
< 256; i
++) {
510 mpic
[i
] = qdev_get_gpio_in(dev
, i
);
513 memory_region_add_subregion(ccsr_addr_space
, MPC8544_MPIC_REGS_OFFSET
,
518 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL0_REGS_OFFSET
,
520 serial_hds
[0], DEVICE_BIG_ENDIAN
);
524 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL1_REGS_OFFSET
,
526 serial_hds
[1], DEVICE_BIG_ENDIAN
);
529 /* General Utility device */
530 dev
= qdev_create(NULL
, "mpc8544-guts");
531 qdev_init_nofail(dev
);
532 s
= SYS_BUS_DEVICE(dev
);
533 memory_region_add_subregion(ccsr_addr_space
, MPC8544_UTIL_OFFSET
,
534 sysbus_mmio_get_region(s
, 0));
537 dev
= qdev_create(NULL
, "e500-pcihost");
538 qdev_init_nofail(dev
);
539 s
= SYS_BUS_DEVICE(dev
);
540 sysbus_connect_irq(s
, 0, mpic
[pci_irq_nrs
[0]]);
541 sysbus_connect_irq(s
, 1, mpic
[pci_irq_nrs
[1]]);
542 sysbus_connect_irq(s
, 2, mpic
[pci_irq_nrs
[2]]);
543 sysbus_connect_irq(s
, 3, mpic
[pci_irq_nrs
[3]]);
544 memory_region_add_subregion(ccsr_addr_space
, MPC8544_PCI_REGS_OFFSET
,
545 sysbus_mmio_get_region(s
, 0));
547 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci.0");
549 printf("couldn't create PCI controller!\n");
551 sysbus_mmio_map(sysbus_from_qdev(dev
), 1, MPC8544_PCI_IO
);
554 /* Register network interfaces. */
555 for (i
= 0; i
< nb_nics
; i
++) {
556 pci_nic_init_nofail(&nd_table
[i
], "virtio", NULL
);
560 /* Register spinning region */
561 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE
, NULL
);
564 if (params
->kernel_filename
) {
565 kernel_size
= load_uimage(params
->kernel_filename
, &entry
,
567 if (kernel_size
< 0) {
568 kernel_size
= load_elf(params
->kernel_filename
, NULL
, NULL
,
569 &elf_entry
, &elf_lowaddr
, NULL
, 1,
572 loadaddr
= elf_lowaddr
;
574 /* XXX try again as binary */
575 if (kernel_size
< 0) {
576 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
577 params
->kernel_filename
);
583 if (params
->initrd_filename
) {
584 initrd_base
= (loadaddr
+ kernel_size
+ INITRD_LOAD_PAD
) &
586 initrd_size
= load_image_targphys(params
->initrd_filename
, initrd_base
,
587 ram_size
- initrd_base
);
589 if (initrd_size
< 0) {
590 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
591 params
->initrd_filename
);
596 /* If we're loading a kernel directly, we must load the device tree too. */
597 if (params
->kernel_filename
) {
598 struct boot_info
*boot_info
;
601 dt_base
= (loadaddr
+ kernel_size
+ DTC_LOAD_PAD
) & ~DTC_PAD_MASK
;
602 dt_size
= ppce500_load_device_tree(env
, params
, dt_base
, initrd_base
,
605 fprintf(stderr
, "couldn't load device tree\n");
609 boot_info
= env
->load_info
;
610 boot_info
->entry
= entry
;
611 boot_info
->dt_base
= dt_base
;
612 boot_info
->dt_size
= dt_size
;
620 static int e500_ccsr_initfn(SysBusDevice
*dev
)
622 PPCE500CCSRState
*ccsr
;
625 memory_region_init(&ccsr
->ccsr_space
, "e500-ccsr",
626 MPC8544_CCSRBAR_SIZE
);
630 static void e500_ccsr_class_init(ObjectClass
*klass
, void *data
)
632 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
633 k
->init
= e500_ccsr_initfn
;
636 static const TypeInfo e500_ccsr_info
= {
638 .parent
= TYPE_SYS_BUS_DEVICE
,
639 .instance_size
= sizeof(PPCE500CCSRState
),
640 .class_init
= e500_ccsr_class_init
,
643 static void e500_register_types(void)
645 type_register_static(&e500_ccsr_info
);
648 type_init(e500_register_types
)