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macio: move macio related structures and defines into separate macio.h file
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1
2 /*
3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
4 *
5 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Copyright (c) 2007 Jocelyn Mayer
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
28 #include "hw/hw.h"
29 #include "hw/ppc/ppc.h"
30 #include "mac.h"
31 #include "hw/input/adb.h"
32 #include "hw/timer/m48t59.h"
33 #include "sysemu/sysemu.h"
34 #include "net/net.h"
35 #include "hw/isa/isa.h"
36 #include "hw/pci/pci.h"
37 #include "hw/boards.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/char/escc.h"
40 #include "hw/misc/macio/macio.h"
41 #include "hw/ide.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "qemu/error-report.h"
45 #include "sysemu/kvm.h"
46 #include "kvm_ppc.h"
47 #include "sysemu/block-backend.h"
48 #include "exec/address-spaces.h"
49 #include "qemu/cutils.h"
50
51 #define MAX_IDE_BUS 2
52 #define CFG_ADDR 0xf0000510
53 #define TBFREQ 16600000UL
54 #define CLOCKFREQ 266000000UL
55 #define BUSFREQ 66000000UL
56
57 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
58
59 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
60 Error **errp)
61 {
62 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
63 }
64
65 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
66 {
67 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
68 }
69
70 static void ppc_heathrow_reset(void *opaque)
71 {
72 PowerPCCPU *cpu = opaque;
73
74 cpu_reset(CPU(cpu));
75 }
76
77 static void ppc_heathrow_init(MachineState *machine)
78 {
79 ram_addr_t ram_size = machine->ram_size;
80 const char *kernel_filename = machine->kernel_filename;
81 const char *kernel_cmdline = machine->kernel_cmdline;
82 const char *initrd_filename = machine->initrd_filename;
83 const char *boot_device = machine->boot_order;
84 MemoryRegion *sysmem = get_system_memory();
85 PowerPCCPU *cpu = NULL;
86 CPUPPCState *env = NULL;
87 char *filename;
88 qemu_irq *pic, **heathrow_irqs;
89 int linux_boot, i;
90 MemoryRegion *ram = g_new(MemoryRegion, 1);
91 MemoryRegion *bios = g_new(MemoryRegion, 1);
92 MemoryRegion *isa = g_new(MemoryRegion, 1);
93 uint32_t kernel_base, initrd_base, cmdline_base = 0;
94 int32_t kernel_size, initrd_size;
95 PCIBus *pci_bus;
96 PCIDevice *macio;
97 MACIOIDEState *macio_ide;
98 DeviceState *dev, *pic_dev;
99 SysBusDevice *sbd;
100 BusState *adb_bus;
101 int bios_size, ndrv_size;
102 uint8_t *ndrv_file;
103 uint16_t ppc_boot_device;
104 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
105 void *fw_cfg;
106 uint64_t tbfreq;
107
108 linux_boot = (kernel_filename != NULL);
109
110 /* init CPUs */
111 for (i = 0; i < smp_cpus; i++) {
112 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
113 env = &cpu->env;
114
115 /* Set time-base frequency to 16.6 Mhz */
116 cpu_ppc_tb_init(env, TBFREQ);
117 qemu_register_reset(ppc_heathrow_reset, cpu);
118 }
119
120 /* allocate RAM */
121 if (ram_size > (2047 << 20)) {
122 fprintf(stderr,
123 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
124 ((unsigned int)ram_size / (1 << 20)));
125 exit(1);
126 }
127
128 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
129 ram_size);
130 memory_region_add_subregion(sysmem, 0, ram);
131
132 /* allocate and load BIOS */
133 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
134 &error_fatal);
135
136 if (bios_name == NULL)
137 bios_name = PROM_FILENAME;
138 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
139 memory_region_set_readonly(bios, true);
140 memory_region_add_subregion(sysmem, PROM_ADDR, bios);
141
142 /* Load OpenBIOS (ELF) */
143 if (filename) {
144 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
145 1, PPC_ELF_MACHINE, 0, 0);
146 g_free(filename);
147 } else {
148 bios_size = -1;
149 }
150 if (bios_size < 0 || bios_size > BIOS_SIZE) {
151 error_report("could not load PowerPC bios '%s'", bios_name);
152 exit(1);
153 }
154
155 if (linux_boot) {
156 uint64_t lowaddr = 0;
157 int bswap_needed;
158
159 #ifdef BSWAP_NEEDED
160 bswap_needed = 1;
161 #else
162 bswap_needed = 0;
163 #endif
164 kernel_base = KERNEL_LOAD_ADDR;
165 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
166 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
167 0, 0);
168 if (kernel_size < 0)
169 kernel_size = load_aout(kernel_filename, kernel_base,
170 ram_size - kernel_base, bswap_needed,
171 TARGET_PAGE_SIZE);
172 if (kernel_size < 0)
173 kernel_size = load_image_targphys(kernel_filename,
174 kernel_base,
175 ram_size - kernel_base);
176 if (kernel_size < 0) {
177 error_report("could not load kernel '%s'", kernel_filename);
178 exit(1);
179 }
180 /* load initrd */
181 if (initrd_filename) {
182 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
183 initrd_size = load_image_targphys(initrd_filename, initrd_base,
184 ram_size - initrd_base);
185 if (initrd_size < 0) {
186 error_report("could not load initial ram disk '%s'",
187 initrd_filename);
188 exit(1);
189 }
190 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
191 } else {
192 initrd_base = 0;
193 initrd_size = 0;
194 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
195 }
196 ppc_boot_device = 'm';
197 } else {
198 kernel_base = 0;
199 kernel_size = 0;
200 initrd_base = 0;
201 initrd_size = 0;
202 ppc_boot_device = '\0';
203 for (i = 0; boot_device[i] != '\0'; i++) {
204 /* TOFIX: for now, the second IDE channel is not properly
205 * used by OHW. The Mac floppy disk are not emulated.
206 * For now, OHW cannot boot from the network.
207 */
208 #if 0
209 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
210 ppc_boot_device = boot_device[i];
211 break;
212 }
213 #else
214 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
215 ppc_boot_device = boot_device[i];
216 break;
217 }
218 #endif
219 }
220 if (ppc_boot_device == '\0') {
221 error_report("No valid boot device for G3 Beige machine");
222 exit(1);
223 }
224 }
225
226 /* Register 2 MB of ISA IO space */
227 memory_region_init_alias(isa, NULL, "isa_mmio",
228 get_system_io(), 0, 0x00200000);
229 memory_region_add_subregion(sysmem, 0xfe000000, isa);
230
231 /* XXX: we register only 1 output pin for heathrow PIC */
232 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
233 heathrow_irqs[0] =
234 g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
235 /* Connect the heathrow PIC outputs to the 6xx bus */
236 for (i = 0; i < smp_cpus; i++) {
237 switch (PPC_INPUT(env)) {
238 case PPC_FLAGS_INPUT_6xx:
239 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
240 heathrow_irqs[i][0] =
241 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
242 break;
243 default:
244 error_report("Bus model not supported on OldWorld Mac machine");
245 exit(1);
246 }
247 }
248
249 /* Timebase Frequency */
250 if (kvm_enabled()) {
251 tbfreq = kvmppc_get_tbfreq();
252 } else {
253 tbfreq = TBFREQ;
254 }
255
256 /* init basic PC hardware */
257 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
258 error_report("Only 6xx bus is supported on heathrow machine");
259 exit(1);
260 }
261 pic_dev = heathrow_pic_init(1, heathrow_irqs, &pic);
262 pci_bus = pci_grackle_init(0xfec00000, pic,
263 get_system_memory(),
264 get_system_io());
265 pci_vga_init(pci_bus);
266
267 for (i = 0; i < nb_nics; i++) {
268 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
269 }
270
271 ide_drive_get(hd, ARRAY_SIZE(hd));
272
273 /* MacIO */
274 macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
275 dev = DEVICE(macio);
276 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
277 qdev_connect_gpio_out(dev, 1, pic[0x10]); /* ESCC-B */
278 qdev_connect_gpio_out(dev, 2, pic[0x0F]); /* ESCC-A */
279 qdev_connect_gpio_out(dev, 3, pic[0x0D]); /* IDE-0 */
280 qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE-0 DMA */
281 qdev_connect_gpio_out(dev, 5, pic[0x0E]); /* IDE-1 */
282 qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE-1 DMA */
283 qdev_prop_set_uint64(dev, "frequency", tbfreq);
284 sbd = SYS_BUS_DEVICE(pic_dev);
285 macio_init(macio, sysbus_mmio_get_region(sbd, 0));
286
287 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
288 "ide[0]"));
289 macio_ide_init_drives(macio_ide, hd);
290
291 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
292 "ide[1]"));
293 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
294
295 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
296 adb_bus = qdev_get_child_bus(dev, "adb.0");
297 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
298 qdev_init_nofail(dev);
299 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
300 qdev_init_nofail(dev);
301
302 if (machine_usb(machine)) {
303 pci_create_simple(pci_bus, -1, "pci-ohci");
304 }
305
306 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
307 graphic_depth = 15;
308
309 /* No PCI init: the BIOS will do it */
310
311 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
312 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
313 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
314 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
315 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
316 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
317 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
318 if (kernel_cmdline) {
319 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
320 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
321 } else {
322 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
323 }
324 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
325 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
326 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
327
328 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
329 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
330 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
331
332 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
333 if (kvm_enabled()) {
334 #ifdef CONFIG_KVM
335 uint8_t *hypercall;
336
337 hypercall = g_malloc(16);
338 kvmppc_get_hypercall(env, hypercall, 16);
339 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
340 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
341 #endif
342 }
343 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
344 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
345 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
346 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
347
348 /* MacOS NDRV VGA driver */
349 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
350 if (filename) {
351 ndrv_size = get_image_size(filename);
352 if (ndrv_size != -1) {
353 ndrv_file = g_malloc(ndrv_size);
354 ndrv_size = load_image(filename, ndrv_file);
355
356 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
357 }
358 g_free(filename);
359 }
360
361 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
362 }
363
364 static int heathrow_kvm_type(const char *arg)
365 {
366 /* Always force PR KVM */
367 return 2;
368 }
369
370 static void heathrow_class_init(ObjectClass *oc, void *data)
371 {
372 MachineClass *mc = MACHINE_CLASS(oc);
373
374 mc->desc = "Heathrow based PowerMAC";
375 mc->init = ppc_heathrow_init;
376 mc->block_default_type = IF_IDE;
377 mc->max_cpus = MAX_CPUS;
378 #ifndef TARGET_PPC64
379 mc->is_default = 1;
380 #endif
381 /* TOFIX "cad" when Mac floppy is implemented */
382 mc->default_boot_order = "cd";
383 mc->kvm_type = heathrow_kvm_type;
384 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
385 }
386
387 static const TypeInfo ppc_heathrow_machine_info = {
388 .name = MACHINE_TYPE_NAME("g3beige"),
389 .parent = TYPE_MACHINE,
390 .class_init = heathrow_class_init
391 };
392
393 static void ppc_heathrow_register_types(void)
394 {
395 type_register_static(&ppc_heathrow_machine_info);
396 }
397
398 type_init(ppc_heathrow_register_types);