hw/ppc/mac_oldworld.c

   1
   2 /*
   3  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   4  *
   5  * Copyright (c) 2004-2007 Fabrice Bellard
   6  * Copyright (c) 2007 Jocelyn Mayer
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "qemu/osdep.h"
  27 #include "qapi/error.h"
  28 #include "hw/hw.h"
  29 #include "hw/ppc/ppc.h"
  30 #include "mac.h"
  31 #include "hw/input/adb.h"
  32 #include "hw/timer/m48t59.h"
  33 #include "sysemu/sysemu.h"
  34 #include "net/net.h"
  35 #include "hw/isa/isa.h"
  36 #include "hw/pci/pci.h"
  37 #include "hw/boards.h"
  38 #include "hw/nvram/fw_cfg.h"
  39 #include "hw/char/escc.h"
  40 #include "hw/ide.h"
  41 #include "hw/loader.h"
  42 #include "elf.h"
  43 #include "qemu/error-report.h"
  44 #include "sysemu/kvm.h"
  45 #include "kvm_ppc.h"
  46 #include "sysemu/block-backend.h"
  47 #include "exec/address-spaces.h"
  48
  49 #define MAX_IDE_BUS 2
  50 #define CFG_ADDR 0xf0000510
  51 #define TBFREQ 16600000UL
  52 #define CLOCKFREQ 266000000UL
  53 #define BUSFREQ 66000000UL
  54
  55 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  56                             Error **errp)
  57 {
  58     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  59 }
  60
  61 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
  62 {
  63     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
  64 }
  65
  66 static hwaddr round_page(hwaddr addr)
  67 {
  68     return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
  69 }
  70
  71 static void ppc_heathrow_reset(void *opaque)
  72 {
  73     PowerPCCPU *cpu = opaque;
  74
  75     cpu_reset(CPU(cpu));
  76 }
  77
  78 static void ppc_heathrow_init(MachineState *machine)
  79 {
  80     ram_addr_t ram_size = machine->ram_size;
  81     const char *kernel_filename = machine->kernel_filename;
  82     const char *kernel_cmdline = machine->kernel_cmdline;
  83     const char *initrd_filename = machine->initrd_filename;
  84     const char *boot_device = machine->boot_order;
  85     MemoryRegion *sysmem = get_system_memory();
  86     PowerPCCPU *cpu = NULL;
  87     CPUPPCState *env = NULL;
  88     char *filename;
  89     qemu_irq *pic, **heathrow_irqs;
  90     int linux_boot, i;
  91     MemoryRegion *ram = g_new(MemoryRegion, 1);
  92     MemoryRegion *bios = g_new(MemoryRegion, 1);
  93     MemoryRegion *isa = g_new(MemoryRegion, 1);
  94     uint32_t kernel_base, initrd_base, cmdline_base = 0;
  95     int32_t kernel_size, initrd_size;
  96     PCIBus *pci_bus;
  97     PCIDevice *macio;
  98     MACIOIDEState *macio_ide;
  99     DeviceState *dev;
 100     BusState *adb_bus;
 101     int bios_size;
 102     MemoryRegion *pic_mem;
 103     MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1);
 104     uint16_t ppc_boot_device;
 105     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 106     void *fw_cfg;
 107     uint64_t tbfreq;
 108
 109     linux_boot = (kernel_filename != NULL);
 110
 111     /* init CPUs */
 112     if (machine->cpu_model == NULL)
 113         machine->cpu_model = "G3";
 114     for (i = 0; i < smp_cpus; i++) {
 115         cpu = cpu_ppc_init(machine->cpu_model);
 116         if (cpu == NULL) {
 117             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 118             exit(1);
 119         }
 120         env = &cpu->env;
 121
 122         /* Set time-base frequency to 16.6 Mhz */
 123         cpu_ppc_tb_init(env,  TBFREQ);
 124         qemu_register_reset(ppc_heathrow_reset, cpu);
 125     }
 126
 127     /* allocate RAM */
 128     if (ram_size > (2047 << 20)) {
 129         fprintf(stderr,
 130                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 131                 ((unsigned int)ram_size / (1 << 20)));
 132         exit(1);
 133     }
 134
 135     memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
 136                                          ram_size);
 137     memory_region_add_subregion(sysmem, 0, ram);
 138
 139     /* allocate and load BIOS */
 140     memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
 141                            &error_fatal);
 142     vmstate_register_ram_global(bios);
 143
 144     if (bios_name == NULL)
 145         bios_name = PROM_FILENAME;
 146     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 147     memory_region_set_readonly(bios, true);
 148     memory_region_add_subregion(sysmem, PROM_ADDR, bios);
 149
 150     /* Load OpenBIOS (ELF) */
 151     if (filename) {
 152         bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
 153                              1, PPC_ELF_MACHINE, 0, 0);
 154         g_free(filename);
 155     } else {
 156         bios_size = -1;
 157     }
 158     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 159         error_report("could not load PowerPC bios '%s'", bios_name);
 160         exit(1);
 161     }
 162
 163     if (linux_boot) {
 164         uint64_t lowaddr = 0;
 165         int bswap_needed;
 166
 167 #ifdef BSWAP_NEEDED
 168         bswap_needed = 1;
 169 #else
 170         bswap_needed = 0;
 171 #endif
 172         kernel_base = KERNEL_LOAD_ADDR;
 173         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 174                                NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
 175                                0, 0);
 176         if (kernel_size < 0)
 177             kernel_size = load_aout(kernel_filename, kernel_base,
 178                                     ram_size - kernel_base, bswap_needed,
 179                                     TARGET_PAGE_SIZE);
 180         if (kernel_size < 0)
 181             kernel_size = load_image_targphys(kernel_filename,
 182                                               kernel_base,
 183                                               ram_size - kernel_base);
 184         if (kernel_size < 0) {
 185             error_report("could not load kernel '%s'", kernel_filename);
 186             exit(1);
 187         }
 188         /* load initrd */
 189         if (initrd_filename) {
 190             initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 191             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 192                                               ram_size - initrd_base);
 193             if (initrd_size < 0) {
 194                 error_report("could not load initial ram disk '%s'",
 195                              initrd_filename);
 196                 exit(1);
 197             }
 198             cmdline_base = round_page(initrd_base + initrd_size);
 199         } else {
 200             initrd_base = 0;
 201             initrd_size = 0;
 202             cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 203         }
 204         ppc_boot_device = 'm';
 205     } else {
 206         kernel_base = 0;
 207         kernel_size = 0;
 208         initrd_base = 0;
 209         initrd_size = 0;
 210         ppc_boot_device = '\0';
 211         for (i = 0; boot_device[i] != '\0'; i++) {
 212             /* TOFIX: for now, the second IDE channel is not properly
 213              *        used by OHW. The Mac floppy disk are not emulated.
 214              *        For now, OHW cannot boot from the network.
 215              */
 216 #if 0
 217             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 218                 ppc_boot_device = boot_device[i];
 219                 break;
 220             }
 221 #else
 222             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 223                 ppc_boot_device = boot_device[i];
 224                 break;
 225             }
 226 #endif
 227         }
 228         if (ppc_boot_device == '\0') {
 229             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 230             exit(1);
 231         }
 232     }
 233
 234     /* Register 2 MB of ISA IO space */
 235     memory_region_init_alias(isa, NULL, "isa_mmio",
 236                              get_system_io(), 0, 0x00200000);
 237     memory_region_add_subregion(sysmem, 0xfe000000, isa);
 238
 239     /* XXX: we register only 1 output pin for heathrow PIC */
 240     heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 241     heathrow_irqs[0] =
 242         g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
 243     /* Connect the heathrow PIC outputs to the 6xx bus */
 244     for (i = 0; i < smp_cpus; i++) {
 245         switch (PPC_INPUT(env)) {
 246         case PPC_FLAGS_INPUT_6xx:
 247             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 248             heathrow_irqs[i][0] =
 249                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 250             break;
 251         default:
 252             error_report("Bus model not supported on OldWorld Mac machine");
 253             exit(1);
 254         }
 255     }
 256
 257     /* Timebase Frequency */
 258     if (kvm_enabled()) {
 259         tbfreq = kvmppc_get_tbfreq();
 260     } else {
 261         tbfreq = TBFREQ;
 262     }
 263
 264     /* init basic PC hardware */
 265     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 266         error_report("Only 6xx bus is supported on heathrow machine");
 267         exit(1);
 268     }
 269     pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
 270     pci_bus = pci_grackle_init(0xfec00000, pic,
 271                                get_system_memory(),
 272                                get_system_io());
 273     pci_vga_init(pci_bus);
 274
 275     escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
 276                                serial_hds[1], ESCC_CLOCK, 4);
 277     memory_region_init_alias(escc_bar, NULL, "escc-bar",
 278                              escc_mem, 0, memory_region_size(escc_mem));
 279
 280     for(i = 0; i < nb_nics; i++)
 281         pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 282
 283
 284     ide_drive_get(hd, ARRAY_SIZE(hd));
 285
 286     macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
 287     dev = DEVICE(macio);
 288     qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
 289     qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */
 290     qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */
 291     qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */
 292     qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */
 293     qdev_prop_set_uint64(dev, "frequency", tbfreq);
 294     macio_init(macio, pic_mem, escc_bar);
 295
 296     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
 297                                                         "ide[0]"));
 298     macio_ide_init_drives(macio_ide, hd);
 299
 300     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
 301                                                         "ide[1]"));
 302     macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
 303
 304     dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
 305     adb_bus = qdev_get_child_bus(dev, "adb.0");
 306     dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
 307     qdev_init_nofail(dev);
 308     dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
 309     qdev_init_nofail(dev);
 310
 311     if (usb_enabled()) {
 312         pci_create_simple(pci_bus, -1, "pci-ohci");
 313     }
 314
 315     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 316         graphic_depth = 15;
 317
 318     /* No PCI init: the BIOS will do it */
 319
 320     fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
 321     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 322     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 323     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 324     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 325     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 326     if (kernel_cmdline) {
 327         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
 328         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
 329     } else {
 330         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 331     }
 332     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 333     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 334     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 335
 336     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 337     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 338     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 339
 340     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 341     if (kvm_enabled()) {
 342 #ifdef CONFIG_KVM
 343         uint8_t *hypercall;
 344
 345         hypercall = g_malloc(16);
 346         kvmppc_get_hypercall(env, hypercall, 16);
 347         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 348         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 349 #endif
 350     }
 351     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
 352     /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
 353     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
 354     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
 355
 356     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 357 }
 358
 359 static int heathrow_kvm_type(const char *arg)
 360 {
 361     /* Always force PR KVM */
 362     return 2;
 363 }
 364
 365 static void heathrow_machine_init(MachineClass *mc)
 366 {
 367     mc->desc = "Heathrow based PowerMAC";
 368     mc->init = ppc_heathrow_init;
 369     mc->max_cpus = MAX_CPUS;
 370 #ifndef TARGET_PPC64
 371     mc->is_default = 1;
 372 #endif
 373     /* TOFIX "cad" when Mac floppy is implemented */
 374     mc->default_boot_order = "cd";
 375     mc->kvm_type = heathrow_kvm_type;
 376 }
 377
 378 DEFINE_MACHINE("g3beige", heathrow_machine_init)