hw/ppc/pnv.c

   1 /*
   2  * QEMU PowerPC PowerNV machine model
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "sysemu/sysemu.h"
  23 #include "sysemu/numa.h"
  24 #include "sysemu/cpus.h"
  25 #include "hw/hw.h"
  26 #include "target/ppc/cpu.h"
  27 #include "qemu/log.h"
  28 #include "hw/ppc/fdt.h"
  29 #include "hw/ppc/ppc.h"
  30 #include "hw/ppc/pnv.h"
  31 #include "hw/ppc/pnv_core.h"
  32 #include "hw/loader.h"
  33 #include "exec/address-spaces.h"
  34 #include "qemu/cutils.h"
  35 #include "qapi/visitor.h"
  36
  37 #include "hw/ppc/pnv_xscom.h"
  38
  39 #include "hw/isa/isa.h"
  40 #include "hw/char/serial.h"
  41 #include "hw/timer/mc146818rtc.h"
  42
  43 #include <libfdt.h>
  44
  45 #define FDT_MAX_SIZE            0x00100000
  46
  47 #define FW_FILE_NAME            "skiboot.lid"
  48 #define FW_LOAD_ADDR            0x0
  49 #define FW_MAX_SIZE             0x00400000
  50
  51 #define KERNEL_LOAD_ADDR        0x20000000
  52 #define INITRD_LOAD_ADDR        0x40000000
  53
  54 /*
  55  * On Power Systems E880 (POWER8), the max cpus (threads) should be :
  56  *     4 * 4 sockets * 12 cores * 8 threads = 1536
  57  * Let's make it 2^11
  58  */
  59 #define MAX_CPUS                2048
  60
  61 /*
  62  * Memory nodes are created by hostboot, one for each range of memory
  63  * that has a different "affinity". In practice, it means one range
  64  * per chip.
  65  */
  66 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
  67                                          hwaddr size)
  68 {
  69     char *mem_name;
  70     uint64_t mem_reg_property[2];
  71     int off;
  72
  73     mem_reg_property[0] = cpu_to_be64(start);
  74     mem_reg_property[1] = cpu_to_be64(size);
  75
  76     mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
  77     off = fdt_add_subnode(fdt, 0, mem_name);
  78     g_free(mem_name);
  79
  80     _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
  81     _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
  82                        sizeof(mem_reg_property))));
  83     _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
  84 }
  85
  86 static int get_cpus_node(void *fdt)
  87 {
  88     int cpus_offset = fdt_path_offset(fdt, "/cpus");
  89
  90     if (cpus_offset < 0) {
  91         cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
  92                                       "cpus");
  93         if (cpus_offset) {
  94             _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
  95             _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
  96         }
  97     }
  98     _FDT(cpus_offset);
  99     return cpus_offset;
 100 }
 101
 102 /*
 103  * The PowerNV cores (and threads) need to use real HW ids and not an
 104  * incremental index like it has been done on other platforms. This HW
 105  * id is stored in the CPU PIR, it is used to create cpu nodes in the
 106  * device tree, used in XSCOM to address cores and in interrupt
 107  * servers.
 108  */
 109 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
 110 {
 111     CPUState *cs = CPU(DEVICE(pc->threads));
 112     DeviceClass *dc = DEVICE_GET_CLASS(cs);
 113     PowerPCCPU *cpu = POWERPC_CPU(cs);
 114     int smt_threads = CPU_CORE(pc)->nr_threads;
 115     CPUPPCState *env = &cpu->env;
 116     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
 117     uint32_t servers_prop[smt_threads];
 118     int i;
 119     uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
 120                        0xffffffff, 0xffffffff};
 121     uint32_t tbfreq = PNV_TIMEBASE_FREQ;
 122     uint32_t cpufreq = 1000000000;
 123     uint32_t page_sizes_prop[64];
 124     size_t page_sizes_prop_size;
 125     const uint8_t pa_features[] = { 24, 0,
 126                                     0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
 127                                     0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
 128                                     0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
 129                                     0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
 130     int offset;
 131     char *nodename;
 132     int cpus_offset = get_cpus_node(fdt);
 133
 134     nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
 135     offset = fdt_add_subnode(fdt, cpus_offset, nodename);
 136     _FDT(offset);
 137     g_free(nodename);
 138
 139     _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
 140
 141     _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
 142     _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
 143     _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
 144
 145     _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
 146     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
 147                             env->dcache_line_size)));
 148     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
 149                             env->dcache_line_size)));
 150     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
 151                             env->icache_line_size)));
 152     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
 153                             env->icache_line_size)));
 154
 155     if (pcc->l1_dcache_size) {
 156         _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
 157                                pcc->l1_dcache_size)));
 158     } else {
 159         error_report("Warning: Unknown L1 dcache size for cpu");
 160     }
 161     if (pcc->l1_icache_size) {
 162         _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
 163                                pcc->l1_icache_size)));
 164     } else {
 165         error_report("Warning: Unknown L1 icache size for cpu");
 166     }
 167
 168     _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
 169     _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
 170     _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
 171     _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
 172     _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
 173
 174     if (env->spr_cb[SPR_PURR].oea_read) {
 175         _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
 176     }
 177
 178     if (env->mmu_model & POWERPC_MMU_1TSEG) {
 179         _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
 180                            segs, sizeof(segs))));
 181     }
 182
 183     /* Advertise VMX/VSX (vector extensions) if available
 184      *   0 / no property == no vector extensions
 185      *   1               == VMX / Altivec available
 186      *   2               == VSX available */
 187     if (env->insns_flags & PPC_ALTIVEC) {
 188         uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
 189
 190         _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
 191     }
 192
 193     /* Advertise DFP (Decimal Floating Point) if available
 194      *   0 / no property == no DFP
 195      *   1               == DFP available */
 196     if (env->insns_flags2 & PPC2_DFP) {
 197         _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
 198     }
 199
 200     page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
 201                                                   sizeof(page_sizes_prop));
 202     if (page_sizes_prop_size) {
 203         _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
 204                            page_sizes_prop, page_sizes_prop_size)));
 205     }
 206
 207     _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
 208                        pa_features, sizeof(pa_features))));
 209
 210     /* Build interrupt servers properties */
 211     for (i = 0; i < smt_threads; i++) {
 212         servers_prop[i] = cpu_to_be32(pc->pir + i);
 213     }
 214     _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
 215                        servers_prop, sizeof(servers_prop))));
 216 }
 217
 218 static void powernv_populate_chip(PnvChip *chip, void *fdt)
 219 {
 220     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 221     char *typename = pnv_core_typename(pcc->cpu_model);
 222     size_t typesize = object_type_get_instance_size(typename);
 223     int i;
 224
 225     pnv_xscom_populate(chip, fdt, 0);
 226
 227     for (i = 0; i < chip->nr_cores; i++) {
 228         PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
 229
 230         powernv_create_core_node(chip, pnv_core, fdt);
 231     }
 232
 233     if (chip->ram_size) {
 234         powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
 235                                      chip->ram_size);
 236     }
 237     g_free(typename);
 238 }
 239
 240 static void *powernv_create_fdt(MachineState *machine)
 241 {
 242     const char plat_compat[] = "qemu,powernv\0ibm,powernv";
 243     PnvMachineState *pnv = POWERNV_MACHINE(machine);
 244     void *fdt;
 245     char *buf;
 246     int off;
 247     int i;
 248
 249     fdt = g_malloc0(FDT_MAX_SIZE);
 250     _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
 251
 252     /* Root node */
 253     _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
 254     _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
 255     _FDT((fdt_setprop_string(fdt, 0, "model",
 256                              "IBM PowerNV (emulated by qemu)")));
 257     _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
 258                       sizeof(plat_compat))));
 259
 260     buf =  qemu_uuid_unparse_strdup(&qemu_uuid);
 261     _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
 262     if (qemu_uuid_set) {
 263         _FDT((fdt_property_string(fdt, "system-id", buf)));
 264     }
 265     g_free(buf);
 266
 267     off = fdt_add_subnode(fdt, 0, "chosen");
 268     if (machine->kernel_cmdline) {
 269         _FDT((fdt_setprop_string(fdt, off, "bootargs",
 270                                  machine->kernel_cmdline)));
 271     }
 272
 273     if (pnv->initrd_size) {
 274         uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
 275         uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
 276
 277         _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
 278                                &start_prop, sizeof(start_prop))));
 279         _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
 280                                &end_prop, sizeof(end_prop))));
 281     }
 282
 283     /* Populate device tree for each chip */
 284     for (i = 0; i < pnv->num_chips; i++) {
 285         powernv_populate_chip(pnv->chips[i], fdt);
 286     }
 287     return fdt;
 288 }
 289
 290 static void ppc_powernv_reset(void)
 291 {
 292     MachineState *machine = MACHINE(qdev_get_machine());
 293     void *fdt;
 294
 295     qemu_devices_reset();
 296
 297     fdt = powernv_create_fdt(machine);
 298
 299     /* Pack resulting tree */
 300     _FDT((fdt_pack(fdt)));
 301
 302     cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
 303 }
 304
 305 /* If we don't use the built-in LPC interrupt deserializer, we need
 306  * to provide a set of qirqs for the ISA bus or things will go bad.
 307  *
 308  * Most machines using pre-Naples chips (without said deserializer)
 309  * have a CPLD that will collect the SerIRQ and shoot them as a
 310  * single level interrupt to the P8 chip. So let's setup a hook
 311  * for doing just that.
 312  *
 313  * Note: The actual interrupt input isn't emulated yet, this will
 314  * come with the PSI bridge model.
 315  */
 316 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
 317 {
 318     /* We don't yet emulate the PSI bridge which provides the external
 319      * interrupt, so just drop interrupts on the floor
 320      */
 321 }
 322
 323 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
 324 {
 325      /* XXX TODO */
 326 }
 327
 328 static ISABus *pnv_isa_create(PnvChip *chip)
 329 {
 330     PnvLpcController *lpc = &chip->lpc;
 331     ISABus *isa_bus;
 332     qemu_irq *irqs;
 333     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 334
 335     /* let isa_bus_new() create its own bridge on SysBus otherwise
 336      * devices speficied on the command line won't find the bus and
 337      * will fail to create.
 338      */
 339     isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
 340                           &error_fatal);
 341
 342     /* Not all variants have a working serial irq decoder. If not,
 343      * handling of LPC interrupts becomes a platform issue (some
 344      * platforms have a CPLD to do it).
 345      */
 346     if (pcc->chip_type == PNV_CHIP_POWER8NVL) {
 347         irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, chip, ISA_NUM_IRQS);
 348     } else {
 349         irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, chip,
 350                                   ISA_NUM_IRQS);
 351     }
 352
 353     isa_bus_irqs(isa_bus, irqs);
 354     return isa_bus;
 355 }
 356
 357 static void ppc_powernv_init(MachineState *machine)
 358 {
 359     PnvMachineState *pnv = POWERNV_MACHINE(machine);
 360     MemoryRegion *ram;
 361     char *fw_filename;
 362     long fw_size;
 363     int i;
 364     char *chip_typename;
 365
 366     /* allocate RAM */
 367     if (machine->ram_size < (1 * G_BYTE)) {
 368         error_report("Warning: skiboot may not work with < 1GB of RAM");
 369     }
 370
 371     ram = g_new(MemoryRegion, 1);
 372     memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
 373                                          machine->ram_size);
 374     memory_region_add_subregion(get_system_memory(), 0, ram);
 375
 376     /* load skiboot firmware  */
 377     if (bios_name == NULL) {
 378         bios_name = FW_FILE_NAME;
 379     }
 380
 381     fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 382
 383     fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
 384     if (fw_size < 0) {
 385         error_report("Could not load OPAL '%s'", fw_filename);
 386         exit(1);
 387     }
 388     g_free(fw_filename);
 389
 390     /* load kernel */
 391     if (machine->kernel_filename) {
 392         long kernel_size;
 393
 394         kernel_size = load_image_targphys(machine->kernel_filename,
 395                                           KERNEL_LOAD_ADDR, 0x2000000);
 396         if (kernel_size < 0) {
 397             error_report("Could not load kernel '%s'",
 398                          machine->kernel_filename);
 399             exit(1);
 400         }
 401     }
 402
 403     /* load initrd */
 404     if (machine->initrd_filename) {
 405         pnv->initrd_base = INITRD_LOAD_ADDR;
 406         pnv->initrd_size = load_image_targphys(machine->initrd_filename,
 407                                   pnv->initrd_base, 0x10000000); /* 128MB max */
 408         if (pnv->initrd_size < 0) {
 409             error_report("Could not load initial ram disk '%s'",
 410                          machine->initrd_filename);
 411             exit(1);
 412         }
 413     }
 414
 415     /* We need some cpu model to instantiate the PnvChip class */
 416     if (machine->cpu_model == NULL) {
 417         machine->cpu_model = "POWER8";
 418     }
 419
 420     /* Create the processor chips */
 421     chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
 422     if (!object_class_by_name(chip_typename)) {
 423         error_report("qemu: invalid CPU model '%s' for %s machine",
 424                      machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
 425         exit(1);
 426     }
 427
 428     pnv->chips = g_new0(PnvChip *, pnv->num_chips);
 429     for (i = 0; i < pnv->num_chips; i++) {
 430         char chip_name[32];
 431         Object *chip = object_new(chip_typename);
 432
 433         pnv->chips[i] = PNV_CHIP(chip);
 434
 435         /* TODO: put all the memory in one node on chip 0 until we find a
 436          * way to specify different ranges for each chip
 437          */
 438         if (i == 0) {
 439             object_property_set_int(chip, machine->ram_size, "ram-size",
 440                                     &error_fatal);
 441         }
 442
 443         snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
 444         object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
 445         object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
 446                                 &error_fatal);
 447         object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
 448         object_property_set_bool(chip, true, "realized", &error_fatal);
 449     }
 450     g_free(chip_typename);
 451
 452     /* Instantiate ISA bus on chip 0 */
 453     pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
 454
 455     /* Create serial port */
 456     serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS);
 457
 458     /* Create an RTC ISA device too */
 459     rtc_init(pnv->isa_bus, 2000, NULL);
 460 }
 461
 462 /*
 463  *    0:21  Reserved - Read as zeros
 464  *   22:24  Chip ID
 465  *   25:28  Core number
 466  *   29:31  Thread ID
 467  */
 468 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
 469 {
 470     return (chip->chip_id << 7) | (core_id << 3);
 471 }
 472
 473 /*
 474  *    0:48  Reserved - Read as zeroes
 475  *   49:52  Node ID
 476  *   53:55  Chip ID
 477  *   56     Reserved - Read as zero
 478  *   57:61  Core number
 479  *   62:63  Thread ID
 480  *
 481  * We only care about the lower bits. uint32_t is fine for the moment.
 482  */
 483 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
 484 {
 485     return (chip->chip_id << 8) | (core_id << 2);
 486 }
 487
 488 /* Allowed core identifiers on a POWER8 Processor Chip :
 489  *
 490  * <EX0 reserved>
 491  *  EX1  - Venice only
 492  *  EX2  - Venice only
 493  *  EX3  - Venice only
 494  *  EX4
 495  *  EX5
 496  *  EX6
 497  * <EX7,8 reserved> <reserved>
 498  *  EX9  - Venice only
 499  *  EX10 - Venice only
 500  *  EX11 - Venice only
 501  *  EX12
 502  *  EX13
 503  *  EX14
 504  * <EX15 reserved>
 505  */
 506 #define POWER8E_CORE_MASK  (0x7070ull)
 507 #define POWER8_CORE_MASK   (0x7e7eull)
 508
 509 /*
 510  * POWER9 has 24 cores, ids starting at 0x20
 511  */
 512 #define POWER9_CORE_MASK   (0xffffff00000000ull)
 513
 514 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
 515 {
 516     DeviceClass *dc = DEVICE_CLASS(klass);
 517     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 518
 519     k->cpu_model = "POWER8E";
 520     k->chip_type = PNV_CHIP_POWER8E;
 521     k->chip_cfam_id = 0x221ef04980000000ull;  /* P8 Murano DD2.1 */
 522     k->cores_mask = POWER8E_CORE_MASK;
 523     k->core_pir = pnv_chip_core_pir_p8;
 524     k->xscom_base = 0x003fc0000000000ull;
 525     k->xscom_core_base = 0x10000000ull;
 526     dc->desc = "PowerNV Chip POWER8E";
 527 }
 528
 529 static const TypeInfo pnv_chip_power8e_info = {
 530     .name          = TYPE_PNV_CHIP_POWER8E,
 531     .parent        = TYPE_PNV_CHIP,
 532     .instance_size = sizeof(PnvChip),
 533     .class_init    = pnv_chip_power8e_class_init,
 534 };
 535
 536 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
 537 {
 538     DeviceClass *dc = DEVICE_CLASS(klass);
 539     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 540
 541     k->cpu_model = "POWER8";
 542     k->chip_type = PNV_CHIP_POWER8;
 543     k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
 544     k->cores_mask = POWER8_CORE_MASK;
 545     k->core_pir = pnv_chip_core_pir_p8;
 546     k->xscom_base = 0x003fc0000000000ull;
 547     k->xscom_core_base = 0x10000000ull;
 548     dc->desc = "PowerNV Chip POWER8";
 549 }
 550
 551 static const TypeInfo pnv_chip_power8_info = {
 552     .name          = TYPE_PNV_CHIP_POWER8,
 553     .parent        = TYPE_PNV_CHIP,
 554     .instance_size = sizeof(PnvChip),
 555     .class_init    = pnv_chip_power8_class_init,
 556 };
 557
 558 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
 559 {
 560     DeviceClass *dc = DEVICE_CLASS(klass);
 561     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 562
 563     k->cpu_model = "POWER8NVL";
 564     k->chip_type = PNV_CHIP_POWER8NVL;
 565     k->chip_cfam_id = 0x120d304980000000ull;  /* P8 Naples DD1.0 */
 566     k->cores_mask = POWER8_CORE_MASK;
 567     k->core_pir = pnv_chip_core_pir_p8;
 568     k->xscom_base = 0x003fc0000000000ull;
 569     k->xscom_core_base = 0x10000000ull;
 570     dc->desc = "PowerNV Chip POWER8NVL";
 571 }
 572
 573 static const TypeInfo pnv_chip_power8nvl_info = {
 574     .name          = TYPE_PNV_CHIP_POWER8NVL,
 575     .parent        = TYPE_PNV_CHIP,
 576     .instance_size = sizeof(PnvChip),
 577     .class_init    = pnv_chip_power8nvl_class_init,
 578 };
 579
 580 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
 581 {
 582     DeviceClass *dc = DEVICE_CLASS(klass);
 583     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 584
 585     k->cpu_model = "POWER9";
 586     k->chip_type = PNV_CHIP_POWER9;
 587     k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
 588     k->cores_mask = POWER9_CORE_MASK;
 589     k->core_pir = pnv_chip_core_pir_p9;
 590     k->xscom_base = 0x00603fc00000000ull;
 591     k->xscom_core_base = 0x0ull;
 592     dc->desc = "PowerNV Chip POWER9";
 593 }
 594
 595 static const TypeInfo pnv_chip_power9_info = {
 596     .name          = TYPE_PNV_CHIP_POWER9,
 597     .parent        = TYPE_PNV_CHIP,
 598     .instance_size = sizeof(PnvChip),
 599     .class_init    = pnv_chip_power9_class_init,
 600 };
 601
 602 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
 603 {
 604     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 605     int cores_max;
 606
 607     /*
 608      * No custom mask for this chip, let's use the default one from *
 609      * the chip class
 610      */
 611     if (!chip->cores_mask) {
 612         chip->cores_mask = pcc->cores_mask;
 613     }
 614
 615     /* filter alien core ids ! some are reserved */
 616     if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
 617         error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
 618                    chip->cores_mask);
 619         return;
 620     }
 621     chip->cores_mask &= pcc->cores_mask;
 622
 623     /* now that we have a sane layout, let check the number of cores */
 624     cores_max = ctpop64(chip->cores_mask);
 625     if (chip->nr_cores > cores_max) {
 626         error_setg(errp, "warning: too many cores for chip ! Limit is %d",
 627                    cores_max);
 628         return;
 629     }
 630 }
 631
 632 static void pnv_chip_init(Object *obj)
 633 {
 634     PnvChip *chip = PNV_CHIP(obj);
 635     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 636
 637     chip->xscom_base = pcc->xscom_base;
 638
 639     object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
 640     object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
 641 }
 642
 643 static void pnv_chip_realize(DeviceState *dev, Error **errp)
 644 {
 645     PnvChip *chip = PNV_CHIP(dev);
 646     Error *error = NULL;
 647     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 648     char *typename = pnv_core_typename(pcc->cpu_model);
 649     size_t typesize = object_type_get_instance_size(typename);
 650     int i, core_hwid;
 651
 652     if (!object_class_by_name(typename)) {
 653         error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
 654         return;
 655     }
 656
 657     /* XSCOM bridge */
 658     pnv_xscom_realize(chip, &error);
 659     if (error) {
 660         error_propagate(errp, error);
 661         return;
 662     }
 663     sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
 664
 665     /* Cores */
 666     pnv_chip_core_sanitize(chip, &error);
 667     if (error) {
 668         error_propagate(errp, error);
 669         return;
 670     }
 671
 672     chip->cores = g_malloc0(typesize * chip->nr_cores);
 673
 674     for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
 675              && (i < chip->nr_cores); core_hwid++) {
 676         char core_name[32];
 677         void *pnv_core = chip->cores + i * typesize;
 678
 679         if (!(chip->cores_mask & (1ull << core_hwid))) {
 680             continue;
 681         }
 682
 683         object_initialize(pnv_core, typesize, typename);
 684         snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
 685         object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
 686                                   &error_fatal);
 687         object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
 688                                 &error_fatal);
 689         object_property_set_int(OBJECT(pnv_core), core_hwid,
 690                                 CPU_CORE_PROP_CORE_ID, &error_fatal);
 691         object_property_set_int(OBJECT(pnv_core),
 692                                 pcc->core_pir(chip, core_hwid),
 693                                 "pir", &error_fatal);
 694         object_property_set_bool(OBJECT(pnv_core), true, "realized",
 695                                  &error_fatal);
 696         object_unref(OBJECT(pnv_core));
 697
 698         /* Each core has an XSCOM MMIO region */
 699         pnv_xscom_add_subregion(chip,
 700                                 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
 701                                                        core_hwid),
 702                                 &PNV_CORE(pnv_core)->xscom_regs);
 703         i++;
 704     }
 705     g_free(typename);
 706
 707     /* Create LPC controller */
 708     object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
 709                              &error_fatal);
 710     pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
 711 }
 712
 713 static Property pnv_chip_properties[] = {
 714     DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
 715     DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
 716     DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
 717     DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
 718     DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
 719     DEFINE_PROP_END_OF_LIST(),
 720 };
 721
 722 static void pnv_chip_class_init(ObjectClass *klass, void *data)
 723 {
 724     DeviceClass *dc = DEVICE_CLASS(klass);
 725
 726     dc->realize = pnv_chip_realize;
 727     dc->props = pnv_chip_properties;
 728     dc->desc = "PowerNV Chip";
 729 }
 730
 731 static const TypeInfo pnv_chip_info = {
 732     .name          = TYPE_PNV_CHIP,
 733     .parent        = TYPE_SYS_BUS_DEVICE,
 734     .class_init    = pnv_chip_class_init,
 735     .instance_init = pnv_chip_init,
 736     .class_size    = sizeof(PnvChipClass),
 737     .abstract      = true,
 738 };
 739
 740 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
 741                               void *opaque, Error **errp)
 742 {
 743     visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
 744 }
 745
 746 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
 747                               void *opaque, Error **errp)
 748 {
 749     PnvMachineState *pnv = POWERNV_MACHINE(obj);
 750     uint32_t num_chips;
 751     Error *local_err = NULL;
 752
 753     visit_type_uint32(v, name, &num_chips, &local_err);
 754     if (local_err) {
 755         error_propagate(errp, local_err);
 756         return;
 757     }
 758
 759     /*
 760      * TODO: should we decide on how many chips we can create based
 761      * on #cores and Venice vs. Murano vs. Naples chip type etc...,
 762      */
 763     if (!is_power_of_2(num_chips) || num_chips > 4) {
 764         error_setg(errp, "invalid number of chips: '%d'", num_chips);
 765         return;
 766     }
 767
 768     pnv->num_chips = num_chips;
 769 }
 770
 771 static void powernv_machine_initfn(Object *obj)
 772 {
 773     PnvMachineState *pnv = POWERNV_MACHINE(obj);
 774     pnv->num_chips = 1;
 775 }
 776
 777 static void powernv_machine_class_props_init(ObjectClass *oc)
 778 {
 779     object_class_property_add(oc, "num-chips", "uint32_t",
 780                               pnv_get_num_chips, pnv_set_num_chips,
 781                               NULL, NULL, NULL);
 782     object_class_property_set_description(oc, "num-chips",
 783                               "Specifies the number of processor chips",
 784                               NULL);
 785 }
 786
 787 static void powernv_machine_class_init(ObjectClass *oc, void *data)
 788 {
 789     MachineClass *mc = MACHINE_CLASS(oc);
 790
 791     mc->desc = "IBM PowerNV (Non-Virtualized)";
 792     mc->init = ppc_powernv_init;
 793     mc->reset = ppc_powernv_reset;
 794     mc->max_cpus = MAX_CPUS;
 795     mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
 796                                       * storage */
 797     mc->no_parallel = 1;
 798     mc->default_boot_order = NULL;
 799     mc->default_ram_size = 1 * G_BYTE;
 800
 801     powernv_machine_class_props_init(oc);
 802 }
 803
 804 static const TypeInfo powernv_machine_info = {
 805     .name          = TYPE_POWERNV_MACHINE,
 806     .parent        = TYPE_MACHINE,
 807     .instance_size = sizeof(PnvMachineState),
 808     .instance_init = powernv_machine_initfn,
 809     .class_init    = powernv_machine_class_init,
 810 };
 811
 812 static void powernv_machine_register_types(void)
 813 {
 814     type_register_static(&powernv_machine_info);
 815     type_register_static(&pnv_chip_info);
 816     type_register_static(&pnv_chip_power8e_info);
 817     type_register_static(&pnv_chip_power8_info);
 818     type_register_static(&pnv_chip_power8nvl_info);
 819     type_register_static(&pnv_chip_power9_info);
 820 }
 821
 822 type_init(powernv_machine_register_types)