2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qemu/units.h"
24 #include "qemu/cutils.h"
25 #include "qapi/error.h"
26 #include "sysemu/qtest.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/numa.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/runstate.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/device_tree.h"
33 #include "sysemu/hw_accel.h"
34 #include "target/ppc/cpu.h"
36 #include "hw/ppc/fdt.h"
37 #include "hw/ppc/ppc.h"
38 #include "hw/ppc/pnv.h"
39 #include "hw/ppc/pnv_core.h"
40 #include "hw/loader.h"
42 #include "exec/address-spaces.h"
43 #include "qapi/visitor.h"
44 #include "monitor/monitor.h"
45 #include "hw/intc/intc.h"
46 #include "hw/ipmi/ipmi.h"
47 #include "target/ppc/mmu-hash64.h"
48 #include "hw/pci/msi.h"
50 #include "hw/ppc/xics.h"
51 #include "hw/qdev-properties.h"
52 #include "hw/ppc/pnv_xscom.h"
53 #include "hw/ppc/pnv_pnor.h"
55 #include "hw/isa/isa.h"
56 #include "hw/boards.h"
57 #include "hw/char/serial.h"
58 #include "hw/rtc/mc146818rtc.h"
62 #define FDT_MAX_SIZE (1 * MiB)
64 #define FW_FILE_NAME "skiboot.lid"
65 #define FW_LOAD_ADDR 0x0
66 #define FW_MAX_SIZE (16 * MiB)
68 #define KERNEL_LOAD_ADDR 0x20000000
69 #define KERNEL_MAX_SIZE (128 * MiB)
70 #define INITRD_LOAD_ADDR 0x28000000
71 #define INITRD_MAX_SIZE (128 * MiB)
73 static const char *pnv_chip_core_typename(const PnvChip
*o
)
75 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
76 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
77 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
78 const char *core_type
= object_class_get_name(object_class_by_name(s
));
84 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
85 * 4 * 4 sockets * 12 cores * 8 threads = 1536
91 * Memory nodes are created by hostboot, one for each range of memory
92 * that has a different "affinity". In practice, it means one range
95 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
98 uint64_t mem_reg_property
[2];
101 mem_reg_property
[0] = cpu_to_be64(start
);
102 mem_reg_property
[1] = cpu_to_be64(size
);
104 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
105 off
= fdt_add_subnode(fdt
, 0, mem_name
);
108 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
109 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
110 sizeof(mem_reg_property
))));
111 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
114 static int get_cpus_node(void *fdt
)
116 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
118 if (cpus_offset
< 0) {
119 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
121 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
122 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
130 * The PowerNV cores (and threads) need to use real HW ids and not an
131 * incremental index like it has been done on other platforms. This HW
132 * id is stored in the CPU PIR, it is used to create cpu nodes in the
133 * device tree, used in XSCOM to address cores and in interrupt
136 static void pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
138 PowerPCCPU
*cpu
= pc
->threads
[0];
139 CPUState
*cs
= CPU(cpu
);
140 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
141 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
142 CPUPPCState
*env
= &cpu
->env
;
143 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
144 uint32_t servers_prop
[smt_threads
];
146 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
147 0xffffffff, 0xffffffff};
148 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
149 uint32_t cpufreq
= 1000000000;
150 uint32_t page_sizes_prop
[64];
151 size_t page_sizes_prop_size
;
152 const uint8_t pa_features
[] = { 24, 0,
153 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
159 int cpus_offset
= get_cpus_node(fdt
);
161 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
162 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
166 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
168 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
169 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
170 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
172 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
173 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
174 env
->dcache_line_size
)));
175 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
176 env
->dcache_line_size
)));
177 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
178 env
->icache_line_size
)));
179 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
180 env
->icache_line_size
)));
182 if (pcc
->l1_dcache_size
) {
183 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
184 pcc
->l1_dcache_size
)));
186 warn_report("Unknown L1 dcache size for cpu");
188 if (pcc
->l1_icache_size
) {
189 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
190 pcc
->l1_icache_size
)));
192 warn_report("Unknown L1 icache size for cpu");
195 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
196 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
197 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size",
198 cpu
->hash64_opts
->slb_size
)));
199 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
200 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
202 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
203 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
206 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
207 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
208 segs
, sizeof(segs
))));
212 * Advertise VMX/VSX (vector extensions) if available
213 * 0 / no property == no vector extensions
214 * 1 == VMX / Altivec available
217 if (env
->insns_flags
& PPC_ALTIVEC
) {
218 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
220 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
224 * Advertise DFP (Decimal Floating Point) if available
225 * 0 / no property == no DFP
228 if (env
->insns_flags2
& PPC2_DFP
) {
229 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
232 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
233 sizeof(page_sizes_prop
));
234 if (page_sizes_prop_size
) {
235 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
236 page_sizes_prop
, page_sizes_prop_size
)));
239 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
240 pa_features
, sizeof(pa_features
))));
242 /* Build interrupt servers properties */
243 for (i
= 0; i
< smt_threads
; i
++) {
244 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
246 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
247 servers_prop
, sizeof(servers_prop
))));
250 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
253 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
255 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
256 uint32_t irange
[2], i
, rsize
;
260 irange
[0] = cpu_to_be32(pir
);
261 irange
[1] = cpu_to_be32(nr_threads
);
263 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
264 reg
= g_malloc(rsize
);
265 for (i
= 0; i
< nr_threads
; i
++) {
266 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
267 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
270 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
271 offset
= fdt_add_subnode(fdt
, 0, name
);
275 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
276 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
277 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
278 "PowerPC-External-Interrupt-Presentation")));
279 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
280 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
281 irange
, sizeof(irange
))));
282 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
283 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
287 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
289 static const char compat
[] = "ibm,power8-xscom\0ibm,xscom";
292 pnv_dt_xscom(chip
, fdt
, 0,
293 cpu_to_be64(PNV_XSCOM_BASE(chip
)),
294 cpu_to_be64(PNV_XSCOM_SIZE
),
295 compat
, sizeof(compat
));
297 for (i
= 0; i
< chip
->nr_cores
; i
++) {
298 PnvCore
*pnv_core
= chip
->cores
[i
];
300 pnv_dt_core(chip
, pnv_core
, fdt
);
302 /* Interrupt Control Presenters (ICP). One per core. */
303 pnv_dt_icp(chip
, fdt
, pnv_core
->pir
, CPU_CORE(pnv_core
)->nr_threads
);
306 if (chip
->ram_size
) {
307 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
311 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
313 static const char compat
[] = "ibm,power9-xscom\0ibm,xscom";
316 pnv_dt_xscom(chip
, fdt
, 0,
317 cpu_to_be64(PNV9_XSCOM_BASE(chip
)),
318 cpu_to_be64(PNV9_XSCOM_SIZE
),
319 compat
, sizeof(compat
));
321 for (i
= 0; i
< chip
->nr_cores
; i
++) {
322 PnvCore
*pnv_core
= chip
->cores
[i
];
324 pnv_dt_core(chip
, pnv_core
, fdt
);
327 if (chip
->ram_size
) {
328 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
331 pnv_dt_lpc(chip
, fdt
, 0, PNV9_LPCM_BASE(chip
), PNV9_LPCM_SIZE
);
334 static void pnv_chip_power10_dt_populate(PnvChip
*chip
, void *fdt
)
336 static const char compat
[] = "ibm,power10-xscom\0ibm,xscom";
339 pnv_dt_xscom(chip
, fdt
, 0,
340 cpu_to_be64(PNV10_XSCOM_BASE(chip
)),
341 cpu_to_be64(PNV10_XSCOM_SIZE
),
342 compat
, sizeof(compat
));
344 for (i
= 0; i
< chip
->nr_cores
; i
++) {
345 PnvCore
*pnv_core
= chip
->cores
[i
];
347 pnv_dt_core(chip
, pnv_core
, fdt
);
350 if (chip
->ram_size
) {
351 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
354 pnv_dt_lpc(chip
, fdt
, 0, PNV10_LPCM_BASE(chip
), PNV10_LPCM_SIZE
);
357 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
359 uint32_t io_base
= d
->ioport_id
;
360 uint32_t io_regs
[] = {
362 cpu_to_be32(io_base
),
368 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
369 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
373 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
374 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
377 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
379 const char compatible
[] = "ns16550\0pnpPNP,501";
380 uint32_t io_base
= d
->ioport_id
;
381 uint32_t io_regs
[] = {
383 cpu_to_be32(io_base
),
389 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
390 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
394 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
395 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
396 sizeof(compatible
))));
398 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
399 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
400 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
401 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
402 fdt_get_phandle(fdt
, lpc_off
))));
404 /* This is needed by Linux */
405 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
408 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
410 const char compatible
[] = "bt\0ipmi-bt";
412 uint32_t io_regs
[] = {
414 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
421 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
422 io_regs
[1] = cpu_to_be32(io_base
);
424 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
426 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
427 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
431 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
432 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
433 sizeof(compatible
))));
435 /* Mark it as reserved to avoid Linux trying to claim it */
436 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
437 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
438 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
439 fdt_get_phandle(fdt
, lpc_off
))));
442 typedef struct ForeachPopulateArgs
{
445 } ForeachPopulateArgs
;
447 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
449 ForeachPopulateArgs
*args
= opaque
;
450 ISADevice
*d
= ISA_DEVICE(dev
);
452 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
453 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
454 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
455 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
456 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
457 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
459 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
467 * The default LPC bus of a multichip system is on chip 0. It's
468 * recognized by the firmware (skiboot) using a "primary" property.
470 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
472 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
473 ForeachPopulateArgs args
= {
475 .offset
= isa_offset
,
479 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
481 phandle
= qemu_fdt_alloc_phandle(fdt
);
483 _FDT((fdt_setprop_cell(fdt
, isa_offset
, "phandle", phandle
)));
486 * ISA devices are not necessarily parented to the ISA bus so we
487 * can not use object_child_foreach()
489 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
493 static void pnv_dt_power_mgt(PnvMachineState
*pnv
, void *fdt
)
497 off
= fdt_add_subnode(fdt
, 0, "ibm,opal");
498 off
= fdt_add_subnode(fdt
, off
, "power-mgt");
500 _FDT(fdt_setprop_cell(fdt
, off
, "ibm,enabled-stop-levels", 0xc0000000));
503 static void *pnv_dt_create(MachineState
*machine
)
505 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
506 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
512 fdt
= g_malloc0(FDT_MAX_SIZE
);
513 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
516 _FDT((fdt_add_subnode(fdt
, 0, "qemu")));
519 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
520 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
521 _FDT((fdt_setprop_string(fdt
, 0, "model",
522 "IBM PowerNV (emulated by qemu)")));
523 _FDT((fdt_setprop(fdt
, 0, "compatible", pmc
->compat
, pmc
->compat_size
)));
525 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
526 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
528 _FDT((fdt_property_string(fdt
, "system-id", buf
)));
532 off
= fdt_add_subnode(fdt
, 0, "chosen");
533 if (machine
->kernel_cmdline
) {
534 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
535 machine
->kernel_cmdline
)));
538 if (pnv
->initrd_size
) {
539 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
540 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
542 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
543 &start_prop
, sizeof(start_prop
))));
544 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
545 &end_prop
, sizeof(end_prop
))));
548 /* Populate device tree for each chip */
549 for (i
= 0; i
< pnv
->num_chips
; i
++) {
550 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
553 /* Populate ISA devices on chip 0 */
554 pnv_dt_isa(pnv
, fdt
);
557 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
560 /* Create an extra node for power management on machines that support it */
561 if (pmc
->dt_power_mgt
) {
562 pmc
->dt_power_mgt(pnv
, fdt
);
568 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
570 PnvMachineState
*pnv
= container_of(n
, PnvMachineState
, powerdown_notifier
);
573 pnv_bmc_powerdown(pnv
->bmc
);
577 static void pnv_reset(MachineState
*machine
)
579 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
583 qemu_devices_reset();
586 * The machine should provide by default an internal BMC simulator.
587 * If not, try to use the BMC device that was provided on the command
590 bmc
= pnv_bmc_find(&error_fatal
);
593 if (!qtest_enabled()) {
594 warn_report("machine has no BMC device. Use '-device "
595 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
599 pnv_bmc_set_pnor(bmc
, pnv
->pnor
);
604 fdt
= pnv_dt_create(machine
);
606 /* Pack resulting tree */
607 _FDT((fdt_pack(fdt
)));
609 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
610 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
615 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
617 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
618 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
621 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
623 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
624 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
627 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
629 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
630 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
633 static ISABus
*pnv_chip_power10_isa_create(PnvChip
*chip
, Error
**errp
)
635 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
636 return pnv_lpc_isa_create(&chip10
->lpc
, false, errp
);
639 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
641 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
644 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
646 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
649 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
650 for (i
= 0; i
< chip
->num_phbs
; i
++) {
651 pnv_phb3_msi_pic_print_info(&chip8
->phbs
[i
].msis
, mon
);
652 ics_pic_print_info(&chip8
->phbs
[i
].lsis
, mon
);
656 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
658 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
661 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
662 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
664 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
665 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
666 for (j
= 0; j
< pec
->num_stacks
; j
++) {
667 pnv_phb4_pic_print_info(&pec
->stacks
[j
].phb
, mon
);
672 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip
*chip
,
675 return PNV_XSCOM_EX_BASE(core_id
);
678 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip
*chip
,
681 return PNV9_XSCOM_EC_BASE(core_id
);
684 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip
*chip
,
687 return PNV10_XSCOM_EC_BASE(core_id
);
690 static bool pnv_match_cpu(const char *default_type
, const char *cpu_type
)
692 PowerPCCPUClass
*ppc_default
=
693 POWERPC_CPU_CLASS(object_class_by_name(default_type
));
694 PowerPCCPUClass
*ppc
=
695 POWERPC_CPU_CLASS(object_class_by_name(cpu_type
));
697 return ppc_default
->pvr_match(ppc_default
, ppc
->pvr
);
700 static void pnv_ipmi_bt_init(ISABus
*bus
, IPMIBmc
*bmc
, uint32_t irq
)
702 ISADevice
*dev
= isa_new("isa-ipmi-bt");
704 object_property_set_link(OBJECT(dev
), "bmc", OBJECT(bmc
), &error_fatal
);
705 object_property_set_int(OBJECT(dev
), "irq", irq
, &error_fatal
);
706 isa_realize_and_unref(dev
, bus
, &error_fatal
);
709 static void pnv_chip_power10_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
711 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
713 pnv_psi_pic_print_info(&chip10
->psi
, mon
);
716 static void pnv_init(MachineState
*machine
)
718 const char *bios_name
= machine
->firmware
?: FW_FILE_NAME
;
719 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
720 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
725 DriveInfo
*pnor
= drive_get(IF_MTD
, 0, 0);
729 if (machine
->ram_size
< mc
->default_ram_size
) {
730 char *sz
= size_to_str(mc
->default_ram_size
);
731 error_report("Invalid RAM size, should be bigger than %s", sz
);
735 memory_region_add_subregion(get_system_memory(), 0, machine
->ram
);
738 * Create our simple PNOR device
740 dev
= qdev_new(TYPE_PNV_PNOR
);
742 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(pnor
));
744 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
745 pnv
->pnor
= PNV_PNOR(dev
);
747 /* load skiboot firmware */
748 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
750 error_report("Could not find OPAL firmware '%s'", bios_name
);
754 fw_size
= load_image_targphys(fw_filename
, pnv
->fw_load_addr
, FW_MAX_SIZE
);
756 error_report("Could not load OPAL firmware '%s'", fw_filename
);
762 if (machine
->kernel_filename
) {
765 kernel_size
= load_image_targphys(machine
->kernel_filename
,
766 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
767 if (kernel_size
< 0) {
768 error_report("Could not load kernel '%s'",
769 machine
->kernel_filename
);
775 if (machine
->initrd_filename
) {
776 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
777 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
778 pnv
->initrd_base
, INITRD_MAX_SIZE
);
779 if (pnv
->initrd_size
< 0) {
780 error_report("Could not load initial ram disk '%s'",
781 machine
->initrd_filename
);
786 /* MSIs are supported on this platform */
787 msi_nonbroken
= true;
790 * Check compatibility of the specified CPU with the machine
793 if (!pnv_match_cpu(mc
->default_cpu_type
, machine
->cpu_type
)) {
794 error_report("invalid CPU model '%s' for %s machine",
795 machine
->cpu_type
, mc
->name
);
799 /* Create the processor chips */
800 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
801 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
802 i
, machine
->cpu_type
);
803 if (!object_class_by_name(chip_typename
)) {
804 error_report("invalid chip model '%.*s' for %s machine",
805 i
, machine
->cpu_type
, mc
->name
);
810 machine
->smp
.max_cpus
/ (machine
->smp
.cores
* machine
->smp
.threads
);
812 * TODO: should we decide on how many chips we can create based
813 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
815 if (!is_power_of_2(pnv
->num_chips
) || pnv
->num_chips
> 4) {
816 error_report("invalid number of chips: '%d'", pnv
->num_chips
);
817 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
821 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
822 for (i
= 0; i
< pnv
->num_chips
; i
++) {
824 Object
*chip
= OBJECT(qdev_new(chip_typename
));
826 pnv
->chips
[i
] = PNV_CHIP(chip
);
829 * TODO: put all the memory in one node on chip 0 until we find a
830 * way to specify different ranges for each chip
833 object_property_set_int(chip
, "ram-size", machine
->ram_size
,
837 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", PNV_CHIP_HWID(i
));
838 object_property_add_child(OBJECT(pnv
), chip_name
, chip
);
839 object_property_set_int(chip
, "chip-id", PNV_CHIP_HWID(i
),
841 object_property_set_int(chip
, "nr-cores", machine
->smp
.cores
,
843 object_property_set_int(chip
, "nr-threads", machine
->smp
.threads
,
846 * The POWER8 machine use the XICS interrupt interface.
847 * Propagate the XICS fabric to the chip and its controllers.
849 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XICS_FABRIC
)) {
850 object_property_set_link(chip
, "xics", OBJECT(pnv
), &error_abort
);
852 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XIVE_FABRIC
)) {
853 object_property_set_link(chip
, "xive-fabric", OBJECT(pnv
),
856 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip
), &error_fatal
);
858 g_free(chip_typename
);
860 /* Instantiate ISA bus on chip 0 */
861 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
863 /* Create serial port */
864 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
866 /* Create an RTC ISA device too */
867 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
870 * Create the machine BMC simulator and the IPMI BT device for
871 * communication with the BMC
873 if (defaults_enabled()) {
874 pnv
->bmc
= pnv_bmc_create(pnv
->pnor
);
875 pnv_ipmi_bt_init(pnv
->isa_bus
, pnv
->bmc
, 10);
879 * The PNOR is mapped on the LPC FW address space by the BMC.
880 * Since we can not reach the remote BMC machine with LPC memops,
881 * map it always for now.
883 memory_region_add_subregion(pnv
->chips
[0]->fw_mr
, PNOR_SPI_OFFSET
,
887 * OpenPOWER systems use a IPMI SEL Event message to notify the
890 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
891 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
895 * 0:21 Reserved - Read as zeros
900 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
902 return (chip
->chip_id
<< 7) | (core_id
<< 3);
905 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
908 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
909 Error
*local_err
= NULL
;
911 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
913 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, chip8
->xics
, &local_err
);
915 error_propagate(errp
, local_err
);
923 static void pnv_chip_power8_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
925 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
927 icp_reset(ICP(pnv_cpu
->intc
));
930 static void pnv_chip_power8_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
932 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
934 icp_destroy(ICP(pnv_cpu
->intc
));
935 pnv_cpu
->intc
= NULL
;
938 static void pnv_chip_power8_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
941 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
945 * 0:48 Reserved - Read as zeroes
948 * 56 Reserved - Read as zero
952 * We only care about the lower bits. uint32_t is fine for the moment.
954 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
956 return (chip
->chip_id
<< 8) | (core_id
<< 2);
959 static uint32_t pnv_chip_core_pir_p10(PnvChip
*chip
, uint32_t core_id
)
961 return (chip
->chip_id
<< 8) | (core_id
<< 2);
964 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
967 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
968 Error
*local_err
= NULL
;
970 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
973 * The core creates its interrupt presenter but the XIVE interrupt
974 * controller object is initialized afterwards. Hopefully, it's
975 * only used at runtime.
977 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip9
->xive
),
980 error_propagate(errp
, local_err
);
987 static void pnv_chip_power9_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
989 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
991 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
994 static void pnv_chip_power9_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
996 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
998 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
999 pnv_cpu
->intc
= NULL
;
1002 static void pnv_chip_power9_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1005 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1008 static void pnv_chip_power10_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1011 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1013 /* Will be defined when the interrupt controller is */
1014 pnv_cpu
->intc
= NULL
;
1017 static void pnv_chip_power10_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1022 static void pnv_chip_power10_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1024 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1026 pnv_cpu
->intc
= NULL
;
1029 static void pnv_chip_power10_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1035 * Allowed core identifiers on a POWER8 Processor Chip :
1044 * <EX7,8 reserved> <reserved>
1046 * EX10 - Venice only
1047 * EX11 - Venice only
1053 #define POWER8E_CORE_MASK (0x7070ull)
1054 #define POWER8_CORE_MASK (0x7e7eull)
1057 * POWER9 has 24 cores, ids starting at 0x0
1059 #define POWER9_CORE_MASK (0xffffffffffffffull)
1062 #define POWER10_CORE_MASK (0xffffffffffffffull)
1064 static void pnv_chip_power8_instance_init(Object
*obj
)
1066 PnvChip
*chip
= PNV_CHIP(obj
);
1067 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
1068 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1071 object_property_add_link(obj
, "xics", TYPE_XICS_FABRIC
,
1072 (Object
**)&chip8
->xics
,
1073 object_property_allow_set_link
,
1074 OBJ_PROP_LINK_STRONG
);
1076 object_initialize_child(obj
, "psi", &chip8
->psi
, TYPE_PNV8_PSI
);
1078 object_initialize_child(obj
, "lpc", &chip8
->lpc
, TYPE_PNV8_LPC
);
1080 object_initialize_child(obj
, "occ", &chip8
->occ
, TYPE_PNV8_OCC
);
1082 object_initialize_child(obj
, "homer", &chip8
->homer
, TYPE_PNV8_HOMER
);
1084 for (i
= 0; i
< pcc
->num_phbs
; i
++) {
1085 object_initialize_child(obj
, "phb[*]", &chip8
->phbs
[i
], TYPE_PNV_PHB3
);
1089 * Number of PHBs is the chip default
1091 chip
->num_phbs
= pcc
->num_phbs
;
1094 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
1096 PnvChip
*chip
= PNV_CHIP(chip8
);
1097 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1101 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
1102 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
1103 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip8
->icp_mmio
);
1106 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
1108 /* Map the ICP registers for each thread */
1109 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1110 PnvCore
*pnv_core
= chip
->cores
[i
];
1111 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
1113 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
1114 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
1115 PnvICPState
*icp
= PNV_ICP(xics_icp_get(chip8
->xics
, pir
));
1117 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
1123 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
1125 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1126 PnvChip
*chip
= PNV_CHIP(dev
);
1127 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
1128 Pnv8Psi
*psi8
= &chip8
->psi
;
1129 Error
*local_err
= NULL
;
1132 assert(chip8
->xics
);
1134 /* XSCOM bridge is first */
1135 pnv_xscom_realize(chip
, PNV_XSCOM_SIZE
, &local_err
);
1137 error_propagate(errp
, local_err
);
1140 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
1142 pcc
->parent_realize(dev
, &local_err
);
1144 error_propagate(errp
, local_err
);
1148 /* Processor Service Interface (PSI) Host Bridge */
1149 object_property_set_int(OBJECT(&chip8
->psi
), "bar", PNV_PSIHB_BASE(chip
),
1151 object_property_set_link(OBJECT(&chip8
->psi
), ICS_PROP_XICS
,
1152 OBJECT(chip8
->xics
), &error_abort
);
1153 if (!qdev_realize(DEVICE(&chip8
->psi
), NULL
, errp
)) {
1156 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
1157 &PNV_PSI(psi8
)->xscom_regs
);
1159 /* Create LPC controller */
1160 object_property_set_link(OBJECT(&chip8
->lpc
), "psi", OBJECT(&chip8
->psi
),
1162 qdev_realize(DEVICE(&chip8
->lpc
), NULL
, &error_fatal
);
1163 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
1165 chip
->fw_mr
= &chip8
->lpc
.isa_fw
;
1166 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
1167 (uint64_t) PNV_XSCOM_BASE(chip
),
1168 PNV_XSCOM_LPC_BASE
);
1171 * Interrupt Management Area. This is the memory region holding
1172 * all the Interrupt Control Presenter (ICP) registers
1174 pnv_chip_icp_realize(chip8
, &local_err
);
1176 error_propagate(errp
, local_err
);
1180 /* Create the simplified OCC model */
1181 object_property_set_link(OBJECT(&chip8
->occ
), "psi", OBJECT(&chip8
->psi
),
1183 if (!qdev_realize(DEVICE(&chip8
->occ
), NULL
, errp
)) {
1186 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
1188 /* OCC SRAM model */
1189 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip
),
1190 &chip8
->occ
.sram_regs
);
1193 object_property_set_link(OBJECT(&chip8
->homer
), "chip", OBJECT(chip
),
1195 if (!qdev_realize(DEVICE(&chip8
->homer
), NULL
, errp
)) {
1198 /* Homer Xscom region */
1199 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PBA_BASE
, &chip8
->homer
.pba_regs
);
1201 /* Homer mmio region */
1202 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip
),
1203 &chip8
->homer
.regs
);
1205 /* PHB3 controllers */
1206 for (i
= 0; i
< chip
->num_phbs
; i
++) {
1207 PnvPHB3
*phb
= &chip8
->phbs
[i
];
1208 PnvPBCQState
*pbcq
= &phb
->pbcq
;
1210 object_property_set_int(OBJECT(phb
), "index", i
, &error_fatal
);
1211 object_property_set_int(OBJECT(phb
), "chip-id", chip
->chip_id
,
1213 if (!sysbus_realize(SYS_BUS_DEVICE(phb
), errp
)) {
1217 /* Populate the XSCOM address space. */
1218 pnv_xscom_add_subregion(chip
,
1219 PNV_XSCOM_PBCQ_NEST_BASE
+ 0x400 * phb
->phb_id
,
1220 &pbcq
->xscom_nest_regs
);
1221 pnv_xscom_add_subregion(chip
,
1222 PNV_XSCOM_PBCQ_PCI_BASE
+ 0x400 * phb
->phb_id
,
1223 &pbcq
->xscom_pci_regs
);
1224 pnv_xscom_add_subregion(chip
,
1225 PNV_XSCOM_PBCQ_SPCI_BASE
+ 0x040 * phb
->phb_id
,
1226 &pbcq
->xscom_spci_regs
);
1230 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1232 addr
&= (PNV_XSCOM_SIZE
- 1);
1233 return ((addr
>> 4) & ~0xfull
) | ((addr
>> 3) & 0xf);
1236 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
1238 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1239 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1241 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
1242 k
->cores_mask
= POWER8E_CORE_MASK
;
1244 k
->core_pir
= pnv_chip_core_pir_p8
;
1245 k
->intc_create
= pnv_chip_power8_intc_create
;
1246 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1247 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1248 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1249 k
->isa_create
= pnv_chip_power8_isa_create
;
1250 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1251 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1252 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1253 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1254 dc
->desc
= "PowerNV Chip POWER8E";
1256 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1257 &k
->parent_realize
);
1260 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
1262 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1263 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1265 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
1266 k
->cores_mask
= POWER8_CORE_MASK
;
1268 k
->core_pir
= pnv_chip_core_pir_p8
;
1269 k
->intc_create
= pnv_chip_power8_intc_create
;
1270 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1271 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1272 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1273 k
->isa_create
= pnv_chip_power8_isa_create
;
1274 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1275 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1276 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1277 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1278 dc
->desc
= "PowerNV Chip POWER8";
1280 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1281 &k
->parent_realize
);
1284 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
1286 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1287 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1289 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
1290 k
->cores_mask
= POWER8_CORE_MASK
;
1292 k
->core_pir
= pnv_chip_core_pir_p8
;
1293 k
->intc_create
= pnv_chip_power8_intc_create
;
1294 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1295 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1296 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1297 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
1298 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1299 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1300 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1301 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1302 dc
->desc
= "PowerNV Chip POWER8NVL";
1304 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1305 &k
->parent_realize
);
1308 static void pnv_chip_power9_instance_init(Object
*obj
)
1310 PnvChip
*chip
= PNV_CHIP(obj
);
1311 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
1312 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1315 object_initialize_child(obj
, "xive", &chip9
->xive
, TYPE_PNV_XIVE
);
1316 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip9
->xive
),
1319 object_initialize_child(obj
, "psi", &chip9
->psi
, TYPE_PNV9_PSI
);
1321 object_initialize_child(obj
, "lpc", &chip9
->lpc
, TYPE_PNV9_LPC
);
1323 object_initialize_child(obj
, "occ", &chip9
->occ
, TYPE_PNV9_OCC
);
1325 object_initialize_child(obj
, "homer", &chip9
->homer
, TYPE_PNV9_HOMER
);
1327 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
1328 object_initialize_child(obj
, "pec[*]", &chip9
->pecs
[i
],
1333 * Number of PHBs is the chip default
1335 chip
->num_phbs
= pcc
->num_phbs
;
1338 static void pnv_chip_quad_realize(Pnv9Chip
*chip9
, Error
**errp
)
1340 PnvChip
*chip
= PNV_CHIP(chip9
);
1343 chip9
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1344 chip9
->quads
= g_new0(PnvQuad
, chip9
->nr_quads
);
1346 for (i
= 0; i
< chip9
->nr_quads
; i
++) {
1348 PnvQuad
*eq
= &chip9
->quads
[i
];
1349 PnvCore
*pnv_core
= chip
->cores
[i
* 4];
1350 int core_id
= CPU_CORE(pnv_core
)->core_id
;
1352 snprintf(eq_name
, sizeof(eq_name
), "eq[%d]", core_id
);
1353 object_initialize_child_with_props(OBJECT(chip
), eq_name
, eq
,
1354 sizeof(*eq
), TYPE_PNV_QUAD
,
1355 &error_fatal
, NULL
);
1357 object_property_set_int(OBJECT(eq
), "id", core_id
, &error_fatal
);
1358 qdev_realize(DEVICE(eq
), NULL
, &error_fatal
);
1360 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_EQ_BASE(eq
->id
),
1365 static void pnv_chip_power9_phb_realize(PnvChip
*chip
, Error
**errp
)
1367 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1371 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
1372 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
1373 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1374 uint32_t pec_nest_base
;
1375 uint32_t pec_pci_base
;
1377 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1383 object_property_set_int(OBJECT(pec
), "num-stacks", i
+ 1,
1385 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1387 object_property_set_link(OBJECT(pec
), "system-memory",
1388 OBJECT(get_system_memory()), &error_abort
);
1389 if (!qdev_realize(DEVICE(pec
), NULL
, errp
)) {
1393 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1394 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1396 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1397 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1399 for (j
= 0; j
< pec
->num_stacks
&& phb_id
< chip
->num_phbs
;
1401 PnvPhb4PecStack
*stack
= &pec
->stacks
[j
];
1402 Object
*obj
= OBJECT(&stack
->phb
);
1404 object_property_set_int(obj
, "index", phb_id
, &error_fatal
);
1405 object_property_set_int(obj
, "chip-id", chip
->chip_id
,
1407 object_property_set_int(obj
, "version", PNV_PHB4_VERSION
,
1409 object_property_set_int(obj
, "device-id", PNV_PHB4_DEVICE_ID
,
1411 object_property_set_link(obj
, "stack", OBJECT(stack
),
1413 if (!sysbus_realize(SYS_BUS_DEVICE(obj
), errp
)) {
1417 /* Populate the XSCOM address space. */
1418 pnv_xscom_add_subregion(chip
,
1419 pec_nest_base
+ 0x40 * (stack
->stack_no
+ 1),
1420 &stack
->nest_regs_mr
);
1421 pnv_xscom_add_subregion(chip
,
1422 pec_pci_base
+ 0x40 * (stack
->stack_no
+ 1),
1423 &stack
->pci_regs_mr
);
1424 pnv_xscom_add_subregion(chip
,
1425 pec_pci_base
+ PNV9_XSCOM_PEC_PCI_STK0
+
1426 0x40 * stack
->stack_no
,
1427 &stack
->phb_regs_mr
);
1432 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
1434 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1435 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
1436 PnvChip
*chip
= PNV_CHIP(dev
);
1437 Pnv9Psi
*psi9
= &chip9
->psi
;
1438 Error
*local_err
= NULL
;
1440 /* XSCOM bridge is first */
1441 pnv_xscom_realize(chip
, PNV9_XSCOM_SIZE
, &local_err
);
1443 error_propagate(errp
, local_err
);
1446 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV9_XSCOM_BASE(chip
));
1448 pcc
->parent_realize(dev
, &local_err
);
1450 error_propagate(errp
, local_err
);
1454 pnv_chip_quad_realize(chip9
, &local_err
);
1456 error_propagate(errp
, local_err
);
1460 /* XIVE interrupt controller (POWER9) */
1461 object_property_set_int(OBJECT(&chip9
->xive
), "ic-bar",
1462 PNV9_XIVE_IC_BASE(chip
), &error_fatal
);
1463 object_property_set_int(OBJECT(&chip9
->xive
), "vc-bar",
1464 PNV9_XIVE_VC_BASE(chip
), &error_fatal
);
1465 object_property_set_int(OBJECT(&chip9
->xive
), "pc-bar",
1466 PNV9_XIVE_PC_BASE(chip
), &error_fatal
);
1467 object_property_set_int(OBJECT(&chip9
->xive
), "tm-bar",
1468 PNV9_XIVE_TM_BASE(chip
), &error_fatal
);
1469 object_property_set_link(OBJECT(&chip9
->xive
), "chip", OBJECT(chip
),
1471 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9
->xive
), errp
)) {
1474 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
1475 &chip9
->xive
.xscom_regs
);
1477 /* Processor Service Interface (PSI) Host Bridge */
1478 object_property_set_int(OBJECT(&chip9
->psi
), "bar", PNV9_PSIHB_BASE(chip
),
1480 if (!qdev_realize(DEVICE(&chip9
->psi
), NULL
, errp
)) {
1483 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1484 &PNV_PSI(psi9
)->xscom_regs
);
1487 object_property_set_link(OBJECT(&chip9
->lpc
), "psi", OBJECT(&chip9
->psi
),
1489 if (!qdev_realize(DEVICE(&chip9
->lpc
), NULL
, errp
)) {
1492 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1493 &chip9
->lpc
.xscom_regs
);
1495 chip
->fw_mr
= &chip9
->lpc
.isa_fw
;
1496 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1497 (uint64_t) PNV9_LPCM_BASE(chip
));
1499 /* Create the simplified OCC model */
1500 object_property_set_link(OBJECT(&chip9
->occ
), "psi", OBJECT(&chip9
->psi
),
1502 if (!qdev_realize(DEVICE(&chip9
->occ
), NULL
, errp
)) {
1505 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_OCC_BASE
, &chip9
->occ
.xscom_regs
);
1507 /* OCC SRAM model */
1508 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip
),
1509 &chip9
->occ
.sram_regs
);
1512 object_property_set_link(OBJECT(&chip9
->homer
), "chip", OBJECT(chip
),
1514 if (!qdev_realize(DEVICE(&chip9
->homer
), NULL
, errp
)) {
1517 /* Homer Xscom region */
1518 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PBA_BASE
, &chip9
->homer
.pba_regs
);
1520 /* Homer mmio region */
1521 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip
),
1522 &chip9
->homer
.regs
);
1525 pnv_chip_power9_phb_realize(chip
, &local_err
);
1527 error_propagate(errp
, local_err
);
1532 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1534 addr
&= (PNV9_XSCOM_SIZE
- 1);
1538 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1540 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1541 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1543 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1544 k
->cores_mask
= POWER9_CORE_MASK
;
1545 k
->core_pir
= pnv_chip_core_pir_p9
;
1546 k
->intc_create
= pnv_chip_power9_intc_create
;
1547 k
->intc_reset
= pnv_chip_power9_intc_reset
;
1548 k
->intc_destroy
= pnv_chip_power9_intc_destroy
;
1549 k
->intc_print_info
= pnv_chip_power9_intc_print_info
;
1550 k
->isa_create
= pnv_chip_power9_isa_create
;
1551 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1552 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1553 k
->xscom_core_base
= pnv_chip_power9_xscom_core_base
;
1554 k
->xscom_pcba
= pnv_chip_power9_xscom_pcba
;
1555 dc
->desc
= "PowerNV Chip POWER9";
1558 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1559 &k
->parent_realize
);
1562 static void pnv_chip_power10_instance_init(Object
*obj
)
1564 Pnv10Chip
*chip10
= PNV10_CHIP(obj
);
1566 object_initialize_child(obj
, "psi", &chip10
->psi
, TYPE_PNV10_PSI
);
1567 object_initialize_child(obj
, "lpc", &chip10
->lpc
, TYPE_PNV10_LPC
);
1570 static void pnv_chip_power10_realize(DeviceState
*dev
, Error
**errp
)
1572 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1573 PnvChip
*chip
= PNV_CHIP(dev
);
1574 Pnv10Chip
*chip10
= PNV10_CHIP(dev
);
1575 Error
*local_err
= NULL
;
1577 /* XSCOM bridge is first */
1578 pnv_xscom_realize(chip
, PNV10_XSCOM_SIZE
, &local_err
);
1580 error_propagate(errp
, local_err
);
1583 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV10_XSCOM_BASE(chip
));
1585 pcc
->parent_realize(dev
, &local_err
);
1587 error_propagate(errp
, local_err
);
1591 /* Processor Service Interface (PSI) Host Bridge */
1592 object_property_set_int(OBJECT(&chip10
->psi
), "bar",
1593 PNV10_PSIHB_BASE(chip
), &error_fatal
);
1594 if (!qdev_realize(DEVICE(&chip10
->psi
), NULL
, errp
)) {
1597 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PSIHB_BASE
,
1598 &PNV_PSI(&chip10
->psi
)->xscom_regs
);
1601 object_property_set_link(OBJECT(&chip10
->lpc
), "psi",
1602 OBJECT(&chip10
->psi
), &error_abort
);
1603 if (!qdev_realize(DEVICE(&chip10
->lpc
), NULL
, errp
)) {
1606 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip
),
1607 &chip10
->lpc
.xscom_regs
);
1609 chip
->fw_mr
= &chip10
->lpc
.isa_fw
;
1610 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1611 (uint64_t) PNV10_LPCM_BASE(chip
));
1614 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1616 addr
&= (PNV10_XSCOM_SIZE
- 1);
1620 static void pnv_chip_power10_class_init(ObjectClass
*klass
, void *data
)
1622 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1623 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1625 k
->chip_cfam_id
= 0x120da04900008000ull
; /* P10 DD1.0 (with NX) */
1626 k
->cores_mask
= POWER10_CORE_MASK
;
1627 k
->core_pir
= pnv_chip_core_pir_p10
;
1628 k
->intc_create
= pnv_chip_power10_intc_create
;
1629 k
->intc_reset
= pnv_chip_power10_intc_reset
;
1630 k
->intc_destroy
= pnv_chip_power10_intc_destroy
;
1631 k
->intc_print_info
= pnv_chip_power10_intc_print_info
;
1632 k
->isa_create
= pnv_chip_power10_isa_create
;
1633 k
->dt_populate
= pnv_chip_power10_dt_populate
;
1634 k
->pic_print_info
= pnv_chip_power10_pic_print_info
;
1635 k
->xscom_core_base
= pnv_chip_power10_xscom_core_base
;
1636 k
->xscom_pcba
= pnv_chip_power10_xscom_pcba
;
1637 dc
->desc
= "PowerNV Chip POWER10";
1639 device_class_set_parent_realize(dc
, pnv_chip_power10_realize
,
1640 &k
->parent_realize
);
1643 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
1645 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1649 * No custom mask for this chip, let's use the default one from *
1652 if (!chip
->cores_mask
) {
1653 chip
->cores_mask
= pcc
->cores_mask
;
1656 /* filter alien core ids ! some are reserved */
1657 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
1658 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
1662 chip
->cores_mask
&= pcc
->cores_mask
;
1664 /* now that we have a sane layout, let check the number of cores */
1665 cores_max
= ctpop64(chip
->cores_mask
);
1666 if (chip
->nr_cores
> cores_max
) {
1667 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
1673 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
1675 Error
*error
= NULL
;
1676 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1677 const char *typename
= pnv_chip_core_typename(chip
);
1679 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
1681 if (!object_class_by_name(typename
)) {
1682 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
1687 pnv_chip_core_sanitize(chip
, &error
);
1689 error_propagate(errp
, error
);
1693 chip
->cores
= g_new0(PnvCore
*, chip
->nr_cores
);
1695 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
1696 && (i
< chip
->nr_cores
); core_hwid
++) {
1699 uint64_t xscom_core_base
;
1701 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
1705 pnv_core
= PNV_CORE(object_new(typename
));
1707 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
1708 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
));
1709 chip
->cores
[i
] = pnv_core
;
1710 object_property_set_int(OBJECT(pnv_core
), "nr-threads",
1711 chip
->nr_threads
, &error_fatal
);
1712 object_property_set_int(OBJECT(pnv_core
), CPU_CORE_PROP_CORE_ID
,
1713 core_hwid
, &error_fatal
);
1714 object_property_set_int(OBJECT(pnv_core
), "pir",
1715 pcc
->core_pir(chip
, core_hwid
), &error_fatal
);
1716 object_property_set_int(OBJECT(pnv_core
), "hrmor", pnv
->fw_load_addr
,
1718 object_property_set_link(OBJECT(pnv_core
), "chip", OBJECT(chip
),
1720 qdev_realize(DEVICE(pnv_core
), NULL
, &error_fatal
);
1722 /* Each core has an XSCOM MMIO region */
1723 xscom_core_base
= pcc
->xscom_core_base(chip
, core_hwid
);
1725 pnv_xscom_add_subregion(chip
, xscom_core_base
,
1726 &pnv_core
->xscom_regs
);
1731 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
1733 PnvChip
*chip
= PNV_CHIP(dev
);
1734 Error
*error
= NULL
;
1737 pnv_chip_core_realize(chip
, &error
);
1739 error_propagate(errp
, error
);
1744 static Property pnv_chip_properties
[] = {
1745 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
1746 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
1747 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
1748 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
1749 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
1750 DEFINE_PROP_UINT32("nr-threads", PnvChip
, nr_threads
, 1),
1751 DEFINE_PROP_UINT32("num-phbs", PnvChip
, num_phbs
, 0),
1752 DEFINE_PROP_END_OF_LIST(),
1755 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
1757 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1759 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
1760 dc
->realize
= pnv_chip_realize
;
1761 device_class_set_props(dc
, pnv_chip_properties
);
1762 dc
->desc
= "PowerNV Chip";
1765 PowerPCCPU
*pnv_chip_find_cpu(PnvChip
*chip
, uint32_t pir
)
1769 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1770 PnvCore
*pc
= chip
->cores
[i
];
1771 CPUCore
*cc
= CPU_CORE(pc
);
1773 for (j
= 0; j
< cc
->nr_threads
; j
++) {
1774 if (ppc_cpu_pir(pc
->threads
[j
]) == pir
) {
1775 return pc
->threads
[j
];
1782 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
1784 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1787 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1788 PnvChip
*chip
= pnv
->chips
[i
];
1789 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1791 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
1792 return &chip8
->psi
.ics
;
1794 for (j
= 0; j
< chip
->num_phbs
; j
++) {
1795 if (ics_valid_irq(&chip8
->phbs
[j
].lsis
, irq
)) {
1796 return &chip8
->phbs
[j
].lsis
;
1798 if (ics_valid_irq(ICS(&chip8
->phbs
[j
].msis
), irq
)) {
1799 return ICS(&chip8
->phbs
[j
].msis
);
1806 static void pnv_ics_resend(XICSFabric
*xi
)
1808 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1811 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1812 PnvChip
*chip
= pnv
->chips
[i
];
1813 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1815 ics_resend(&chip8
->psi
.ics
);
1816 for (j
= 0; j
< chip
->num_phbs
; j
++) {
1817 ics_resend(&chip8
->phbs
[j
].lsis
);
1818 ics_resend(ICS(&chip8
->phbs
[j
].msis
));
1823 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
1825 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
1827 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
1830 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
1833 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1838 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1840 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1841 PNV_CHIP_GET_CLASS(pnv
->chips
[0])->intc_print_info(pnv
->chips
[0], cpu
,
1845 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1846 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
1850 static int pnv_match_nvt(XiveFabric
*xfb
, uint8_t format
,
1851 uint8_t nvt_blk
, uint32_t nvt_idx
,
1852 bool cam_ignore
, uint8_t priority
,
1853 uint32_t logic_serv
,
1854 XiveTCTXMatch
*match
)
1856 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
1857 int total_count
= 0;
1860 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1861 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
1862 XivePresenter
*xptr
= XIVE_PRESENTER(&chip9
->xive
);
1863 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
1866 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1867 priority
, logic_serv
, match
);
1873 total_count
+= count
;
1879 static void pnv_machine_power8_class_init(ObjectClass
*oc
, void *data
)
1881 MachineClass
*mc
= MACHINE_CLASS(oc
);
1882 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1883 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1884 static const char compat
[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1886 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER8";
1887 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
1889 xic
->icp_get
= pnv_icp_get
;
1890 xic
->ics_get
= pnv_ics_get
;
1891 xic
->ics_resend
= pnv_ics_resend
;
1893 pmc
->compat
= compat
;
1894 pmc
->compat_size
= sizeof(compat
);
1897 static void pnv_machine_power9_class_init(ObjectClass
*oc
, void *data
)
1899 MachineClass
*mc
= MACHINE_CLASS(oc
);
1900 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
1901 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1902 static const char compat
[] = "qemu,powernv9\0ibm,powernv";
1904 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER9";
1905 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
1906 xfc
->match_nvt
= pnv_match_nvt
;
1908 mc
->alias
= "powernv";
1910 pmc
->compat
= compat
;
1911 pmc
->compat_size
= sizeof(compat
);
1912 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
1915 static void pnv_machine_power10_class_init(ObjectClass
*oc
, void *data
)
1917 MachineClass
*mc
= MACHINE_CLASS(oc
);
1918 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1919 static const char compat
[] = "qemu,powernv10\0ibm,powernv";
1921 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10";
1922 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power10_v1.0");
1924 pmc
->compat
= compat
;
1925 pmc
->compat_size
= sizeof(compat
);
1926 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
1929 static bool pnv_machine_get_hb(Object
*obj
, Error
**errp
)
1931 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1933 return !!pnv
->fw_load_addr
;
1936 static void pnv_machine_set_hb(Object
*obj
, bool value
, Error
**errp
)
1938 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1941 pnv
->fw_load_addr
= 0x8000000;
1945 static void pnv_cpu_do_nmi_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
1947 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1948 CPUPPCState
*env
= &cpu
->env
;
1950 cpu_synchronize_state(cs
);
1951 ppc_cpu_do_system_reset(cs
);
1952 if (env
->spr
[SPR_SRR1
] & SRR1_WAKESTATE
) {
1954 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
1955 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
1958 if (!(env
->spr
[SPR_SRR1
] & SRR1_WAKERESET
)) {
1959 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
1960 env
->spr
[SPR_SRR1
] |= SRR1_WAKERESET
;
1964 * For non-powersave system resets, SRR1[42:45] are defined to be
1965 * implementation-dependent. The POWER9 User Manual specifies that
1966 * an external (SCOM driven, which may come from a BMC nmi command or
1967 * another CPU requesting a NMI IPI) system reset exception should be
1968 * 0b0010 (PPC_BIT(44)).
1970 env
->spr
[SPR_SRR1
] |= SRR1_WAKESCOM
;
1974 static void pnv_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
1979 async_run_on_cpu(cs
, pnv_cpu_do_nmi_on_cpu
, RUN_ON_CPU_NULL
);
1983 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
1985 MachineClass
*mc
= MACHINE_CLASS(oc
);
1986 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1987 NMIClass
*nc
= NMI_CLASS(oc
);
1989 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
1990 mc
->init
= pnv_init
;
1991 mc
->reset
= pnv_reset
;
1992 mc
->max_cpus
= MAX_CPUS
;
1993 /* Pnv provides a AHCI device for storage */
1994 mc
->block_default_type
= IF_IDE
;
1995 mc
->no_parallel
= 1;
1996 mc
->default_boot_order
= NULL
;
1998 * RAM defaults to less than 2048 for 32-bit hosts, and large
1999 * enough to fit the maximum initrd size at it's load address
2001 mc
->default_ram_size
= 1 * GiB
;
2002 mc
->default_ram_id
= "pnv.ram";
2003 ispc
->print_info
= pnv_pic_print_info
;
2004 nc
->nmi_monitor_handler
= pnv_nmi
;
2006 object_class_property_add_bool(oc
, "hb-mode",
2007 pnv_machine_get_hb
, pnv_machine_set_hb
);
2008 object_class_property_set_description(oc
, "hb-mode",
2009 "Use a hostboot like boot loader");
2012 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2015 .class_init = class_initfn, \
2016 .parent = TYPE_PNV8_CHIP, \
2019 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2022 .class_init = class_initfn, \
2023 .parent = TYPE_PNV9_CHIP, \
2026 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2029 .class_init = class_initfn, \
2030 .parent = TYPE_PNV10_CHIP, \
2033 static const TypeInfo types
[] = {
2035 .name
= MACHINE_TYPE_NAME("powernv10"),
2036 .parent
= TYPE_PNV_MACHINE
,
2037 .class_init
= pnv_machine_power10_class_init
,
2040 .name
= MACHINE_TYPE_NAME("powernv9"),
2041 .parent
= TYPE_PNV_MACHINE
,
2042 .class_init
= pnv_machine_power9_class_init
,
2043 .interfaces
= (InterfaceInfo
[]) {
2044 { TYPE_XIVE_FABRIC
},
2049 .name
= MACHINE_TYPE_NAME("powernv8"),
2050 .parent
= TYPE_PNV_MACHINE
,
2051 .class_init
= pnv_machine_power8_class_init
,
2052 .interfaces
= (InterfaceInfo
[]) {
2053 { TYPE_XICS_FABRIC
},
2058 .name
= TYPE_PNV_MACHINE
,
2059 .parent
= TYPE_MACHINE
,
2061 .instance_size
= sizeof(PnvMachineState
),
2062 .class_init
= pnv_machine_class_init
,
2063 .class_size
= sizeof(PnvMachineClass
),
2064 .interfaces
= (InterfaceInfo
[]) {
2065 { TYPE_INTERRUPT_STATS_PROVIDER
},
2071 .name
= TYPE_PNV_CHIP
,
2072 .parent
= TYPE_SYS_BUS_DEVICE
,
2073 .class_init
= pnv_chip_class_init
,
2074 .instance_size
= sizeof(PnvChip
),
2075 .class_size
= sizeof(PnvChipClass
),
2080 * P10 chip and variants
2083 .name
= TYPE_PNV10_CHIP
,
2084 .parent
= TYPE_PNV_CHIP
,
2085 .instance_init
= pnv_chip_power10_instance_init
,
2086 .instance_size
= sizeof(Pnv10Chip
),
2088 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10
, pnv_chip_power10_class_init
),
2091 * P9 chip and variants
2094 .name
= TYPE_PNV9_CHIP
,
2095 .parent
= TYPE_PNV_CHIP
,
2096 .instance_init
= pnv_chip_power9_instance_init
,
2097 .instance_size
= sizeof(Pnv9Chip
),
2099 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
2102 * P8 chip and variants
2105 .name
= TYPE_PNV8_CHIP
,
2106 .parent
= TYPE_PNV_CHIP
,
2107 .instance_init
= pnv_chip_power8_instance_init
,
2108 .instance_size
= sizeof(Pnv8Chip
),
2110 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
2111 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
2112 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
2113 pnv_chip_power8nvl_class_init
),