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ppc/pnv: Fix number of I2C engines and ports for power9/10
[mirror_qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
39 #include "hw/nmi.h"
40 #include "qapi/visitor.h"
41 #include "monitor/monitor.h"
42 #include "hw/intc/intc.h"
43 #include "hw/ipmi/ipmi.h"
44 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci-host/pnv_phb.h"
47 #include "hw/pci-host/pnv_phb3.h"
48 #include "hw/pci-host/pnv_phb4.h"
49
50 #include "hw/ppc/xics.h"
51 #include "hw/qdev-properties.h"
52 #include "hw/ppc/pnv_chip.h"
53 #include "hw/ppc/pnv_xscom.h"
54 #include "hw/ppc/pnv_pnor.h"
55
56 #include "hw/isa/isa.h"
57 #include "hw/char/serial.h"
58 #include "hw/rtc/mc146818rtc.h"
59
60 #include <libfdt.h>
61
62 #define FDT_MAX_SIZE (1 * MiB)
63
64 #define FW_FILE_NAME "skiboot.lid"
65 #define FW_LOAD_ADDR 0x0
66 #define FW_MAX_SIZE (16 * MiB)
67
68 #define KERNEL_LOAD_ADDR 0x20000000
69 #define KERNEL_MAX_SIZE (128 * MiB)
70 #define INITRD_LOAD_ADDR 0x28000000
71 #define INITRD_MAX_SIZE (128 * MiB)
72
73 static const char *pnv_chip_core_typename(const PnvChip *o)
74 {
75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
78 const char *core_type = object_class_get_name(object_class_by_name(s));
79 g_free(s);
80 return core_type;
81 }
82
83 /*
84 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
85 * 4 * 4 sockets * 12 cores * 8 threads = 1536
86 * Let's make it 2^11
87 */
88 #define MAX_CPUS 2048
89
90 /*
91 * Memory nodes are created by hostboot, one for each range of memory
92 * that has a different "affinity". In practice, it means one range
93 * per chip.
94 */
95 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
96 {
97 char *mem_name;
98 uint64_t mem_reg_property[2];
99 int off;
100
101 mem_reg_property[0] = cpu_to_be64(start);
102 mem_reg_property[1] = cpu_to_be64(size);
103
104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
105 off = fdt_add_subnode(fdt, 0, mem_name);
106 g_free(mem_name);
107
108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
110 sizeof(mem_reg_property))));
111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
112 }
113
114 static int get_cpus_node(void *fdt)
115 {
116 int cpus_offset = fdt_path_offset(fdt, "/cpus");
117
118 if (cpus_offset < 0) {
119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
120 if (cpus_offset) {
121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
123 }
124 }
125 _FDT(cpus_offset);
126 return cpus_offset;
127 }
128
129 /*
130 * The PowerNV cores (and threads) need to use real HW ids and not an
131 * incremental index like it has been done on other platforms. This HW
132 * id is stored in the CPU PIR, it is used to create cpu nodes in the
133 * device tree, used in XSCOM to address cores and in interrupt
134 * servers.
135 */
136 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
137 {
138 PowerPCCPU *cpu = pc->threads[0];
139 CPUState *cs = CPU(cpu);
140 DeviceClass *dc = DEVICE_GET_CLASS(cs);
141 int smt_threads = CPU_CORE(pc)->nr_threads;
142 CPUPPCState *env = &cpu->env;
143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
145 int i;
146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
147 0xffffffff, 0xffffffff};
148 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
149 uint32_t cpufreq = 1000000000;
150 uint32_t page_sizes_prop[64];
151 size_t page_sizes_prop_size;
152 const uint8_t pa_features[] = { 24, 0,
153 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
157 int offset;
158 char *nodename;
159 int cpus_offset = get_cpus_node(fdt);
160
161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
162 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
163 _FDT(offset);
164 g_free(nodename);
165
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
167
168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
171
172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
174 env->dcache_line_size)));
175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
176 env->dcache_line_size)));
177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
178 env->icache_line_size)));
179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
180 env->icache_line_size)));
181
182 if (pcc->l1_dcache_size) {
183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
184 pcc->l1_dcache_size)));
185 } else {
186 warn_report("Unknown L1 dcache size for cpu");
187 }
188 if (pcc->l1_icache_size) {
189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
190 pcc->l1_icache_size)));
191 } else {
192 warn_report("Unknown L1 icache size for cpu");
193 }
194
195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
198 cpu->hash64_opts->slb_size)));
199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
201
202 if (ppc_has_spr(cpu, SPR_PURR)) {
203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
204 }
205
206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
208 segs, sizeof(segs))));
209 }
210
211 /*
212 * Advertise VMX/VSX (vector extensions) if available
213 * 0 / no property == no vector extensions
214 * 1 == VMX / Altivec available
215 * 2 == VSX available
216 */
217 if (env->insns_flags & PPC_ALTIVEC) {
218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
219
220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
221 }
222
223 /*
224 * Advertise DFP (Decimal Floating Point) if available
225 * 0 / no property == no DFP
226 * 1 == DFP available
227 */
228 if (env->insns_flags2 & PPC2_DFP) {
229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
230 }
231
232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
233 sizeof(page_sizes_prop));
234 if (page_sizes_prop_size) {
235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
236 page_sizes_prop, page_sizes_prop_size)));
237 }
238
239 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
240 pa_features, sizeof(pa_features))));
241
242 /* Build interrupt servers properties */
243 for (i = 0; i < smt_threads; i++) {
244 servers_prop[i] = cpu_to_be32(pc->pir + i);
245 }
246 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
247 servers_prop, sizeof(*servers_prop) * smt_threads)));
248 }
249
250 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
251 uint32_t nr_threads)
252 {
253 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
254 char *name;
255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
256 uint32_t irange[2], i, rsize;
257 uint64_t *reg;
258 int offset;
259
260 irange[0] = cpu_to_be32(pir);
261 irange[1] = cpu_to_be32(nr_threads);
262
263 rsize = sizeof(uint64_t) * 2 * nr_threads;
264 reg = g_malloc(rsize);
265 for (i = 0; i < nr_threads; i++) {
266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
267 reg[i * 2 + 1] = cpu_to_be64(0x1000);
268 }
269
270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
271 offset = fdt_add_subnode(fdt, 0, name);
272 _FDT(offset);
273 g_free(name);
274
275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
277 _FDT((fdt_setprop_string(fdt, offset, "device_type",
278 "PowerPC-External-Interrupt-Presentation")));
279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
281 irange, sizeof(irange))));
282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
284 g_free(reg);
285 }
286
287 /*
288 * Adds a PnvPHB to the chip on P8.
289 * Implemented here, like for defaults PHBs
290 */
291 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
292 {
293 Pnv8Chip *chip8 = PNV8_CHIP(chip);
294
295 phb->chip = chip;
296
297 chip8->phbs[chip8->num_phbs] = phb;
298 chip8->num_phbs++;
299 return chip;
300 }
301
302 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
303 {
304 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
305 int i;
306
307 pnv_dt_xscom(chip, fdt, 0,
308 cpu_to_be64(PNV_XSCOM_BASE(chip)),
309 cpu_to_be64(PNV_XSCOM_SIZE),
310 compat, sizeof(compat));
311
312 for (i = 0; i < chip->nr_cores; i++) {
313 PnvCore *pnv_core = chip->cores[i];
314
315 pnv_dt_core(chip, pnv_core, fdt);
316
317 /* Interrupt Control Presenters (ICP). One per core. */
318 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
319 }
320
321 if (chip->ram_size) {
322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
323 }
324 }
325
326 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
327 {
328 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
329 int i;
330
331 pnv_dt_xscom(chip, fdt, 0,
332 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
333 cpu_to_be64(PNV9_XSCOM_SIZE),
334 compat, sizeof(compat));
335
336 for (i = 0; i < chip->nr_cores; i++) {
337 PnvCore *pnv_core = chip->cores[i];
338
339 pnv_dt_core(chip, pnv_core, fdt);
340 }
341
342 if (chip->ram_size) {
343 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
344 }
345
346 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
347 }
348
349 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
350 {
351 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
352 int i;
353
354 pnv_dt_xscom(chip, fdt, 0,
355 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
356 cpu_to_be64(PNV10_XSCOM_SIZE),
357 compat, sizeof(compat));
358
359 for (i = 0; i < chip->nr_cores; i++) {
360 PnvCore *pnv_core = chip->cores[i];
361
362 pnv_dt_core(chip, pnv_core, fdt);
363 }
364
365 if (chip->ram_size) {
366 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
367 }
368
369 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
370 }
371
372 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
373 {
374 uint32_t io_base = d->ioport_id;
375 uint32_t io_regs[] = {
376 cpu_to_be32(1),
377 cpu_to_be32(io_base),
378 cpu_to_be32(2)
379 };
380 char *name;
381 int node;
382
383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
384 node = fdt_add_subnode(fdt, lpc_off, name);
385 _FDT(node);
386 g_free(name);
387
388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
389 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
390 }
391
392 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
393 {
394 const char compatible[] = "ns16550\0pnpPNP,501";
395 uint32_t io_base = d->ioport_id;
396 uint32_t io_regs[] = {
397 cpu_to_be32(1),
398 cpu_to_be32(io_base),
399 cpu_to_be32(8)
400 };
401 uint32_t irq;
402 char *name;
403 int node;
404
405 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
406
407 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
408 node = fdt_add_subnode(fdt, lpc_off, name);
409 _FDT(node);
410 g_free(name);
411
412 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
413 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
414 sizeof(compatible))));
415
416 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
417 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
418 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
419 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
420 fdt_get_phandle(fdt, lpc_off))));
421
422 /* This is needed by Linux */
423 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
424 }
425
426 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
427 {
428 const char compatible[] = "bt\0ipmi-bt";
429 uint32_t io_base;
430 uint32_t io_regs[] = {
431 cpu_to_be32(1),
432 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
433 cpu_to_be32(3)
434 };
435 uint32_t irq;
436 char *name;
437 int node;
438
439 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
440 io_regs[1] = cpu_to_be32(io_base);
441
442 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
443
444 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
445 node = fdt_add_subnode(fdt, lpc_off, name);
446 _FDT(node);
447 g_free(name);
448
449 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
450 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
451 sizeof(compatible))));
452
453 /* Mark it as reserved to avoid Linux trying to claim it */
454 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
455 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
456 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
457 fdt_get_phandle(fdt, lpc_off))));
458 }
459
460 typedef struct ForeachPopulateArgs {
461 void *fdt;
462 int offset;
463 } ForeachPopulateArgs;
464
465 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
466 {
467 ForeachPopulateArgs *args = opaque;
468 ISADevice *d = ISA_DEVICE(dev);
469
470 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
471 pnv_dt_rtc(d, args->fdt, args->offset);
472 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
473 pnv_dt_serial(d, args->fdt, args->offset);
474 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
475 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
476 } else {
477 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
478 d->ioport_id);
479 }
480
481 return 0;
482 }
483
484 /*
485 * The default LPC bus of a multichip system is on chip 0. It's
486 * recognized by the firmware (skiboot) using a "primary" property.
487 */
488 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
489 {
490 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
491 ForeachPopulateArgs args = {
492 .fdt = fdt,
493 .offset = isa_offset,
494 };
495 uint32_t phandle;
496
497 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
498
499 phandle = qemu_fdt_alloc_phandle(fdt);
500 assert(phandle > 0);
501 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
502
503 /*
504 * ISA devices are not necessarily parented to the ISA bus so we
505 * can not use object_child_foreach()
506 */
507 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
508 &args);
509 }
510
511 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
512 {
513 int off;
514
515 off = fdt_add_subnode(fdt, 0, "ibm,opal");
516 off = fdt_add_subnode(fdt, off, "power-mgt");
517
518 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
519 }
520
521 static void *pnv_dt_create(MachineState *machine)
522 {
523 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
524 PnvMachineState *pnv = PNV_MACHINE(machine);
525 void *fdt;
526 char *buf;
527 int off;
528 int i;
529
530 fdt = g_malloc0(FDT_MAX_SIZE);
531 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
532
533 /* /qemu node */
534 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
535
536 /* Root node */
537 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
538 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
539 _FDT((fdt_setprop_string(fdt, 0, "model",
540 "IBM PowerNV (emulated by qemu)")));
541 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
542
543 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
544 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
545 if (qemu_uuid_set) {
546 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
547 }
548 g_free(buf);
549
550 off = fdt_add_subnode(fdt, 0, "chosen");
551 if (machine->kernel_cmdline) {
552 _FDT((fdt_setprop_string(fdt, off, "bootargs",
553 machine->kernel_cmdline)));
554 }
555
556 if (pnv->initrd_size) {
557 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
558 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
559
560 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
561 &start_prop, sizeof(start_prop))));
562 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
563 &end_prop, sizeof(end_prop))));
564 }
565
566 /* Populate device tree for each chip */
567 for (i = 0; i < pnv->num_chips; i++) {
568 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
569 }
570
571 /* Populate ISA devices on chip 0 */
572 pnv_dt_isa(pnv, fdt);
573
574 if (pnv->bmc) {
575 pnv_dt_bmc_sensors(pnv->bmc, fdt);
576 }
577
578 /* Create an extra node for power management on machines that support it */
579 if (pmc->dt_power_mgt) {
580 pmc->dt_power_mgt(pnv, fdt);
581 }
582
583 return fdt;
584 }
585
586 static void pnv_powerdown_notify(Notifier *n, void *opaque)
587 {
588 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
589
590 if (pnv->bmc) {
591 pnv_bmc_powerdown(pnv->bmc);
592 }
593 }
594
595 static void pnv_reset(MachineState *machine, ShutdownCause reason)
596 {
597 PnvMachineState *pnv = PNV_MACHINE(machine);
598 IPMIBmc *bmc;
599 void *fdt;
600
601 qemu_devices_reset(reason);
602
603 /*
604 * The machine should provide by default an internal BMC simulator.
605 * If not, try to use the BMC device that was provided on the command
606 * line.
607 */
608 bmc = pnv_bmc_find(&error_fatal);
609 if (!pnv->bmc) {
610 if (!bmc) {
611 if (!qtest_enabled()) {
612 warn_report("machine has no BMC device. Use '-device "
613 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
614 "to define one");
615 }
616 } else {
617 pnv_bmc_set_pnor(bmc, pnv->pnor);
618 pnv->bmc = bmc;
619 }
620 }
621
622 fdt = pnv_dt_create(machine);
623
624 /* Pack resulting tree */
625 _FDT((fdt_pack(fdt)));
626
627 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
628 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
629
630 /*
631 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free
632 * the existing machine->fdt to avoid leaking it during
633 * a reset.
634 */
635 g_free(machine->fdt);
636 machine->fdt = fdt;
637 }
638
639 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
640 {
641 Pnv8Chip *chip8 = PNV8_CHIP(chip);
642 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
643
644 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
645 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
646 }
647
648 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
649 {
650 Pnv8Chip *chip8 = PNV8_CHIP(chip);
651 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
652
653 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
654 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
655 }
656
657 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
658 {
659 Pnv9Chip *chip9 = PNV9_CHIP(chip);
660 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
661
662 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
663 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
664 }
665
666 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
667 {
668 Pnv10Chip *chip10 = PNV10_CHIP(chip);
669 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
670
671 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
672 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
673 }
674
675 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
676 {
677 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
678 }
679
680 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
681 {
682 Pnv8Chip *chip8 = PNV8_CHIP(chip);
683 int i;
684
685 ics_pic_print_info(&chip8->psi.ics, mon);
686
687 for (i = 0; i < chip8->num_phbs; i++) {
688 PnvPHB *phb = chip8->phbs[i];
689 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
690
691 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
692 ics_pic_print_info(&phb3->lsis, mon);
693 }
694 }
695
696 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
697 {
698 Monitor *mon = opaque;
699 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
700
701 if (!phb) {
702 return 0;
703 }
704
705 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
706
707 return 0;
708 }
709
710 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
711 {
712 Pnv9Chip *chip9 = PNV9_CHIP(chip);
713
714 pnv_xive_pic_print_info(&chip9->xive, mon);
715 pnv_psi_pic_print_info(&chip9->psi, mon);
716
717 object_child_foreach_recursive(OBJECT(chip),
718 pnv_chip_power9_pic_print_info_child, mon);
719 }
720
721 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
722 uint32_t core_id)
723 {
724 return PNV_XSCOM_EX_BASE(core_id);
725 }
726
727 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
728 uint32_t core_id)
729 {
730 return PNV9_XSCOM_EC_BASE(core_id);
731 }
732
733 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
734 uint32_t core_id)
735 {
736 return PNV10_XSCOM_EC_BASE(core_id);
737 }
738
739 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
740 {
741 PowerPCCPUClass *ppc_default =
742 POWERPC_CPU_CLASS(object_class_by_name(default_type));
743 PowerPCCPUClass *ppc =
744 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
745
746 return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
747 }
748
749 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
750 {
751 ISADevice *dev = isa_new("isa-ipmi-bt");
752
753 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
754 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
755 isa_realize_and_unref(dev, bus, &error_fatal);
756 }
757
758 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
759 {
760 Pnv10Chip *chip10 = PNV10_CHIP(chip);
761
762 pnv_xive2_pic_print_info(&chip10->xive, mon);
763 pnv_psi_pic_print_info(&chip10->psi, mon);
764
765 object_child_foreach_recursive(OBJECT(chip),
766 pnv_chip_power9_pic_print_info_child, mon);
767 }
768
769 /* Always give the first 1GB to chip 0 else we won't boot */
770 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
771 {
772 MachineState *machine = MACHINE(pnv);
773 uint64_t ram_per_chip;
774
775 assert(machine->ram_size >= 1 * GiB);
776
777 ram_per_chip = machine->ram_size / pnv->num_chips;
778 if (ram_per_chip >= 1 * GiB) {
779 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
780 }
781
782 assert(pnv->num_chips > 1);
783
784 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
785 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
786 }
787
788 static void pnv_init(MachineState *machine)
789 {
790 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
791 PnvMachineState *pnv = PNV_MACHINE(machine);
792 MachineClass *mc = MACHINE_GET_CLASS(machine);
793 char *fw_filename;
794 long fw_size;
795 uint64_t chip_ram_start = 0;
796 int i;
797 char *chip_typename;
798 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
799 DeviceState *dev;
800
801 if (kvm_enabled()) {
802 error_report("machine %s does not support the KVM accelerator",
803 mc->name);
804 exit(EXIT_FAILURE);
805 }
806
807 /* allocate RAM */
808 if (machine->ram_size < mc->default_ram_size) {
809 char *sz = size_to_str(mc->default_ram_size);
810 error_report("Invalid RAM size, should be bigger than %s", sz);
811 g_free(sz);
812 exit(EXIT_FAILURE);
813 }
814 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
815
816 /*
817 * Create our simple PNOR device
818 */
819 dev = qdev_new(TYPE_PNV_PNOR);
820 if (pnor) {
821 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
822 }
823 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
824 pnv->pnor = PNV_PNOR(dev);
825
826 /* load skiboot firmware */
827 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
828 if (!fw_filename) {
829 error_report("Could not find OPAL firmware '%s'", bios_name);
830 exit(1);
831 }
832
833 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
834 if (fw_size < 0) {
835 error_report("Could not load OPAL firmware '%s'", fw_filename);
836 exit(1);
837 }
838 g_free(fw_filename);
839
840 /* load kernel */
841 if (machine->kernel_filename) {
842 long kernel_size;
843
844 kernel_size = load_image_targphys(machine->kernel_filename,
845 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
846 if (kernel_size < 0) {
847 error_report("Could not load kernel '%s'",
848 machine->kernel_filename);
849 exit(1);
850 }
851 }
852
853 /* load initrd */
854 if (machine->initrd_filename) {
855 pnv->initrd_base = INITRD_LOAD_ADDR;
856 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
857 pnv->initrd_base, INITRD_MAX_SIZE);
858 if (pnv->initrd_size < 0) {
859 error_report("Could not load initial ram disk '%s'",
860 machine->initrd_filename);
861 exit(1);
862 }
863 }
864
865 /* MSIs are supported on this platform */
866 msi_nonbroken = true;
867
868 /*
869 * Check compatibility of the specified CPU with the machine
870 * default.
871 */
872 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
873 error_report("invalid CPU model '%s' for %s machine",
874 machine->cpu_type, mc->name);
875 exit(1);
876 }
877
878 /* Create the processor chips */
879 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
880 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
881 i, machine->cpu_type);
882 if (!object_class_by_name(chip_typename)) {
883 error_report("invalid chip model '%.*s' for %s machine",
884 i, machine->cpu_type, mc->name);
885 exit(1);
886 }
887
888 pnv->num_chips =
889 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
890
891 if (machine->smp.threads > 8) {
892 error_report("Cannot support more than 8 threads/core "
893 "on a powernv machine");
894 exit(1);
895 }
896 if (!is_power_of_2(machine->smp.threads)) {
897 error_report("Cannot support %d threads/core on a powernv"
898 "machine because it must be a power of 2",
899 machine->smp.threads);
900 exit(1);
901 }
902 /*
903 * TODO: should we decide on how many chips we can create based
904 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
905 */
906 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
907 error_report("invalid number of chips: '%d'", pnv->num_chips);
908 error_printf(
909 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
910 exit(1);
911 }
912
913 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
914 for (i = 0; i < pnv->num_chips; i++) {
915 char chip_name[32];
916 Object *chip = OBJECT(qdev_new(chip_typename));
917 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
918
919 pnv->chips[i] = PNV_CHIP(chip);
920
921 /* Distribute RAM among the chips */
922 object_property_set_int(chip, "ram-start", chip_ram_start,
923 &error_fatal);
924 object_property_set_int(chip, "ram-size", chip_ram_size,
925 &error_fatal);
926 chip_ram_start += chip_ram_size;
927
928 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
929 object_property_add_child(OBJECT(pnv), chip_name, chip);
930 object_property_set_int(chip, "chip-id", i, &error_fatal);
931 object_property_set_int(chip, "nr-cores", machine->smp.cores,
932 &error_fatal);
933 object_property_set_int(chip, "nr-threads", machine->smp.threads,
934 &error_fatal);
935 /*
936 * The POWER8 machine use the XICS interrupt interface.
937 * Propagate the XICS fabric to the chip and its controllers.
938 */
939 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
940 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
941 }
942 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
943 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
944 &error_abort);
945 }
946 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
947 }
948 g_free(chip_typename);
949
950 /* Instantiate ISA bus on chip 0 */
951 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
952
953 /* Create serial port */
954 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
955
956 /* Create an RTC ISA device too */
957 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
958
959 /*
960 * Create the machine BMC simulator and the IPMI BT device for
961 * communication with the BMC
962 */
963 if (defaults_enabled()) {
964 pnv->bmc = pnv_bmc_create(pnv->pnor);
965 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
966 }
967
968 /*
969 * The PNOR is mapped on the LPC FW address space by the BMC.
970 * Since we can not reach the remote BMC machine with LPC memops,
971 * map it always for now.
972 */
973 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
974 &pnv->pnor->mmio);
975
976 /*
977 * OpenPOWER systems use a IPMI SEL Event message to notify the
978 * host to powerdown
979 */
980 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
981 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
982 }
983
984 /*
985 * 0:21 Reserved - Read as zeros
986 * 22:24 Chip ID
987 * 25:28 Core number
988 * 29:31 Thread ID
989 */
990 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
991 {
992 return (chip->chip_id << 7) | (core_id << 3);
993 }
994
995 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
996 Error **errp)
997 {
998 Pnv8Chip *chip8 = PNV8_CHIP(chip);
999 Error *local_err = NULL;
1000 Object *obj;
1001 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1002
1003 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
1004 if (local_err) {
1005 error_propagate(errp, local_err);
1006 return;
1007 }
1008
1009 pnv_cpu->intc = obj;
1010 }
1011
1012
1013 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1014 {
1015 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1016
1017 icp_reset(ICP(pnv_cpu->intc));
1018 }
1019
1020 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1021 {
1022 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1023
1024 icp_destroy(ICP(pnv_cpu->intc));
1025 pnv_cpu->intc = NULL;
1026 }
1027
1028 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1029 Monitor *mon)
1030 {
1031 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1032 }
1033
1034 /*
1035 * 0:48 Reserved - Read as zeroes
1036 * 49:52 Node ID
1037 * 53:55 Chip ID
1038 * 56 Reserved - Read as zero
1039 * 57:61 Core number
1040 * 62:63 Thread ID
1041 *
1042 * We only care about the lower bits. uint32_t is fine for the moment.
1043 */
1044 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
1045 {
1046 return (chip->chip_id << 8) | (core_id << 2);
1047 }
1048
1049 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
1050 {
1051 return (chip->chip_id << 8) | (core_id << 2);
1052 }
1053
1054 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1055 Error **errp)
1056 {
1057 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1058 Error *local_err = NULL;
1059 Object *obj;
1060 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1061
1062 /*
1063 * The core creates its interrupt presenter but the XIVE interrupt
1064 * controller object is initialized afterwards. Hopefully, it's
1065 * only used at runtime.
1066 */
1067 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1068 &local_err);
1069 if (local_err) {
1070 error_propagate(errp, local_err);
1071 return;
1072 }
1073
1074 pnv_cpu->intc = obj;
1075 }
1076
1077 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1078 {
1079 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1080
1081 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1082 }
1083
1084 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1085 {
1086 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1087
1088 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1089 pnv_cpu->intc = NULL;
1090 }
1091
1092 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1093 Monitor *mon)
1094 {
1095 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1096 }
1097
1098 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1099 Error **errp)
1100 {
1101 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1102 Error *local_err = NULL;
1103 Object *obj;
1104 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1105
1106 /*
1107 * The core creates its interrupt presenter but the XIVE2 interrupt
1108 * controller object is initialized afterwards. Hopefully, it's
1109 * only used at runtime.
1110 */
1111 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1112 &local_err);
1113 if (local_err) {
1114 error_propagate(errp, local_err);
1115 return;
1116 }
1117
1118 pnv_cpu->intc = obj;
1119 }
1120
1121 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1122 {
1123 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1124
1125 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1126 }
1127
1128 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1129 {
1130 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1131
1132 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1133 pnv_cpu->intc = NULL;
1134 }
1135
1136 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1137 Monitor *mon)
1138 {
1139 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1140 }
1141
1142 /*
1143 * Allowed core identifiers on a POWER8 Processor Chip :
1144 *
1145 * <EX0 reserved>
1146 * EX1 - Venice only
1147 * EX2 - Venice only
1148 * EX3 - Venice only
1149 * EX4
1150 * EX5
1151 * EX6
1152 * <EX7,8 reserved> <reserved>
1153 * EX9 - Venice only
1154 * EX10 - Venice only
1155 * EX11 - Venice only
1156 * EX12
1157 * EX13
1158 * EX14
1159 * <EX15 reserved>
1160 */
1161 #define POWER8E_CORE_MASK (0x7070ull)
1162 #define POWER8_CORE_MASK (0x7e7eull)
1163
1164 /*
1165 * POWER9 has 24 cores, ids starting at 0x0
1166 */
1167 #define POWER9_CORE_MASK (0xffffffffffffffull)
1168
1169
1170 #define POWER10_CORE_MASK (0xffffffffffffffull)
1171
1172 static void pnv_chip_power8_instance_init(Object *obj)
1173 {
1174 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1175 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1176 int i;
1177
1178 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1179 (Object **)&chip8->xics,
1180 object_property_allow_set_link,
1181 OBJ_PROP_LINK_STRONG);
1182
1183 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1184
1185 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1186
1187 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1188
1189 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1190
1191 if (defaults_enabled()) {
1192 chip8->num_phbs = pcc->num_phbs;
1193
1194 for (i = 0; i < chip8->num_phbs; i++) {
1195 Object *phb = object_new(TYPE_PNV_PHB);
1196
1197 /*
1198 * We need the chip to parent the PHB to allow the DT
1199 * to build correctly (via pnv_xscom_dt()).
1200 *
1201 * TODO: the PHB should be parented by a PEC device that, at
1202 * this moment, is not modelled powernv8/phb3.
1203 */
1204 object_property_add_child(obj, "phb[*]", phb);
1205 chip8->phbs[i] = PNV_PHB(phb);
1206 }
1207 }
1208
1209 }
1210
1211 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1212 {
1213 PnvChip *chip = PNV_CHIP(chip8);
1214 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1215 int i, j;
1216 char *name;
1217
1218 name = g_strdup_printf("icp-%x", chip->chip_id);
1219 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1220 g_free(name);
1221 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip),
1222 &chip8->icp_mmio);
1223
1224 /* Map the ICP registers for each thread */
1225 for (i = 0; i < chip->nr_cores; i++) {
1226 PnvCore *pnv_core = chip->cores[i];
1227 int core_hwid = CPU_CORE(pnv_core)->core_id;
1228
1229 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1230 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1231 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1232
1233 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1234 &icp->mmio);
1235 }
1236 }
1237 }
1238
1239 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1240 {
1241 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1242 PnvChip *chip = PNV_CHIP(dev);
1243 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1244 Pnv8Psi *psi8 = &chip8->psi;
1245 Error *local_err = NULL;
1246 int i;
1247
1248 assert(chip8->xics);
1249
1250 /* XSCOM bridge is first */
1251 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip));
1252
1253 pcc->parent_realize(dev, &local_err);
1254 if (local_err) {
1255 error_propagate(errp, local_err);
1256 return;
1257 }
1258
1259 /* Processor Service Interface (PSI) Host Bridge */
1260 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1261 &error_fatal);
1262 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1263 OBJECT(chip8->xics), &error_abort);
1264 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1265 return;
1266 }
1267 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1268 &PNV_PSI(psi8)->xscom_regs);
1269
1270 /* Create LPC controller */
1271 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1272 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1273
1274 chip->fw_mr = &chip8->lpc.isa_fw;
1275 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1276 (uint64_t) PNV_XSCOM_BASE(chip),
1277 PNV_XSCOM_LPC_BASE);
1278
1279 /*
1280 * Interrupt Management Area. This is the memory region holding
1281 * all the Interrupt Control Presenter (ICP) registers
1282 */
1283 pnv_chip_icp_realize(chip8, &local_err);
1284 if (local_err) {
1285 error_propagate(errp, local_err);
1286 return;
1287 }
1288
1289 /* Create the simplified OCC model */
1290 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1291 return;
1292 }
1293 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1294 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1295 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
1296
1297 /* OCC SRAM model */
1298 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1299 &chip8->occ.sram_regs);
1300
1301 /* HOMER */
1302 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1303 &error_abort);
1304 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1305 return;
1306 }
1307 /* Homer Xscom region */
1308 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1309
1310 /* Homer mmio region */
1311 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1312 &chip8->homer.regs);
1313
1314 /* PHB controllers */
1315 for (i = 0; i < chip8->num_phbs; i++) {
1316 PnvPHB *phb = chip8->phbs[i];
1317
1318 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1319 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1320 &error_fatal);
1321 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1322 &error_fatal);
1323 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1324 return;
1325 }
1326 }
1327 }
1328
1329 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1330 {
1331 addr &= (PNV_XSCOM_SIZE - 1);
1332 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1333 }
1334
1335 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1336 {
1337 DeviceClass *dc = DEVICE_CLASS(klass);
1338 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1339
1340 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1341 k->cores_mask = POWER8E_CORE_MASK;
1342 k->num_phbs = 3;
1343 k->core_pir = pnv_chip_core_pir_p8;
1344 k->intc_create = pnv_chip_power8_intc_create;
1345 k->intc_reset = pnv_chip_power8_intc_reset;
1346 k->intc_destroy = pnv_chip_power8_intc_destroy;
1347 k->intc_print_info = pnv_chip_power8_intc_print_info;
1348 k->isa_create = pnv_chip_power8_isa_create;
1349 k->dt_populate = pnv_chip_power8_dt_populate;
1350 k->pic_print_info = pnv_chip_power8_pic_print_info;
1351 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1352 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1353 dc->desc = "PowerNV Chip POWER8E";
1354
1355 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1356 &k->parent_realize);
1357 }
1358
1359 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1360 {
1361 DeviceClass *dc = DEVICE_CLASS(klass);
1362 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1363
1364 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1365 k->cores_mask = POWER8_CORE_MASK;
1366 k->num_phbs = 3;
1367 k->core_pir = pnv_chip_core_pir_p8;
1368 k->intc_create = pnv_chip_power8_intc_create;
1369 k->intc_reset = pnv_chip_power8_intc_reset;
1370 k->intc_destroy = pnv_chip_power8_intc_destroy;
1371 k->intc_print_info = pnv_chip_power8_intc_print_info;
1372 k->isa_create = pnv_chip_power8_isa_create;
1373 k->dt_populate = pnv_chip_power8_dt_populate;
1374 k->pic_print_info = pnv_chip_power8_pic_print_info;
1375 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1376 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1377 dc->desc = "PowerNV Chip POWER8";
1378
1379 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1380 &k->parent_realize);
1381 }
1382
1383 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1384 {
1385 DeviceClass *dc = DEVICE_CLASS(klass);
1386 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1387
1388 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1389 k->cores_mask = POWER8_CORE_MASK;
1390 k->num_phbs = 4;
1391 k->core_pir = pnv_chip_core_pir_p8;
1392 k->intc_create = pnv_chip_power8_intc_create;
1393 k->intc_reset = pnv_chip_power8_intc_reset;
1394 k->intc_destroy = pnv_chip_power8_intc_destroy;
1395 k->intc_print_info = pnv_chip_power8_intc_print_info;
1396 k->isa_create = pnv_chip_power8nvl_isa_create;
1397 k->dt_populate = pnv_chip_power8_dt_populate;
1398 k->pic_print_info = pnv_chip_power8_pic_print_info;
1399 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1400 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1401 dc->desc = "PowerNV Chip POWER8NVL";
1402
1403 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1404 &k->parent_realize);
1405 }
1406
1407 static void pnv_chip_power9_instance_init(Object *obj)
1408 {
1409 PnvChip *chip = PNV_CHIP(obj);
1410 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1411 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1412 int i;
1413
1414 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1415 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1416 "xive-fabric");
1417
1418 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1419
1420 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1421
1422 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1423
1424 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1425
1426 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1427
1428 /* Number of PECs is the chip default */
1429 chip->num_pecs = pcc->num_pecs;
1430
1431 for (i = 0; i < chip->num_pecs; i++) {
1432 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1433 TYPE_PNV_PHB4_PEC);
1434 }
1435
1436 for (i = 0; i < pcc->i2c_num_engines; i++) {
1437 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C);
1438 }
1439 }
1440
1441 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1442 PnvCore *pnv_core,
1443 const char *type)
1444 {
1445 char eq_name[32];
1446 int core_id = CPU_CORE(pnv_core)->core_id;
1447
1448 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1449 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1450 sizeof(*eq), type,
1451 &error_fatal, NULL);
1452
1453 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1454 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1455 }
1456
1457 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1458 {
1459 PnvChip *chip = PNV_CHIP(chip9);
1460 int i;
1461
1462 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1463 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1464
1465 for (i = 0; i < chip9->nr_quads; i++) {
1466 PnvQuad *eq = &chip9->quads[i];
1467
1468 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
1469 PNV_QUAD_TYPE_NAME("power9"));
1470
1471 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1472 &eq->xscom_regs);
1473 }
1474 }
1475
1476 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1477 {
1478 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1479 int i;
1480
1481 for (i = 0; i < chip->num_pecs; i++) {
1482 PnvPhb4PecState *pec = &chip9->pecs[i];
1483 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1484 uint32_t pec_nest_base;
1485 uint32_t pec_pci_base;
1486
1487 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1488 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1489 &error_fatal);
1490 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1491 &error_fatal);
1492 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1493 return;
1494 }
1495
1496 pec_nest_base = pecc->xscom_nest_base(pec);
1497 pec_pci_base = pecc->xscom_pci_base(pec);
1498
1499 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1500 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1501 }
1502 }
1503
1504 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1505 {
1506 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1507 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1508 PnvChip *chip = PNV_CHIP(dev);
1509 Pnv9Psi *psi9 = &chip9->psi;
1510 Error *local_err = NULL;
1511 int i;
1512
1513 /* XSCOM bridge is first */
1514 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip));
1515
1516 pcc->parent_realize(dev, &local_err);
1517 if (local_err) {
1518 error_propagate(errp, local_err);
1519 return;
1520 }
1521
1522 pnv_chip_quad_realize(chip9, &local_err);
1523 if (local_err) {
1524 error_propagate(errp, local_err);
1525 return;
1526 }
1527
1528 /* XIVE interrupt controller (POWER9) */
1529 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1530 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1531 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1532 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1533 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1534 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1535 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1536 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1537 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1538 &error_abort);
1539 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1540 return;
1541 }
1542 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1543 &chip9->xive.xscom_regs);
1544
1545 /* Processor Service Interface (PSI) Host Bridge */
1546 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1547 &error_fatal);
1548 /* This is the only device with 4k ESB pages */
1549 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
1550 &error_fatal);
1551 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1552 return;
1553 }
1554 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1555 &PNV_PSI(psi9)->xscom_regs);
1556
1557 /* LPC */
1558 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1559 return;
1560 }
1561 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1562 &chip9->lpc.xscom_regs);
1563
1564 chip->fw_mr = &chip9->lpc.isa_fw;
1565 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1566 (uint64_t) PNV9_LPCM_BASE(chip));
1567
1568 /* Create the simplified OCC model */
1569 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1570 return;
1571 }
1572 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1573 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
1574 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
1575
1576 /* OCC SRAM model */
1577 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1578 &chip9->occ.sram_regs);
1579
1580 /* SBE */
1581 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
1582 return;
1583 }
1584 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
1585 &chip9->sbe.xscom_ctrl_regs);
1586 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
1587 &chip9->sbe.xscom_mbox_regs);
1588 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
1589 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU));
1590
1591 /* HOMER */
1592 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1593 &error_abort);
1594 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1595 return;
1596 }
1597 /* Homer Xscom region */
1598 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1599
1600 /* Homer mmio region */
1601 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1602 &chip9->homer.regs);
1603
1604 /* PEC PHBs */
1605 pnv_chip_power9_pec_realize(chip, &local_err);
1606 if (local_err) {
1607 error_propagate(errp, local_err);
1608 return;
1609 }
1610
1611 /*
1612 * I2C
1613 */
1614 for (i = 0; i < pcc->i2c_num_engines; i++) {
1615 Object *obj = OBJECT(&chip9->i2c[i]);
1616
1617 object_property_set_int(obj, "engine", i + 1, &error_fatal);
1618 object_property_set_int(obj, "num-busses",
1619 pcc->i2c_ports_per_engine[i],
1620 &error_fatal);
1621 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
1622 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
1623 return;
1624 }
1625 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE +
1626 chip9->i2c[i].engine * PNV9_XSCOM_I2CM_SIZE,
1627 &chip9->i2c[i].xscom_regs);
1628 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0,
1629 qdev_get_gpio_in(DEVICE(&chip9->psi),
1630 PSIHB9_IRQ_SBE_I2C));
1631 }
1632 }
1633
1634 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1635 {
1636 addr &= (PNV9_XSCOM_SIZE - 1);
1637 return addr >> 3;
1638 }
1639
1640 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1641 {
1642 DeviceClass *dc = DEVICE_CLASS(klass);
1643 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1644 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2};
1645
1646 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1647 k->cores_mask = POWER9_CORE_MASK;
1648 k->core_pir = pnv_chip_core_pir_p9;
1649 k->intc_create = pnv_chip_power9_intc_create;
1650 k->intc_reset = pnv_chip_power9_intc_reset;
1651 k->intc_destroy = pnv_chip_power9_intc_destroy;
1652 k->intc_print_info = pnv_chip_power9_intc_print_info;
1653 k->isa_create = pnv_chip_power9_isa_create;
1654 k->dt_populate = pnv_chip_power9_dt_populate;
1655 k->pic_print_info = pnv_chip_power9_pic_print_info;
1656 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1657 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1658 dc->desc = "PowerNV Chip POWER9";
1659 k->num_pecs = PNV9_CHIP_MAX_PEC;
1660 k->i2c_num_engines = PNV9_CHIP_MAX_I2C;
1661 k->i2c_ports_per_engine = i2c_ports_per_engine;
1662
1663 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1664 &k->parent_realize);
1665 }
1666
1667 static void pnv_chip_power10_instance_init(Object *obj)
1668 {
1669 PnvChip *chip = PNV_CHIP(obj);
1670 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1671 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1672 int i;
1673
1674 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1675 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1676 "xive-fabric");
1677 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1678 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1679 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
1680 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
1681 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1682
1683 chip->num_pecs = pcc->num_pecs;
1684
1685 for (i = 0; i < chip->num_pecs; i++) {
1686 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1687 TYPE_PNV_PHB5_PEC);
1688 }
1689
1690 for (i = 0; i < pcc->i2c_num_engines; i++) {
1691 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C);
1692 }
1693 }
1694
1695 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1696 {
1697 PnvChip *chip = PNV_CHIP(chip10);
1698 int i;
1699
1700 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1701 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1702
1703 for (i = 0; i < chip10->nr_quads; i++) {
1704 PnvQuad *eq = &chip10->quads[i];
1705
1706 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
1707 PNV_QUAD_TYPE_NAME("power10"));
1708
1709 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1710 &eq->xscom_regs);
1711
1712 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id),
1713 &eq->xscom_qme_regs);
1714 }
1715 }
1716
1717 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1718 {
1719 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1720 int i;
1721
1722 for (i = 0; i < chip->num_pecs; i++) {
1723 PnvPhb4PecState *pec = &chip10->pecs[i];
1724 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1725 uint32_t pec_nest_base;
1726 uint32_t pec_pci_base;
1727
1728 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1729 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1730 &error_fatal);
1731 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1732 &error_fatal);
1733 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1734 return;
1735 }
1736
1737 pec_nest_base = pecc->xscom_nest_base(pec);
1738 pec_pci_base = pecc->xscom_pci_base(pec);
1739
1740 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1741 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1742 }
1743 }
1744
1745 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1746 {
1747 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1748 PnvChip *chip = PNV_CHIP(dev);
1749 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1750 Error *local_err = NULL;
1751 int i;
1752
1753 /* XSCOM bridge is first */
1754 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip));
1755
1756 pcc->parent_realize(dev, &local_err);
1757 if (local_err) {
1758 error_propagate(errp, local_err);
1759 return;
1760 }
1761
1762 pnv_chip_power10_quad_realize(chip10, &local_err);
1763 if (local_err) {
1764 error_propagate(errp, local_err);
1765 return;
1766 }
1767
1768 /* XIVE2 interrupt controller (POWER10) */
1769 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1770 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1771 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1772 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1773 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1774 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1775 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1776 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1777 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1778 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1779 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1780 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1781 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1782 &error_abort);
1783 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1784 return;
1785 }
1786 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1787 &chip10->xive.xscom_regs);
1788
1789 /* Processor Service Interface (PSI) Host Bridge */
1790 object_property_set_int(OBJECT(&chip10->psi), "bar",
1791 PNV10_PSIHB_BASE(chip), &error_fatal);
1792 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1793 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
1794 &error_fatal);
1795 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1796 return;
1797 }
1798 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1799 &PNV_PSI(&chip10->psi)->xscom_regs);
1800
1801 /* LPC */
1802 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1803 return;
1804 }
1805 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1806 &chip10->lpc.xscom_regs);
1807
1808 chip->fw_mr = &chip10->lpc.isa_fw;
1809 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1810 (uint64_t) PNV10_LPCM_BASE(chip));
1811
1812 /* Create the simplified OCC model */
1813 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
1814 return;
1815 }
1816 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
1817 &chip10->occ.xscom_regs);
1818 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
1819 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
1820
1821 /* OCC SRAM model */
1822 memory_region_add_subregion(get_system_memory(),
1823 PNV10_OCC_SENSOR_BASE(chip),
1824 &chip10->occ.sram_regs);
1825
1826 /* SBE */
1827 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
1828 return;
1829 }
1830 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
1831 &chip10->sbe.xscom_ctrl_regs);
1832 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
1833 &chip10->sbe.xscom_mbox_regs);
1834 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
1835 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
1836
1837 /* HOMER */
1838 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
1839 &error_abort);
1840 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
1841 return;
1842 }
1843 /* Homer Xscom region */
1844 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
1845 &chip10->homer.pba_regs);
1846
1847 /* Homer mmio region */
1848 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
1849 &chip10->homer.regs);
1850
1851 /* PHBs */
1852 pnv_chip_power10_phb_realize(chip, &local_err);
1853 if (local_err) {
1854 error_propagate(errp, local_err);
1855 return;
1856 }
1857
1858
1859 /*
1860 * I2C
1861 */
1862 for (i = 0; i < pcc->i2c_num_engines; i++) {
1863 Object *obj = OBJECT(&chip10->i2c[i]);
1864
1865 object_property_set_int(obj, "engine", i + 1, &error_fatal);
1866 object_property_set_int(obj, "num-busses",
1867 pcc->i2c_ports_per_engine[i],
1868 &error_fatal);
1869 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
1870 if (!qdev_realize(DEVICE(obj), NULL, errp)) {
1871 return;
1872 }
1873 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE +
1874 chip10->i2c[i].engine * PNV10_XSCOM_I2CM_SIZE,
1875 &chip10->i2c[i].xscom_regs);
1876 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0,
1877 qdev_get_gpio_in(DEVICE(&chip10->psi),
1878 PSIHB9_IRQ_SBE_I2C));
1879 }
1880 }
1881
1882 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1883 {
1884 addr &= (PNV10_XSCOM_SIZE - 1);
1885 return addr >> 3;
1886 }
1887
1888 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1889 {
1890 DeviceClass *dc = DEVICE_CLASS(klass);
1891 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1892 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
1893
1894 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1895 k->cores_mask = POWER10_CORE_MASK;
1896 k->core_pir = pnv_chip_core_pir_p10;
1897 k->intc_create = pnv_chip_power10_intc_create;
1898 k->intc_reset = pnv_chip_power10_intc_reset;
1899 k->intc_destroy = pnv_chip_power10_intc_destroy;
1900 k->intc_print_info = pnv_chip_power10_intc_print_info;
1901 k->isa_create = pnv_chip_power10_isa_create;
1902 k->dt_populate = pnv_chip_power10_dt_populate;
1903 k->pic_print_info = pnv_chip_power10_pic_print_info;
1904 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1905 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1906 dc->desc = "PowerNV Chip POWER10";
1907 k->num_pecs = PNV10_CHIP_MAX_PEC;
1908 k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
1909 k->i2c_ports_per_engine = i2c_ports_per_engine;
1910
1911 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1912 &k->parent_realize);
1913 }
1914
1915 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1916 {
1917 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1918 int cores_max;
1919
1920 /*
1921 * No custom mask for this chip, let's use the default one from *
1922 * the chip class
1923 */
1924 if (!chip->cores_mask) {
1925 chip->cores_mask = pcc->cores_mask;
1926 }
1927
1928 /* filter alien core ids ! some are reserved */
1929 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1930 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1931 chip->cores_mask);
1932 return;
1933 }
1934 chip->cores_mask &= pcc->cores_mask;
1935
1936 /* now that we have a sane layout, let check the number of cores */
1937 cores_max = ctpop64(chip->cores_mask);
1938 if (chip->nr_cores > cores_max) {
1939 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1940 cores_max);
1941 return;
1942 }
1943 }
1944
1945 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1946 {
1947 Error *error = NULL;
1948 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1949 const char *typename = pnv_chip_core_typename(chip);
1950 int i, core_hwid;
1951 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1952
1953 if (!object_class_by_name(typename)) {
1954 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1955 return;
1956 }
1957
1958 /* Cores */
1959 pnv_chip_core_sanitize(chip, &error);
1960 if (error) {
1961 error_propagate(errp, error);
1962 return;
1963 }
1964
1965 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1966
1967 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1968 && (i < chip->nr_cores); core_hwid++) {
1969 char core_name[32];
1970 PnvCore *pnv_core;
1971 uint64_t xscom_core_base;
1972
1973 if (!(chip->cores_mask & (1ull << core_hwid))) {
1974 continue;
1975 }
1976
1977 pnv_core = PNV_CORE(object_new(typename));
1978
1979 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1980 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1981 chip->cores[i] = pnv_core;
1982 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1983 chip->nr_threads, &error_fatal);
1984 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1985 core_hwid, &error_fatal);
1986 object_property_set_int(OBJECT(pnv_core), "pir",
1987 pcc->core_pir(chip, core_hwid), &error_fatal);
1988 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1989 &error_fatal);
1990 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1991 &error_abort);
1992 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1993
1994 /* Each core has an XSCOM MMIO region */
1995 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1996
1997 pnv_xscom_add_subregion(chip, xscom_core_base,
1998 &pnv_core->xscom_regs);
1999 i++;
2000 }
2001 }
2002
2003 static void pnv_chip_realize(DeviceState *dev, Error **errp)
2004 {
2005 PnvChip *chip = PNV_CHIP(dev);
2006 Error *error = NULL;
2007
2008 /* Cores */
2009 pnv_chip_core_realize(chip, &error);
2010 if (error) {
2011 error_propagate(errp, error);
2012 return;
2013 }
2014 }
2015
2016 static Property pnv_chip_properties[] = {
2017 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
2018 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
2019 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
2020 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
2021 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
2022 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
2023 DEFINE_PROP_END_OF_LIST(),
2024 };
2025
2026 static void pnv_chip_class_init(ObjectClass *klass, void *data)
2027 {
2028 DeviceClass *dc = DEVICE_CLASS(klass);
2029
2030 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
2031 dc->realize = pnv_chip_realize;
2032 device_class_set_props(dc, pnv_chip_properties);
2033 dc->desc = "PowerNV Chip";
2034 }
2035
2036 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
2037 {
2038 int i, j;
2039
2040 for (i = 0; i < chip->nr_cores; i++) {
2041 PnvCore *pc = chip->cores[i];
2042 CPUCore *cc = CPU_CORE(pc);
2043
2044 for (j = 0; j < cc->nr_threads; j++) {
2045 if (ppc_cpu_pir(pc->threads[j]) == pir) {
2046 return pc->threads[j];
2047 }
2048 }
2049 }
2050 return NULL;
2051 }
2052
2053 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
2054 {
2055 PnvMachineState *pnv = PNV_MACHINE(xi);
2056 int i, j;
2057
2058 for (i = 0; i < pnv->num_chips; i++) {
2059 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2060
2061 if (ics_valid_irq(&chip8->psi.ics, irq)) {
2062 return &chip8->psi.ics;
2063 }
2064
2065 for (j = 0; j < chip8->num_phbs; j++) {
2066 PnvPHB *phb = chip8->phbs[j];
2067 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2068
2069 if (ics_valid_irq(&phb3->lsis, irq)) {
2070 return &phb3->lsis;
2071 }
2072
2073 if (ics_valid_irq(ICS(&phb3->msis), irq)) {
2074 return ICS(&phb3->msis);
2075 }
2076 }
2077 }
2078 return NULL;
2079 }
2080
2081 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
2082 {
2083 int i;
2084
2085 for (i = 0; i < pnv->num_chips; i++) {
2086 PnvChip *chip = pnv->chips[i];
2087 if (chip->chip_id == chip_id) {
2088 return chip;
2089 }
2090 }
2091 return NULL;
2092 }
2093
2094 static void pnv_ics_resend(XICSFabric *xi)
2095 {
2096 PnvMachineState *pnv = PNV_MACHINE(xi);
2097 int i, j;
2098
2099 for (i = 0; i < pnv->num_chips; i++) {
2100 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2101
2102 ics_resend(&chip8->psi.ics);
2103
2104 for (j = 0; j < chip8->num_phbs; j++) {
2105 PnvPHB *phb = chip8->phbs[j];
2106 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2107
2108 ics_resend(&phb3->lsis);
2109 ics_resend(ICS(&phb3->msis));
2110 }
2111 }
2112 }
2113
2114 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2115 {
2116 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2117
2118 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2119 }
2120
2121 static void pnv_pic_print_info(InterruptStatsProvider *obj,
2122 Monitor *mon)
2123 {
2124 PnvMachineState *pnv = PNV_MACHINE(obj);
2125 int i;
2126 CPUState *cs;
2127
2128 CPU_FOREACH(cs) {
2129 PowerPCCPU *cpu = POWERPC_CPU(cs);
2130
2131 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2132 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
2133 mon);
2134 }
2135
2136 for (i = 0; i < pnv->num_chips; i++) {
2137 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
2138 }
2139 }
2140
2141 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2142 uint8_t nvt_blk, uint32_t nvt_idx,
2143 bool cam_ignore, uint8_t priority,
2144 uint32_t logic_serv,
2145 XiveTCTXMatch *match)
2146 {
2147 PnvMachineState *pnv = PNV_MACHINE(xfb);
2148 int total_count = 0;
2149 int i;
2150
2151 for (i = 0; i < pnv->num_chips; i++) {
2152 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2153 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2154 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2155 int count;
2156
2157 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2158 priority, logic_serv, match);
2159
2160 if (count < 0) {
2161 return count;
2162 }
2163
2164 total_count += count;
2165 }
2166
2167 return total_count;
2168 }
2169
2170 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2171 uint8_t nvt_blk, uint32_t nvt_idx,
2172 bool cam_ignore, uint8_t priority,
2173 uint32_t logic_serv,
2174 XiveTCTXMatch *match)
2175 {
2176 PnvMachineState *pnv = PNV_MACHINE(xfb);
2177 int total_count = 0;
2178 int i;
2179
2180 for (i = 0; i < pnv->num_chips; i++) {
2181 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2182 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2183 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2184 int count;
2185
2186 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2187 priority, logic_serv, match);
2188
2189 if (count < 0) {
2190 return count;
2191 }
2192
2193 total_count += count;
2194 }
2195
2196 return total_count;
2197 }
2198
2199 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2200 {
2201 MachineClass *mc = MACHINE_CLASS(oc);
2202 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2203 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2204 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2205
2206 static GlobalProperty phb_compat[] = {
2207 { TYPE_PNV_PHB, "version", "3" },
2208 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
2209 };
2210
2211 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2212 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2213 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2214
2215 xic->icp_get = pnv_icp_get;
2216 xic->ics_get = pnv_ics_get;
2217 xic->ics_resend = pnv_ics_resend;
2218
2219 pmc->compat = compat;
2220 pmc->compat_size = sizeof(compat);
2221
2222 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2223 }
2224
2225 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2226 {
2227 MachineClass *mc = MACHINE_CLASS(oc);
2228 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2229 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2230 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2231
2232 static GlobalProperty phb_compat[] = {
2233 { TYPE_PNV_PHB, "version", "4" },
2234 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
2235 };
2236
2237 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2238 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2");
2239 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2240
2241 xfc->match_nvt = pnv_match_nvt;
2242
2243 mc->alias = "powernv";
2244
2245 pmc->compat = compat;
2246 pmc->compat_size = sizeof(compat);
2247 pmc->dt_power_mgt = pnv_dt_power_mgt;
2248
2249 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2250 }
2251
2252 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2253 {
2254 MachineClass *mc = MACHINE_CLASS(oc);
2255 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2256 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2257 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2258
2259 static GlobalProperty phb_compat[] = {
2260 { TYPE_PNV_PHB, "version", "5" },
2261 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
2262 };
2263
2264 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2265 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2266 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2267
2268 pmc->compat = compat;
2269 pmc->compat_size = sizeof(compat);
2270 pmc->dt_power_mgt = pnv_dt_power_mgt;
2271
2272 xfc->match_nvt = pnv10_xive_match_nvt;
2273
2274 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2275 }
2276
2277 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2278 {
2279 PnvMachineState *pnv = PNV_MACHINE(obj);
2280
2281 return !!pnv->fw_load_addr;
2282 }
2283
2284 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2285 {
2286 PnvMachineState *pnv = PNV_MACHINE(obj);
2287
2288 if (value) {
2289 pnv->fw_load_addr = 0x8000000;
2290 }
2291 }
2292
2293 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2294 {
2295 PowerPCCPU *cpu = POWERPC_CPU(cs);
2296 CPUPPCState *env = &cpu->env;
2297
2298 cpu_synchronize_state(cs);
2299 ppc_cpu_do_system_reset(cs);
2300 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2301 /*
2302 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2303 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2304 * (PPC_BIT(43)).
2305 */
2306 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2307 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2308 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2309 }
2310 } else {
2311 /*
2312 * For non-powersave system resets, SRR1[42:45] are defined to be
2313 * implementation-dependent. The POWER9 User Manual specifies that
2314 * an external (SCOM driven, which may come from a BMC nmi command or
2315 * another CPU requesting a NMI IPI) system reset exception should be
2316 * 0b0010 (PPC_BIT(44)).
2317 */
2318 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2319 }
2320 }
2321
2322 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2323 {
2324 CPUState *cs;
2325
2326 CPU_FOREACH(cs) {
2327 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2328 }
2329 }
2330
2331 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2332 {
2333 MachineClass *mc = MACHINE_CLASS(oc);
2334 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2335 NMIClass *nc = NMI_CLASS(oc);
2336
2337 mc->desc = "IBM PowerNV (Non-Virtualized)";
2338 mc->init = pnv_init;
2339 mc->reset = pnv_reset;
2340 mc->max_cpus = MAX_CPUS;
2341 /* Pnv provides a AHCI device for storage */
2342 mc->block_default_type = IF_IDE;
2343 mc->no_parallel = 1;
2344 mc->default_boot_order = NULL;
2345 /*
2346 * RAM defaults to less than 2048 for 32-bit hosts, and large
2347 * enough to fit the maximum initrd size at it's load address
2348 */
2349 mc->default_ram_size = 1 * GiB;
2350 mc->default_ram_id = "pnv.ram";
2351 ispc->print_info = pnv_pic_print_info;
2352 nc->nmi_monitor_handler = pnv_nmi;
2353
2354 object_class_property_add_bool(oc, "hb-mode",
2355 pnv_machine_get_hb, pnv_machine_set_hb);
2356 object_class_property_set_description(oc, "hb-mode",
2357 "Use a hostboot like boot loader");
2358 }
2359
2360 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2361 { \
2362 .name = type, \
2363 .class_init = class_initfn, \
2364 .parent = TYPE_PNV8_CHIP, \
2365 }
2366
2367 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2368 { \
2369 .name = type, \
2370 .class_init = class_initfn, \
2371 .parent = TYPE_PNV9_CHIP, \
2372 }
2373
2374 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2375 { \
2376 .name = type, \
2377 .class_init = class_initfn, \
2378 .parent = TYPE_PNV10_CHIP, \
2379 }
2380
2381 static const TypeInfo types[] = {
2382 {
2383 .name = MACHINE_TYPE_NAME("powernv10"),
2384 .parent = TYPE_PNV_MACHINE,
2385 .class_init = pnv_machine_power10_class_init,
2386 .interfaces = (InterfaceInfo[]) {
2387 { TYPE_XIVE_FABRIC },
2388 { },
2389 },
2390 },
2391 {
2392 .name = MACHINE_TYPE_NAME("powernv9"),
2393 .parent = TYPE_PNV_MACHINE,
2394 .class_init = pnv_machine_power9_class_init,
2395 .interfaces = (InterfaceInfo[]) {
2396 { TYPE_XIVE_FABRIC },
2397 { },
2398 },
2399 },
2400 {
2401 .name = MACHINE_TYPE_NAME("powernv8"),
2402 .parent = TYPE_PNV_MACHINE,
2403 .class_init = pnv_machine_power8_class_init,
2404 .interfaces = (InterfaceInfo[]) {
2405 { TYPE_XICS_FABRIC },
2406 { },
2407 },
2408 },
2409 {
2410 .name = TYPE_PNV_MACHINE,
2411 .parent = TYPE_MACHINE,
2412 .abstract = true,
2413 .instance_size = sizeof(PnvMachineState),
2414 .class_init = pnv_machine_class_init,
2415 .class_size = sizeof(PnvMachineClass),
2416 .interfaces = (InterfaceInfo[]) {
2417 { TYPE_INTERRUPT_STATS_PROVIDER },
2418 { TYPE_NMI },
2419 { },
2420 },
2421 },
2422 {
2423 .name = TYPE_PNV_CHIP,
2424 .parent = TYPE_SYS_BUS_DEVICE,
2425 .class_init = pnv_chip_class_init,
2426 .instance_size = sizeof(PnvChip),
2427 .class_size = sizeof(PnvChipClass),
2428 .abstract = true,
2429 },
2430
2431 /*
2432 * P10 chip and variants
2433 */
2434 {
2435 .name = TYPE_PNV10_CHIP,
2436 .parent = TYPE_PNV_CHIP,
2437 .instance_init = pnv_chip_power10_instance_init,
2438 .instance_size = sizeof(Pnv10Chip),
2439 },
2440 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2441
2442 /*
2443 * P9 chip and variants
2444 */
2445 {
2446 .name = TYPE_PNV9_CHIP,
2447 .parent = TYPE_PNV_CHIP,
2448 .instance_init = pnv_chip_power9_instance_init,
2449 .instance_size = sizeof(Pnv9Chip),
2450 },
2451 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2452
2453 /*
2454 * P8 chip and variants
2455 */
2456 {
2457 .name = TYPE_PNV8_CHIP,
2458 .parent = TYPE_PNV_CHIP,
2459 .instance_init = pnv_chip_power8_instance_init,
2460 .instance_size = sizeof(Pnv8Chip),
2461 },
2462 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2463 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2464 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2465 pnv_chip_power8nvl_class_init),
2466 };
2467
2468 DEFINE_TYPES(types)
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