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ppc/pnv: Add a "pnor" const link property to the BMC internal simulator
[mirror_qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/units.h"
23 #include "qapi/error.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/numa.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/cpus.h"
29 #include "sysemu/device_tree.h"
30 #include "target/ppc/cpu.h"
31 #include "qemu/log.h"
32 #include "hw/ppc/fdt.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/ppc/pnv.h"
35 #include "hw/ppc/pnv_core.h"
36 #include "hw/loader.h"
37 #include "exec/address-spaces.h"
38 #include "qapi/visitor.h"
39 #include "monitor/monitor.h"
40 #include "hw/intc/intc.h"
41 #include "hw/ipmi/ipmi.h"
42 #include "target/ppc/mmu-hash64.h"
43
44 #include "hw/ppc/xics.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/ppc/pnv_xscom.h"
47 #include "hw/ppc/pnv_pnor.h"
48
49 #include "hw/isa/isa.h"
50 #include "hw/boards.h"
51 #include "hw/char/serial.h"
52 #include "hw/rtc/mc146818rtc.h"
53
54 #include <libfdt.h>
55
56 #define FDT_MAX_SIZE (1 * MiB)
57
58 #define FW_FILE_NAME "skiboot.lid"
59 #define FW_LOAD_ADDR 0x0
60 #define FW_MAX_SIZE (4 * MiB)
61
62 #define KERNEL_LOAD_ADDR 0x20000000
63 #define KERNEL_MAX_SIZE (256 * MiB)
64 #define INITRD_LOAD_ADDR 0x60000000
65 #define INITRD_MAX_SIZE (256 * MiB)
66
67 static const char *pnv_chip_core_typename(const PnvChip *o)
68 {
69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
72 const char *core_type = object_class_get_name(object_class_by_name(s));
73 g_free(s);
74 return core_type;
75 }
76
77 /*
78 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
79 * 4 * 4 sockets * 12 cores * 8 threads = 1536
80 * Let's make it 2^11
81 */
82 #define MAX_CPUS 2048
83
84 /*
85 * Memory nodes are created by hostboot, one for each range of memory
86 * that has a different "affinity". In practice, it means one range
87 * per chip.
88 */
89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
90 {
91 char *mem_name;
92 uint64_t mem_reg_property[2];
93 int off;
94
95 mem_reg_property[0] = cpu_to_be64(start);
96 mem_reg_property[1] = cpu_to_be64(size);
97
98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
99 off = fdt_add_subnode(fdt, 0, mem_name);
100 g_free(mem_name);
101
102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
104 sizeof(mem_reg_property))));
105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
106 }
107
108 static int get_cpus_node(void *fdt)
109 {
110 int cpus_offset = fdt_path_offset(fdt, "/cpus");
111
112 if (cpus_offset < 0) {
113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
114 if (cpus_offset) {
115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
117 }
118 }
119 _FDT(cpus_offset);
120 return cpus_offset;
121 }
122
123 /*
124 * The PowerNV cores (and threads) need to use real HW ids and not an
125 * incremental index like it has been done on other platforms. This HW
126 * id is stored in the CPU PIR, it is used to create cpu nodes in the
127 * device tree, used in XSCOM to address cores and in interrupt
128 * servers.
129 */
130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
131 {
132 PowerPCCPU *cpu = pc->threads[0];
133 CPUState *cs = CPU(cpu);
134 DeviceClass *dc = DEVICE_GET_CLASS(cs);
135 int smt_threads = CPU_CORE(pc)->nr_threads;
136 CPUPPCState *env = &cpu->env;
137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
138 uint32_t servers_prop[smt_threads];
139 int i;
140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
141 0xffffffff, 0xffffffff};
142 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
143 uint32_t cpufreq = 1000000000;
144 uint32_t page_sizes_prop[64];
145 size_t page_sizes_prop_size;
146 const uint8_t pa_features[] = { 24, 0,
147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
151 int offset;
152 char *nodename;
153 int cpus_offset = get_cpus_node(fdt);
154
155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
156 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
157 _FDT(offset);
158 g_free(nodename);
159
160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
161
162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
165
166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
168 env->dcache_line_size)));
169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
170 env->dcache_line_size)));
171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
172 env->icache_line_size)));
173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
174 env->icache_line_size)));
175
176 if (pcc->l1_dcache_size) {
177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
178 pcc->l1_dcache_size)));
179 } else {
180 warn_report("Unknown L1 dcache size for cpu");
181 }
182 if (pcc->l1_icache_size) {
183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
184 pcc->l1_icache_size)));
185 } else {
186 warn_report("Unknown L1 icache size for cpu");
187 }
188
189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
192 cpu->hash64_opts->slb_size)));
193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
195
196 if (env->spr_cb[SPR_PURR].oea_read) {
197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
198 }
199
200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
202 segs, sizeof(segs))));
203 }
204
205 /*
206 * Advertise VMX/VSX (vector extensions) if available
207 * 0 / no property == no vector extensions
208 * 1 == VMX / Altivec available
209 * 2 == VSX available
210 */
211 if (env->insns_flags & PPC_ALTIVEC) {
212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
213
214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
215 }
216
217 /*
218 * Advertise DFP (Decimal Floating Point) if available
219 * 0 / no property == no DFP
220 * 1 == DFP available
221 */
222 if (env->insns_flags2 & PPC2_DFP) {
223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
224 }
225
226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
227 sizeof(page_sizes_prop));
228 if (page_sizes_prop_size) {
229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
230 page_sizes_prop, page_sizes_prop_size)));
231 }
232
233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
234 pa_features, sizeof(pa_features))));
235
236 /* Build interrupt servers properties */
237 for (i = 0; i < smt_threads; i++) {
238 servers_prop[i] = cpu_to_be32(pc->pir + i);
239 }
240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
241 servers_prop, sizeof(servers_prop))));
242 }
243
244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
245 uint32_t nr_threads)
246 {
247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
248 char *name;
249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
250 uint32_t irange[2], i, rsize;
251 uint64_t *reg;
252 int offset;
253
254 irange[0] = cpu_to_be32(pir);
255 irange[1] = cpu_to_be32(nr_threads);
256
257 rsize = sizeof(uint64_t) * 2 * nr_threads;
258 reg = g_malloc(rsize);
259 for (i = 0; i < nr_threads; i++) {
260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
261 reg[i * 2 + 1] = cpu_to_be64(0x1000);
262 }
263
264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
265 offset = fdt_add_subnode(fdt, 0, name);
266 _FDT(offset);
267 g_free(name);
268
269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
271 _FDT((fdt_setprop_string(fdt, offset, "device_type",
272 "PowerPC-External-Interrupt-Presentation")));
273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
275 irange, sizeof(irange))));
276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
278 g_free(reg);
279 }
280
281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
282 {
283 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
284 int i;
285
286 pnv_dt_xscom(chip, fdt, 0,
287 cpu_to_be64(PNV_XSCOM_BASE(chip)),
288 cpu_to_be64(PNV_XSCOM_SIZE),
289 compat, sizeof(compat));
290
291 for (i = 0; i < chip->nr_cores; i++) {
292 PnvCore *pnv_core = chip->cores[i];
293
294 pnv_dt_core(chip, pnv_core, fdt);
295
296 /* Interrupt Control Presenters (ICP). One per core. */
297 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
298 }
299
300 if (chip->ram_size) {
301 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
302 }
303 }
304
305 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
306 {
307 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
308 int i;
309
310 pnv_dt_xscom(chip, fdt, 0,
311 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
312 cpu_to_be64(PNV9_XSCOM_SIZE),
313 compat, sizeof(compat));
314
315 for (i = 0; i < chip->nr_cores; i++) {
316 PnvCore *pnv_core = chip->cores[i];
317
318 pnv_dt_core(chip, pnv_core, fdt);
319 }
320
321 if (chip->ram_size) {
322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
323 }
324
325 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
326 }
327
328 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
329 {
330 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
331 int i;
332
333 pnv_dt_xscom(chip, fdt, 0,
334 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
335 cpu_to_be64(PNV10_XSCOM_SIZE),
336 compat, sizeof(compat));
337
338 for (i = 0; i < chip->nr_cores; i++) {
339 PnvCore *pnv_core = chip->cores[i];
340
341 pnv_dt_core(chip, pnv_core, fdt);
342 }
343
344 if (chip->ram_size) {
345 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
346 }
347
348 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
349 }
350
351 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
352 {
353 uint32_t io_base = d->ioport_id;
354 uint32_t io_regs[] = {
355 cpu_to_be32(1),
356 cpu_to_be32(io_base),
357 cpu_to_be32(2)
358 };
359 char *name;
360 int node;
361
362 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
363 node = fdt_add_subnode(fdt, lpc_off, name);
364 _FDT(node);
365 g_free(name);
366
367 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
368 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
369 }
370
371 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
372 {
373 const char compatible[] = "ns16550\0pnpPNP,501";
374 uint32_t io_base = d->ioport_id;
375 uint32_t io_regs[] = {
376 cpu_to_be32(1),
377 cpu_to_be32(io_base),
378 cpu_to_be32(8)
379 };
380 char *name;
381 int node;
382
383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
384 node = fdt_add_subnode(fdt, lpc_off, name);
385 _FDT(node);
386 g_free(name);
387
388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
389 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
390 sizeof(compatible))));
391
392 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
393 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
394 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
395 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
396 fdt_get_phandle(fdt, lpc_off))));
397
398 /* This is needed by Linux */
399 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
400 }
401
402 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
403 {
404 const char compatible[] = "bt\0ipmi-bt";
405 uint32_t io_base;
406 uint32_t io_regs[] = {
407 cpu_to_be32(1),
408 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
409 cpu_to_be32(3)
410 };
411 uint32_t irq;
412 char *name;
413 int node;
414
415 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
416 io_regs[1] = cpu_to_be32(io_base);
417
418 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
419
420 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
421 node = fdt_add_subnode(fdt, lpc_off, name);
422 _FDT(node);
423 g_free(name);
424
425 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
426 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
427 sizeof(compatible))));
428
429 /* Mark it as reserved to avoid Linux trying to claim it */
430 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
431 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
432 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
433 fdt_get_phandle(fdt, lpc_off))));
434 }
435
436 typedef struct ForeachPopulateArgs {
437 void *fdt;
438 int offset;
439 } ForeachPopulateArgs;
440
441 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
442 {
443 ForeachPopulateArgs *args = opaque;
444 ISADevice *d = ISA_DEVICE(dev);
445
446 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
447 pnv_dt_rtc(d, args->fdt, args->offset);
448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
449 pnv_dt_serial(d, args->fdt, args->offset);
450 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
451 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
452 } else {
453 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
454 d->ioport_id);
455 }
456
457 return 0;
458 }
459
460 /*
461 * The default LPC bus of a multichip system is on chip 0. It's
462 * recognized by the firmware (skiboot) using a "primary" property.
463 */
464 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
465 {
466 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
467 ForeachPopulateArgs args = {
468 .fdt = fdt,
469 .offset = isa_offset,
470 };
471 uint32_t phandle;
472
473 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
474
475 phandle = qemu_fdt_alloc_phandle(fdt);
476 assert(phandle > 0);
477 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
478
479 /*
480 * ISA devices are not necessarily parented to the ISA bus so we
481 * can not use object_child_foreach()
482 */
483 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
484 &args);
485 }
486
487 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
488 {
489 int off;
490
491 off = fdt_add_subnode(fdt, 0, "ibm,opal");
492 off = fdt_add_subnode(fdt, off, "power-mgt");
493
494 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
495 }
496
497 static void *pnv_dt_create(MachineState *machine)
498 {
499 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
500 PnvMachineState *pnv = PNV_MACHINE(machine);
501 void *fdt;
502 char *buf;
503 int off;
504 int i;
505
506 fdt = g_malloc0(FDT_MAX_SIZE);
507 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
508
509 /* /qemu node */
510 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
511
512 /* Root node */
513 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
514 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
515 _FDT((fdt_setprop_string(fdt, 0, "model",
516 "IBM PowerNV (emulated by qemu)")));
517 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
518
519 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
520 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
521 if (qemu_uuid_set) {
522 _FDT((fdt_property_string(fdt, "system-id", buf)));
523 }
524 g_free(buf);
525
526 off = fdt_add_subnode(fdt, 0, "chosen");
527 if (machine->kernel_cmdline) {
528 _FDT((fdt_setprop_string(fdt, off, "bootargs",
529 machine->kernel_cmdline)));
530 }
531
532 if (pnv->initrd_size) {
533 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
534 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
535
536 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
537 &start_prop, sizeof(start_prop))));
538 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
539 &end_prop, sizeof(end_prop))));
540 }
541
542 /* Populate device tree for each chip */
543 for (i = 0; i < pnv->num_chips; i++) {
544 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
545 }
546
547 /* Populate ISA devices on chip 0 */
548 pnv_dt_isa(pnv, fdt);
549
550 if (pnv->bmc) {
551 pnv_dt_bmc_sensors(pnv->bmc, fdt);
552 }
553
554 /* Create an extra node for power management on machines that support it */
555 if (pmc->dt_power_mgt) {
556 pmc->dt_power_mgt(pnv, fdt);
557 }
558
559 return fdt;
560 }
561
562 static void pnv_powerdown_notify(Notifier *n, void *opaque)
563 {
564 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
565
566 if (pnv->bmc) {
567 pnv_bmc_powerdown(pnv->bmc);
568 }
569 }
570
571 static void pnv_reset(MachineState *machine)
572 {
573 void *fdt;
574
575 qemu_devices_reset();
576
577 fdt = pnv_dt_create(machine);
578
579 /* Pack resulting tree */
580 _FDT((fdt_pack(fdt)));
581
582 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
583 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
584 }
585
586 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
587 {
588 Pnv8Chip *chip8 = PNV8_CHIP(chip);
589 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
590 }
591
592 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
593 {
594 Pnv8Chip *chip8 = PNV8_CHIP(chip);
595 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
596 }
597
598 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
599 {
600 Pnv9Chip *chip9 = PNV9_CHIP(chip);
601 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
602 }
603
604 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
605 {
606 Pnv10Chip *chip10 = PNV10_CHIP(chip);
607 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
608 }
609
610 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
611 {
612 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
613 }
614
615 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
616 {
617 Pnv8Chip *chip8 = PNV8_CHIP(chip);
618
619 ics_pic_print_info(&chip8->psi.ics, mon);
620 }
621
622 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
623 {
624 Pnv9Chip *chip9 = PNV9_CHIP(chip);
625
626 pnv_xive_pic_print_info(&chip9->xive, mon);
627 pnv_psi_pic_print_info(&chip9->psi, mon);
628 }
629
630 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
631 uint32_t core_id)
632 {
633 return PNV_XSCOM_EX_BASE(core_id);
634 }
635
636 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
637 uint32_t core_id)
638 {
639 return PNV9_XSCOM_EC_BASE(core_id);
640 }
641
642 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
643 uint32_t core_id)
644 {
645 return PNV10_XSCOM_EC_BASE(core_id);
646 }
647
648 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
649 {
650 PowerPCCPUClass *ppc_default =
651 POWERPC_CPU_CLASS(object_class_by_name(default_type));
652 PowerPCCPUClass *ppc =
653 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
654
655 return ppc_default->pvr_match(ppc_default, ppc->pvr);
656 }
657
658 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
659 {
660 Object *obj;
661
662 obj = OBJECT(isa_create(bus, "isa-ipmi-bt"));
663 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal);
664 object_property_set_int(obj, irq, "irq", &error_fatal);
665 object_property_set_bool(obj, true, "realized", &error_fatal);
666 }
667
668 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
669 {
670 Pnv10Chip *chip10 = PNV10_CHIP(chip);
671
672 pnv_psi_pic_print_info(&chip10->psi, mon);
673 }
674
675 static void pnv_init(MachineState *machine)
676 {
677 PnvMachineState *pnv = PNV_MACHINE(machine);
678 MachineClass *mc = MACHINE_GET_CLASS(machine);
679 MemoryRegion *ram;
680 char *fw_filename;
681 long fw_size;
682 int i;
683 char *chip_typename;
684 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
685 DeviceState *dev;
686
687 /* allocate RAM */
688 if (machine->ram_size < (1 * GiB)) {
689 warn_report("skiboot may not work with < 1GB of RAM");
690 }
691
692 ram = g_new(MemoryRegion, 1);
693 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
694 machine->ram_size);
695 memory_region_add_subregion(get_system_memory(), 0, ram);
696
697 /*
698 * Create our simple PNOR device
699 */
700 dev = qdev_create(NULL, TYPE_PNV_PNOR);
701 if (pnor) {
702 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
703 &error_abort);
704 }
705 qdev_init_nofail(dev);
706 pnv->pnor = PNV_PNOR(dev);
707
708 /* load skiboot firmware */
709 if (bios_name == NULL) {
710 bios_name = FW_FILE_NAME;
711 }
712
713 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
714 if (!fw_filename) {
715 error_report("Could not find OPAL firmware '%s'", bios_name);
716 exit(1);
717 }
718
719 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
720 if (fw_size < 0) {
721 error_report("Could not load OPAL firmware '%s'", fw_filename);
722 exit(1);
723 }
724 g_free(fw_filename);
725
726 /* load kernel */
727 if (machine->kernel_filename) {
728 long kernel_size;
729
730 kernel_size = load_image_targphys(machine->kernel_filename,
731 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
732 if (kernel_size < 0) {
733 error_report("Could not load kernel '%s'",
734 machine->kernel_filename);
735 exit(1);
736 }
737 }
738
739 /* load initrd */
740 if (machine->initrd_filename) {
741 pnv->initrd_base = INITRD_LOAD_ADDR;
742 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
743 pnv->initrd_base, INITRD_MAX_SIZE);
744 if (pnv->initrd_size < 0) {
745 error_report("Could not load initial ram disk '%s'",
746 machine->initrd_filename);
747 exit(1);
748 }
749 }
750
751 /*
752 * Check compatibility of the specified CPU with the machine
753 * default.
754 */
755 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
756 error_report("invalid CPU model '%s' for %s machine",
757 machine->cpu_type, mc->name);
758 exit(1);
759 }
760
761 /* Create the processor chips */
762 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
763 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
764 i, machine->cpu_type);
765 if (!object_class_by_name(chip_typename)) {
766 error_report("invalid chip model '%.*s' for %s machine",
767 i, machine->cpu_type, mc->name);
768 exit(1);
769 }
770
771 pnv->num_chips =
772 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
773 /*
774 * TODO: should we decide on how many chips we can create based
775 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
776 */
777 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
778 error_report("invalid number of chips: '%d'", pnv->num_chips);
779 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
780 exit(1);
781 }
782
783 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
784 for (i = 0; i < pnv->num_chips; i++) {
785 char chip_name[32];
786 Object *chip = object_new(chip_typename);
787
788 pnv->chips[i] = PNV_CHIP(chip);
789
790 /*
791 * TODO: put all the memory in one node on chip 0 until we find a
792 * way to specify different ranges for each chip
793 */
794 if (i == 0) {
795 object_property_set_int(chip, machine->ram_size, "ram-size",
796 &error_fatal);
797 }
798
799 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
800 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
801 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
802 &error_fatal);
803 object_property_set_int(chip, machine->smp.cores,
804 "nr-cores", &error_fatal);
805 object_property_set_int(chip, machine->smp.threads,
806 "nr-threads", &error_fatal);
807 /*
808 * The POWER8 machine use the XICS interrupt interface.
809 * Propagate the XICS fabric to the chip and its controllers.
810 */
811 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
812 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort);
813 }
814 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
815 object_property_set_link(chip, OBJECT(pnv), "xive-fabric",
816 &error_abort);
817 }
818 object_property_set_bool(chip, true, "realized", &error_fatal);
819 }
820 g_free(chip_typename);
821
822 /* Create the machine BMC simulator */
823 pnv->bmc = pnv_bmc_create(pnv->pnor);
824
825 /* Instantiate ISA bus on chip 0 */
826 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
827
828 /* Create serial port */
829 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
830
831 /* Create an RTC ISA device too */
832 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
833
834 /* Create the IPMI BT device for communication with the BMC */
835 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
836
837 /*
838 * OpenPOWER systems use a IPMI SEL Event message to notify the
839 * host to powerdown
840 */
841 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
842 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
843 }
844
845 /*
846 * 0:21 Reserved - Read as zeros
847 * 22:24 Chip ID
848 * 25:28 Core number
849 * 29:31 Thread ID
850 */
851 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
852 {
853 return (chip->chip_id << 7) | (core_id << 3);
854 }
855
856 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
857 Error **errp)
858 {
859 Pnv8Chip *chip8 = PNV8_CHIP(chip);
860 Error *local_err = NULL;
861 Object *obj;
862 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
863
864 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
865 if (local_err) {
866 error_propagate(errp, local_err);
867 return;
868 }
869
870 pnv_cpu->intc = obj;
871 }
872
873
874 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
875 {
876 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
877
878 icp_reset(ICP(pnv_cpu->intc));
879 }
880
881 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
882 {
883 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
884
885 icp_destroy(ICP(pnv_cpu->intc));
886 pnv_cpu->intc = NULL;
887 }
888
889 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
890 Monitor *mon)
891 {
892 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
893 }
894
895 /*
896 * 0:48 Reserved - Read as zeroes
897 * 49:52 Node ID
898 * 53:55 Chip ID
899 * 56 Reserved - Read as zero
900 * 57:61 Core number
901 * 62:63 Thread ID
902 *
903 * We only care about the lower bits. uint32_t is fine for the moment.
904 */
905 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
906 {
907 return (chip->chip_id << 8) | (core_id << 2);
908 }
909
910 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
911 {
912 return (chip->chip_id << 8) | (core_id << 2);
913 }
914
915 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
916 Error **errp)
917 {
918 Pnv9Chip *chip9 = PNV9_CHIP(chip);
919 Error *local_err = NULL;
920 Object *obj;
921 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
922
923 /*
924 * The core creates its interrupt presenter but the XIVE interrupt
925 * controller object is initialized afterwards. Hopefully, it's
926 * only used at runtime.
927 */
928 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err);
929 if (local_err) {
930 error_propagate(errp, local_err);
931 return;
932 }
933
934 pnv_cpu->intc = obj;
935 }
936
937 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
938 {
939 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
940
941 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
942 }
943
944 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
945 {
946 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
947
948 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
949 pnv_cpu->intc = NULL;
950 }
951
952 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
953 Monitor *mon)
954 {
955 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
956 }
957
958 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
959 Error **errp)
960 {
961 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
962
963 /* Will be defined when the interrupt controller is */
964 pnv_cpu->intc = NULL;
965 }
966
967 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
968 {
969 ;
970 }
971
972 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
973 {
974 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
975
976 pnv_cpu->intc = NULL;
977 }
978
979 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
980 Monitor *mon)
981 {
982 }
983
984 /*
985 * Allowed core identifiers on a POWER8 Processor Chip :
986 *
987 * <EX0 reserved>
988 * EX1 - Venice only
989 * EX2 - Venice only
990 * EX3 - Venice only
991 * EX4
992 * EX5
993 * EX6
994 * <EX7,8 reserved> <reserved>
995 * EX9 - Venice only
996 * EX10 - Venice only
997 * EX11 - Venice only
998 * EX12
999 * EX13
1000 * EX14
1001 * <EX15 reserved>
1002 */
1003 #define POWER8E_CORE_MASK (0x7070ull)
1004 #define POWER8_CORE_MASK (0x7e7eull)
1005
1006 /*
1007 * POWER9 has 24 cores, ids starting at 0x0
1008 */
1009 #define POWER9_CORE_MASK (0xffffffffffffffull)
1010
1011
1012 #define POWER10_CORE_MASK (0xffffffffffffffull)
1013
1014 static void pnv_chip_power8_instance_init(Object *obj)
1015 {
1016 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1017
1018 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1019 (Object **)&chip8->xics,
1020 object_property_allow_set_link,
1021 OBJ_PROP_LINK_STRONG,
1022 &error_abort);
1023
1024 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
1025 TYPE_PNV8_PSI, &error_abort, NULL);
1026
1027 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
1028 TYPE_PNV8_LPC, &error_abort, NULL);
1029
1030 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
1031 TYPE_PNV8_OCC, &error_abort, NULL);
1032
1033 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
1034 TYPE_PNV8_HOMER, &error_abort, NULL);
1035 }
1036
1037 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1038 {
1039 PnvChip *chip = PNV_CHIP(chip8);
1040 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1041 int i, j;
1042 char *name;
1043
1044 name = g_strdup_printf("icp-%x", chip->chip_id);
1045 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1046 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1047 g_free(name);
1048
1049 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1050
1051 /* Map the ICP registers for each thread */
1052 for (i = 0; i < chip->nr_cores; i++) {
1053 PnvCore *pnv_core = chip->cores[i];
1054 int core_hwid = CPU_CORE(pnv_core)->core_id;
1055
1056 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1057 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1058 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1059
1060 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1061 &icp->mmio);
1062 }
1063 }
1064 }
1065
1066 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1067 {
1068 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1069 PnvChip *chip = PNV_CHIP(dev);
1070 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1071 Pnv8Psi *psi8 = &chip8->psi;
1072 Error *local_err = NULL;
1073
1074 assert(chip8->xics);
1075
1076 /* XSCOM bridge is first */
1077 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1078 if (local_err) {
1079 error_propagate(errp, local_err);
1080 return;
1081 }
1082 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1083
1084 pcc->parent_realize(dev, &local_err);
1085 if (local_err) {
1086 error_propagate(errp, local_err);
1087 return;
1088 }
1089
1090 /* Processor Service Interface (PSI) Host Bridge */
1091 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
1092 "bar", &error_fatal);
1093 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics),
1094 ICS_PROP_XICS, &error_abort);
1095 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
1096 if (local_err) {
1097 error_propagate(errp, local_err);
1098 return;
1099 }
1100 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1101 &PNV_PSI(psi8)->xscom_regs);
1102
1103 /* Create LPC controller */
1104 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
1105 &error_abort);
1106 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
1107 &error_fatal);
1108 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1109
1110 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1111 (uint64_t) PNV_XSCOM_BASE(chip),
1112 PNV_XSCOM_LPC_BASE);
1113
1114 /*
1115 * Interrupt Management Area. This is the memory region holding
1116 * all the Interrupt Control Presenter (ICP) registers
1117 */
1118 pnv_chip_icp_realize(chip8, &local_err);
1119 if (local_err) {
1120 error_propagate(errp, local_err);
1121 return;
1122 }
1123
1124 /* Create the simplified OCC model */
1125 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
1126 &error_abort);
1127 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
1128 if (local_err) {
1129 error_propagate(errp, local_err);
1130 return;
1131 }
1132 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1133
1134 /* OCC SRAM model */
1135 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1136 &chip8->occ.sram_regs);
1137
1138 /* HOMER */
1139 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
1140 &error_abort);
1141 object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
1142 &local_err);
1143 if (local_err) {
1144 error_propagate(errp, local_err);
1145 return;
1146 }
1147 /* Homer Xscom region */
1148 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1149
1150 /* Homer mmio region */
1151 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1152 &chip8->homer.regs);
1153 }
1154
1155 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1156 {
1157 addr &= (PNV_XSCOM_SIZE - 1);
1158 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1159 }
1160
1161 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1162 {
1163 DeviceClass *dc = DEVICE_CLASS(klass);
1164 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1165
1166 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1167 k->cores_mask = POWER8E_CORE_MASK;
1168 k->core_pir = pnv_chip_core_pir_p8;
1169 k->intc_create = pnv_chip_power8_intc_create;
1170 k->intc_reset = pnv_chip_power8_intc_reset;
1171 k->intc_destroy = pnv_chip_power8_intc_destroy;
1172 k->intc_print_info = pnv_chip_power8_intc_print_info;
1173 k->isa_create = pnv_chip_power8_isa_create;
1174 k->dt_populate = pnv_chip_power8_dt_populate;
1175 k->pic_print_info = pnv_chip_power8_pic_print_info;
1176 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1177 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1178 dc->desc = "PowerNV Chip POWER8E";
1179
1180 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1181 &k->parent_realize);
1182 }
1183
1184 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1185 {
1186 DeviceClass *dc = DEVICE_CLASS(klass);
1187 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1188
1189 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1190 k->cores_mask = POWER8_CORE_MASK;
1191 k->core_pir = pnv_chip_core_pir_p8;
1192 k->intc_create = pnv_chip_power8_intc_create;
1193 k->intc_reset = pnv_chip_power8_intc_reset;
1194 k->intc_destroy = pnv_chip_power8_intc_destroy;
1195 k->intc_print_info = pnv_chip_power8_intc_print_info;
1196 k->isa_create = pnv_chip_power8_isa_create;
1197 k->dt_populate = pnv_chip_power8_dt_populate;
1198 k->pic_print_info = pnv_chip_power8_pic_print_info;
1199 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1200 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1201 dc->desc = "PowerNV Chip POWER8";
1202
1203 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1204 &k->parent_realize);
1205 }
1206
1207 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1208 {
1209 DeviceClass *dc = DEVICE_CLASS(klass);
1210 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1211
1212 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1213 k->cores_mask = POWER8_CORE_MASK;
1214 k->core_pir = pnv_chip_core_pir_p8;
1215 k->intc_create = pnv_chip_power8_intc_create;
1216 k->intc_reset = pnv_chip_power8_intc_reset;
1217 k->intc_destroy = pnv_chip_power8_intc_destroy;
1218 k->intc_print_info = pnv_chip_power8_intc_print_info;
1219 k->isa_create = pnv_chip_power8nvl_isa_create;
1220 k->dt_populate = pnv_chip_power8_dt_populate;
1221 k->pic_print_info = pnv_chip_power8_pic_print_info;
1222 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1223 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1224 dc->desc = "PowerNV Chip POWER8NVL";
1225
1226 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1227 &k->parent_realize);
1228 }
1229
1230 static void pnv_chip_power9_instance_init(Object *obj)
1231 {
1232 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1233
1234 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
1235 TYPE_PNV_XIVE, &error_abort, NULL);
1236 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1237 "xive-fabric", &error_abort);
1238
1239 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
1240 TYPE_PNV9_PSI, &error_abort, NULL);
1241
1242 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
1243 TYPE_PNV9_LPC, &error_abort, NULL);
1244
1245 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
1246 TYPE_PNV9_OCC, &error_abort, NULL);
1247
1248 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
1249 TYPE_PNV9_HOMER, &error_abort, NULL);
1250 }
1251
1252 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1253 {
1254 PnvChip *chip = PNV_CHIP(chip9);
1255 int i;
1256
1257 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1258 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1259
1260 for (i = 0; i < chip9->nr_quads; i++) {
1261 char eq_name[32];
1262 PnvQuad *eq = &chip9->quads[i];
1263 PnvCore *pnv_core = chip->cores[i * 4];
1264 int core_id = CPU_CORE(pnv_core)->core_id;
1265
1266 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1267 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1268 TYPE_PNV_QUAD, &error_fatal, NULL);
1269
1270 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1271 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
1272
1273 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1274 &eq->xscom_regs);
1275 }
1276 }
1277
1278 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1279 {
1280 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1281 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1282 PnvChip *chip = PNV_CHIP(dev);
1283 Pnv9Psi *psi9 = &chip9->psi;
1284 Error *local_err = NULL;
1285
1286 /* XSCOM bridge is first */
1287 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1288 if (local_err) {
1289 error_propagate(errp, local_err);
1290 return;
1291 }
1292 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1293
1294 pcc->parent_realize(dev, &local_err);
1295 if (local_err) {
1296 error_propagate(errp, local_err);
1297 return;
1298 }
1299
1300 pnv_chip_quad_realize(chip9, &local_err);
1301 if (local_err) {
1302 error_propagate(errp, local_err);
1303 return;
1304 }
1305
1306 /* XIVE interrupt controller (POWER9) */
1307 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1308 "ic-bar", &error_fatal);
1309 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1310 "vc-bar", &error_fatal);
1311 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1312 "pc-bar", &error_fatal);
1313 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1314 "tm-bar", &error_fatal);
1315 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
1316 &error_abort);
1317 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1318 &local_err);
1319 if (local_err) {
1320 error_propagate(errp, local_err);
1321 return;
1322 }
1323 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1324 &chip9->xive.xscom_regs);
1325
1326 /* Processor Service Interface (PSI) Host Bridge */
1327 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1328 "bar", &error_fatal);
1329 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1330 if (local_err) {
1331 error_propagate(errp, local_err);
1332 return;
1333 }
1334 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1335 &PNV_PSI(psi9)->xscom_regs);
1336
1337 /* LPC */
1338 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
1339 &error_abort);
1340 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1341 if (local_err) {
1342 error_propagate(errp, local_err);
1343 return;
1344 }
1345 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1346 &chip9->lpc.xscom_regs);
1347
1348 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1349 (uint64_t) PNV9_LPCM_BASE(chip));
1350
1351 /* Create the simplified OCC model */
1352 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
1353 &error_abort);
1354 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1355 if (local_err) {
1356 error_propagate(errp, local_err);
1357 return;
1358 }
1359 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1360
1361 /* OCC SRAM model */
1362 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1363 &chip9->occ.sram_regs);
1364
1365 /* HOMER */
1366 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
1367 &error_abort);
1368 object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
1369 &local_err);
1370 if (local_err) {
1371 error_propagate(errp, local_err);
1372 return;
1373 }
1374 /* Homer Xscom region */
1375 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1376
1377 /* Homer mmio region */
1378 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1379 &chip9->homer.regs);
1380 }
1381
1382 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1383 {
1384 addr &= (PNV9_XSCOM_SIZE - 1);
1385 return addr >> 3;
1386 }
1387
1388 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1389 {
1390 DeviceClass *dc = DEVICE_CLASS(klass);
1391 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1392
1393 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1394 k->cores_mask = POWER9_CORE_MASK;
1395 k->core_pir = pnv_chip_core_pir_p9;
1396 k->intc_create = pnv_chip_power9_intc_create;
1397 k->intc_reset = pnv_chip_power9_intc_reset;
1398 k->intc_destroy = pnv_chip_power9_intc_destroy;
1399 k->intc_print_info = pnv_chip_power9_intc_print_info;
1400 k->isa_create = pnv_chip_power9_isa_create;
1401 k->dt_populate = pnv_chip_power9_dt_populate;
1402 k->pic_print_info = pnv_chip_power9_pic_print_info;
1403 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1404 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1405 dc->desc = "PowerNV Chip POWER9";
1406
1407 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1408 &k->parent_realize);
1409 }
1410
1411 static void pnv_chip_power10_instance_init(Object *obj)
1412 {
1413 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1414
1415 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
1416 TYPE_PNV10_PSI, &error_abort, NULL);
1417 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
1418 TYPE_PNV10_LPC, &error_abort, NULL);
1419 }
1420
1421 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1422 {
1423 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1424 PnvChip *chip = PNV_CHIP(dev);
1425 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1426 Error *local_err = NULL;
1427
1428 /* XSCOM bridge is first */
1429 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1430 if (local_err) {
1431 error_propagate(errp, local_err);
1432 return;
1433 }
1434 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1435
1436 pcc->parent_realize(dev, &local_err);
1437 if (local_err) {
1438 error_propagate(errp, local_err);
1439 return;
1440 }
1441
1442 /* Processor Service Interface (PSI) Host Bridge */
1443 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
1444 "bar", &error_fatal);
1445 object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
1446 &local_err);
1447 if (local_err) {
1448 error_propagate(errp, local_err);
1449 return;
1450 }
1451 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1452 &PNV_PSI(&chip10->psi)->xscom_regs);
1453
1454 /* LPC */
1455 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
1456 &error_abort);
1457 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
1458 &local_err);
1459 if (local_err) {
1460 error_propagate(errp, local_err);
1461 return;
1462 }
1463 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1464 &chip10->lpc.xscom_regs);
1465
1466 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1467 (uint64_t) PNV10_LPCM_BASE(chip));
1468 }
1469
1470 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1471 {
1472 addr &= (PNV10_XSCOM_SIZE - 1);
1473 return addr >> 3;
1474 }
1475
1476 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1477 {
1478 DeviceClass *dc = DEVICE_CLASS(klass);
1479 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1480
1481 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1482 k->cores_mask = POWER10_CORE_MASK;
1483 k->core_pir = pnv_chip_core_pir_p10;
1484 k->intc_create = pnv_chip_power10_intc_create;
1485 k->intc_reset = pnv_chip_power10_intc_reset;
1486 k->intc_destroy = pnv_chip_power10_intc_destroy;
1487 k->intc_print_info = pnv_chip_power10_intc_print_info;
1488 k->isa_create = pnv_chip_power10_isa_create;
1489 k->dt_populate = pnv_chip_power10_dt_populate;
1490 k->pic_print_info = pnv_chip_power10_pic_print_info;
1491 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1492 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1493 dc->desc = "PowerNV Chip POWER10";
1494
1495 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1496 &k->parent_realize);
1497 }
1498
1499 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1500 {
1501 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1502 int cores_max;
1503
1504 /*
1505 * No custom mask for this chip, let's use the default one from *
1506 * the chip class
1507 */
1508 if (!chip->cores_mask) {
1509 chip->cores_mask = pcc->cores_mask;
1510 }
1511
1512 /* filter alien core ids ! some are reserved */
1513 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1514 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1515 chip->cores_mask);
1516 return;
1517 }
1518 chip->cores_mask &= pcc->cores_mask;
1519
1520 /* now that we have a sane layout, let check the number of cores */
1521 cores_max = ctpop64(chip->cores_mask);
1522 if (chip->nr_cores > cores_max) {
1523 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1524 cores_max);
1525 return;
1526 }
1527 }
1528
1529 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1530 {
1531 Error *error = NULL;
1532 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1533 const char *typename = pnv_chip_core_typename(chip);
1534 int i, core_hwid;
1535
1536 if (!object_class_by_name(typename)) {
1537 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1538 return;
1539 }
1540
1541 /* Cores */
1542 pnv_chip_core_sanitize(chip, &error);
1543 if (error) {
1544 error_propagate(errp, error);
1545 return;
1546 }
1547
1548 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1549
1550 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1551 && (i < chip->nr_cores); core_hwid++) {
1552 char core_name[32];
1553 PnvCore *pnv_core;
1554 uint64_t xscom_core_base;
1555
1556 if (!(chip->cores_mask & (1ull << core_hwid))) {
1557 continue;
1558 }
1559
1560 pnv_core = PNV_CORE(object_new(typename));
1561
1562 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1563 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
1564 &error_abort);
1565 chip->cores[i] = pnv_core;
1566 object_property_set_int(OBJECT(pnv_core), chip->nr_threads,
1567 "nr-threads", &error_fatal);
1568 object_property_set_int(OBJECT(pnv_core), core_hwid,
1569 CPU_CORE_PROP_CORE_ID, &error_fatal);
1570 object_property_set_int(OBJECT(pnv_core),
1571 pcc->core_pir(chip, core_hwid),
1572 "pir", &error_fatal);
1573 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
1574 &error_abort);
1575 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1576 &error_fatal);
1577
1578 /* Each core has an XSCOM MMIO region */
1579 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1580
1581 pnv_xscom_add_subregion(chip, xscom_core_base,
1582 &pnv_core->xscom_regs);
1583 i++;
1584 }
1585 }
1586
1587 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1588 {
1589 PnvChip *chip = PNV_CHIP(dev);
1590 Error *error = NULL;
1591
1592 /* Cores */
1593 pnv_chip_core_realize(chip, &error);
1594 if (error) {
1595 error_propagate(errp, error);
1596 return;
1597 }
1598 }
1599
1600 static Property pnv_chip_properties[] = {
1601 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1602 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1603 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1604 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1605 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1606 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1607 DEFINE_PROP_END_OF_LIST(),
1608 };
1609
1610 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1611 {
1612 DeviceClass *dc = DEVICE_CLASS(klass);
1613
1614 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1615 dc->realize = pnv_chip_realize;
1616 dc->props = pnv_chip_properties;
1617 dc->desc = "PowerNV Chip";
1618 }
1619
1620 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1621 {
1622 int i, j;
1623
1624 for (i = 0; i < chip->nr_cores; i++) {
1625 PnvCore *pc = chip->cores[i];
1626 CPUCore *cc = CPU_CORE(pc);
1627
1628 for (j = 0; j < cc->nr_threads; j++) {
1629 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1630 return pc->threads[j];
1631 }
1632 }
1633 }
1634 return NULL;
1635 }
1636
1637 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1638 {
1639 PnvMachineState *pnv = PNV_MACHINE(xi);
1640 int i;
1641
1642 for (i = 0; i < pnv->num_chips; i++) {
1643 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1644
1645 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1646 return &chip8->psi.ics;
1647 }
1648 }
1649 return NULL;
1650 }
1651
1652 static void pnv_ics_resend(XICSFabric *xi)
1653 {
1654 PnvMachineState *pnv = PNV_MACHINE(xi);
1655 int i;
1656
1657 for (i = 0; i < pnv->num_chips; i++) {
1658 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1659 ics_resend(&chip8->psi.ics);
1660 }
1661 }
1662
1663 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1664 {
1665 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1666
1667 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1668 }
1669
1670 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1671 Monitor *mon)
1672 {
1673 PnvMachineState *pnv = PNV_MACHINE(obj);
1674 int i;
1675 CPUState *cs;
1676
1677 CPU_FOREACH(cs) {
1678 PowerPCCPU *cpu = POWERPC_CPU(cs);
1679
1680 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1681 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1682 mon);
1683 }
1684
1685 for (i = 0; i < pnv->num_chips; i++) {
1686 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1687 }
1688 }
1689
1690 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1691 uint8_t nvt_blk, uint32_t nvt_idx,
1692 bool cam_ignore, uint8_t priority,
1693 uint32_t logic_serv,
1694 XiveTCTXMatch *match)
1695 {
1696 PnvMachineState *pnv = PNV_MACHINE(xfb);
1697 int total_count = 0;
1698 int i;
1699
1700 for (i = 0; i < pnv->num_chips; i++) {
1701 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1702 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1703 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1704 int count;
1705
1706 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1707 priority, logic_serv, match);
1708
1709 if (count < 0) {
1710 return count;
1711 }
1712
1713 total_count += count;
1714 }
1715
1716 return total_count;
1717 }
1718
1719 PnvChip *pnv_get_chip(uint32_t chip_id)
1720 {
1721 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1722 int i;
1723
1724 for (i = 0; i < pnv->num_chips; i++) {
1725 PnvChip *chip = pnv->chips[i];
1726 if (chip->chip_id == chip_id) {
1727 return chip;
1728 }
1729 }
1730 return NULL;
1731 }
1732
1733 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
1734 {
1735 MachineClass *mc = MACHINE_CLASS(oc);
1736 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1737 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1738 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1739
1740 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1741 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1742
1743 xic->icp_get = pnv_icp_get;
1744 xic->ics_get = pnv_ics_get;
1745 xic->ics_resend = pnv_ics_resend;
1746
1747 pmc->compat = compat;
1748 pmc->compat_size = sizeof(compat);
1749 }
1750
1751 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1752 {
1753 MachineClass *mc = MACHINE_CLASS(oc);
1754 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
1755 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1756 static const char compat[] = "qemu,powernv9\0ibm,powernv";
1757
1758 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1759 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
1760 xfc->match_nvt = pnv_match_nvt;
1761
1762 mc->alias = "powernv";
1763
1764 pmc->compat = compat;
1765 pmc->compat_size = sizeof(compat);
1766 pmc->dt_power_mgt = pnv_dt_power_mgt;
1767 }
1768
1769 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1770 {
1771 MachineClass *mc = MACHINE_CLASS(oc);
1772 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1773 static const char compat[] = "qemu,powernv10\0ibm,powernv";
1774
1775 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1776 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
1777
1778 pmc->compat = compat;
1779 pmc->compat_size = sizeof(compat);
1780 pmc->dt_power_mgt = pnv_dt_power_mgt;
1781 }
1782
1783 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1784 {
1785 MachineClass *mc = MACHINE_CLASS(oc);
1786 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1787
1788 mc->desc = "IBM PowerNV (Non-Virtualized)";
1789 mc->init = pnv_init;
1790 mc->reset = pnv_reset;
1791 mc->max_cpus = MAX_CPUS;
1792 /* Pnv provides a AHCI device for storage */
1793 mc->block_default_type = IF_IDE;
1794 mc->no_parallel = 1;
1795 mc->default_boot_order = NULL;
1796 /*
1797 * RAM defaults to less than 2048 for 32-bit hosts, and large
1798 * enough to fit the maximum initrd size at it's load address
1799 */
1800 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
1801 ispc->print_info = pnv_pic_print_info;
1802 }
1803
1804 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1805 { \
1806 .name = type, \
1807 .class_init = class_initfn, \
1808 .parent = TYPE_PNV8_CHIP, \
1809 }
1810
1811 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1812 { \
1813 .name = type, \
1814 .class_init = class_initfn, \
1815 .parent = TYPE_PNV9_CHIP, \
1816 }
1817
1818 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
1819 { \
1820 .name = type, \
1821 .class_init = class_initfn, \
1822 .parent = TYPE_PNV10_CHIP, \
1823 }
1824
1825 static const TypeInfo types[] = {
1826 {
1827 .name = MACHINE_TYPE_NAME("powernv10"),
1828 .parent = TYPE_PNV_MACHINE,
1829 .class_init = pnv_machine_power10_class_init,
1830 },
1831 {
1832 .name = MACHINE_TYPE_NAME("powernv9"),
1833 .parent = TYPE_PNV_MACHINE,
1834 .class_init = pnv_machine_power9_class_init,
1835 .interfaces = (InterfaceInfo[]) {
1836 { TYPE_XIVE_FABRIC },
1837 { },
1838 },
1839 },
1840 {
1841 .name = MACHINE_TYPE_NAME("powernv8"),
1842 .parent = TYPE_PNV_MACHINE,
1843 .class_init = pnv_machine_power8_class_init,
1844 .interfaces = (InterfaceInfo[]) {
1845 { TYPE_XICS_FABRIC },
1846 { },
1847 },
1848 },
1849 {
1850 .name = TYPE_PNV_MACHINE,
1851 .parent = TYPE_MACHINE,
1852 .abstract = true,
1853 .instance_size = sizeof(PnvMachineState),
1854 .class_init = pnv_machine_class_init,
1855 .class_size = sizeof(PnvMachineClass),
1856 .interfaces = (InterfaceInfo[]) {
1857 { TYPE_INTERRUPT_STATS_PROVIDER },
1858 { },
1859 },
1860 },
1861 {
1862 .name = TYPE_PNV_CHIP,
1863 .parent = TYPE_SYS_BUS_DEVICE,
1864 .class_init = pnv_chip_class_init,
1865 .instance_size = sizeof(PnvChip),
1866 .class_size = sizeof(PnvChipClass),
1867 .abstract = true,
1868 },
1869
1870 /*
1871 * P10 chip and variants
1872 */
1873 {
1874 .name = TYPE_PNV10_CHIP,
1875 .parent = TYPE_PNV_CHIP,
1876 .instance_init = pnv_chip_power10_instance_init,
1877 .instance_size = sizeof(Pnv10Chip),
1878 },
1879 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
1880
1881 /*
1882 * P9 chip and variants
1883 */
1884 {
1885 .name = TYPE_PNV9_CHIP,
1886 .parent = TYPE_PNV_CHIP,
1887 .instance_init = pnv_chip_power9_instance_init,
1888 .instance_size = sizeof(Pnv9Chip),
1889 },
1890 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1891
1892 /*
1893 * P8 chip and variants
1894 */
1895 {
1896 .name = TYPE_PNV8_CHIP,
1897 .parent = TYPE_PNV_CHIP,
1898 .instance_init = pnv_chip_power8_instance_init,
1899 .instance_size = sizeof(Pnv8Chip),
1900 },
1901 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1902 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1903 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1904 pnv_chip_power8nvl_class_init),
1905 };
1906
1907 DEFINE_TYPES(types)
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