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ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR
[mirror_qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qemu/units.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "qemu/log.h"
35 #include "hw/ppc/fdt.h"
36 #include "hw/ppc/ppc.h"
37 #include "hw/ppc/pnv.h"
38 #include "hw/ppc/pnv_core.h"
39 #include "hw/loader.h"
40 #include "hw/nmi.h"
41 #include "exec/address-spaces.h"
42 #include "qapi/visitor.h"
43 #include "monitor/monitor.h"
44 #include "hw/intc/intc.h"
45 #include "hw/ipmi/ipmi.h"
46 #include "target/ppc/mmu-hash64.h"
47 #include "hw/pci/msi.h"
48
49 #include "hw/ppc/xics.h"
50 #include "hw/qdev-properties.h"
51 #include "hw/ppc/pnv_xscom.h"
52 #include "hw/ppc/pnv_pnor.h"
53
54 #include "hw/isa/isa.h"
55 #include "hw/boards.h"
56 #include "hw/char/serial.h"
57 #include "hw/rtc/mc146818rtc.h"
58
59 #include <libfdt.h>
60
61 #define FDT_MAX_SIZE (1 * MiB)
62
63 #define FW_FILE_NAME "skiboot.lid"
64 #define FW_LOAD_ADDR 0x0
65 #define FW_MAX_SIZE (16 * MiB)
66
67 #define KERNEL_LOAD_ADDR 0x20000000
68 #define KERNEL_MAX_SIZE (128 * MiB)
69 #define INITRD_LOAD_ADDR 0x28000000
70 #define INITRD_MAX_SIZE (128 * MiB)
71
72 static const char *pnv_chip_core_typename(const PnvChip *o)
73 {
74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
77 const char *core_type = object_class_get_name(object_class_by_name(s));
78 g_free(s);
79 return core_type;
80 }
81
82 /*
83 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
84 * 4 * 4 sockets * 12 cores * 8 threads = 1536
85 * Let's make it 2^11
86 */
87 #define MAX_CPUS 2048
88
89 /*
90 * Memory nodes are created by hostboot, one for each range of memory
91 * that has a different "affinity". In practice, it means one range
92 * per chip.
93 */
94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
95 {
96 char *mem_name;
97 uint64_t mem_reg_property[2];
98 int off;
99
100 mem_reg_property[0] = cpu_to_be64(start);
101 mem_reg_property[1] = cpu_to_be64(size);
102
103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
104 off = fdt_add_subnode(fdt, 0, mem_name);
105 g_free(mem_name);
106
107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
109 sizeof(mem_reg_property))));
110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
111 }
112
113 static int get_cpus_node(void *fdt)
114 {
115 int cpus_offset = fdt_path_offset(fdt, "/cpus");
116
117 if (cpus_offset < 0) {
118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
119 if (cpus_offset) {
120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
122 }
123 }
124 _FDT(cpus_offset);
125 return cpus_offset;
126 }
127
128 /*
129 * The PowerNV cores (and threads) need to use real HW ids and not an
130 * incremental index like it has been done on other platforms. This HW
131 * id is stored in the CPU PIR, it is used to create cpu nodes in the
132 * device tree, used in XSCOM to address cores and in interrupt
133 * servers.
134 */
135 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
136 {
137 PowerPCCPU *cpu = pc->threads[0];
138 CPUState *cs = CPU(cpu);
139 DeviceClass *dc = DEVICE_GET_CLASS(cs);
140 int smt_threads = CPU_CORE(pc)->nr_threads;
141 CPUPPCState *env = &cpu->env;
142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
143 uint32_t servers_prop[smt_threads];
144 int i;
145 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
146 0xffffffff, 0xffffffff};
147 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
148 uint32_t cpufreq = 1000000000;
149 uint32_t page_sizes_prop[64];
150 size_t page_sizes_prop_size;
151 const uint8_t pa_features[] = { 24, 0,
152 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
153 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
154 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
155 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
156 int offset;
157 char *nodename;
158 int cpus_offset = get_cpus_node(fdt);
159
160 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
161 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
162 _FDT(offset);
163 g_free(nodename);
164
165 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
166
167 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
168 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
169 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
170
171 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
175 env->dcache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
177 env->icache_line_size)));
178 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
179 env->icache_line_size)));
180
181 if (pcc->l1_dcache_size) {
182 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
183 pcc->l1_dcache_size)));
184 } else {
185 warn_report("Unknown L1 dcache size for cpu");
186 }
187 if (pcc->l1_icache_size) {
188 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
189 pcc->l1_icache_size)));
190 } else {
191 warn_report("Unknown L1 icache size for cpu");
192 }
193
194 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
195 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
196 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
197 cpu->hash64_opts->slb_size)));
198 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
199 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
200
201 if (env->spr_cb[SPR_PURR].oea_read) {
202 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
203 }
204
205 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
206 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
207 segs, sizeof(segs))));
208 }
209
210 /*
211 * Advertise VMX/VSX (vector extensions) if available
212 * 0 / no property == no vector extensions
213 * 1 == VMX / Altivec available
214 * 2 == VSX available
215 */
216 if (env->insns_flags & PPC_ALTIVEC) {
217 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
218
219 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
220 }
221
222 /*
223 * Advertise DFP (Decimal Floating Point) if available
224 * 0 / no property == no DFP
225 * 1 == DFP available
226 */
227 if (env->insns_flags2 & PPC2_DFP) {
228 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
229 }
230
231 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
232 sizeof(page_sizes_prop));
233 if (page_sizes_prop_size) {
234 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
235 page_sizes_prop, page_sizes_prop_size)));
236 }
237
238 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
239 pa_features, sizeof(pa_features))));
240
241 /* Build interrupt servers properties */
242 for (i = 0; i < smt_threads; i++) {
243 servers_prop[i] = cpu_to_be32(pc->pir + i);
244 }
245 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
246 servers_prop, sizeof(servers_prop))));
247 }
248
249 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
250 uint32_t nr_threads)
251 {
252 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
253 char *name;
254 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
255 uint32_t irange[2], i, rsize;
256 uint64_t *reg;
257 int offset;
258
259 irange[0] = cpu_to_be32(pir);
260 irange[1] = cpu_to_be32(nr_threads);
261
262 rsize = sizeof(uint64_t) * 2 * nr_threads;
263 reg = g_malloc(rsize);
264 for (i = 0; i < nr_threads; i++) {
265 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
266 reg[i * 2 + 1] = cpu_to_be64(0x1000);
267 }
268
269 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
270 offset = fdt_add_subnode(fdt, 0, name);
271 _FDT(offset);
272 g_free(name);
273
274 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
275 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
276 _FDT((fdt_setprop_string(fdt, offset, "device_type",
277 "PowerPC-External-Interrupt-Presentation")));
278 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
279 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
280 irange, sizeof(irange))));
281 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
282 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
283 g_free(reg);
284 }
285
286 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
287 {
288 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
289 int i;
290
291 pnv_dt_xscom(chip, fdt, 0,
292 cpu_to_be64(PNV_XSCOM_BASE(chip)),
293 cpu_to_be64(PNV_XSCOM_SIZE),
294 compat, sizeof(compat));
295
296 for (i = 0; i < chip->nr_cores; i++) {
297 PnvCore *pnv_core = chip->cores[i];
298
299 pnv_dt_core(chip, pnv_core, fdt);
300
301 /* Interrupt Control Presenters (ICP). One per core. */
302 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
303 }
304
305 if (chip->ram_size) {
306 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
307 }
308 }
309
310 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
311 {
312 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
313 int i;
314
315 pnv_dt_xscom(chip, fdt, 0,
316 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
317 cpu_to_be64(PNV9_XSCOM_SIZE),
318 compat, sizeof(compat));
319
320 for (i = 0; i < chip->nr_cores; i++) {
321 PnvCore *pnv_core = chip->cores[i];
322
323 pnv_dt_core(chip, pnv_core, fdt);
324 }
325
326 if (chip->ram_size) {
327 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
328 }
329
330 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
331 }
332
333 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
334 {
335 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
336 int i;
337
338 pnv_dt_xscom(chip, fdt, 0,
339 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
340 cpu_to_be64(PNV10_XSCOM_SIZE),
341 compat, sizeof(compat));
342
343 for (i = 0; i < chip->nr_cores; i++) {
344 PnvCore *pnv_core = chip->cores[i];
345
346 pnv_dt_core(chip, pnv_core, fdt);
347 }
348
349 if (chip->ram_size) {
350 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
351 }
352
353 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
354 }
355
356 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
357 {
358 uint32_t io_base = d->ioport_id;
359 uint32_t io_regs[] = {
360 cpu_to_be32(1),
361 cpu_to_be32(io_base),
362 cpu_to_be32(2)
363 };
364 char *name;
365 int node;
366
367 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
368 node = fdt_add_subnode(fdt, lpc_off, name);
369 _FDT(node);
370 g_free(name);
371
372 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
373 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
374 }
375
376 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
377 {
378 const char compatible[] = "ns16550\0pnpPNP,501";
379 uint32_t io_base = d->ioport_id;
380 uint32_t io_regs[] = {
381 cpu_to_be32(1),
382 cpu_to_be32(io_base),
383 cpu_to_be32(8)
384 };
385 char *name;
386 int node;
387
388 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
389 node = fdt_add_subnode(fdt, lpc_off, name);
390 _FDT(node);
391 g_free(name);
392
393 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
394 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
395 sizeof(compatible))));
396
397 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
398 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
399 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
400 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
401 fdt_get_phandle(fdt, lpc_off))));
402
403 /* This is needed by Linux */
404 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
405 }
406
407 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
408 {
409 const char compatible[] = "bt\0ipmi-bt";
410 uint32_t io_base;
411 uint32_t io_regs[] = {
412 cpu_to_be32(1),
413 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
414 cpu_to_be32(3)
415 };
416 uint32_t irq;
417 char *name;
418 int node;
419
420 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
421 io_regs[1] = cpu_to_be32(io_base);
422
423 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
424
425 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
426 node = fdt_add_subnode(fdt, lpc_off, name);
427 _FDT(node);
428 g_free(name);
429
430 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
431 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
432 sizeof(compatible))));
433
434 /* Mark it as reserved to avoid Linux trying to claim it */
435 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
436 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
437 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
438 fdt_get_phandle(fdt, lpc_off))));
439 }
440
441 typedef struct ForeachPopulateArgs {
442 void *fdt;
443 int offset;
444 } ForeachPopulateArgs;
445
446 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
447 {
448 ForeachPopulateArgs *args = opaque;
449 ISADevice *d = ISA_DEVICE(dev);
450
451 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
452 pnv_dt_rtc(d, args->fdt, args->offset);
453 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
454 pnv_dt_serial(d, args->fdt, args->offset);
455 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
456 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
457 } else {
458 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
459 d->ioport_id);
460 }
461
462 return 0;
463 }
464
465 /*
466 * The default LPC bus of a multichip system is on chip 0. It's
467 * recognized by the firmware (skiboot) using a "primary" property.
468 */
469 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
470 {
471 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
472 ForeachPopulateArgs args = {
473 .fdt = fdt,
474 .offset = isa_offset,
475 };
476 uint32_t phandle;
477
478 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
479
480 phandle = qemu_fdt_alloc_phandle(fdt);
481 assert(phandle > 0);
482 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
483
484 /*
485 * ISA devices are not necessarily parented to the ISA bus so we
486 * can not use object_child_foreach()
487 */
488 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
489 &args);
490 }
491
492 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
493 {
494 int off;
495
496 off = fdt_add_subnode(fdt, 0, "ibm,opal");
497 off = fdt_add_subnode(fdt, off, "power-mgt");
498
499 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
500 }
501
502 static void *pnv_dt_create(MachineState *machine)
503 {
504 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
505 PnvMachineState *pnv = PNV_MACHINE(machine);
506 void *fdt;
507 char *buf;
508 int off;
509 int i;
510
511 fdt = g_malloc0(FDT_MAX_SIZE);
512 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
513
514 /* /qemu node */
515 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
516
517 /* Root node */
518 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
519 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
520 _FDT((fdt_setprop_string(fdt, 0, "model",
521 "IBM PowerNV (emulated by qemu)")));
522 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
523
524 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
525 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
526 if (qemu_uuid_set) {
527 _FDT((fdt_property_string(fdt, "system-id", buf)));
528 }
529 g_free(buf);
530
531 off = fdt_add_subnode(fdt, 0, "chosen");
532 if (machine->kernel_cmdline) {
533 _FDT((fdt_setprop_string(fdt, off, "bootargs",
534 machine->kernel_cmdline)));
535 }
536
537 if (pnv->initrd_size) {
538 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
539 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
540
541 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
542 &start_prop, sizeof(start_prop))));
543 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
544 &end_prop, sizeof(end_prop))));
545 }
546
547 /* Populate device tree for each chip */
548 for (i = 0; i < pnv->num_chips; i++) {
549 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
550 }
551
552 /* Populate ISA devices on chip 0 */
553 pnv_dt_isa(pnv, fdt);
554
555 if (pnv->bmc) {
556 pnv_dt_bmc_sensors(pnv->bmc, fdt);
557 }
558
559 /* Create an extra node for power management on machines that support it */
560 if (pmc->dt_power_mgt) {
561 pmc->dt_power_mgt(pnv, fdt);
562 }
563
564 return fdt;
565 }
566
567 static void pnv_powerdown_notify(Notifier *n, void *opaque)
568 {
569 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
570
571 if (pnv->bmc) {
572 pnv_bmc_powerdown(pnv->bmc);
573 }
574 }
575
576 static void pnv_reset(MachineState *machine)
577 {
578 PnvMachineState *pnv = PNV_MACHINE(machine);
579 IPMIBmc *bmc;
580 void *fdt;
581
582 qemu_devices_reset();
583
584 /*
585 * The machine should provide by default an internal BMC simulator.
586 * If not, try to use the BMC device that was provided on the command
587 * line.
588 */
589 bmc = pnv_bmc_find(&error_fatal);
590 if (!pnv->bmc) {
591 if (!bmc) {
592 if (!qtest_enabled()) {
593 warn_report("machine has no BMC device. Use '-device "
594 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
595 "to define one");
596 }
597 } else {
598 pnv_bmc_set_pnor(bmc, pnv->pnor);
599 pnv->bmc = bmc;
600 }
601 }
602
603 fdt = pnv_dt_create(machine);
604
605 /* Pack resulting tree */
606 _FDT((fdt_pack(fdt)));
607
608 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
609 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
610
611 g_free(fdt);
612 }
613
614 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
615 {
616 Pnv8Chip *chip8 = PNV8_CHIP(chip);
617 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
618 }
619
620 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
621 {
622 Pnv8Chip *chip8 = PNV8_CHIP(chip);
623 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
624 }
625
626 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
627 {
628 Pnv9Chip *chip9 = PNV9_CHIP(chip);
629 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
630 }
631
632 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
633 {
634 Pnv10Chip *chip10 = PNV10_CHIP(chip);
635 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
636 }
637
638 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
639 {
640 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
641 }
642
643 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
644 {
645 Pnv8Chip *chip8 = PNV8_CHIP(chip);
646 int i;
647
648 ics_pic_print_info(&chip8->psi.ics, mon);
649 for (i = 0; i < chip->num_phbs; i++) {
650 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon);
651 ics_pic_print_info(&chip8->phbs[i].lsis, mon);
652 }
653 }
654
655 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
656 {
657 Pnv9Chip *chip9 = PNV9_CHIP(chip);
658 int i, j;
659
660 pnv_xive_pic_print_info(&chip9->xive, mon);
661 pnv_psi_pic_print_info(&chip9->psi, mon);
662
663 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
664 PnvPhb4PecState *pec = &chip9->pecs[i];
665 for (j = 0; j < pec->num_stacks; j++) {
666 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon);
667 }
668 }
669 }
670
671 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
672 uint32_t core_id)
673 {
674 return PNV_XSCOM_EX_BASE(core_id);
675 }
676
677 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
678 uint32_t core_id)
679 {
680 return PNV9_XSCOM_EC_BASE(core_id);
681 }
682
683 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
684 uint32_t core_id)
685 {
686 return PNV10_XSCOM_EC_BASE(core_id);
687 }
688
689 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
690 {
691 PowerPCCPUClass *ppc_default =
692 POWERPC_CPU_CLASS(object_class_by_name(default_type));
693 PowerPCCPUClass *ppc =
694 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
695
696 return ppc_default->pvr_match(ppc_default, ppc->pvr);
697 }
698
699 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
700 {
701 ISADevice *dev = isa_new("isa-ipmi-bt");
702
703 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
704 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
705 isa_realize_and_unref(dev, bus, &error_fatal);
706 }
707
708 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
709 {
710 Pnv10Chip *chip10 = PNV10_CHIP(chip);
711
712 pnv_psi_pic_print_info(&chip10->psi, mon);
713 }
714
715 static void pnv_init(MachineState *machine)
716 {
717 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
718 PnvMachineState *pnv = PNV_MACHINE(machine);
719 MachineClass *mc = MACHINE_GET_CLASS(machine);
720 char *fw_filename;
721 long fw_size;
722 int i;
723 char *chip_typename;
724 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
725 DeviceState *dev;
726
727 /* allocate RAM */
728 if (machine->ram_size < (1 * GiB)) {
729 warn_report("skiboot may not work with < 1GB of RAM");
730 }
731 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
732
733 /*
734 * Create our simple PNOR device
735 */
736 dev = qdev_new(TYPE_PNV_PNOR);
737 if (pnor) {
738 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
739 }
740 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
741 pnv->pnor = PNV_PNOR(dev);
742
743 /* load skiboot firmware */
744 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
745 if (!fw_filename) {
746 error_report("Could not find OPAL firmware '%s'", bios_name);
747 exit(1);
748 }
749
750 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
751 if (fw_size < 0) {
752 error_report("Could not load OPAL firmware '%s'", fw_filename);
753 exit(1);
754 }
755 g_free(fw_filename);
756
757 /* load kernel */
758 if (machine->kernel_filename) {
759 long kernel_size;
760
761 kernel_size = load_image_targphys(machine->kernel_filename,
762 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
763 if (kernel_size < 0) {
764 error_report("Could not load kernel '%s'",
765 machine->kernel_filename);
766 exit(1);
767 }
768 }
769
770 /* load initrd */
771 if (machine->initrd_filename) {
772 pnv->initrd_base = INITRD_LOAD_ADDR;
773 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
774 pnv->initrd_base, INITRD_MAX_SIZE);
775 if (pnv->initrd_size < 0) {
776 error_report("Could not load initial ram disk '%s'",
777 machine->initrd_filename);
778 exit(1);
779 }
780 }
781
782 /* MSIs are supported on this platform */
783 msi_nonbroken = true;
784
785 /*
786 * Check compatibility of the specified CPU with the machine
787 * default.
788 */
789 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
790 error_report("invalid CPU model '%s' for %s machine",
791 machine->cpu_type, mc->name);
792 exit(1);
793 }
794
795 /* Create the processor chips */
796 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
797 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
798 i, machine->cpu_type);
799 if (!object_class_by_name(chip_typename)) {
800 error_report("invalid chip model '%.*s' for %s machine",
801 i, machine->cpu_type, mc->name);
802 exit(1);
803 }
804
805 pnv->num_chips =
806 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
807 /*
808 * TODO: should we decide on how many chips we can create based
809 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
810 */
811 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
812 error_report("invalid number of chips: '%d'", pnv->num_chips);
813 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
814 exit(1);
815 }
816
817 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
818 for (i = 0; i < pnv->num_chips; i++) {
819 char chip_name[32];
820 Object *chip = OBJECT(qdev_new(chip_typename));
821
822 pnv->chips[i] = PNV_CHIP(chip);
823
824 /*
825 * TODO: put all the memory in one node on chip 0 until we find a
826 * way to specify different ranges for each chip
827 */
828 if (i == 0) {
829 object_property_set_int(chip, "ram-size", machine->ram_size,
830 &error_fatal);
831 }
832
833 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
834 object_property_add_child(OBJECT(pnv), chip_name, chip);
835 object_property_set_int(chip, "chip-id", PNV_CHIP_HWID(i),
836 &error_fatal);
837 object_property_set_int(chip, "nr-cores", machine->smp.cores,
838 &error_fatal);
839 object_property_set_int(chip, "nr-threads", machine->smp.threads,
840 &error_fatal);
841 /*
842 * The POWER8 machine use the XICS interrupt interface.
843 * Propagate the XICS fabric to the chip and its controllers.
844 */
845 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
846 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
847 }
848 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
849 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
850 &error_abort);
851 }
852 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
853 }
854 g_free(chip_typename);
855
856 /* Instantiate ISA bus on chip 0 */
857 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
858
859 /* Create serial port */
860 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
861
862 /* Create an RTC ISA device too */
863 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
864
865 /*
866 * Create the machine BMC simulator and the IPMI BT device for
867 * communication with the BMC
868 */
869 if (defaults_enabled()) {
870 pnv->bmc = pnv_bmc_create(pnv->pnor);
871 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
872 }
873
874 /*
875 * The PNOR is mapped on the LPC FW address space by the BMC.
876 * Since we can not reach the remote BMC machine with LPC memops,
877 * map it always for now.
878 */
879 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
880 &pnv->pnor->mmio);
881
882 /*
883 * OpenPOWER systems use a IPMI SEL Event message to notify the
884 * host to powerdown
885 */
886 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
887 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
888 }
889
890 /*
891 * 0:21 Reserved - Read as zeros
892 * 22:24 Chip ID
893 * 25:28 Core number
894 * 29:31 Thread ID
895 */
896 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
897 {
898 return (chip->chip_id << 7) | (core_id << 3);
899 }
900
901 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
902 Error **errp)
903 {
904 Pnv8Chip *chip8 = PNV8_CHIP(chip);
905 Error *local_err = NULL;
906 Object *obj;
907 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
908
909 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
910 if (local_err) {
911 error_propagate(errp, local_err);
912 return;
913 }
914
915 pnv_cpu->intc = obj;
916 }
917
918
919 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
920 {
921 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
922
923 icp_reset(ICP(pnv_cpu->intc));
924 }
925
926 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
927 {
928 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
929
930 icp_destroy(ICP(pnv_cpu->intc));
931 pnv_cpu->intc = NULL;
932 }
933
934 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
935 Monitor *mon)
936 {
937 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
938 }
939
940 /*
941 * 0:48 Reserved - Read as zeroes
942 * 49:52 Node ID
943 * 53:55 Chip ID
944 * 56 Reserved - Read as zero
945 * 57:61 Core number
946 * 62:63 Thread ID
947 *
948 * We only care about the lower bits. uint32_t is fine for the moment.
949 */
950 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
951 {
952 return (chip->chip_id << 8) | (core_id << 2);
953 }
954
955 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
956 {
957 return (chip->chip_id << 8) | (core_id << 2);
958 }
959
960 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
961 Error **errp)
962 {
963 Pnv9Chip *chip9 = PNV9_CHIP(chip);
964 Error *local_err = NULL;
965 Object *obj;
966 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
967
968 /*
969 * The core creates its interrupt presenter but the XIVE interrupt
970 * controller object is initialized afterwards. Hopefully, it's
971 * only used at runtime.
972 */
973 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
974 &local_err);
975 if (local_err) {
976 error_propagate(errp, local_err);
977 return;
978 }
979
980 pnv_cpu->intc = obj;
981 }
982
983 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
984 {
985 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
986
987 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
988 }
989
990 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
991 {
992 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
993
994 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
995 pnv_cpu->intc = NULL;
996 }
997
998 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
999 Monitor *mon)
1000 {
1001 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1002 }
1003
1004 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1005 Error **errp)
1006 {
1007 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1008
1009 /* Will be defined when the interrupt controller is */
1010 pnv_cpu->intc = NULL;
1011 }
1012
1013 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1014 {
1015 ;
1016 }
1017
1018 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1019 {
1020 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1021
1022 pnv_cpu->intc = NULL;
1023 }
1024
1025 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1026 Monitor *mon)
1027 {
1028 }
1029
1030 /*
1031 * Allowed core identifiers on a POWER8 Processor Chip :
1032 *
1033 * <EX0 reserved>
1034 * EX1 - Venice only
1035 * EX2 - Venice only
1036 * EX3 - Venice only
1037 * EX4
1038 * EX5
1039 * EX6
1040 * <EX7,8 reserved> <reserved>
1041 * EX9 - Venice only
1042 * EX10 - Venice only
1043 * EX11 - Venice only
1044 * EX12
1045 * EX13
1046 * EX14
1047 * <EX15 reserved>
1048 */
1049 #define POWER8E_CORE_MASK (0x7070ull)
1050 #define POWER8_CORE_MASK (0x7e7eull)
1051
1052 /*
1053 * POWER9 has 24 cores, ids starting at 0x0
1054 */
1055 #define POWER9_CORE_MASK (0xffffffffffffffull)
1056
1057
1058 #define POWER10_CORE_MASK (0xffffffffffffffull)
1059
1060 static void pnv_chip_power8_instance_init(Object *obj)
1061 {
1062 PnvChip *chip = PNV_CHIP(obj);
1063 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1064 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1065 int i;
1066
1067 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1068 (Object **)&chip8->xics,
1069 object_property_allow_set_link,
1070 OBJ_PROP_LINK_STRONG);
1071
1072 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1073
1074 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1075
1076 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1077
1078 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1079
1080 for (i = 0; i < pcc->num_phbs; i++) {
1081 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
1082 }
1083
1084 /*
1085 * Number of PHBs is the chip default
1086 */
1087 chip->num_phbs = pcc->num_phbs;
1088 }
1089
1090 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1091 {
1092 PnvChip *chip = PNV_CHIP(chip8);
1093 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1094 int i, j;
1095 char *name;
1096
1097 name = g_strdup_printf("icp-%x", chip->chip_id);
1098 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1099 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1100 g_free(name);
1101
1102 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1103
1104 /* Map the ICP registers for each thread */
1105 for (i = 0; i < chip->nr_cores; i++) {
1106 PnvCore *pnv_core = chip->cores[i];
1107 int core_hwid = CPU_CORE(pnv_core)->core_id;
1108
1109 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1110 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1111 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1112
1113 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1114 &icp->mmio);
1115 }
1116 }
1117 }
1118
1119 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1120 {
1121 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1122 PnvChip *chip = PNV_CHIP(dev);
1123 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1124 Pnv8Psi *psi8 = &chip8->psi;
1125 Error *local_err = NULL;
1126 int i;
1127
1128 assert(chip8->xics);
1129
1130 /* XSCOM bridge is first */
1131 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1132 if (local_err) {
1133 error_propagate(errp, local_err);
1134 return;
1135 }
1136 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1137
1138 pcc->parent_realize(dev, &local_err);
1139 if (local_err) {
1140 error_propagate(errp, local_err);
1141 return;
1142 }
1143
1144 /* Processor Service Interface (PSI) Host Bridge */
1145 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1146 &error_fatal);
1147 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1148 OBJECT(chip8->xics), &error_abort);
1149 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1150 return;
1151 }
1152 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1153 &PNV_PSI(psi8)->xscom_regs);
1154
1155 /* Create LPC controller */
1156 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
1157 &error_abort);
1158 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1159 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1160
1161 chip->fw_mr = &chip8->lpc.isa_fw;
1162 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1163 (uint64_t) PNV_XSCOM_BASE(chip),
1164 PNV_XSCOM_LPC_BASE);
1165
1166 /*
1167 * Interrupt Management Area. This is the memory region holding
1168 * all the Interrupt Control Presenter (ICP) registers
1169 */
1170 pnv_chip_icp_realize(chip8, &local_err);
1171 if (local_err) {
1172 error_propagate(errp, local_err);
1173 return;
1174 }
1175
1176 /* Create the simplified OCC model */
1177 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
1178 &error_abort);
1179 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1180 return;
1181 }
1182 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1183
1184 /* OCC SRAM model */
1185 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1186 &chip8->occ.sram_regs);
1187
1188 /* HOMER */
1189 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1190 &error_abort);
1191 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1192 return;
1193 }
1194 /* Homer Xscom region */
1195 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1196
1197 /* Homer mmio region */
1198 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1199 &chip8->homer.regs);
1200
1201 /* PHB3 controllers */
1202 for (i = 0; i < chip->num_phbs; i++) {
1203 PnvPHB3 *phb = &chip8->phbs[i];
1204 PnvPBCQState *pbcq = &phb->pbcq;
1205
1206 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1207 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1208 &error_fatal);
1209 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1210 return;
1211 }
1212
1213 /* Populate the XSCOM address space. */
1214 pnv_xscom_add_subregion(chip,
1215 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id,
1216 &pbcq->xscom_nest_regs);
1217 pnv_xscom_add_subregion(chip,
1218 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id,
1219 &pbcq->xscom_pci_regs);
1220 pnv_xscom_add_subregion(chip,
1221 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id,
1222 &pbcq->xscom_spci_regs);
1223 }
1224 }
1225
1226 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1227 {
1228 addr &= (PNV_XSCOM_SIZE - 1);
1229 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1230 }
1231
1232 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1233 {
1234 DeviceClass *dc = DEVICE_CLASS(klass);
1235 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1236
1237 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1238 k->cores_mask = POWER8E_CORE_MASK;
1239 k->num_phbs = 3;
1240 k->core_pir = pnv_chip_core_pir_p8;
1241 k->intc_create = pnv_chip_power8_intc_create;
1242 k->intc_reset = pnv_chip_power8_intc_reset;
1243 k->intc_destroy = pnv_chip_power8_intc_destroy;
1244 k->intc_print_info = pnv_chip_power8_intc_print_info;
1245 k->isa_create = pnv_chip_power8_isa_create;
1246 k->dt_populate = pnv_chip_power8_dt_populate;
1247 k->pic_print_info = pnv_chip_power8_pic_print_info;
1248 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1249 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1250 dc->desc = "PowerNV Chip POWER8E";
1251
1252 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1253 &k->parent_realize);
1254 }
1255
1256 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1257 {
1258 DeviceClass *dc = DEVICE_CLASS(klass);
1259 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1260
1261 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1262 k->cores_mask = POWER8_CORE_MASK;
1263 k->num_phbs = 3;
1264 k->core_pir = pnv_chip_core_pir_p8;
1265 k->intc_create = pnv_chip_power8_intc_create;
1266 k->intc_reset = pnv_chip_power8_intc_reset;
1267 k->intc_destroy = pnv_chip_power8_intc_destroy;
1268 k->intc_print_info = pnv_chip_power8_intc_print_info;
1269 k->isa_create = pnv_chip_power8_isa_create;
1270 k->dt_populate = pnv_chip_power8_dt_populate;
1271 k->pic_print_info = pnv_chip_power8_pic_print_info;
1272 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1273 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1274 dc->desc = "PowerNV Chip POWER8";
1275
1276 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1277 &k->parent_realize);
1278 }
1279
1280 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1281 {
1282 DeviceClass *dc = DEVICE_CLASS(klass);
1283 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1284
1285 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1286 k->cores_mask = POWER8_CORE_MASK;
1287 k->num_phbs = 3;
1288 k->core_pir = pnv_chip_core_pir_p8;
1289 k->intc_create = pnv_chip_power8_intc_create;
1290 k->intc_reset = pnv_chip_power8_intc_reset;
1291 k->intc_destroy = pnv_chip_power8_intc_destroy;
1292 k->intc_print_info = pnv_chip_power8_intc_print_info;
1293 k->isa_create = pnv_chip_power8nvl_isa_create;
1294 k->dt_populate = pnv_chip_power8_dt_populate;
1295 k->pic_print_info = pnv_chip_power8_pic_print_info;
1296 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1297 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1298 dc->desc = "PowerNV Chip POWER8NVL";
1299
1300 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1301 &k->parent_realize);
1302 }
1303
1304 static void pnv_chip_power9_instance_init(Object *obj)
1305 {
1306 PnvChip *chip = PNV_CHIP(obj);
1307 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1308 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1309 int i;
1310
1311 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1312 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1313 "xive-fabric");
1314
1315 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1316
1317 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1318
1319 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1320
1321 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1322
1323 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
1324 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1325 TYPE_PNV_PHB4_PEC);
1326 }
1327
1328 /*
1329 * Number of PHBs is the chip default
1330 */
1331 chip->num_phbs = pcc->num_phbs;
1332 }
1333
1334 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1335 {
1336 PnvChip *chip = PNV_CHIP(chip9);
1337 int i;
1338
1339 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1340 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1341
1342 for (i = 0; i < chip9->nr_quads; i++) {
1343 char eq_name[32];
1344 PnvQuad *eq = &chip9->quads[i];
1345 PnvCore *pnv_core = chip->cores[i * 4];
1346 int core_id = CPU_CORE(pnv_core)->core_id;
1347
1348 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1349 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1350 sizeof(*eq), TYPE_PNV_QUAD,
1351 &error_fatal, NULL);
1352
1353 object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal);
1354 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1355
1356 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1357 &eq->xscom_regs);
1358 }
1359 }
1360
1361 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
1362 {
1363 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1364 int i, j;
1365 int phb_id = 0;
1366
1367 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
1368 PnvPhb4PecState *pec = &chip9->pecs[i];
1369 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1370 uint32_t pec_nest_base;
1371 uint32_t pec_pci_base;
1372
1373 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1374 /*
1375 * PEC0 -> 1 stack
1376 * PEC1 -> 2 stacks
1377 * PEC2 -> 3 stacks
1378 */
1379 object_property_set_int(OBJECT(pec), "num-stacks", i + 1,
1380 &error_fatal);
1381 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1382 &error_fatal);
1383 object_property_set_link(OBJECT(pec), "system-memory",
1384 OBJECT(get_system_memory()), &error_abort);
1385 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1386 return;
1387 }
1388
1389 pec_nest_base = pecc->xscom_nest_base(pec);
1390 pec_pci_base = pecc->xscom_pci_base(pec);
1391
1392 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1393 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1394
1395 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs;
1396 j++, phb_id++) {
1397 PnvPhb4PecStack *stack = &pec->stacks[j];
1398 Object *obj = OBJECT(&stack->phb);
1399
1400 object_property_set_int(obj, "index", phb_id, &error_fatal);
1401 object_property_set_int(obj, "chip-id", chip->chip_id,
1402 &error_fatal);
1403 object_property_set_int(obj, "version", PNV_PHB4_VERSION,
1404 &error_fatal);
1405 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID,
1406 &error_fatal);
1407 object_property_set_link(obj, "stack", OBJECT(stack),
1408 &error_abort);
1409 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) {
1410 return;
1411 }
1412
1413 /* Populate the XSCOM address space. */
1414 pnv_xscom_add_subregion(chip,
1415 pec_nest_base + 0x40 * (stack->stack_no + 1),
1416 &stack->nest_regs_mr);
1417 pnv_xscom_add_subregion(chip,
1418 pec_pci_base + 0x40 * (stack->stack_no + 1),
1419 &stack->pci_regs_mr);
1420 pnv_xscom_add_subregion(chip,
1421 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
1422 0x40 * stack->stack_no,
1423 &stack->phb_regs_mr);
1424 }
1425 }
1426 }
1427
1428 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1429 {
1430 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1431 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1432 PnvChip *chip = PNV_CHIP(dev);
1433 Pnv9Psi *psi9 = &chip9->psi;
1434 Error *local_err = NULL;
1435
1436 /* XSCOM bridge is first */
1437 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1438 if (local_err) {
1439 error_propagate(errp, local_err);
1440 return;
1441 }
1442 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1443
1444 pcc->parent_realize(dev, &local_err);
1445 if (local_err) {
1446 error_propagate(errp, local_err);
1447 return;
1448 }
1449
1450 pnv_chip_quad_realize(chip9, &local_err);
1451 if (local_err) {
1452 error_propagate(errp, local_err);
1453 return;
1454 }
1455
1456 /* XIVE interrupt controller (POWER9) */
1457 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1458 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1459 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1460 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1461 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1462 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1463 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1464 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1465 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1466 &error_abort);
1467 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1468 return;
1469 }
1470 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1471 &chip9->xive.xscom_regs);
1472
1473 /* Processor Service Interface (PSI) Host Bridge */
1474 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1475 &error_fatal);
1476 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1477 return;
1478 }
1479 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1480 &PNV_PSI(psi9)->xscom_regs);
1481
1482 /* LPC */
1483 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
1484 &error_abort);
1485 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1486 return;
1487 }
1488 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1489 &chip9->lpc.xscom_regs);
1490
1491 chip->fw_mr = &chip9->lpc.isa_fw;
1492 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1493 (uint64_t) PNV9_LPCM_BASE(chip));
1494
1495 /* Create the simplified OCC model */
1496 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
1497 &error_abort);
1498 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1499 return;
1500 }
1501 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1502
1503 /* OCC SRAM model */
1504 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1505 &chip9->occ.sram_regs);
1506
1507 /* HOMER */
1508 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1509 &error_abort);
1510 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1511 return;
1512 }
1513 /* Homer Xscom region */
1514 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1515
1516 /* Homer mmio region */
1517 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1518 &chip9->homer.regs);
1519
1520 /* PHBs */
1521 pnv_chip_power9_phb_realize(chip, &local_err);
1522 if (local_err) {
1523 error_propagate(errp, local_err);
1524 return;
1525 }
1526 }
1527
1528 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1529 {
1530 addr &= (PNV9_XSCOM_SIZE - 1);
1531 return addr >> 3;
1532 }
1533
1534 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1535 {
1536 DeviceClass *dc = DEVICE_CLASS(klass);
1537 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1538
1539 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1540 k->cores_mask = POWER9_CORE_MASK;
1541 k->core_pir = pnv_chip_core_pir_p9;
1542 k->intc_create = pnv_chip_power9_intc_create;
1543 k->intc_reset = pnv_chip_power9_intc_reset;
1544 k->intc_destroy = pnv_chip_power9_intc_destroy;
1545 k->intc_print_info = pnv_chip_power9_intc_print_info;
1546 k->isa_create = pnv_chip_power9_isa_create;
1547 k->dt_populate = pnv_chip_power9_dt_populate;
1548 k->pic_print_info = pnv_chip_power9_pic_print_info;
1549 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1550 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1551 dc->desc = "PowerNV Chip POWER9";
1552 k->num_phbs = 6;
1553
1554 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1555 &k->parent_realize);
1556 }
1557
1558 static void pnv_chip_power10_instance_init(Object *obj)
1559 {
1560 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1561
1562 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1563 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1564 }
1565
1566 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1567 {
1568 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1569 PnvChip *chip = PNV_CHIP(dev);
1570 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1571 Error *local_err = NULL;
1572
1573 /* XSCOM bridge is first */
1574 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1575 if (local_err) {
1576 error_propagate(errp, local_err);
1577 return;
1578 }
1579 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1580
1581 pcc->parent_realize(dev, &local_err);
1582 if (local_err) {
1583 error_propagate(errp, local_err);
1584 return;
1585 }
1586
1587 /* Processor Service Interface (PSI) Host Bridge */
1588 object_property_set_int(OBJECT(&chip10->psi), "bar",
1589 PNV10_PSIHB_BASE(chip), &error_fatal);
1590 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1591 return;
1592 }
1593 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1594 &PNV_PSI(&chip10->psi)->xscom_regs);
1595
1596 /* LPC */
1597 object_property_set_link(OBJECT(&chip10->lpc), "psi",
1598 OBJECT(&chip10->psi), &error_abort);
1599 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1600 return;
1601 }
1602 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1603 &chip10->lpc.xscom_regs);
1604
1605 chip->fw_mr = &chip10->lpc.isa_fw;
1606 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1607 (uint64_t) PNV10_LPCM_BASE(chip));
1608 }
1609
1610 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1611 {
1612 addr &= (PNV10_XSCOM_SIZE - 1);
1613 return addr >> 3;
1614 }
1615
1616 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1617 {
1618 DeviceClass *dc = DEVICE_CLASS(klass);
1619 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1620
1621 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1622 k->cores_mask = POWER10_CORE_MASK;
1623 k->core_pir = pnv_chip_core_pir_p10;
1624 k->intc_create = pnv_chip_power10_intc_create;
1625 k->intc_reset = pnv_chip_power10_intc_reset;
1626 k->intc_destroy = pnv_chip_power10_intc_destroy;
1627 k->intc_print_info = pnv_chip_power10_intc_print_info;
1628 k->isa_create = pnv_chip_power10_isa_create;
1629 k->dt_populate = pnv_chip_power10_dt_populate;
1630 k->pic_print_info = pnv_chip_power10_pic_print_info;
1631 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1632 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1633 dc->desc = "PowerNV Chip POWER10";
1634
1635 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1636 &k->parent_realize);
1637 }
1638
1639 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1640 {
1641 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1642 int cores_max;
1643
1644 /*
1645 * No custom mask for this chip, let's use the default one from *
1646 * the chip class
1647 */
1648 if (!chip->cores_mask) {
1649 chip->cores_mask = pcc->cores_mask;
1650 }
1651
1652 /* filter alien core ids ! some are reserved */
1653 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1654 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1655 chip->cores_mask);
1656 return;
1657 }
1658 chip->cores_mask &= pcc->cores_mask;
1659
1660 /* now that we have a sane layout, let check the number of cores */
1661 cores_max = ctpop64(chip->cores_mask);
1662 if (chip->nr_cores > cores_max) {
1663 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1664 cores_max);
1665 return;
1666 }
1667 }
1668
1669 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1670 {
1671 Error *error = NULL;
1672 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1673 const char *typename = pnv_chip_core_typename(chip);
1674 int i, core_hwid;
1675 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1676
1677 if (!object_class_by_name(typename)) {
1678 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1679 return;
1680 }
1681
1682 /* Cores */
1683 pnv_chip_core_sanitize(chip, &error);
1684 if (error) {
1685 error_propagate(errp, error);
1686 return;
1687 }
1688
1689 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1690
1691 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1692 && (i < chip->nr_cores); core_hwid++) {
1693 char core_name[32];
1694 PnvCore *pnv_core;
1695 uint64_t xscom_core_base;
1696
1697 if (!(chip->cores_mask & (1ull << core_hwid))) {
1698 continue;
1699 }
1700
1701 pnv_core = PNV_CORE(object_new(typename));
1702
1703 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1704 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1705 chip->cores[i] = pnv_core;
1706 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1707 chip->nr_threads, &error_fatal);
1708 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1709 core_hwid, &error_fatal);
1710 object_property_set_int(OBJECT(pnv_core), "pir",
1711 pcc->core_pir(chip, core_hwid), &error_fatal);
1712 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1713 &error_fatal);
1714 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1715 &error_abort);
1716 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1717
1718 /* Each core has an XSCOM MMIO region */
1719 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1720
1721 pnv_xscom_add_subregion(chip, xscom_core_base,
1722 &pnv_core->xscom_regs);
1723 i++;
1724 }
1725 }
1726
1727 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1728 {
1729 PnvChip *chip = PNV_CHIP(dev);
1730 Error *error = NULL;
1731
1732 /* Cores */
1733 pnv_chip_core_realize(chip, &error);
1734 if (error) {
1735 error_propagate(errp, error);
1736 return;
1737 }
1738 }
1739
1740 static Property pnv_chip_properties[] = {
1741 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1742 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1743 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1744 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1745 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1746 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1747 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0),
1748 DEFINE_PROP_END_OF_LIST(),
1749 };
1750
1751 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1752 {
1753 DeviceClass *dc = DEVICE_CLASS(klass);
1754
1755 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1756 dc->realize = pnv_chip_realize;
1757 device_class_set_props(dc, pnv_chip_properties);
1758 dc->desc = "PowerNV Chip";
1759 }
1760
1761 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1762 {
1763 int i, j;
1764
1765 for (i = 0; i < chip->nr_cores; i++) {
1766 PnvCore *pc = chip->cores[i];
1767 CPUCore *cc = CPU_CORE(pc);
1768
1769 for (j = 0; j < cc->nr_threads; j++) {
1770 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1771 return pc->threads[j];
1772 }
1773 }
1774 }
1775 return NULL;
1776 }
1777
1778 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1779 {
1780 PnvMachineState *pnv = PNV_MACHINE(xi);
1781 int i, j;
1782
1783 for (i = 0; i < pnv->num_chips; i++) {
1784 PnvChip *chip = pnv->chips[i];
1785 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1786
1787 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1788 return &chip8->psi.ics;
1789 }
1790 for (j = 0; j < chip->num_phbs; j++) {
1791 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) {
1792 return &chip8->phbs[j].lsis;
1793 }
1794 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) {
1795 return ICS(&chip8->phbs[j].msis);
1796 }
1797 }
1798 }
1799 return NULL;
1800 }
1801
1802 static void pnv_ics_resend(XICSFabric *xi)
1803 {
1804 PnvMachineState *pnv = PNV_MACHINE(xi);
1805 int i, j;
1806
1807 for (i = 0; i < pnv->num_chips; i++) {
1808 PnvChip *chip = pnv->chips[i];
1809 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1810
1811 ics_resend(&chip8->psi.ics);
1812 for (j = 0; j < chip->num_phbs; j++) {
1813 ics_resend(&chip8->phbs[j].lsis);
1814 ics_resend(ICS(&chip8->phbs[j].msis));
1815 }
1816 }
1817 }
1818
1819 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1820 {
1821 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1822
1823 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1824 }
1825
1826 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1827 Monitor *mon)
1828 {
1829 PnvMachineState *pnv = PNV_MACHINE(obj);
1830 int i;
1831 CPUState *cs;
1832
1833 CPU_FOREACH(cs) {
1834 PowerPCCPU *cpu = POWERPC_CPU(cs);
1835
1836 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1837 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1838 mon);
1839 }
1840
1841 for (i = 0; i < pnv->num_chips; i++) {
1842 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1843 }
1844 }
1845
1846 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1847 uint8_t nvt_blk, uint32_t nvt_idx,
1848 bool cam_ignore, uint8_t priority,
1849 uint32_t logic_serv,
1850 XiveTCTXMatch *match)
1851 {
1852 PnvMachineState *pnv = PNV_MACHINE(xfb);
1853 int total_count = 0;
1854 int i;
1855
1856 for (i = 0; i < pnv->num_chips; i++) {
1857 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1858 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1859 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1860 int count;
1861
1862 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1863 priority, logic_serv, match);
1864
1865 if (count < 0) {
1866 return count;
1867 }
1868
1869 total_count += count;
1870 }
1871
1872 return total_count;
1873 }
1874
1875 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
1876 {
1877 MachineClass *mc = MACHINE_CLASS(oc);
1878 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1879 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1880 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1881
1882 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1883 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1884
1885 xic->icp_get = pnv_icp_get;
1886 xic->ics_get = pnv_ics_get;
1887 xic->ics_resend = pnv_ics_resend;
1888
1889 pmc->compat = compat;
1890 pmc->compat_size = sizeof(compat);
1891 }
1892
1893 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1894 {
1895 MachineClass *mc = MACHINE_CLASS(oc);
1896 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
1897 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1898 static const char compat[] = "qemu,powernv9\0ibm,powernv";
1899
1900 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1901 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
1902 xfc->match_nvt = pnv_match_nvt;
1903
1904 mc->alias = "powernv";
1905
1906 pmc->compat = compat;
1907 pmc->compat_size = sizeof(compat);
1908 pmc->dt_power_mgt = pnv_dt_power_mgt;
1909 }
1910
1911 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1912 {
1913 MachineClass *mc = MACHINE_CLASS(oc);
1914 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1915 static const char compat[] = "qemu,powernv10\0ibm,powernv";
1916
1917 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1918 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
1919
1920 pmc->compat = compat;
1921 pmc->compat_size = sizeof(compat);
1922 pmc->dt_power_mgt = pnv_dt_power_mgt;
1923 }
1924
1925 static bool pnv_machine_get_hb(Object *obj, Error **errp)
1926 {
1927 PnvMachineState *pnv = PNV_MACHINE(obj);
1928
1929 return !!pnv->fw_load_addr;
1930 }
1931
1932 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
1933 {
1934 PnvMachineState *pnv = PNV_MACHINE(obj);
1935
1936 if (value) {
1937 pnv->fw_load_addr = 0x8000000;
1938 }
1939 }
1940
1941 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
1942 {
1943 PowerPCCPU *cpu = POWERPC_CPU(cs);
1944 CPUPPCState *env = &cpu->env;
1945
1946 cpu_synchronize_state(cs);
1947 ppc_cpu_do_system_reset(cs);
1948 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
1949 /*
1950 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
1951 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
1952 * (PPC_BIT(43)).
1953 */
1954 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
1955 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
1956 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
1957 }
1958 } else {
1959 /*
1960 * For non-powersave system resets, SRR1[42:45] are defined to be
1961 * implementation-dependent. The POWER9 User Manual specifies that
1962 * an external (SCOM driven, which may come from a BMC nmi command or
1963 * another CPU requesting a NMI IPI) system reset exception should be
1964 * 0b0010 (PPC_BIT(44)).
1965 */
1966 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
1967 }
1968 }
1969
1970 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
1971 {
1972 CPUState *cs;
1973
1974 CPU_FOREACH(cs) {
1975 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
1976 }
1977 }
1978
1979 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1980 {
1981 MachineClass *mc = MACHINE_CLASS(oc);
1982 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1983 NMIClass *nc = NMI_CLASS(oc);
1984
1985 mc->desc = "IBM PowerNV (Non-Virtualized)";
1986 mc->init = pnv_init;
1987 mc->reset = pnv_reset;
1988 mc->max_cpus = MAX_CPUS;
1989 /* Pnv provides a AHCI device for storage */
1990 mc->block_default_type = IF_IDE;
1991 mc->no_parallel = 1;
1992 mc->default_boot_order = NULL;
1993 /*
1994 * RAM defaults to less than 2048 for 32-bit hosts, and large
1995 * enough to fit the maximum initrd size at it's load address
1996 */
1997 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
1998 mc->default_ram_id = "pnv.ram";
1999 ispc->print_info = pnv_pic_print_info;
2000 nc->nmi_monitor_handler = pnv_nmi;
2001
2002 object_class_property_add_bool(oc, "hb-mode",
2003 pnv_machine_get_hb, pnv_machine_set_hb);
2004 object_class_property_set_description(oc, "hb-mode",
2005 "Use a hostboot like boot loader");
2006 }
2007
2008 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2009 { \
2010 .name = type, \
2011 .class_init = class_initfn, \
2012 .parent = TYPE_PNV8_CHIP, \
2013 }
2014
2015 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2016 { \
2017 .name = type, \
2018 .class_init = class_initfn, \
2019 .parent = TYPE_PNV9_CHIP, \
2020 }
2021
2022 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2023 { \
2024 .name = type, \
2025 .class_init = class_initfn, \
2026 .parent = TYPE_PNV10_CHIP, \
2027 }
2028
2029 static const TypeInfo types[] = {
2030 {
2031 .name = MACHINE_TYPE_NAME("powernv10"),
2032 .parent = TYPE_PNV_MACHINE,
2033 .class_init = pnv_machine_power10_class_init,
2034 },
2035 {
2036 .name = MACHINE_TYPE_NAME("powernv9"),
2037 .parent = TYPE_PNV_MACHINE,
2038 .class_init = pnv_machine_power9_class_init,
2039 .interfaces = (InterfaceInfo[]) {
2040 { TYPE_XIVE_FABRIC },
2041 { },
2042 },
2043 },
2044 {
2045 .name = MACHINE_TYPE_NAME("powernv8"),
2046 .parent = TYPE_PNV_MACHINE,
2047 .class_init = pnv_machine_power8_class_init,
2048 .interfaces = (InterfaceInfo[]) {
2049 { TYPE_XICS_FABRIC },
2050 { },
2051 },
2052 },
2053 {
2054 .name = TYPE_PNV_MACHINE,
2055 .parent = TYPE_MACHINE,
2056 .abstract = true,
2057 .instance_size = sizeof(PnvMachineState),
2058 .class_init = pnv_machine_class_init,
2059 .class_size = sizeof(PnvMachineClass),
2060 .interfaces = (InterfaceInfo[]) {
2061 { TYPE_INTERRUPT_STATS_PROVIDER },
2062 { TYPE_NMI },
2063 { },
2064 },
2065 },
2066 {
2067 .name = TYPE_PNV_CHIP,
2068 .parent = TYPE_SYS_BUS_DEVICE,
2069 .class_init = pnv_chip_class_init,
2070 .instance_size = sizeof(PnvChip),
2071 .class_size = sizeof(PnvChipClass),
2072 .abstract = true,
2073 },
2074
2075 /*
2076 * P10 chip and variants
2077 */
2078 {
2079 .name = TYPE_PNV10_CHIP,
2080 .parent = TYPE_PNV_CHIP,
2081 .instance_init = pnv_chip_power10_instance_init,
2082 .instance_size = sizeof(Pnv10Chip),
2083 },
2084 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2085
2086 /*
2087 * P9 chip and variants
2088 */
2089 {
2090 .name = TYPE_PNV9_CHIP,
2091 .parent = TYPE_PNV_CHIP,
2092 .instance_init = pnv_chip_power9_instance_init,
2093 .instance_size = sizeof(Pnv9Chip),
2094 },
2095 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2096
2097 /*
2098 * P8 chip and variants
2099 */
2100 {
2101 .name = TYPE_PNV8_CHIP,
2102 .parent = TYPE_PNV_CHIP,
2103 .instance_init = pnv_chip_power8_instance_init,
2104 .instance_size = sizeof(Pnv8Chip),
2105 },
2106 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2107 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2108 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2109 pnv_chip_power8nvl_class_init),
2110 };
2111
2112 DEFINE_TYPES(types)
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