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[mirror_qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/units.h"
23 #include "qapi/error.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/numa.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/cpus.h"
29 #include "sysemu/device_tree.h"
30 #include "target/ppc/cpu.h"
31 #include "qemu/log.h"
32 #include "hw/ppc/fdt.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/ppc/pnv.h"
35 #include "hw/ppc/pnv_core.h"
36 #include "hw/loader.h"
37 #include "exec/address-spaces.h"
38 #include "qapi/visitor.h"
39 #include "monitor/monitor.h"
40 #include "hw/intc/intc.h"
41 #include "hw/ipmi/ipmi.h"
42 #include "target/ppc/mmu-hash64.h"
43
44 #include "hw/ppc/xics.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/ppc/pnv_xscom.h"
47 #include "hw/ppc/pnv_pnor.h"
48
49 #include "hw/isa/isa.h"
50 #include "hw/boards.h"
51 #include "hw/char/serial.h"
52 #include "hw/rtc/mc146818rtc.h"
53
54 #include <libfdt.h>
55
56 #define FDT_MAX_SIZE (1 * MiB)
57
58 #define FW_FILE_NAME "skiboot.lid"
59 #define FW_LOAD_ADDR 0x0
60 #define FW_MAX_SIZE (4 * MiB)
61
62 #define KERNEL_LOAD_ADDR 0x20000000
63 #define KERNEL_MAX_SIZE (256 * MiB)
64 #define INITRD_LOAD_ADDR 0x60000000
65 #define INITRD_MAX_SIZE (256 * MiB)
66
67 static const char *pnv_chip_core_typename(const PnvChip *o)
68 {
69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
72 const char *core_type = object_class_get_name(object_class_by_name(s));
73 g_free(s);
74 return core_type;
75 }
76
77 /*
78 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
79 * 4 * 4 sockets * 12 cores * 8 threads = 1536
80 * Let's make it 2^11
81 */
82 #define MAX_CPUS 2048
83
84 /*
85 * Memory nodes are created by hostboot, one for each range of memory
86 * that has a different "affinity". In practice, it means one range
87 * per chip.
88 */
89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
90 {
91 char *mem_name;
92 uint64_t mem_reg_property[2];
93 int off;
94
95 mem_reg_property[0] = cpu_to_be64(start);
96 mem_reg_property[1] = cpu_to_be64(size);
97
98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
99 off = fdt_add_subnode(fdt, 0, mem_name);
100 g_free(mem_name);
101
102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
104 sizeof(mem_reg_property))));
105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
106 }
107
108 static int get_cpus_node(void *fdt)
109 {
110 int cpus_offset = fdt_path_offset(fdt, "/cpus");
111
112 if (cpus_offset < 0) {
113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
114 if (cpus_offset) {
115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
117 }
118 }
119 _FDT(cpus_offset);
120 return cpus_offset;
121 }
122
123 /*
124 * The PowerNV cores (and threads) need to use real HW ids and not an
125 * incremental index like it has been done on other platforms. This HW
126 * id is stored in the CPU PIR, it is used to create cpu nodes in the
127 * device tree, used in XSCOM to address cores and in interrupt
128 * servers.
129 */
130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
131 {
132 PowerPCCPU *cpu = pc->threads[0];
133 CPUState *cs = CPU(cpu);
134 DeviceClass *dc = DEVICE_GET_CLASS(cs);
135 int smt_threads = CPU_CORE(pc)->nr_threads;
136 CPUPPCState *env = &cpu->env;
137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
138 uint32_t servers_prop[smt_threads];
139 int i;
140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
141 0xffffffff, 0xffffffff};
142 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
143 uint32_t cpufreq = 1000000000;
144 uint32_t page_sizes_prop[64];
145 size_t page_sizes_prop_size;
146 const uint8_t pa_features[] = { 24, 0,
147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
151 int offset;
152 char *nodename;
153 int cpus_offset = get_cpus_node(fdt);
154
155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
156 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
157 _FDT(offset);
158 g_free(nodename);
159
160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
161
162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
165
166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
168 env->dcache_line_size)));
169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
170 env->dcache_line_size)));
171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
172 env->icache_line_size)));
173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
174 env->icache_line_size)));
175
176 if (pcc->l1_dcache_size) {
177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
178 pcc->l1_dcache_size)));
179 } else {
180 warn_report("Unknown L1 dcache size for cpu");
181 }
182 if (pcc->l1_icache_size) {
183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
184 pcc->l1_icache_size)));
185 } else {
186 warn_report("Unknown L1 icache size for cpu");
187 }
188
189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
192 cpu->hash64_opts->slb_size)));
193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
195
196 if (env->spr_cb[SPR_PURR].oea_read) {
197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
198 }
199
200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
202 segs, sizeof(segs))));
203 }
204
205 /*
206 * Advertise VMX/VSX (vector extensions) if available
207 * 0 / no property == no vector extensions
208 * 1 == VMX / Altivec available
209 * 2 == VSX available
210 */
211 if (env->insns_flags & PPC_ALTIVEC) {
212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
213
214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
215 }
216
217 /*
218 * Advertise DFP (Decimal Floating Point) if available
219 * 0 / no property == no DFP
220 * 1 == DFP available
221 */
222 if (env->insns_flags2 & PPC2_DFP) {
223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
224 }
225
226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
227 sizeof(page_sizes_prop));
228 if (page_sizes_prop_size) {
229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
230 page_sizes_prop, page_sizes_prop_size)));
231 }
232
233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
234 pa_features, sizeof(pa_features))));
235
236 /* Build interrupt servers properties */
237 for (i = 0; i < smt_threads; i++) {
238 servers_prop[i] = cpu_to_be32(pc->pir + i);
239 }
240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
241 servers_prop, sizeof(servers_prop))));
242 }
243
244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
245 uint32_t nr_threads)
246 {
247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
248 char *name;
249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
250 uint32_t irange[2], i, rsize;
251 uint64_t *reg;
252 int offset;
253
254 irange[0] = cpu_to_be32(pir);
255 irange[1] = cpu_to_be32(nr_threads);
256
257 rsize = sizeof(uint64_t) * 2 * nr_threads;
258 reg = g_malloc(rsize);
259 for (i = 0; i < nr_threads; i++) {
260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
261 reg[i * 2 + 1] = cpu_to_be64(0x1000);
262 }
263
264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
265 offset = fdt_add_subnode(fdt, 0, name);
266 _FDT(offset);
267 g_free(name);
268
269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
271 _FDT((fdt_setprop_string(fdt, offset, "device_type",
272 "PowerPC-External-Interrupt-Presentation")));
273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
275 irange, sizeof(irange))));
276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
278 g_free(reg);
279 }
280
281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
282 {
283 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
284 int i;
285
286 pnv_dt_xscom(chip, fdt, 0,
287 cpu_to_be64(PNV_XSCOM_BASE(chip)),
288 cpu_to_be64(PNV_XSCOM_SIZE),
289 compat, sizeof(compat));
290
291 for (i = 0; i < chip->nr_cores; i++) {
292 PnvCore *pnv_core = chip->cores[i];
293
294 pnv_dt_core(chip, pnv_core, fdt);
295
296 /* Interrupt Control Presenters (ICP). One per core. */
297 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
298 }
299
300 if (chip->ram_size) {
301 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
302 }
303 }
304
305 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
306 {
307 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
308 int i;
309
310 pnv_dt_xscom(chip, fdt, 0,
311 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
312 cpu_to_be64(PNV9_XSCOM_SIZE),
313 compat, sizeof(compat));
314
315 for (i = 0; i < chip->nr_cores; i++) {
316 PnvCore *pnv_core = chip->cores[i];
317
318 pnv_dt_core(chip, pnv_core, fdt);
319 }
320
321 if (chip->ram_size) {
322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
323 }
324
325 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
326 }
327
328 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
329 {
330 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
331 int i;
332
333 pnv_dt_xscom(chip, fdt, 0,
334 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
335 cpu_to_be64(PNV10_XSCOM_SIZE),
336 compat, sizeof(compat));
337
338 for (i = 0; i < chip->nr_cores; i++) {
339 PnvCore *pnv_core = chip->cores[i];
340
341 pnv_dt_core(chip, pnv_core, fdt);
342 }
343
344 if (chip->ram_size) {
345 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
346 }
347
348 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
349 }
350
351 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
352 {
353 uint32_t io_base = d->ioport_id;
354 uint32_t io_regs[] = {
355 cpu_to_be32(1),
356 cpu_to_be32(io_base),
357 cpu_to_be32(2)
358 };
359 char *name;
360 int node;
361
362 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
363 node = fdt_add_subnode(fdt, lpc_off, name);
364 _FDT(node);
365 g_free(name);
366
367 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
368 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
369 }
370
371 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
372 {
373 const char compatible[] = "ns16550\0pnpPNP,501";
374 uint32_t io_base = d->ioport_id;
375 uint32_t io_regs[] = {
376 cpu_to_be32(1),
377 cpu_to_be32(io_base),
378 cpu_to_be32(8)
379 };
380 char *name;
381 int node;
382
383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
384 node = fdt_add_subnode(fdt, lpc_off, name);
385 _FDT(node);
386 g_free(name);
387
388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
389 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
390 sizeof(compatible))));
391
392 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
393 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
394 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
395 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
396 fdt_get_phandle(fdt, lpc_off))));
397
398 /* This is needed by Linux */
399 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
400 }
401
402 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
403 {
404 const char compatible[] = "bt\0ipmi-bt";
405 uint32_t io_base;
406 uint32_t io_regs[] = {
407 cpu_to_be32(1),
408 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
409 cpu_to_be32(3)
410 };
411 uint32_t irq;
412 char *name;
413 int node;
414
415 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
416 io_regs[1] = cpu_to_be32(io_base);
417
418 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
419
420 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
421 node = fdt_add_subnode(fdt, lpc_off, name);
422 _FDT(node);
423 g_free(name);
424
425 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
426 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
427 sizeof(compatible))));
428
429 /* Mark it as reserved to avoid Linux trying to claim it */
430 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
431 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
432 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
433 fdt_get_phandle(fdt, lpc_off))));
434 }
435
436 typedef struct ForeachPopulateArgs {
437 void *fdt;
438 int offset;
439 } ForeachPopulateArgs;
440
441 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
442 {
443 ForeachPopulateArgs *args = opaque;
444 ISADevice *d = ISA_DEVICE(dev);
445
446 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
447 pnv_dt_rtc(d, args->fdt, args->offset);
448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
449 pnv_dt_serial(d, args->fdt, args->offset);
450 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
451 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
452 } else {
453 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
454 d->ioport_id);
455 }
456
457 return 0;
458 }
459
460 /*
461 * The default LPC bus of a multichip system is on chip 0. It's
462 * recognized by the firmware (skiboot) using a "primary" property.
463 */
464 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
465 {
466 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
467 ForeachPopulateArgs args = {
468 .fdt = fdt,
469 .offset = isa_offset,
470 };
471 uint32_t phandle;
472
473 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
474
475 phandle = qemu_fdt_alloc_phandle(fdt);
476 assert(phandle > 0);
477 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
478
479 /*
480 * ISA devices are not necessarily parented to the ISA bus so we
481 * can not use object_child_foreach()
482 */
483 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
484 &args);
485 }
486
487 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
488 {
489 int off;
490
491 off = fdt_add_subnode(fdt, 0, "ibm,opal");
492 off = fdt_add_subnode(fdt, off, "power-mgt");
493
494 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
495 }
496
497 static void *pnv_dt_create(MachineState *machine)
498 {
499 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
500 PnvMachineState *pnv = PNV_MACHINE(machine);
501 void *fdt;
502 char *buf;
503 int off;
504 int i;
505
506 fdt = g_malloc0(FDT_MAX_SIZE);
507 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
508
509 /* /qemu node */
510 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
511
512 /* Root node */
513 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
514 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
515 _FDT((fdt_setprop_string(fdt, 0, "model",
516 "IBM PowerNV (emulated by qemu)")));
517 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
518
519 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
520 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
521 if (qemu_uuid_set) {
522 _FDT((fdt_property_string(fdt, "system-id", buf)));
523 }
524 g_free(buf);
525
526 off = fdt_add_subnode(fdt, 0, "chosen");
527 if (machine->kernel_cmdline) {
528 _FDT((fdt_setprop_string(fdt, off, "bootargs",
529 machine->kernel_cmdline)));
530 }
531
532 if (pnv->initrd_size) {
533 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
534 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
535
536 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
537 &start_prop, sizeof(start_prop))));
538 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
539 &end_prop, sizeof(end_prop))));
540 }
541
542 /* Populate device tree for each chip */
543 for (i = 0; i < pnv->num_chips; i++) {
544 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
545 }
546
547 /* Populate ISA devices on chip 0 */
548 pnv_dt_isa(pnv, fdt);
549
550 if (pnv->bmc) {
551 pnv_dt_bmc_sensors(pnv->bmc, fdt);
552 }
553
554 /* Create an extra node for power management on machines that support it */
555 if (pmc->dt_power_mgt) {
556 pmc->dt_power_mgt(pnv, fdt);
557 }
558
559 return fdt;
560 }
561
562 static void pnv_powerdown_notify(Notifier *n, void *opaque)
563 {
564 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
565
566 if (pnv->bmc) {
567 pnv_bmc_powerdown(pnv->bmc);
568 }
569 }
570
571 static void pnv_reset(MachineState *machine)
572 {
573 void *fdt;
574
575 qemu_devices_reset();
576
577 fdt = pnv_dt_create(machine);
578
579 /* Pack resulting tree */
580 _FDT((fdt_pack(fdt)));
581
582 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
583 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
584 }
585
586 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
587 {
588 Pnv8Chip *chip8 = PNV8_CHIP(chip);
589 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
590 }
591
592 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
593 {
594 Pnv8Chip *chip8 = PNV8_CHIP(chip);
595 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
596 }
597
598 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
599 {
600 Pnv9Chip *chip9 = PNV9_CHIP(chip);
601 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
602 }
603
604 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
605 {
606 Pnv10Chip *chip10 = PNV10_CHIP(chip);
607 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
608 }
609
610 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
611 {
612 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
613 }
614
615 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
616 {
617 Pnv8Chip *chip8 = PNV8_CHIP(chip);
618
619 ics_pic_print_info(&chip8->psi.ics, mon);
620 }
621
622 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
623 {
624 Pnv9Chip *chip9 = PNV9_CHIP(chip);
625
626 pnv_xive_pic_print_info(&chip9->xive, mon);
627 pnv_psi_pic_print_info(&chip9->psi, mon);
628 }
629
630 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
631 uint32_t core_id)
632 {
633 return PNV_XSCOM_EX_BASE(core_id);
634 }
635
636 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
637 uint32_t core_id)
638 {
639 return PNV9_XSCOM_EC_BASE(core_id);
640 }
641
642 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
643 uint32_t core_id)
644 {
645 return PNV10_XSCOM_EC_BASE(core_id);
646 }
647
648 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
649 {
650 PowerPCCPUClass *ppc_default =
651 POWERPC_CPU_CLASS(object_class_by_name(default_type));
652 PowerPCCPUClass *ppc =
653 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
654
655 return ppc_default->pvr_match(ppc_default, ppc->pvr);
656 }
657
658 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
659 {
660 Object *obj;
661
662 obj = OBJECT(isa_create(bus, "isa-ipmi-bt"));
663 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal);
664 object_property_set_int(obj, irq, "irq", &error_fatal);
665 object_property_set_bool(obj, true, "realized", &error_fatal);
666 }
667
668 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
669 {
670 Pnv10Chip *chip10 = PNV10_CHIP(chip);
671
672 pnv_psi_pic_print_info(&chip10->psi, mon);
673 }
674
675 static void pnv_init(MachineState *machine)
676 {
677 PnvMachineState *pnv = PNV_MACHINE(machine);
678 MachineClass *mc = MACHINE_GET_CLASS(machine);
679 MemoryRegion *ram;
680 char *fw_filename;
681 long fw_size;
682 int i;
683 char *chip_typename;
684 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
685 DeviceState *dev;
686
687 /* allocate RAM */
688 if (machine->ram_size < (1 * GiB)) {
689 warn_report("skiboot may not work with < 1GB of RAM");
690 }
691
692 ram = g_new(MemoryRegion, 1);
693 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
694 machine->ram_size);
695 memory_region_add_subregion(get_system_memory(), 0, ram);
696
697 /*
698 * Create our simple PNOR device
699 */
700 dev = qdev_create(NULL, TYPE_PNV_PNOR);
701 if (pnor) {
702 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
703 &error_abort);
704 }
705 qdev_init_nofail(dev);
706 pnv->pnor = PNV_PNOR(dev);
707
708 /* load skiboot firmware */
709 if (bios_name == NULL) {
710 bios_name = FW_FILE_NAME;
711 }
712
713 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
714 if (!fw_filename) {
715 error_report("Could not find OPAL firmware '%s'", bios_name);
716 exit(1);
717 }
718
719 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
720 if (fw_size < 0) {
721 error_report("Could not load OPAL firmware '%s'", fw_filename);
722 exit(1);
723 }
724 g_free(fw_filename);
725
726 /* load kernel */
727 if (machine->kernel_filename) {
728 long kernel_size;
729
730 kernel_size = load_image_targphys(machine->kernel_filename,
731 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
732 if (kernel_size < 0) {
733 error_report("Could not load kernel '%s'",
734 machine->kernel_filename);
735 exit(1);
736 }
737 }
738
739 /* load initrd */
740 if (machine->initrd_filename) {
741 pnv->initrd_base = INITRD_LOAD_ADDR;
742 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
743 pnv->initrd_base, INITRD_MAX_SIZE);
744 if (pnv->initrd_size < 0) {
745 error_report("Could not load initial ram disk '%s'",
746 machine->initrd_filename);
747 exit(1);
748 }
749 }
750
751 /*
752 * Check compatibility of the specified CPU with the machine
753 * default.
754 */
755 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
756 error_report("invalid CPU model '%s' for %s machine",
757 machine->cpu_type, mc->name);
758 exit(1);
759 }
760
761 /* Create the processor chips */
762 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
763 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
764 i, machine->cpu_type);
765 if (!object_class_by_name(chip_typename)) {
766 error_report("invalid chip model '%.*s' for %s machine",
767 i, machine->cpu_type, mc->name);
768 exit(1);
769 }
770
771 pnv->num_chips =
772 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
773 /*
774 * TODO: should we decide on how many chips we can create based
775 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
776 */
777 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
778 error_report("invalid number of chips: '%d'", pnv->num_chips);
779 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
780 exit(1);
781 }
782
783 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
784 for (i = 0; i < pnv->num_chips; i++) {
785 char chip_name[32];
786 Object *chip = object_new(chip_typename);
787
788 pnv->chips[i] = PNV_CHIP(chip);
789
790 /*
791 * TODO: put all the memory in one node on chip 0 until we find a
792 * way to specify different ranges for each chip
793 */
794 if (i == 0) {
795 object_property_set_int(chip, machine->ram_size, "ram-size",
796 &error_fatal);
797 }
798
799 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
800 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
801 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
802 &error_fatal);
803 object_property_set_int(chip, machine->smp.cores,
804 "nr-cores", &error_fatal);
805 object_property_set_int(chip, machine->smp.threads,
806 "nr-threads", &error_fatal);
807 /*
808 * The POWER8 machine use the XICS interrupt interface.
809 * Propagate the XICS fabric to the chip and its controllers.
810 */
811 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
812 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort);
813 }
814 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
815 object_property_set_link(chip, OBJECT(pnv), "xive-fabric",
816 &error_abort);
817 }
818 object_property_set_bool(chip, true, "realized", &error_fatal);
819 }
820 g_free(chip_typename);
821
822 /* Create the machine BMC simulator */
823 pnv->bmc = pnv_bmc_create(pnv->pnor);
824
825 /* Instantiate ISA bus on chip 0 */
826 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
827
828 /* Create serial port */
829 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
830
831 /* Create an RTC ISA device too */
832 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
833
834 /* Create the IPMI BT device for communication with the BMC */
835 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
836
837 /*
838 * OpenPOWER systems use a IPMI SEL Event message to notify the
839 * host to powerdown
840 */
841 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
842 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
843 }
844
845 /*
846 * 0:21 Reserved - Read as zeros
847 * 22:24 Chip ID
848 * 25:28 Core number
849 * 29:31 Thread ID
850 */
851 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
852 {
853 return (chip->chip_id << 7) | (core_id << 3);
854 }
855
856 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
857 Error **errp)
858 {
859 Pnv8Chip *chip8 = PNV8_CHIP(chip);
860 Error *local_err = NULL;
861 Object *obj;
862 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
863
864 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
865 if (local_err) {
866 error_propagate(errp, local_err);
867 return;
868 }
869
870 pnv_cpu->intc = obj;
871 }
872
873
874 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
875 {
876 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
877
878 icp_reset(ICP(pnv_cpu->intc));
879 }
880
881 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
882 {
883 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
884
885 icp_destroy(ICP(pnv_cpu->intc));
886 pnv_cpu->intc = NULL;
887 }
888
889 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
890 Monitor *mon)
891 {
892 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
893 }
894
895 /*
896 * 0:48 Reserved - Read as zeroes
897 * 49:52 Node ID
898 * 53:55 Chip ID
899 * 56 Reserved - Read as zero
900 * 57:61 Core number
901 * 62:63 Thread ID
902 *
903 * We only care about the lower bits. uint32_t is fine for the moment.
904 */
905 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
906 {
907 return (chip->chip_id << 8) | (core_id << 2);
908 }
909
910 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
911 {
912 return (chip->chip_id << 8) | (core_id << 2);
913 }
914
915 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
916 Error **errp)
917 {
918 Pnv9Chip *chip9 = PNV9_CHIP(chip);
919 Error *local_err = NULL;
920 Object *obj;
921 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
922
923 /*
924 * The core creates its interrupt presenter but the XIVE interrupt
925 * controller object is initialized afterwards. Hopefully, it's
926 * only used at runtime.
927 */
928 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
929 &local_err);
930 if (local_err) {
931 error_propagate(errp, local_err);
932 return;
933 }
934
935 pnv_cpu->intc = obj;
936 }
937
938 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
939 {
940 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
941
942 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
943 }
944
945 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
946 {
947 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
948
949 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
950 pnv_cpu->intc = NULL;
951 }
952
953 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
954 Monitor *mon)
955 {
956 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
957 }
958
959 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
960 Error **errp)
961 {
962 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
963
964 /* Will be defined when the interrupt controller is */
965 pnv_cpu->intc = NULL;
966 }
967
968 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
969 {
970 ;
971 }
972
973 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
974 {
975 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
976
977 pnv_cpu->intc = NULL;
978 }
979
980 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
981 Monitor *mon)
982 {
983 }
984
985 /*
986 * Allowed core identifiers on a POWER8 Processor Chip :
987 *
988 * <EX0 reserved>
989 * EX1 - Venice only
990 * EX2 - Venice only
991 * EX3 - Venice only
992 * EX4
993 * EX5
994 * EX6
995 * <EX7,8 reserved> <reserved>
996 * EX9 - Venice only
997 * EX10 - Venice only
998 * EX11 - Venice only
999 * EX12
1000 * EX13
1001 * EX14
1002 * <EX15 reserved>
1003 */
1004 #define POWER8E_CORE_MASK (0x7070ull)
1005 #define POWER8_CORE_MASK (0x7e7eull)
1006
1007 /*
1008 * POWER9 has 24 cores, ids starting at 0x0
1009 */
1010 #define POWER9_CORE_MASK (0xffffffffffffffull)
1011
1012
1013 #define POWER10_CORE_MASK (0xffffffffffffffull)
1014
1015 static void pnv_chip_power8_instance_init(Object *obj)
1016 {
1017 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1018
1019 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1020 (Object **)&chip8->xics,
1021 object_property_allow_set_link,
1022 OBJ_PROP_LINK_STRONG,
1023 &error_abort);
1024
1025 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
1026 TYPE_PNV8_PSI, &error_abort, NULL);
1027
1028 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
1029 TYPE_PNV8_LPC, &error_abort, NULL);
1030
1031 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
1032 TYPE_PNV8_OCC, &error_abort, NULL);
1033
1034 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
1035 TYPE_PNV8_HOMER, &error_abort, NULL);
1036 }
1037
1038 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1039 {
1040 PnvChip *chip = PNV_CHIP(chip8);
1041 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1042 int i, j;
1043 char *name;
1044
1045 name = g_strdup_printf("icp-%x", chip->chip_id);
1046 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1047 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1048 g_free(name);
1049
1050 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1051
1052 /* Map the ICP registers for each thread */
1053 for (i = 0; i < chip->nr_cores; i++) {
1054 PnvCore *pnv_core = chip->cores[i];
1055 int core_hwid = CPU_CORE(pnv_core)->core_id;
1056
1057 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1058 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1059 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1060
1061 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1062 &icp->mmio);
1063 }
1064 }
1065 }
1066
1067 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1068 {
1069 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1070 PnvChip *chip = PNV_CHIP(dev);
1071 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1072 Pnv8Psi *psi8 = &chip8->psi;
1073 Error *local_err = NULL;
1074
1075 assert(chip8->xics);
1076
1077 /* XSCOM bridge is first */
1078 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1079 if (local_err) {
1080 error_propagate(errp, local_err);
1081 return;
1082 }
1083 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1084
1085 pcc->parent_realize(dev, &local_err);
1086 if (local_err) {
1087 error_propagate(errp, local_err);
1088 return;
1089 }
1090
1091 /* Processor Service Interface (PSI) Host Bridge */
1092 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
1093 "bar", &error_fatal);
1094 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics),
1095 ICS_PROP_XICS, &error_abort);
1096 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
1097 if (local_err) {
1098 error_propagate(errp, local_err);
1099 return;
1100 }
1101 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1102 &PNV_PSI(psi8)->xscom_regs);
1103
1104 /* Create LPC controller */
1105 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
1106 &error_abort);
1107 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
1108 &error_fatal);
1109 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1110
1111 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1112 (uint64_t) PNV_XSCOM_BASE(chip),
1113 PNV_XSCOM_LPC_BASE);
1114
1115 /*
1116 * Interrupt Management Area. This is the memory region holding
1117 * all the Interrupt Control Presenter (ICP) registers
1118 */
1119 pnv_chip_icp_realize(chip8, &local_err);
1120 if (local_err) {
1121 error_propagate(errp, local_err);
1122 return;
1123 }
1124
1125 /* Create the simplified OCC model */
1126 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
1127 &error_abort);
1128 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
1129 if (local_err) {
1130 error_propagate(errp, local_err);
1131 return;
1132 }
1133 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1134
1135 /* OCC SRAM model */
1136 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1137 &chip8->occ.sram_regs);
1138
1139 /* HOMER */
1140 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
1141 &error_abort);
1142 object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
1143 &local_err);
1144 if (local_err) {
1145 error_propagate(errp, local_err);
1146 return;
1147 }
1148 /* Homer Xscom region */
1149 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1150
1151 /* Homer mmio region */
1152 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1153 &chip8->homer.regs);
1154 }
1155
1156 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1157 {
1158 addr &= (PNV_XSCOM_SIZE - 1);
1159 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1160 }
1161
1162 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1163 {
1164 DeviceClass *dc = DEVICE_CLASS(klass);
1165 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1166
1167 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1168 k->cores_mask = POWER8E_CORE_MASK;
1169 k->core_pir = pnv_chip_core_pir_p8;
1170 k->intc_create = pnv_chip_power8_intc_create;
1171 k->intc_reset = pnv_chip_power8_intc_reset;
1172 k->intc_destroy = pnv_chip_power8_intc_destroy;
1173 k->intc_print_info = pnv_chip_power8_intc_print_info;
1174 k->isa_create = pnv_chip_power8_isa_create;
1175 k->dt_populate = pnv_chip_power8_dt_populate;
1176 k->pic_print_info = pnv_chip_power8_pic_print_info;
1177 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1178 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1179 dc->desc = "PowerNV Chip POWER8E";
1180
1181 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1182 &k->parent_realize);
1183 }
1184
1185 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1186 {
1187 DeviceClass *dc = DEVICE_CLASS(klass);
1188 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1189
1190 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1191 k->cores_mask = POWER8_CORE_MASK;
1192 k->core_pir = pnv_chip_core_pir_p8;
1193 k->intc_create = pnv_chip_power8_intc_create;
1194 k->intc_reset = pnv_chip_power8_intc_reset;
1195 k->intc_destroy = pnv_chip_power8_intc_destroy;
1196 k->intc_print_info = pnv_chip_power8_intc_print_info;
1197 k->isa_create = pnv_chip_power8_isa_create;
1198 k->dt_populate = pnv_chip_power8_dt_populate;
1199 k->pic_print_info = pnv_chip_power8_pic_print_info;
1200 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1201 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1202 dc->desc = "PowerNV Chip POWER8";
1203
1204 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1205 &k->parent_realize);
1206 }
1207
1208 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1209 {
1210 DeviceClass *dc = DEVICE_CLASS(klass);
1211 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1212
1213 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1214 k->cores_mask = POWER8_CORE_MASK;
1215 k->core_pir = pnv_chip_core_pir_p8;
1216 k->intc_create = pnv_chip_power8_intc_create;
1217 k->intc_reset = pnv_chip_power8_intc_reset;
1218 k->intc_destroy = pnv_chip_power8_intc_destroy;
1219 k->intc_print_info = pnv_chip_power8_intc_print_info;
1220 k->isa_create = pnv_chip_power8nvl_isa_create;
1221 k->dt_populate = pnv_chip_power8_dt_populate;
1222 k->pic_print_info = pnv_chip_power8_pic_print_info;
1223 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1224 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1225 dc->desc = "PowerNV Chip POWER8NVL";
1226
1227 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1228 &k->parent_realize);
1229 }
1230
1231 static void pnv_chip_power9_instance_init(Object *obj)
1232 {
1233 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1234
1235 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
1236 TYPE_PNV_XIVE, &error_abort, NULL);
1237 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1238 "xive-fabric", &error_abort);
1239
1240 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
1241 TYPE_PNV9_PSI, &error_abort, NULL);
1242
1243 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
1244 TYPE_PNV9_LPC, &error_abort, NULL);
1245
1246 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
1247 TYPE_PNV9_OCC, &error_abort, NULL);
1248
1249 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
1250 TYPE_PNV9_HOMER, &error_abort, NULL);
1251 }
1252
1253 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1254 {
1255 PnvChip *chip = PNV_CHIP(chip9);
1256 int i;
1257
1258 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1259 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1260
1261 for (i = 0; i < chip9->nr_quads; i++) {
1262 char eq_name[32];
1263 PnvQuad *eq = &chip9->quads[i];
1264 PnvCore *pnv_core = chip->cores[i * 4];
1265 int core_id = CPU_CORE(pnv_core)->core_id;
1266
1267 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1268 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1269 TYPE_PNV_QUAD, &error_fatal, NULL);
1270
1271 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1272 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
1273
1274 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1275 &eq->xscom_regs);
1276 }
1277 }
1278
1279 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1280 {
1281 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1282 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1283 PnvChip *chip = PNV_CHIP(dev);
1284 Pnv9Psi *psi9 = &chip9->psi;
1285 Error *local_err = NULL;
1286
1287 /* XSCOM bridge is first */
1288 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1289 if (local_err) {
1290 error_propagate(errp, local_err);
1291 return;
1292 }
1293 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1294
1295 pcc->parent_realize(dev, &local_err);
1296 if (local_err) {
1297 error_propagate(errp, local_err);
1298 return;
1299 }
1300
1301 pnv_chip_quad_realize(chip9, &local_err);
1302 if (local_err) {
1303 error_propagate(errp, local_err);
1304 return;
1305 }
1306
1307 /* XIVE interrupt controller (POWER9) */
1308 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1309 "ic-bar", &error_fatal);
1310 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1311 "vc-bar", &error_fatal);
1312 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1313 "pc-bar", &error_fatal);
1314 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1315 "tm-bar", &error_fatal);
1316 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
1317 &error_abort);
1318 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1319 &local_err);
1320 if (local_err) {
1321 error_propagate(errp, local_err);
1322 return;
1323 }
1324 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1325 &chip9->xive.xscom_regs);
1326
1327 /* Processor Service Interface (PSI) Host Bridge */
1328 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1329 "bar", &error_fatal);
1330 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1331 if (local_err) {
1332 error_propagate(errp, local_err);
1333 return;
1334 }
1335 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1336 &PNV_PSI(psi9)->xscom_regs);
1337
1338 /* LPC */
1339 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
1340 &error_abort);
1341 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1342 if (local_err) {
1343 error_propagate(errp, local_err);
1344 return;
1345 }
1346 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1347 &chip9->lpc.xscom_regs);
1348
1349 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1350 (uint64_t) PNV9_LPCM_BASE(chip));
1351
1352 /* Create the simplified OCC model */
1353 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
1354 &error_abort);
1355 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1356 if (local_err) {
1357 error_propagate(errp, local_err);
1358 return;
1359 }
1360 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1361
1362 /* OCC SRAM model */
1363 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1364 &chip9->occ.sram_regs);
1365
1366 /* HOMER */
1367 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
1368 &error_abort);
1369 object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
1370 &local_err);
1371 if (local_err) {
1372 error_propagate(errp, local_err);
1373 return;
1374 }
1375 /* Homer Xscom region */
1376 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1377
1378 /* Homer mmio region */
1379 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1380 &chip9->homer.regs);
1381 }
1382
1383 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1384 {
1385 addr &= (PNV9_XSCOM_SIZE - 1);
1386 return addr >> 3;
1387 }
1388
1389 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1390 {
1391 DeviceClass *dc = DEVICE_CLASS(klass);
1392 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1393
1394 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1395 k->cores_mask = POWER9_CORE_MASK;
1396 k->core_pir = pnv_chip_core_pir_p9;
1397 k->intc_create = pnv_chip_power9_intc_create;
1398 k->intc_reset = pnv_chip_power9_intc_reset;
1399 k->intc_destroy = pnv_chip_power9_intc_destroy;
1400 k->intc_print_info = pnv_chip_power9_intc_print_info;
1401 k->isa_create = pnv_chip_power9_isa_create;
1402 k->dt_populate = pnv_chip_power9_dt_populate;
1403 k->pic_print_info = pnv_chip_power9_pic_print_info;
1404 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1405 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1406 dc->desc = "PowerNV Chip POWER9";
1407
1408 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1409 &k->parent_realize);
1410 }
1411
1412 static void pnv_chip_power10_instance_init(Object *obj)
1413 {
1414 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1415
1416 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
1417 TYPE_PNV10_PSI, &error_abort, NULL);
1418 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
1419 TYPE_PNV10_LPC, &error_abort, NULL);
1420 }
1421
1422 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1423 {
1424 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1425 PnvChip *chip = PNV_CHIP(dev);
1426 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1427 Error *local_err = NULL;
1428
1429 /* XSCOM bridge is first */
1430 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1431 if (local_err) {
1432 error_propagate(errp, local_err);
1433 return;
1434 }
1435 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1436
1437 pcc->parent_realize(dev, &local_err);
1438 if (local_err) {
1439 error_propagate(errp, local_err);
1440 return;
1441 }
1442
1443 /* Processor Service Interface (PSI) Host Bridge */
1444 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
1445 "bar", &error_fatal);
1446 object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
1447 &local_err);
1448 if (local_err) {
1449 error_propagate(errp, local_err);
1450 return;
1451 }
1452 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1453 &PNV_PSI(&chip10->psi)->xscom_regs);
1454
1455 /* LPC */
1456 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
1457 &error_abort);
1458 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
1459 &local_err);
1460 if (local_err) {
1461 error_propagate(errp, local_err);
1462 return;
1463 }
1464 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1465 &chip10->lpc.xscom_regs);
1466
1467 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1468 (uint64_t) PNV10_LPCM_BASE(chip));
1469 }
1470
1471 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1472 {
1473 addr &= (PNV10_XSCOM_SIZE - 1);
1474 return addr >> 3;
1475 }
1476
1477 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1478 {
1479 DeviceClass *dc = DEVICE_CLASS(klass);
1480 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1481
1482 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1483 k->cores_mask = POWER10_CORE_MASK;
1484 k->core_pir = pnv_chip_core_pir_p10;
1485 k->intc_create = pnv_chip_power10_intc_create;
1486 k->intc_reset = pnv_chip_power10_intc_reset;
1487 k->intc_destroy = pnv_chip_power10_intc_destroy;
1488 k->intc_print_info = pnv_chip_power10_intc_print_info;
1489 k->isa_create = pnv_chip_power10_isa_create;
1490 k->dt_populate = pnv_chip_power10_dt_populate;
1491 k->pic_print_info = pnv_chip_power10_pic_print_info;
1492 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1493 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1494 dc->desc = "PowerNV Chip POWER10";
1495
1496 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1497 &k->parent_realize);
1498 }
1499
1500 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1501 {
1502 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1503 int cores_max;
1504
1505 /*
1506 * No custom mask for this chip, let's use the default one from *
1507 * the chip class
1508 */
1509 if (!chip->cores_mask) {
1510 chip->cores_mask = pcc->cores_mask;
1511 }
1512
1513 /* filter alien core ids ! some are reserved */
1514 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1515 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1516 chip->cores_mask);
1517 return;
1518 }
1519 chip->cores_mask &= pcc->cores_mask;
1520
1521 /* now that we have a sane layout, let check the number of cores */
1522 cores_max = ctpop64(chip->cores_mask);
1523 if (chip->nr_cores > cores_max) {
1524 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1525 cores_max);
1526 return;
1527 }
1528 }
1529
1530 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1531 {
1532 Error *error = NULL;
1533 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1534 const char *typename = pnv_chip_core_typename(chip);
1535 int i, core_hwid;
1536
1537 if (!object_class_by_name(typename)) {
1538 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1539 return;
1540 }
1541
1542 /* Cores */
1543 pnv_chip_core_sanitize(chip, &error);
1544 if (error) {
1545 error_propagate(errp, error);
1546 return;
1547 }
1548
1549 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1550
1551 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1552 && (i < chip->nr_cores); core_hwid++) {
1553 char core_name[32];
1554 PnvCore *pnv_core;
1555 uint64_t xscom_core_base;
1556
1557 if (!(chip->cores_mask & (1ull << core_hwid))) {
1558 continue;
1559 }
1560
1561 pnv_core = PNV_CORE(object_new(typename));
1562
1563 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1564 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
1565 &error_abort);
1566 chip->cores[i] = pnv_core;
1567 object_property_set_int(OBJECT(pnv_core), chip->nr_threads,
1568 "nr-threads", &error_fatal);
1569 object_property_set_int(OBJECT(pnv_core), core_hwid,
1570 CPU_CORE_PROP_CORE_ID, &error_fatal);
1571 object_property_set_int(OBJECT(pnv_core),
1572 pcc->core_pir(chip, core_hwid),
1573 "pir", &error_fatal);
1574 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
1575 &error_abort);
1576 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1577 &error_fatal);
1578
1579 /* Each core has an XSCOM MMIO region */
1580 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1581
1582 pnv_xscom_add_subregion(chip, xscom_core_base,
1583 &pnv_core->xscom_regs);
1584 i++;
1585 }
1586 }
1587
1588 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1589 {
1590 PnvChip *chip = PNV_CHIP(dev);
1591 Error *error = NULL;
1592
1593 /* Cores */
1594 pnv_chip_core_realize(chip, &error);
1595 if (error) {
1596 error_propagate(errp, error);
1597 return;
1598 }
1599 }
1600
1601 static Property pnv_chip_properties[] = {
1602 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1603 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1604 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1605 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1606 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1607 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1608 DEFINE_PROP_END_OF_LIST(),
1609 };
1610
1611 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1612 {
1613 DeviceClass *dc = DEVICE_CLASS(klass);
1614
1615 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1616 dc->realize = pnv_chip_realize;
1617 dc->props = pnv_chip_properties;
1618 dc->desc = "PowerNV Chip";
1619 }
1620
1621 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1622 {
1623 int i, j;
1624
1625 for (i = 0; i < chip->nr_cores; i++) {
1626 PnvCore *pc = chip->cores[i];
1627 CPUCore *cc = CPU_CORE(pc);
1628
1629 for (j = 0; j < cc->nr_threads; j++) {
1630 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1631 return pc->threads[j];
1632 }
1633 }
1634 }
1635 return NULL;
1636 }
1637
1638 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1639 {
1640 PnvMachineState *pnv = PNV_MACHINE(xi);
1641 int i;
1642
1643 for (i = 0; i < pnv->num_chips; i++) {
1644 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1645
1646 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1647 return &chip8->psi.ics;
1648 }
1649 }
1650 return NULL;
1651 }
1652
1653 static void pnv_ics_resend(XICSFabric *xi)
1654 {
1655 PnvMachineState *pnv = PNV_MACHINE(xi);
1656 int i;
1657
1658 for (i = 0; i < pnv->num_chips; i++) {
1659 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1660 ics_resend(&chip8->psi.ics);
1661 }
1662 }
1663
1664 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1665 {
1666 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1667
1668 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1669 }
1670
1671 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1672 Monitor *mon)
1673 {
1674 PnvMachineState *pnv = PNV_MACHINE(obj);
1675 int i;
1676 CPUState *cs;
1677
1678 CPU_FOREACH(cs) {
1679 PowerPCCPU *cpu = POWERPC_CPU(cs);
1680
1681 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1682 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1683 mon);
1684 }
1685
1686 for (i = 0; i < pnv->num_chips; i++) {
1687 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1688 }
1689 }
1690
1691 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1692 uint8_t nvt_blk, uint32_t nvt_idx,
1693 bool cam_ignore, uint8_t priority,
1694 uint32_t logic_serv,
1695 XiveTCTXMatch *match)
1696 {
1697 PnvMachineState *pnv = PNV_MACHINE(xfb);
1698 int total_count = 0;
1699 int i;
1700
1701 for (i = 0; i < pnv->num_chips; i++) {
1702 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1703 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1704 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1705 int count;
1706
1707 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1708 priority, logic_serv, match);
1709
1710 if (count < 0) {
1711 return count;
1712 }
1713
1714 total_count += count;
1715 }
1716
1717 return total_count;
1718 }
1719
1720 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
1721 {
1722 MachineClass *mc = MACHINE_CLASS(oc);
1723 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1724 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1725 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1726
1727 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1728 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1729
1730 xic->icp_get = pnv_icp_get;
1731 xic->ics_get = pnv_ics_get;
1732 xic->ics_resend = pnv_ics_resend;
1733
1734 pmc->compat = compat;
1735 pmc->compat_size = sizeof(compat);
1736 }
1737
1738 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1739 {
1740 MachineClass *mc = MACHINE_CLASS(oc);
1741 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
1742 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1743 static const char compat[] = "qemu,powernv9\0ibm,powernv";
1744
1745 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1746 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
1747 xfc->match_nvt = pnv_match_nvt;
1748
1749 mc->alias = "powernv";
1750
1751 pmc->compat = compat;
1752 pmc->compat_size = sizeof(compat);
1753 pmc->dt_power_mgt = pnv_dt_power_mgt;
1754 }
1755
1756 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1757 {
1758 MachineClass *mc = MACHINE_CLASS(oc);
1759 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1760 static const char compat[] = "qemu,powernv10\0ibm,powernv";
1761
1762 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1763 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
1764
1765 pmc->compat = compat;
1766 pmc->compat_size = sizeof(compat);
1767 pmc->dt_power_mgt = pnv_dt_power_mgt;
1768 }
1769
1770 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1771 {
1772 MachineClass *mc = MACHINE_CLASS(oc);
1773 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1774
1775 mc->desc = "IBM PowerNV (Non-Virtualized)";
1776 mc->init = pnv_init;
1777 mc->reset = pnv_reset;
1778 mc->max_cpus = MAX_CPUS;
1779 /* Pnv provides a AHCI device for storage */
1780 mc->block_default_type = IF_IDE;
1781 mc->no_parallel = 1;
1782 mc->default_boot_order = NULL;
1783 /*
1784 * RAM defaults to less than 2048 for 32-bit hosts, and large
1785 * enough to fit the maximum initrd size at it's load address
1786 */
1787 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
1788 ispc->print_info = pnv_pic_print_info;
1789 }
1790
1791 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1792 { \
1793 .name = type, \
1794 .class_init = class_initfn, \
1795 .parent = TYPE_PNV8_CHIP, \
1796 }
1797
1798 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1799 { \
1800 .name = type, \
1801 .class_init = class_initfn, \
1802 .parent = TYPE_PNV9_CHIP, \
1803 }
1804
1805 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
1806 { \
1807 .name = type, \
1808 .class_init = class_initfn, \
1809 .parent = TYPE_PNV10_CHIP, \
1810 }
1811
1812 static const TypeInfo types[] = {
1813 {
1814 .name = MACHINE_TYPE_NAME("powernv10"),
1815 .parent = TYPE_PNV_MACHINE,
1816 .class_init = pnv_machine_power10_class_init,
1817 },
1818 {
1819 .name = MACHINE_TYPE_NAME("powernv9"),
1820 .parent = TYPE_PNV_MACHINE,
1821 .class_init = pnv_machine_power9_class_init,
1822 .interfaces = (InterfaceInfo[]) {
1823 { TYPE_XIVE_FABRIC },
1824 { },
1825 },
1826 },
1827 {
1828 .name = MACHINE_TYPE_NAME("powernv8"),
1829 .parent = TYPE_PNV_MACHINE,
1830 .class_init = pnv_machine_power8_class_init,
1831 .interfaces = (InterfaceInfo[]) {
1832 { TYPE_XICS_FABRIC },
1833 { },
1834 },
1835 },
1836 {
1837 .name = TYPE_PNV_MACHINE,
1838 .parent = TYPE_MACHINE,
1839 .abstract = true,
1840 .instance_size = sizeof(PnvMachineState),
1841 .class_init = pnv_machine_class_init,
1842 .class_size = sizeof(PnvMachineClass),
1843 .interfaces = (InterfaceInfo[]) {
1844 { TYPE_INTERRUPT_STATS_PROVIDER },
1845 { },
1846 },
1847 },
1848 {
1849 .name = TYPE_PNV_CHIP,
1850 .parent = TYPE_SYS_BUS_DEVICE,
1851 .class_init = pnv_chip_class_init,
1852 .instance_size = sizeof(PnvChip),
1853 .class_size = sizeof(PnvChipClass),
1854 .abstract = true,
1855 },
1856
1857 /*
1858 * P10 chip and variants
1859 */
1860 {
1861 .name = TYPE_PNV10_CHIP,
1862 .parent = TYPE_PNV_CHIP,
1863 .instance_init = pnv_chip_power10_instance_init,
1864 .instance_size = sizeof(Pnv10Chip),
1865 },
1866 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
1867
1868 /*
1869 * P9 chip and variants
1870 */
1871 {
1872 .name = TYPE_PNV9_CHIP,
1873 .parent = TYPE_PNV_CHIP,
1874 .instance_init = pnv_chip_power9_instance_init,
1875 .instance_size = sizeof(Pnv9Chip),
1876 },
1877 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1878
1879 /*
1880 * P8 chip and variants
1881 */
1882 {
1883 .name = TYPE_PNV8_CHIP,
1884 .parent = TYPE_PNV_CHIP,
1885 .instance_init = pnv_chip_power8_instance_init,
1886 .instance_size = sizeof(Pnv8Chip),
1887 },
1888 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1889 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1890 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1891 pnv_chip_power8nvl_class_init),
1892 };
1893
1894 DEFINE_TYPES(types)
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