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[mirror_qemu.git] / hw / ppc / pnv_i2c.c
1 /*
2 * QEMU PowerPC PowerNV Processor I2C model
3 *
4 * Copyright (c) 2019-2023, IBM Corporation.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "qemu/module.h"
11 #include "qemu/log.h"
12 #include "sysemu/reset.h"
13
14 #include "hw/irq.h"
15 #include "hw/qdev-properties.h"
16
17 #include "hw/ppc/pnv.h"
18 #include "hw/ppc/pnv_chip.h"
19 #include "hw/ppc/pnv_i2c.h"
20 #include "hw/ppc/pnv_xscom.h"
21 #include "hw/ppc/fdt.h"
22
23 #include <libfdt.h>
24
25 /* I2C FIFO register */
26 #define I2C_FIFO_REG 0x4
27 #define I2C_FIFO PPC_BITMASK(0, 7)
28
29 /* I2C command register */
30 #define I2C_CMD_REG 0x5
31 #define I2C_CMD_WITH_START PPC_BIT(0)
32 #define I2C_CMD_WITH_ADDR PPC_BIT(1)
33 #define I2C_CMD_READ_CONT PPC_BIT(2)
34 #define I2C_CMD_WITH_STOP PPC_BIT(3)
35 #define I2C_CMD_INTR_STEERING PPC_BITMASK(6, 7) /* P9 */
36 #define I2C_CMD_INTR_STEER_HOST 1
37 #define I2C_CMD_INTR_STEER_OCC 2
38 #define I2C_CMD_DEV_ADDR PPC_BITMASK(8, 14)
39 #define I2C_CMD_READ_NOT_WRITE PPC_BIT(15)
40 #define I2C_CMD_LEN_BYTES PPC_BITMASK(16, 31)
41 #define I2C_MAX_TFR_LEN 0xfff0ull
42
43 /* I2C mode register */
44 #define I2C_MODE_REG 0x6
45 #define I2C_MODE_BIT_RATE_DIV PPC_BITMASK(0, 15)
46 #define I2C_MODE_PORT_NUM PPC_BITMASK(16, 21)
47 #define I2C_MODE_ENHANCED PPC_BIT(28)
48 #define I2C_MODE_DIAGNOSTIC PPC_BIT(29)
49 #define I2C_MODE_PACING_ALLOW PPC_BIT(30)
50 #define I2C_MODE_WRAP PPC_BIT(31)
51
52 /* I2C watermark register */
53 #define I2C_WATERMARK_REG 0x7
54 #define I2C_WATERMARK_HIGH PPC_BITMASK(16, 19)
55 #define I2C_WATERMARK_LOW PPC_BITMASK(24, 27)
56
57 /*
58 * I2C interrupt mask and condition registers
59 *
60 * NB: The function of 0x9 and 0xa changes depending on whether you're reading
61 * or writing to them. When read they return the interrupt condition bits
62 * and on writes they update the interrupt mask register.
63 *
64 * The bit definitions are the same for all the interrupt registers.
65 */
66 #define I2C_INTR_MASK_REG 0x8
67
68 #define I2C_INTR_RAW_COND_REG 0x9 /* read */
69 #define I2C_INTR_MASK_OR_REG 0x9 /* write*/
70
71 #define I2C_INTR_COND_REG 0xa /* read */
72 #define I2C_INTR_MASK_AND_REG 0xa /* write */
73
74 #define I2C_INTR_ALL PPC_BITMASK(16, 31)
75 #define I2C_INTR_INVALID_CMD PPC_BIT(16)
76 #define I2C_INTR_LBUS_PARITY_ERR PPC_BIT(17)
77 #define I2C_INTR_BKEND_OVERRUN_ERR PPC_BIT(18)
78 #define I2C_INTR_BKEND_ACCESS_ERR PPC_BIT(19)
79 #define I2C_INTR_ARBT_LOST_ERR PPC_BIT(20)
80 #define I2C_INTR_NACK_RCVD_ERR PPC_BIT(21)
81 #define I2C_INTR_DATA_REQ PPC_BIT(22)
82 #define I2C_INTR_CMD_COMP PPC_BIT(23)
83 #define I2C_INTR_STOP_ERR PPC_BIT(24)
84 #define I2C_INTR_I2C_BUSY PPC_BIT(25)
85 #define I2C_INTR_NOT_I2C_BUSY PPC_BIT(26)
86 #define I2C_INTR_SCL_EQ_1 PPC_BIT(28)
87 #define I2C_INTR_SCL_EQ_0 PPC_BIT(29)
88 #define I2C_INTR_SDA_EQ_1 PPC_BIT(30)
89 #define I2C_INTR_SDA_EQ_0 PPC_BIT(31)
90
91 /* I2C status register */
92 #define I2C_RESET_I2C_REG 0xb /* write */
93 #define I2C_RESET_ERRORS 0xc
94 #define I2C_STAT_REG 0xb /* read */
95 #define I2C_STAT_INVALID_CMD PPC_BIT(0)
96 #define I2C_STAT_LBUS_PARITY_ERR PPC_BIT(1)
97 #define I2C_STAT_BKEND_OVERRUN_ERR PPC_BIT(2)
98 #define I2C_STAT_BKEND_ACCESS_ERR PPC_BIT(3)
99 #define I2C_STAT_ARBT_LOST_ERR PPC_BIT(4)
100 #define I2C_STAT_NACK_RCVD_ERR PPC_BIT(5)
101 #define I2C_STAT_DATA_REQ PPC_BIT(6)
102 #define I2C_STAT_CMD_COMP PPC_BIT(7)
103 #define I2C_STAT_STOP_ERR PPC_BIT(8)
104 #define I2C_STAT_UPPER_THRS PPC_BITMASK(9, 15)
105 #define I2C_STAT_ANY_I2C_INTR PPC_BIT(16)
106 #define I2C_STAT_PORT_HISTORY_BUSY PPC_BIT(19)
107 #define I2C_STAT_SCL_INPUT_LEVEL PPC_BIT(20)
108 #define I2C_STAT_SDA_INPUT_LEVEL PPC_BIT(21)
109 #define I2C_STAT_PORT_BUSY PPC_BIT(22)
110 #define I2C_STAT_INTERFACE_BUSY PPC_BIT(23)
111 #define I2C_STAT_FIFO_ENTRY_COUNT PPC_BITMASK(24, 31)
112
113 #define I2C_STAT_ANY_ERR (I2C_STAT_INVALID_CMD | I2C_STAT_LBUS_PARITY_ERR | \
114 I2C_STAT_BKEND_OVERRUN_ERR | \
115 I2C_STAT_BKEND_ACCESS_ERR | I2C_STAT_ARBT_LOST_ERR | \
116 I2C_STAT_NACK_RCVD_ERR | I2C_STAT_STOP_ERR)
117
118
119 #define I2C_INTR_ACTIVE \
120 ((I2C_STAT_ANY_ERR >> 16) | I2C_INTR_CMD_COMP | I2C_INTR_DATA_REQ)
121
122 /* Pseudo-status used for timeouts */
123 #define I2C_STAT_PSEUDO_TIMEOUT PPC_BIT(63)
124
125 /* I2C extended status register */
126 #define I2C_EXTD_STAT_REG 0xc
127 #define I2C_EXTD_STAT_FIFO_SIZE PPC_BITMASK(0, 7)
128 #define I2C_EXTD_STAT_MSM_CURSTATE PPC_BITMASK(11, 15)
129 #define I2C_EXTD_STAT_SCL_IN_SYNC PPC_BIT(16)
130 #define I2C_EXTD_STAT_SDA_IN_SYNC PPC_BIT(17)
131 #define I2C_EXTD_STAT_S_SCL PPC_BIT(18)
132 #define I2C_EXTD_STAT_S_SDA PPC_BIT(19)
133 #define I2C_EXTD_STAT_M_SCL PPC_BIT(20)
134 #define I2C_EXTD_STAT_M_SDA PPC_BIT(21)
135 #define I2C_EXTD_STAT_HIGH_WATER PPC_BIT(22)
136 #define I2C_EXTD_STAT_LOW_WATER PPC_BIT(23)
137 #define I2C_EXTD_STAT_I2C_BUSY PPC_BIT(24)
138 #define I2C_EXTD_STAT_SELF_BUSY PPC_BIT(25)
139 #define I2C_EXTD_STAT_I2C_VERSION PPC_BITMASK(27, 31)
140
141 /* I2C residual front end/back end length */
142 #define I2C_RESIDUAL_LEN_REG 0xd
143 #define I2C_RESIDUAL_FRONT_END PPC_BITMASK(0, 15)
144 #define I2C_RESIDUAL_BACK_END PPC_BITMASK(16, 31)
145
146 /* Port busy register */
147 #define I2C_PORT_BUSY_REG 0xe
148 #define I2C_SET_S_SCL_REG 0xd
149 #define I2C_RESET_S_SCL_REG 0xf
150 #define I2C_SET_S_SDA_REG 0x10
151 #define I2C_RESET_S_SDA_REG 0x11
152
153 #define PNV_I2C_FIFO_SIZE 8
154 #define PNV_I2C_MAX_BUSSES 64
155
156 static I2CBus *pnv_i2c_get_bus(PnvI2C *i2c)
157 {
158 uint8_t port = GETFIELD(I2C_MODE_PORT_NUM, i2c->regs[I2C_MODE_REG]);
159
160 if (port >= i2c->num_busses) {
161 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid bus number %d/%d\n", port,
162 i2c->num_busses);
163 return NULL;
164 }
165 return i2c->busses[port];
166 }
167
168 static void pnv_i2c_update_irq(PnvI2C *i2c)
169 {
170 I2CBus *bus = pnv_i2c_get_bus(i2c);
171 bool recv = !!(i2c->regs[I2C_CMD_REG] & I2C_CMD_READ_NOT_WRITE);
172 uint16_t front_end = GETFIELD(I2C_RESIDUAL_FRONT_END,
173 i2c->regs[I2C_RESIDUAL_LEN_REG]);
174 uint16_t back_end = GETFIELD(I2C_RESIDUAL_BACK_END,
175 i2c->regs[I2C_RESIDUAL_LEN_REG]);
176 uint8_t fifo_count = GETFIELD(I2C_STAT_FIFO_ENTRY_COUNT,
177 i2c->regs[I2C_STAT_REG]);
178 uint8_t fifo_free = PNV_I2C_FIFO_SIZE - fifo_count;
179
180 if (!bus) {
181 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n");
182 return;
183 }
184
185 if (i2c_bus_busy(bus)) {
186 i2c->regs[I2C_STAT_REG] &= ~I2C_STAT_DATA_REQ;
187
188 if (recv) {
189 if (fifo_count >=
190 GETFIELD(I2C_WATERMARK_HIGH, i2c->regs[I2C_WATERMARK_REG])) {
191 i2c->regs[I2C_EXTD_STAT_REG] |= I2C_EXTD_STAT_HIGH_WATER;
192 } else {
193 i2c->regs[I2C_EXTD_STAT_REG] &= ~I2C_EXTD_STAT_HIGH_WATER;
194 }
195
196 if (((i2c->regs[I2C_EXTD_STAT_REG] & I2C_EXTD_STAT_HIGH_WATER) &&
197 fifo_count != 0) || front_end == 0) {
198 i2c->regs[I2C_STAT_REG] |= I2C_STAT_DATA_REQ;
199 }
200 } else {
201 if (fifo_count <=
202 GETFIELD(I2C_WATERMARK_LOW, i2c->regs[I2C_WATERMARK_REG])) {
203 i2c->regs[I2C_EXTD_STAT_REG] |= I2C_EXTD_STAT_LOW_WATER;
204 } else {
205 i2c->regs[I2C_EXTD_STAT_REG] &= ~I2C_EXTD_STAT_LOW_WATER;
206 }
207
208 if (back_end > 0 &&
209 (fifo_free >= back_end ||
210 (i2c->regs[I2C_EXTD_STAT_REG] & I2C_EXTD_STAT_LOW_WATER))) {
211 i2c->regs[I2C_STAT_REG] |= I2C_STAT_DATA_REQ;
212 }
213 }
214
215 if (back_end == 0 && front_end == 0) {
216 i2c->regs[I2C_STAT_REG] &= ~I2C_STAT_DATA_REQ;
217 i2c->regs[I2C_STAT_REG] |= I2C_STAT_CMD_COMP;
218
219 if (i2c->regs[I2C_CMD_REG] & I2C_CMD_WITH_STOP) {
220 i2c_end_transfer(bus);
221 i2c->regs[I2C_EXTD_STAT_REG] &=
222 ~(I2C_EXTD_STAT_I2C_BUSY | I2C_EXTD_STAT_SELF_BUSY);
223 }
224 } else {
225 i2c->regs[I2C_STAT_REG] &= ~I2C_STAT_CMD_COMP;
226 }
227 }
228
229 /*
230 * Status and interrupt registers have nearly the same layout.
231 */
232 i2c->regs[I2C_INTR_RAW_COND_REG] = i2c->regs[I2C_STAT_REG] >> 16;
233 i2c->regs[I2C_INTR_COND_REG] =
234 i2c->regs[I2C_INTR_RAW_COND_REG] & i2c->regs[I2C_INTR_MASK_REG];
235
236 qemu_set_irq(i2c->psi_irq, i2c->regs[I2C_INTR_COND_REG] != 0);
237 }
238
239 static void pnv_i2c_fifo_update_count(PnvI2C *i2c)
240 {
241 uint64_t stat = i2c->regs[I2C_STAT_REG];
242
243 i2c->regs[I2C_STAT_REG] = SETFIELD(I2C_STAT_FIFO_ENTRY_COUNT, stat,
244 fifo8_num_used(&i2c->fifo));
245 }
246
247 static void pnv_i2c_frontend_update(PnvI2C *i2c)
248 {
249 uint64_t residual_end = i2c->regs[I2C_RESIDUAL_LEN_REG];
250 uint16_t front_end = GETFIELD(I2C_RESIDUAL_FRONT_END, residual_end);
251
252 i2c->regs[I2C_RESIDUAL_LEN_REG] =
253 SETFIELD(I2C_RESIDUAL_FRONT_END, residual_end, front_end - 1);
254 }
255
256 static void pnv_i2c_fifo_flush(PnvI2C *i2c)
257 {
258 I2CBus *bus = pnv_i2c_get_bus(i2c);
259 uint8_t data;
260 int ret;
261
262 if (!bus) {
263 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n");
264 return;
265 }
266 if (!i2c_bus_busy(bus)) {
267 return;
268 }
269
270 if (i2c->regs[I2C_CMD_REG] & I2C_CMD_READ_NOT_WRITE) {
271 if (fifo8_is_full(&i2c->fifo)) {
272 return;
273 }
274
275 data = i2c_recv(bus);
276 fifo8_push(&i2c->fifo, data);
277 } else {
278 if (fifo8_is_empty(&i2c->fifo)) {
279 return;
280 }
281
282 data = fifo8_pop(&i2c->fifo);
283 ret = i2c_send(bus, data);
284 if (ret) {
285 i2c->regs[I2C_STAT_REG] |= I2C_STAT_NACK_RCVD_ERR;
286 i2c_end_transfer(bus);
287 }
288 }
289
290 pnv_i2c_fifo_update_count(i2c);
291 pnv_i2c_frontend_update(i2c);
292 }
293
294 static void pnv_i2c_handle_cmd(PnvI2C *i2c, uint64_t val)
295 {
296 I2CBus *bus = pnv_i2c_get_bus(i2c);
297 uint8_t addr = GETFIELD(I2C_CMD_DEV_ADDR, val);
298 int recv = !!(val & I2C_CMD_READ_NOT_WRITE);
299 uint32_t len_bytes = GETFIELD(I2C_CMD_LEN_BYTES, val);
300
301 if (!(val & I2C_CMD_WITH_START) && !(val & I2C_CMD_WITH_ADDR) &&
302 !(val & I2C_CMD_WITH_STOP) && !len_bytes) {
303 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
304 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid command 0x%"PRIx64"\n",
305 val);
306 return;
307 }
308
309 if (!(i2c->regs[I2C_STAT_REG] & I2C_STAT_CMD_COMP)) {
310 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
311 qemu_log_mask(LOG_GUEST_ERROR, "I2C: command in progress\n");
312 return;
313 }
314
315 if (!bus) {
316 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n");
317 return;
318 }
319
320 i2c->regs[I2C_RESIDUAL_LEN_REG] =
321 SETFIELD(I2C_RESIDUAL_FRONT_END, 0ull, len_bytes) |
322 SETFIELD(I2C_RESIDUAL_BACK_END, 0ull, len_bytes);
323
324 if (val & I2C_CMD_WITH_START) {
325 if (i2c_start_transfer(bus, addr, recv)) {
326 i2c->regs[I2C_STAT_REG] |= I2C_STAT_NACK_RCVD_ERR;
327 } else {
328 i2c->regs[I2C_EXTD_STAT_REG] |=
329 (I2C_EXTD_STAT_I2C_BUSY | I2C_EXTD_STAT_SELF_BUSY);
330 pnv_i2c_fifo_flush(i2c);
331 }
332 }
333 }
334
335 static void pnv_i2c_backend_update(PnvI2C *i2c)
336 {
337 uint64_t residual_end = i2c->regs[I2C_RESIDUAL_LEN_REG];
338 uint16_t back_end = GETFIELD(I2C_RESIDUAL_BACK_END, residual_end);
339
340 if (!back_end) {
341 i2c->regs[I2C_STAT_REG] |= I2C_STAT_BKEND_ACCESS_ERR;
342 return;
343 }
344
345 i2c->regs[I2C_RESIDUAL_LEN_REG] =
346 SETFIELD(I2C_RESIDUAL_BACK_END, residual_end, back_end - 1);
347 }
348
349 static void pnv_i2c_fifo_in(PnvI2C *i2c)
350 {
351 uint8_t data = GETFIELD(I2C_FIFO, i2c->regs[I2C_FIFO_REG]);
352 I2CBus *bus = pnv_i2c_get_bus(i2c);
353
354 if (!bus) {
355 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n");
356 return;
357 }
358
359 if (!i2c_bus_busy(bus)) {
360 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
361 qemu_log_mask(LOG_GUEST_ERROR, "I2C: no command in progress\n");
362 return;
363 }
364
365 if (i2c->regs[I2C_CMD_REG] & I2C_CMD_READ_NOT_WRITE) {
366 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
367 qemu_log_mask(LOG_GUEST_ERROR, "I2C: read command in progress\n");
368 return;
369 }
370
371 if (fifo8_is_full(&i2c->fifo)) {
372 if (!(i2c->regs[I2C_MODE_REG] & I2C_MODE_PACING_ALLOW)) {
373 i2c->regs[I2C_STAT_REG] |= I2C_STAT_BKEND_OVERRUN_ERR;
374 }
375 return;
376 }
377
378 fifo8_push(&i2c->fifo, data);
379 pnv_i2c_fifo_update_count(i2c);
380 pnv_i2c_backend_update(i2c);
381 pnv_i2c_fifo_flush(i2c);
382 }
383
384 static void pnv_i2c_fifo_out(PnvI2C *i2c)
385 {
386 uint8_t data;
387 I2CBus *bus = pnv_i2c_get_bus(i2c);
388
389 if (!bus) {
390 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n");
391 return;
392 }
393
394 if (!i2c_bus_busy(bus)) {
395 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
396 qemu_log_mask(LOG_GUEST_ERROR, "I2C: no command in progress\n");
397 return;
398 }
399
400 if (!(i2c->regs[I2C_CMD_REG] & I2C_CMD_READ_NOT_WRITE)) {
401 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
402 qemu_log_mask(LOG_GUEST_ERROR, "I2C: write command in progress\n");
403 return;
404 }
405
406 if (fifo8_is_empty(&i2c->fifo)) {
407 if (!(i2c->regs[I2C_MODE_REG] & I2C_MODE_PACING_ALLOW)) {
408 i2c->regs[I2C_STAT_REG] |= I2C_STAT_BKEND_OVERRUN_ERR;
409 }
410 return;
411 }
412
413 data = fifo8_pop(&i2c->fifo);
414
415 i2c->regs[I2C_FIFO_REG] = SETFIELD(I2C_FIFO, 0ull, data);
416 pnv_i2c_fifo_update_count(i2c);
417 pnv_i2c_backend_update(i2c);
418 }
419
420 static uint64_t pnv_i2c_xscom_read(void *opaque, hwaddr addr,
421 unsigned size)
422 {
423 PnvI2C *i2c = PNV_I2C(opaque);
424 uint32_t offset = addr >> 3;
425 uint64_t val = -1;
426 int i;
427
428 switch (offset) {
429 case I2C_STAT_REG:
430 val = i2c->regs[offset];
431 break;
432
433 case I2C_FIFO_REG:
434 pnv_i2c_fifo_out(i2c);
435 val = i2c->regs[offset];
436 break;
437
438 case I2C_PORT_BUSY_REG: /* compute busy bit for each port */
439 val = 0;
440 for (i = 0; i < i2c->num_busses; i++) {
441 val |= (uint64_t)i2c_bus_busy(i2c->busses[i]) << i;
442 }
443 break;
444
445 case I2C_CMD_REG:
446 case I2C_MODE_REG:
447 case I2C_WATERMARK_REG:
448 case I2C_INTR_MASK_REG:
449 case I2C_INTR_RAW_COND_REG:
450 case I2C_INTR_COND_REG:
451 case I2C_EXTD_STAT_REG:
452 case I2C_RESIDUAL_LEN_REG:
453 val = i2c->regs[offset];
454 break;
455 default:
456 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
457 qemu_log_mask(LOG_GUEST_ERROR, "I2C: read at register: 0x%"
458 HWADDR_PRIx "\n", addr >> 3);
459 }
460
461 pnv_i2c_update_irq(i2c);
462
463 return val;
464 }
465
466 static void pnv_i2c_reset(void *dev)
467 {
468 PnvI2C *i2c = PNV_I2C(dev);
469
470 memset(i2c->regs, 0, sizeof(i2c->regs));
471
472 i2c->regs[I2C_STAT_REG] =
473 SETFIELD(I2C_STAT_UPPER_THRS, 0ull, i2c->num_busses - 1) |
474 I2C_STAT_CMD_COMP | I2C_STAT_SCL_INPUT_LEVEL |
475 I2C_STAT_SDA_INPUT_LEVEL;
476 i2c->regs[I2C_EXTD_STAT_REG] =
477 SETFIELD(I2C_EXTD_STAT_FIFO_SIZE, 0ull, PNV_I2C_FIFO_SIZE) |
478 SETFIELD(I2C_EXTD_STAT_I2C_VERSION, 0ull, 23); /* last version */
479
480 fifo8_reset(&i2c->fifo);
481 }
482
483 static void pnv_i2c_xscom_write(void *opaque, hwaddr addr,
484 uint64_t val, unsigned size)
485 {
486 PnvI2C *i2c = PNV_I2C(opaque);
487 uint32_t offset = addr >> 3;
488
489 switch (offset) {
490 case I2C_MODE_REG:
491 {
492 i2c->regs[offset] = val;
493 I2CBus *bus = pnv_i2c_get_bus(i2c);
494 if (!bus) {
495 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n");
496 return;
497 }
498 if (i2c_bus_busy(bus)) {
499 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
500 qemu_log_mask(LOG_GUEST_ERROR, "I2C: command in progress\n");
501 }
502 }
503 break;
504
505 case I2C_CMD_REG:
506 i2c->regs[offset] = val;
507 pnv_i2c_handle_cmd(i2c, val);
508 break;
509
510 case I2C_FIFO_REG:
511 i2c->regs[offset] = val;
512 pnv_i2c_fifo_in(i2c);
513 break;
514
515 case I2C_WATERMARK_REG:
516 i2c->regs[offset] = val;
517 break;
518
519 case I2C_RESET_I2C_REG:
520 pnv_i2c_reset(i2c);
521 break;
522
523 case I2C_RESET_ERRORS:
524 i2c->regs[I2C_STAT_REG] &= ~I2C_STAT_ANY_ERR;
525 i2c->regs[I2C_RESIDUAL_LEN_REG] = 0;
526 i2c->regs[I2C_EXTD_STAT_REG] &=
527 (I2C_EXTD_STAT_FIFO_SIZE | I2C_EXTD_STAT_I2C_VERSION);
528 fifo8_reset(&i2c->fifo);
529 break;
530
531 case I2C_INTR_MASK_REG:
532 i2c->regs[offset] = val;
533 break;
534
535 case I2C_INTR_MASK_OR_REG:
536 i2c->regs[I2C_INTR_MASK_REG] |= val;
537 break;
538
539 case I2C_INTR_MASK_AND_REG:
540 i2c->regs[I2C_INTR_MASK_REG] &= val;
541 break;
542
543 case I2C_PORT_BUSY_REG:
544 case I2C_SET_S_SCL_REG:
545 case I2C_RESET_S_SCL_REG:
546 case I2C_SET_S_SDA_REG:
547 case I2C_RESET_S_SDA_REG:
548 i2c->regs[offset] = val;
549 break;
550 default:
551 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD;
552 qemu_log_mask(LOG_GUEST_ERROR, "I2C: write at register: 0x%"
553 HWADDR_PRIx " val=0x%"PRIx64"\n", addr >> 3, val);
554 }
555
556 pnv_i2c_update_irq(i2c);
557 }
558
559 static const MemoryRegionOps pnv_i2c_xscom_ops = {
560 .read = pnv_i2c_xscom_read,
561 .write = pnv_i2c_xscom_write,
562 .valid.min_access_size = 8,
563 .valid.max_access_size = 8,
564 .impl.min_access_size = 8,
565 .impl.max_access_size = 8,
566 .endianness = DEVICE_BIG_ENDIAN,
567 };
568
569 static int pnv_i2c_bus_dt_xscom(PnvI2C *i2c, void *fdt,
570 int offset, int index)
571 {
572 int i2c_bus_offset;
573 const char i2c_compat[] =
574 "ibm,opal-i2c\0ibm,power8-i2c-port\0ibm,power9-i2c-port";
575 g_autofree char *i2c_port_name = NULL;
576 g_autofree char *name = g_strdup_printf("i2c-bus@%x", index);
577
578 i2c_bus_offset = fdt_add_subnode(fdt, offset, name);
579 _FDT(i2c_bus_offset);
580
581 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "reg", index)));
582 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "#address-cells", 1)));
583 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "#size-cells", 0)));
584 _FDT(fdt_setprop(fdt, i2c_bus_offset, "compatible", i2c_compat,
585 sizeof(i2c_compat)));
586 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "bus-frequency", 400000)));
587
588 i2c_port_name = g_strdup_printf("p8_%08x_e%dp%d", i2c->chip->chip_id,
589 i2c->engine, index);
590 _FDT(fdt_setprop_string(fdt, i2c_bus_offset, "ibm,port-name",
591 i2c_port_name));
592 return 0;
593 }
594
595 #define XSCOM_BUS_FREQUENCY 466500000
596 #define I2C_CLOCK_FREQUENCY (XSCOM_BUS_FREQUENCY / 4)
597
598 static int pnv_i2c_dt_xscom(PnvXScomInterface *dev, void *fdt,
599 int offset)
600 {
601 PnvI2C *i2c = PNV_I2C(dev);
602 int i2c_offset;
603 const char i2c_compat[] = "ibm,power8-i2cm\0ibm,power9-i2cm";
604 uint32_t i2c_pcba = PNV9_XSCOM_I2CM_BASE +
605 (i2c->engine - 1) * PNV9_XSCOM_I2CM_SIZE;
606 uint32_t reg[2] = {
607 cpu_to_be32(i2c_pcba),
608 cpu_to_be32(PNV9_XSCOM_I2CM_SIZE)
609 };
610 int i;
611 g_autofree char *name = g_strdup_printf("i2cm@%x", i2c_pcba);
612
613 i2c_offset = fdt_add_subnode(fdt, offset, name);
614 _FDT(i2c_offset);
615
616 _FDT(fdt_setprop(fdt, i2c_offset, "reg", reg, sizeof(reg)));
617
618 _FDT((fdt_setprop_cell(fdt, i2c_offset, "#address-cells", 1)));
619 _FDT((fdt_setprop_cell(fdt, i2c_offset, "#size-cells", 0)));
620 _FDT(fdt_setprop(fdt, i2c_offset, "compatible", i2c_compat,
621 sizeof(i2c_compat)));
622 _FDT((fdt_setprop_cell(fdt, i2c_offset, "chip-engine#", i2c->engine)));
623 _FDT((fdt_setprop_cell(fdt, i2c_offset, "clock-frequency",
624 I2C_CLOCK_FREQUENCY)));
625
626 for (i = 0; i < i2c->num_busses; i++) {
627 pnv_i2c_bus_dt_xscom(i2c, fdt, i2c_offset, i);
628 }
629 return 0;
630 }
631
632 static void pnv_i2c_realize(DeviceState *dev, Error **errp)
633 {
634 PnvI2C *i2c = PNV_I2C(dev);
635 int i;
636
637 assert(i2c->chip);
638
639 if (i2c->num_busses > PNV_I2C_MAX_BUSSES) {
640 error_setg(errp, "Invalid number of busses: %u", i2c->num_busses);
641 return;
642 }
643
644 pnv_xscom_region_init(&i2c->xscom_regs, OBJECT(i2c), &pnv_i2c_xscom_ops,
645 i2c, "xscom-i2c", PNV9_XSCOM_I2CM_SIZE);
646
647 i2c->busses = g_new(I2CBus *, i2c->num_busses);
648 for (i = 0; i < i2c->num_busses; i++) {
649 char name[32];
650
651 snprintf(name, sizeof(name), TYPE_PNV_I2C ".%d", i);
652 i2c->busses[i] = i2c_init_bus(dev, name);
653 }
654
655 fifo8_create(&i2c->fifo, PNV_I2C_FIFO_SIZE);
656
657 qemu_register_reset(pnv_i2c_reset, dev);
658
659 qdev_init_gpio_out(DEVICE(dev), &i2c->psi_irq, 1);
660 }
661
662 static Property pnv_i2c_properties[] = {
663 DEFINE_PROP_LINK("chip", PnvI2C, chip, TYPE_PNV_CHIP, PnvChip *),
664 DEFINE_PROP_UINT32("engine", PnvI2C, engine, 1),
665 DEFINE_PROP_UINT32("num-busses", PnvI2C, num_busses, 1),
666 DEFINE_PROP_END_OF_LIST(),
667 };
668
669 static void pnv_i2c_class_init(ObjectClass *klass, void *data)
670 {
671 DeviceClass *dc = DEVICE_CLASS(klass);
672 PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass);
673
674 xscomc->dt_xscom = pnv_i2c_dt_xscom;
675
676 dc->desc = "PowerNV I2C";
677 dc->realize = pnv_i2c_realize;
678 device_class_set_props(dc, pnv_i2c_properties);
679 }
680
681 static const TypeInfo pnv_i2c_info = {
682 .name = TYPE_PNV_I2C,
683 .parent = TYPE_DEVICE,
684 .instance_size = sizeof(PnvI2C),
685 .class_init = pnv_i2c_class_init,
686 .interfaces = (InterfaceInfo[]) {
687 { TYPE_PNV_XSCOM_INTERFACE },
688 { }
689 }
690 };
691
692 static void pnv_i2c_register_types(void)
693 {
694 type_register_static(&pnv_i2c_info);
695 }
696
697 type_init(pnv_i2c_register_types);