hw/ppc/pnv_psi.c

   1 /*
   2  * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
   3  *
   4  * Copyright (c) 2015-2017, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/irq.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "sysemu/reset.h"
  26 #include "qapi/error.h"
  27 #include "monitor/monitor.h"
  28
  29 #include "exec/address-spaces.h"
  30
  31 #include "hw/ppc/fdt.h"
  32 #include "hw/ppc/pnv.h"
  33 #include "hw/ppc/pnv_xscom.h"
  34 #include "hw/qdev-properties.h"
  35 #include "hw/ppc/pnv_psi.h"
  36
  37 #include <libfdt.h>
  38
  39 #define PSIHB_XSCOM_FIR_RW      0x00
  40 #define PSIHB_XSCOM_FIR_AND     0x01
  41 #define PSIHB_XSCOM_FIR_OR      0x02
  42 #define PSIHB_XSCOM_FIRMASK_RW  0x03
  43 #define PSIHB_XSCOM_FIRMASK_AND 0x04
  44 #define PSIHB_XSCOM_FIRMASK_OR  0x05
  45 #define PSIHB_XSCOM_FIRACT0     0x06
  46 #define PSIHB_XSCOM_FIRACT1     0x07
  47
  48 /* Host Bridge Base Address Register */
  49 #define PSIHB_XSCOM_BAR         0x0a
  50 #define   PSIHB_BAR_EN                  0x0000000000000001ull
  51
  52 /* FSP Base Address Register */
  53 #define PSIHB_XSCOM_FSPBAR      0x0b
  54
  55 /* PSI Host Bridge Control/Status Register */
  56 #define PSIHB_XSCOM_CR          0x0e
  57 #define   PSIHB_CR_FSP_CMD_ENABLE       0x8000000000000000ull
  58 #define   PSIHB_CR_FSP_MMIO_ENABLE      0x4000000000000000ull
  59 #define   PSIHB_CR_FSP_IRQ_ENABLE       0x1000000000000000ull
  60 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE   0x0800000000000000ull
  61 #define   PSIHB_CR_PSI_LINK_ENABLE      0x0400000000000000ull
  62 #define   PSIHB_CR_FSP_RESET            0x0200000000000000ull
  63 #define   PSIHB_CR_PSIHB_RESET          0x0100000000000000ull
  64 #define   PSIHB_CR_PSI_IRQ              0x0000800000000000ull
  65 #define   PSIHB_CR_FSP_IRQ              0x0000400000000000ull
  66 #define   PSIHB_CR_FSP_LINK_ACTIVE      0x0000200000000000ull
  67 #define   PSIHB_CR_IRQ_CMD_EXPECT       0x0000010000000000ull
  68           /* and more ... */
  69
  70 /* PSIHB Status / Error Mask Register */
  71 #define PSIHB_XSCOM_SEMR        0x0f
  72
  73 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
  74 #define PSIHB_XSCOM_XIVR_FSP    0x10
  75 #define   PSIHB_XIVR_SERVER_SH          40
  76 #define   PSIHB_XIVR_SERVER_MSK         (0xffffull << PSIHB_XIVR_SERVER_SH)
  77 #define   PSIHB_XIVR_PRIO_SH            32
  78 #define   PSIHB_XIVR_PRIO_MSK           (0xffull << PSIHB_XIVR_PRIO_SH)
  79 #define   PSIHB_XIVR_SRC_SH             29
  80 #define   PSIHB_XIVR_SRC_MSK            (0x7ull << PSIHB_XIVR_SRC_SH)
  81 #define   PSIHB_XIVR_PENDING            0x01000000ull
  82
  83 /* PSI Host Bridge Set Control/ Status Register */
  84 #define PSIHB_XSCOM_SCR         0x12
  85
  86 /* PSI Host Bridge Clear Control/ Status Register */
  87 #define PSIHB_XSCOM_CCR         0x13
  88
  89 /* DMA Upper Address Register */
  90 #define PSIHB_XSCOM_DMA_UPADD   0x14
  91
  92 /* Interrupt Status */
  93 #define PSIHB_XSCOM_IRQ_STAT    0x15
  94 #define   PSIHB_IRQ_STAT_OCC            0x0000001000000000ull
  95 #define   PSIHB_IRQ_STAT_FSI            0x0000000800000000ull
  96 #define   PSIHB_IRQ_STAT_LPCI2C         0x0000000400000000ull
  97 #define   PSIHB_IRQ_STAT_LOCERR         0x0000000200000000ull
  98 #define   PSIHB_IRQ_STAT_EXT            0x0000000100000000ull
  99
 100 /* remaining XIVR */
 101 #define PSIHB_XSCOM_XIVR_OCC    0x16
 102 #define PSIHB_XSCOM_XIVR_FSI    0x17
 103 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18
 104 #define PSIHB_XSCOM_XIVR_LOCERR 0x19
 105 #define PSIHB_XSCOM_XIVR_EXT    0x1a
 106
 107 /* Interrupt Requester Source Compare Register */
 108 #define PSIHB_XSCOM_IRSN        0x1b
 109 #define   PSIHB_IRSN_COMP_SH            45
 110 #define   PSIHB_IRSN_COMP_MSK           (0x7ffffull << PSIHB_IRSN_COMP_SH)
 111 #define   PSIHB_IRSN_IRQ_MUX            0x0000000800000000ull
 112 #define   PSIHB_IRSN_IRQ_RESET          0x0000000400000000ull
 113 #define   PSIHB_IRSN_DOWNSTREAM_EN      0x0000000200000000ull
 114 #define   PSIHB_IRSN_UPSTREAM_EN        0x0000000100000000ull
 115 #define   PSIHB_IRSN_COMPMASK_SH        13
 116 #define   PSIHB_IRSN_COMPMASK_MSK       (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
 117
 118 #define PSIHB_BAR_MASK                  0x0003fffffff00000ull
 119 #define PSIHB_FSPBAR_MASK               0x0003ffff00000000ull
 120
 121 #define PSIHB9_BAR_MASK                 0x00fffffffff00000ull
 122 #define PSIHB9_FSPBAR_MASK              0x00ffffff00000000ull
 123
 124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
 125
 126 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
 127 {
 128     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
 129     MemoryRegion *sysmem = get_system_memory();
 130     uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
 131
 132     psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
 133
 134     /* Update MR, always remove it first */
 135     if (old & PSIHB_BAR_EN) {
 136         memory_region_del_subregion(sysmem, &psi->regs_mr);
 137     }
 138
 139     /* Then add it back if needed */
 140     if (bar & PSIHB_BAR_EN) {
 141         uint64_t addr = bar & ppc->bar_mask;
 142         memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
 143     }
 144 }
 145
 146 static void pnv_psi_update_fsp_mr(PnvPsi *psi)
 147 {
 148     /* TODO: Update FSP MR if/when we support FSP BAR */
 149 }
 150
 151 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
 152 {
 153     uint64_t old = psi->regs[PSIHB_XSCOM_CR];
 154
 155     psi->regs[PSIHB_XSCOM_CR] = cr;
 156
 157     /* Check some bit changes */
 158     if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
 159         pnv_psi_update_fsp_mr(psi);
 160     }
 161 }
 162
 163 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
 164 {
 165     ICSState *ics = &PNV8_PSI(psi)->ics;
 166
 167     /* In this model we ignore the up/down enable bits for now
 168      * as SW doesn't use them (other than setting them at boot).
 169      * We ignore IRQ_MUX, its meaning isn't clear and we don't use
 170      * it and finally we ignore reset (XXX fix that ?)
 171      */
 172     psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
 173                                          PSIHB_IRSN_IRQ_MUX |
 174                                          PSIHB_IRSN_IRQ_RESET |
 175                                          PSIHB_IRSN_DOWNSTREAM_EN |
 176                                          PSIHB_IRSN_UPSTREAM_EN);
 177
 178     /* We ignore the compare mask as well, our ICS emulation is too
 179      * simplistic to make any use if it, and we extract the offset
 180      * from the compare value
 181      */
 182     ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
 183 }
 184
 185 /*
 186  * FSP and PSI interrupts are muxed under the same number.
 187  */
 188 static const uint32_t xivr_regs[] = {
 189     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_XIVR_FSP,
 190     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_XIVR_FSP,
 191     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_XIVR_OCC,
 192     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_XIVR_FSI,
 193     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_XIVR_LPCI2C,
 194     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
 195     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_XIVR_EXT,
 196 };
 197
 198 static const uint32_t stat_regs[] = {
 199     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_CR,
 200     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_CR,
 201     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_IRQ_STAT,
 202     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_IRQ_STAT,
 203     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_IRQ_STAT,
 204     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
 205     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_IRQ_STAT,
 206 };
 207
 208 static const uint64_t stat_bits[] = {
 209     [PSIHB_IRQ_PSI]       = PSIHB_CR_PSI_IRQ,
 210     [PSIHB_IRQ_FSP]       = PSIHB_CR_FSP_IRQ,
 211     [PSIHB_IRQ_OCC]       = PSIHB_IRQ_STAT_OCC,
 212     [PSIHB_IRQ_FSI]       = PSIHB_IRQ_STAT_FSI,
 213     [PSIHB_IRQ_LPC_I2C]   = PSIHB_IRQ_STAT_LPCI2C,
 214     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
 215     [PSIHB_IRQ_EXTERNAL]  = PSIHB_IRQ_STAT_EXT,
 216 };
 217
 218 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
 219 {
 220     PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
 221 }
 222
 223 static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
 224 {
 225     uint32_t xivr_reg;
 226     uint32_t stat_reg;
 227     uint32_t src;
 228     bool masked;
 229
 230     if (irq > PSIHB_IRQ_EXTERNAL) {
 231         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
 232         return;
 233     }
 234
 235     xivr_reg = xivr_regs[irq];
 236     stat_reg = stat_regs[irq];
 237
 238     src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 239     if (state) {
 240         psi->regs[stat_reg] |= stat_bits[irq];
 241         /* TODO: optimization, check mask here. That means
 242          * re-evaluating when unmasking
 243          */
 244         qemu_irq_raise(psi->qirqs[src]);
 245     } else {
 246         psi->regs[stat_reg] &= ~stat_bits[irq];
 247
 248         /* FSP and PSI are muxed so don't lower if either is still set */
 249         if (stat_reg != PSIHB_XSCOM_CR ||
 250             !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
 251             qemu_irq_lower(psi->qirqs[src]);
 252         } else {
 253             state = true;
 254         }
 255     }
 256
 257     /* Note about the emulation of the pending bit: This isn't
 258      * entirely correct. The pending bit should be cleared when the
 259      * EOI has been received. However, we don't have callbacks on EOI
 260      * (especially not under KVM) so no way to emulate that properly,
 261      * so instead we just set that bit as the logical "output" of the
 262      * XIVR (ie pending & !masked)
 263      *
 264      * CLG: We could define a new ICS object with a custom eoi()
 265      * handler to clear the pending bit. But I am not sure this would
 266      * be useful for the software anyhow.
 267      */
 268     masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
 269     if (state && !masked) {
 270         psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
 271     } else {
 272         psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
 273     }
 274 }
 275
 276 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
 277 {
 278     ICSState *ics = &PNV8_PSI(psi)->ics;
 279     uint16_t server;
 280     uint8_t prio;
 281     uint8_t src;
 282
 283     psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
 284             (val & (PSIHB_XIVR_SERVER_MSK |
 285                     PSIHB_XIVR_PRIO_MSK |
 286                     PSIHB_XIVR_SRC_MSK));
 287     val = psi->regs[reg];
 288     server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
 289     prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
 290     src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 291
 292     if (src >= PSI_NUM_INTERRUPTS) {
 293         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
 294         return;
 295     }
 296
 297     /* Remove pending bit if the IRQ is masked */
 298     if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
 299         psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
 300     }
 301
 302     /* The low order 2 bits are the link pointer (Type II interrupts).
 303      * Shift back to get a valid IRQ server.
 304      */
 305     server >>= 2;
 306
 307     /* Now because of source remapping, weird things can happen
 308      * if you change the source number dynamically, our simple ICS
 309      * doesn't deal with remapping. So we just poke a different
 310      * ICS entry based on what source number was written. This will
 311      * do for now but a more accurate implementation would instead
 312      * use a fixed server/prio and a remapper of the generated irq.
 313      */
 314     ics_write_xive(ics, src, server, prio, prio);
 315 }
 316
 317 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
 318 {
 319     uint64_t val = 0xffffffffffffffffull;
 320
 321     switch (offset) {
 322     case PSIHB_XSCOM_FIR_RW:
 323     case PSIHB_XSCOM_FIRACT0:
 324     case PSIHB_XSCOM_FIRACT1:
 325     case PSIHB_XSCOM_BAR:
 326     case PSIHB_XSCOM_FSPBAR:
 327     case PSIHB_XSCOM_CR:
 328     case PSIHB_XSCOM_XIVR_FSP:
 329     case PSIHB_XSCOM_XIVR_OCC:
 330     case PSIHB_XSCOM_XIVR_FSI:
 331     case PSIHB_XSCOM_XIVR_LPCI2C:
 332     case PSIHB_XSCOM_XIVR_LOCERR:
 333     case PSIHB_XSCOM_XIVR_EXT:
 334     case PSIHB_XSCOM_IRQ_STAT:
 335     case PSIHB_XSCOM_SEMR:
 336     case PSIHB_XSCOM_DMA_UPADD:
 337     case PSIHB_XSCOM_IRSN:
 338         val = psi->regs[offset];
 339         break;
 340     default:
 341         qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
 342     }
 343     return val;
 344 }
 345
 346 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
 347                               bool mmio)
 348 {
 349     switch (offset) {
 350     case PSIHB_XSCOM_FIR_RW:
 351     case PSIHB_XSCOM_FIRACT0:
 352     case PSIHB_XSCOM_FIRACT1:
 353     case PSIHB_XSCOM_SEMR:
 354     case PSIHB_XSCOM_DMA_UPADD:
 355         psi->regs[offset] = val;
 356         break;
 357     case PSIHB_XSCOM_FIR_OR:
 358         psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
 359         break;
 360     case PSIHB_XSCOM_FIR_AND:
 361         psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
 362         break;
 363     case PSIHB_XSCOM_BAR:
 364         /* Only XSCOM can write this one */
 365         if (!mmio) {
 366             pnv_psi_set_bar(psi, val);
 367         } else {
 368             qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
 369         }
 370         break;
 371     case PSIHB_XSCOM_FSPBAR:
 372         psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
 373         pnv_psi_update_fsp_mr(psi);
 374         break;
 375     case PSIHB_XSCOM_CR:
 376         pnv_psi_set_cr(psi, val);
 377         break;
 378     case PSIHB_XSCOM_SCR:
 379         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
 380         break;
 381     case PSIHB_XSCOM_CCR:
 382         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
 383         break;
 384     case PSIHB_XSCOM_XIVR_FSP:
 385     case PSIHB_XSCOM_XIVR_OCC:
 386     case PSIHB_XSCOM_XIVR_FSI:
 387     case PSIHB_XSCOM_XIVR_LPCI2C:
 388     case PSIHB_XSCOM_XIVR_LOCERR:
 389     case PSIHB_XSCOM_XIVR_EXT:
 390         pnv_psi_set_xivr(psi, offset, val);
 391         break;
 392     case PSIHB_XSCOM_IRQ_STAT:
 393         /* Read only */
 394         qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
 395         break;
 396     case PSIHB_XSCOM_IRSN:
 397         pnv_psi_set_irsn(psi, val);
 398         break;
 399     default:
 400         qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
 401     }
 402 }
 403
 404 /*
 405  * The values of the registers when accessed through the MMIO region
 406  * follow the relation : xscom = (mmio + 0x50) >> 3
 407  */
 408 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
 409 {
 410     return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
 411 }
 412
 413 static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
 414                               uint64_t val, unsigned size)
 415 {
 416     pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
 417 }
 418
 419 static const MemoryRegionOps psi_mmio_ops = {
 420     .read = pnv_psi_mmio_read,
 421     .write = pnv_psi_mmio_write,
 422     .endianness = DEVICE_BIG_ENDIAN,
 423     .valid = {
 424         .min_access_size = 8,
 425         .max_access_size = 8,
 426     },
 427     .impl = {
 428         .min_access_size = 8,
 429         .max_access_size = 8,
 430     },
 431 };
 432
 433 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
 434 {
 435     return pnv_psi_reg_read(opaque, addr >> 3, false);
 436 }
 437
 438 static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
 439                                 uint64_t val, unsigned size)
 440 {
 441     pnv_psi_reg_write(opaque, addr >> 3, val, false);
 442 }
 443
 444 static const MemoryRegionOps pnv_psi_xscom_ops = {
 445     .read = pnv_psi_xscom_read,
 446     .write = pnv_psi_xscom_write,
 447     .endianness = DEVICE_BIG_ENDIAN,
 448     .valid = {
 449         .min_access_size = 8,
 450         .max_access_size = 8,
 451     },
 452     .impl = {
 453         .min_access_size = 8,
 454         .max_access_size = 8,
 455     }
 456 };
 457
 458 static void pnv_psi_reset(void *dev)
 459 {
 460     PnvPsi *psi = PNV_PSI(dev);
 461
 462     memset(psi->regs, 0x0, sizeof(psi->regs));
 463
 464     psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
 465 }
 466
 467 static void pnv_psi_power8_instance_init(Object *obj)
 468 {
 469     Pnv8Psi *psi8 = PNV8_PSI(obj);
 470
 471     object_initialize_child(obj, "ics-psi",  &psi8->ics, sizeof(psi8->ics),
 472                             TYPE_ICS, &error_abort, NULL);
 473 }
 474
 475 static const uint8_t irq_to_xivr[] = {
 476     PSIHB_XSCOM_XIVR_FSP,
 477     PSIHB_XSCOM_XIVR_OCC,
 478     PSIHB_XSCOM_XIVR_FSI,
 479     PSIHB_XSCOM_XIVR_LPCI2C,
 480     PSIHB_XSCOM_XIVR_LOCERR,
 481     PSIHB_XSCOM_XIVR_EXT,
 482 };
 483
 484 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
 485 {
 486     PnvPsi *psi = PNV_PSI(dev);
 487     ICSState *ics = &PNV8_PSI(psi)->ics;
 488     Object *obj;
 489     Error *err = NULL;
 490     unsigned int i;
 491
 492     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 493     if (!obj) {
 494         error_setg(errp, "%s: required link 'xics' not found: %s",
 495                    __func__, error_get_pretty(err));
 496         return;
 497     }
 498
 499     /* Create PSI interrupt control source */
 500     object_property_set_link(OBJECT(ics), obj, ICS_PROP_XICS, &error_abort);
 501     object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
 502     if (err) {
 503         error_propagate(errp, err);
 504         return;
 505     }
 506     object_property_set_bool(OBJECT(ics), true, "realized",  &err);
 507     if (err) {
 508         error_propagate(errp, err);
 509         return;
 510     }
 511
 512     for (i = 0; i < ics->nr_irqs; i++) {
 513         ics_set_irq_type(ics, i, true);
 514     }
 515
 516     psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
 517
 518     /* XSCOM region for PSI registers */
 519     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
 520                 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
 521
 522     /* Initialize MMIO region */
 523     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
 524                           "psihb", PNV_PSIHB_SIZE);
 525
 526     /* Default BAR for MMIO region */
 527     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
 528
 529     /* Default sources in XIVR */
 530     for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
 531         uint8_t xivr = irq_to_xivr[i];
 532         psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
 533             ((uint64_t) i << PSIHB_XIVR_SRC_SH);
 534     }
 535
 536     qemu_register_reset(pnv_psi_reset, dev);
 537 }
 538
 539 static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x";
 540 static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x";
 541 static const char compat_p10[] = "ibm,power10-psihb-x\0ibm,psihb-x";
 542
 543 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 544 {
 545     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
 546     char *name;
 547     int offset;
 548     uint32_t reg[] = {
 549         cpu_to_be32(ppc->xscom_pcba),
 550         cpu_to_be32(ppc->xscom_size)
 551     };
 552
 553     name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
 554     offset = fdt_add_subnode(fdt, xscom_offset, name);
 555     _FDT(offset);
 556     g_free(name);
 557
 558     _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
 559     _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
 560     _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
 561     if (ppc->chip_type == PNV_CHIP_POWER10) {
 562         _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10,
 563                          sizeof(compat_p10)));
 564     } else if (ppc->chip_type == PNV_CHIP_POWER9) {
 565         _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9,
 566                          sizeof(compat_p9)));
 567     } else {
 568         _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8,
 569                          sizeof(compat_p8)));
 570     }
 571     return 0;
 572 }
 573
 574 static Property pnv_psi_properties[] = {
 575     DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
 576     DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
 577     DEFINE_PROP_END_OF_LIST(),
 578 };
 579
 580 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
 581 {
 582     DeviceClass *dc = DEVICE_CLASS(klass);
 583     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 584
 585     dc->desc    = "PowerNV PSI Controller POWER8";
 586     dc->realize = pnv_psi_power8_realize;
 587
 588     ppc->chip_type =  PNV_CHIP_POWER8;
 589     ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
 590     ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
 591     ppc->bar_mask   = PSIHB_BAR_MASK;
 592     ppc->irq_set    = pnv_psi_power8_irq_set;
 593 }
 594
 595 static const TypeInfo pnv_psi_power8_info = {
 596     .name          = TYPE_PNV8_PSI,
 597     .parent        = TYPE_PNV_PSI,
 598     .instance_size = sizeof(Pnv8Psi),
 599     .instance_init = pnv_psi_power8_instance_init,
 600     .class_init    = pnv_psi_power8_class_init,
 601 };
 602
 603
 604 /* Common registers */
 605
 606 #define PSIHB9_CR                       0x20
 607 #define PSIHB9_SEMR                     0x28
 608
 609 /* P9 registers */
 610
 611 #define PSIHB9_INTERRUPT_CONTROL        0x58
 612 #define   PSIHB9_IRQ_METHOD             PPC_BIT(0)
 613 #define   PSIHB9_IRQ_RESET              PPC_BIT(1)
 614 #define PSIHB9_ESB_CI_BASE              0x60
 615 #define   PSIHB9_ESB_CI_64K             PPC_BIT(1)
 616 #define   PSIHB9_ESB_CI_ADDR_MASK       PPC_BITMASK(8, 47)
 617 #define   PSIHB9_ESB_CI_VALID           PPC_BIT(63)
 618 #define PSIHB9_ESB_NOTIF_ADDR           0x68
 619 #define   PSIHB9_ESB_NOTIF_ADDR_MASK    PPC_BITMASK(8, 60)
 620 #define   PSIHB9_ESB_NOTIF_VALID        PPC_BIT(63)
 621 #define PSIHB9_IVT_OFFSET               0x70
 622 #define   PSIHB9_IVT_OFF_SHIFT          32
 623
 624 #define PSIHB9_IRQ_LEVEL                0x78 /* assertion */
 625 #define   PSIHB9_IRQ_LEVEL_PSI          PPC_BIT(0)
 626 #define   PSIHB9_IRQ_LEVEL_OCC          PPC_BIT(1)
 627 #define   PSIHB9_IRQ_LEVEL_FSI          PPC_BIT(2)
 628 #define   PSIHB9_IRQ_LEVEL_LPCHC        PPC_BIT(3)
 629 #define   PSIHB9_IRQ_LEVEL_LOCAL_ERR    PPC_BIT(4)
 630 #define   PSIHB9_IRQ_LEVEL_GLOBAL_ERR   PPC_BIT(5)
 631 #define   PSIHB9_IRQ_LEVEL_TPM          PPC_BIT(6)
 632 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ1    PPC_BIT(7)
 633 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ2    PPC_BIT(8)
 634 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ3    PPC_BIT(9)
 635 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ4    PPC_BIT(10)
 636 #define   PSIHB9_IRQ_LEVEL_SBE_I2C      PPC_BIT(11)
 637 #define   PSIHB9_IRQ_LEVEL_DIO          PPC_BIT(12)
 638 #define   PSIHB9_IRQ_LEVEL_PSU          PPC_BIT(13)
 639 #define   PSIHB9_IRQ_LEVEL_I2C_C        PPC_BIT(14)
 640 #define   PSIHB9_IRQ_LEVEL_I2C_D        PPC_BIT(15)
 641 #define   PSIHB9_IRQ_LEVEL_I2C_E        PPC_BIT(16)
 642 #define   PSIHB9_IRQ_LEVEL_SBE          PPC_BIT(19)
 643
 644 #define PSIHB9_IRQ_STAT                 0x80 /* P bit */
 645 #define   PSIHB9_IRQ_STAT_PSI           PPC_BIT(0)
 646 #define   PSIHB9_IRQ_STAT_OCC           PPC_BIT(1)
 647 #define   PSIHB9_IRQ_STAT_FSI           PPC_BIT(2)
 648 #define   PSIHB9_IRQ_STAT_LPCHC         PPC_BIT(3)
 649 #define   PSIHB9_IRQ_STAT_LOCAL_ERR     PPC_BIT(4)
 650 #define   PSIHB9_IRQ_STAT_GLOBAL_ERR    PPC_BIT(5)
 651 #define   PSIHB9_IRQ_STAT_TPM           PPC_BIT(6)
 652 #define   PSIHB9_IRQ_STAT_LPC_SIRQ1     PPC_BIT(7)
 653 #define   PSIHB9_IRQ_STAT_LPC_SIRQ2     PPC_BIT(8)
 654 #define   PSIHB9_IRQ_STAT_LPC_SIRQ3     PPC_BIT(9)
 655 #define   PSIHB9_IRQ_STAT_LPC_SIRQ4     PPC_BIT(10)
 656 #define   PSIHB9_IRQ_STAT_SBE_I2C       PPC_BIT(11)
 657 #define   PSIHB9_IRQ_STAT_DIO           PPC_BIT(12)
 658 #define   PSIHB9_IRQ_STAT_PSU           PPC_BIT(13)
 659
 660 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
 661 {
 662     PnvPsi *psi = PNV_PSI(xf);
 663     uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
 664     bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID;
 665     uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID;
 666
 667     uint32_t offset =
 668         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
 669     uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
 670     MemTxResult result;
 671
 672     if (!valid) {
 673         return;
 674     }
 675
 676     address_space_stq_be(&address_space_memory, notify_addr, data,
 677                          MEMTXATTRS_UNSPECIFIED, &result);
 678     if (result != MEMTX_OK) {
 679         qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%"
 680                       HWADDR_PRIx "\n", __func__, notif_port);
 681         return;
 682     }
 683 }
 684
 685 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size)
 686 {
 687     PnvPsi *psi = PNV_PSI(opaque);
 688     uint32_t reg = PSIHB_REG(addr);
 689     uint64_t val = -1;
 690
 691     switch (addr) {
 692     case PSIHB9_CR:
 693     case PSIHB9_SEMR:
 694         /* FSP stuff */
 695     case PSIHB9_INTERRUPT_CONTROL:
 696     case PSIHB9_ESB_CI_BASE:
 697     case PSIHB9_ESB_NOTIF_ADDR:
 698     case PSIHB9_IVT_OFFSET:
 699         val = psi->regs[reg];
 700         break;
 701     default:
 702         qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr);
 703     }
 704
 705     return val;
 706 }
 707
 708 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
 709                                   uint64_t val, unsigned size)
 710 {
 711     PnvPsi *psi = PNV_PSI(opaque);
 712     Pnv9Psi *psi9 = PNV9_PSI(psi);
 713     uint32_t reg = PSIHB_REG(addr);
 714     MemoryRegion *sysmem = get_system_memory();
 715
 716     switch (addr) {
 717     case PSIHB9_CR:
 718     case PSIHB9_SEMR:
 719         /* FSP stuff */
 720         break;
 721     case PSIHB9_INTERRUPT_CONTROL:
 722         if (val & PSIHB9_IRQ_RESET) {
 723             device_reset(DEVICE(&psi9->source));
 724         }
 725         psi->regs[reg] = val;
 726         break;
 727
 728     case PSIHB9_ESB_CI_BASE:
 729         if (!(val & PSIHB9_ESB_CI_VALID)) {
 730             if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
 731                 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
 732             }
 733         } else {
 734             if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
 735                 memory_region_add_subregion(sysmem,
 736                                         val & ~PSIHB9_ESB_CI_VALID,
 737                                         &psi9->source.esb_mmio);
 738             }
 739         }
 740         psi->regs[reg] = val;
 741         break;
 742
 743     case PSIHB9_ESB_NOTIF_ADDR:
 744         psi->regs[reg] = val;
 745         break;
 746     case PSIHB9_IVT_OFFSET:
 747         psi->regs[reg] = val;
 748         break;
 749     default:
 750         qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr);
 751     }
 752 }
 753
 754 static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
 755     .read = pnv_psi_p9_mmio_read,
 756     .write = pnv_psi_p9_mmio_write,
 757     .endianness = DEVICE_BIG_ENDIAN,
 758     .valid = {
 759         .min_access_size = 8,
 760         .max_access_size = 8,
 761     },
 762     .impl = {
 763         .min_access_size = 8,
 764         .max_access_size = 8,
 765     },
 766 };
 767
 768 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
 769 {
 770     /* No read are expected */
 771     qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
 772     return -1;
 773 }
 774
 775 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
 776                                 uint64_t val, unsigned size)
 777 {
 778     PnvPsi *psi = PNV_PSI(opaque);
 779
 780     /* XSCOM is only used to set the PSIHB MMIO region */
 781     switch (addr >> 3) {
 782     case PSIHB_XSCOM_BAR:
 783         pnv_psi_set_bar(psi, val);
 784         break;
 785     default:
 786         qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
 787                       addr);
 788     }
 789 }
 790
 791 static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
 792     .read = pnv_psi_p9_xscom_read,
 793     .write = pnv_psi_p9_xscom_write,
 794     .endianness = DEVICE_BIG_ENDIAN,
 795     .valid = {
 796         .min_access_size = 8,
 797         .max_access_size = 8,
 798     },
 799     .impl = {
 800         .min_access_size = 8,
 801         .max_access_size = 8,
 802     }
 803 };
 804
 805 static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
 806 {
 807     uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
 808
 809     if (irq > PSIHB9_NUM_IRQS) {
 810         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
 811         return;
 812     }
 813
 814     if (irq_method & PSIHB9_IRQ_METHOD) {
 815         qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
 816         return;
 817     }
 818
 819     /* Update LSI levels */
 820     if (state) {
 821         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
 822     } else {
 823         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
 824     }
 825
 826     qemu_set_irq(psi->qirqs[irq], state);
 827 }
 828
 829 static void pnv_psi_power9_reset(void *dev)
 830 {
 831     Pnv9Psi *psi = PNV9_PSI(dev);
 832
 833     pnv_psi_reset(dev);
 834
 835     if (memory_region_is_mapped(&psi->source.esb_mmio)) {
 836         memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
 837     }
 838 }
 839
 840 static void pnv_psi_power9_instance_init(Object *obj)
 841 {
 842     Pnv9Psi *psi = PNV9_PSI(obj);
 843
 844     object_initialize_child(obj, "source", &psi->source, sizeof(psi->source),
 845                             TYPE_XIVE_SOURCE, &error_abort, NULL);
 846 }
 847
 848 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
 849 {
 850     PnvPsi *psi = PNV_PSI(dev);
 851     XiveSource *xsrc = &PNV9_PSI(psi)->source;
 852     Error *local_err = NULL;
 853     int i;
 854
 855     /* This is the only device with 4k ESB pages */
 856     object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
 857                             &error_fatal);
 858     object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs",
 859                             &error_fatal);
 860     object_property_set_link(OBJECT(xsrc), OBJECT(psi), "xive", &error_abort);
 861     object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
 862     if (local_err) {
 863         error_propagate(errp, local_err);
 864         return;
 865     }
 866
 867     for (i = 0; i < xsrc->nr_irqs; i++) {
 868         xive_source_irq_set_lsi(xsrc, i);
 869     }
 870
 871     psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
 872
 873     /* XSCOM region for PSI registers */
 874     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
 875                 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
 876
 877     /* MMIO region for PSI registers */
 878     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
 879                           "psihb", PNV9_PSIHB_SIZE);
 880
 881     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
 882
 883     qemu_register_reset(pnv_psi_power9_reset, dev);
 884 }
 885
 886 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
 887 {
 888     DeviceClass *dc = DEVICE_CLASS(klass);
 889     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 890     XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
 891
 892     dc->desc    = "PowerNV PSI Controller POWER9";
 893     dc->realize = pnv_psi_power9_realize;
 894
 895     ppc->chip_type  = PNV_CHIP_POWER9;
 896     ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
 897     ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
 898     ppc->bar_mask   = PSIHB9_BAR_MASK;
 899     ppc->irq_set    = pnv_psi_power9_irq_set;
 900
 901     xfc->notify      = pnv_psi_notify;
 902 }
 903
 904 static const TypeInfo pnv_psi_power9_info = {
 905     .name          = TYPE_PNV9_PSI,
 906     .parent        = TYPE_PNV_PSI,
 907     .instance_size = sizeof(Pnv9Psi),
 908     .instance_init = pnv_psi_power9_instance_init,
 909     .class_init    = pnv_psi_power9_class_init,
 910     .interfaces = (InterfaceInfo[]) {
 911             { TYPE_XIVE_NOTIFIER },
 912             { },
 913     },
 914 };
 915
 916 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data)
 917 {
 918     DeviceClass *dc = DEVICE_CLASS(klass);
 919     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 920
 921     dc->desc    = "PowerNV PSI Controller POWER10";
 922
 923     ppc->chip_type  = PNV_CHIP_POWER10;
 924     ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE;
 925     ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE;
 926 }
 927
 928 static const TypeInfo pnv_psi_power10_info = {
 929     .name          = TYPE_PNV10_PSI,
 930     .parent        = TYPE_PNV9_PSI,
 931     .class_init    = pnv_psi_power10_class_init,
 932 };
 933
 934 static void pnv_psi_class_init(ObjectClass *klass, void *data)
 935 {
 936     DeviceClass *dc = DEVICE_CLASS(klass);
 937     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 938
 939     xdc->dt_xscom = pnv_psi_dt_xscom;
 940
 941     dc->desc = "PowerNV PSI Controller";
 942     dc->props = pnv_psi_properties;
 943 }
 944
 945 static const TypeInfo pnv_psi_info = {
 946     .name          = TYPE_PNV_PSI,
 947     .parent        = TYPE_SYS_BUS_DEVICE,
 948     .instance_size = sizeof(PnvPsi),
 949     .class_init    = pnv_psi_class_init,
 950     .class_size    = sizeof(PnvPsiClass),
 951     .abstract      = true,
 952     .interfaces    = (InterfaceInfo[]) {
 953         { TYPE_PNV_XSCOM_INTERFACE },
 954         { }
 955     }
 956 };
 957
 958 static void pnv_psi_register_types(void)
 959 {
 960     type_register_static(&pnv_psi_info);
 961     type_register_static(&pnv_psi_power8_info);
 962     type_register_static(&pnv_psi_power9_info);
 963     type_register_static(&pnv_psi_power10_info);
 964 }
 965
 966 type_init(pnv_psi_register_types);
 967
 968 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
 969 {
 970     PnvPsi *psi = PNV_PSI(psi9);
 971
 972     uint32_t offset =
 973         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
 974
 975     monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
 976                   offset, offset + psi9->source.nr_irqs - 1);
 977     xive_source_pic_print_info(&psi9->source, offset, mon);
 978 }