hw/ppc/pnv_psi.c

   1 /*
   2  * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
   3  *
   4  * Copyright (c) 2015-2017, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/hw.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "qapi/error.h"
  26 #include "monitor/monitor.h"
  27
  28 #include "exec/address-spaces.h"
  29
  30 #include "hw/ppc/fdt.h"
  31 #include "hw/ppc/pnv.h"
  32 #include "hw/ppc/pnv_xscom.h"
  33 #include "hw/ppc/pnv_psi.h"
  34
  35 #include <libfdt.h>
  36
  37 #define PSIHB_XSCOM_FIR_RW      0x00
  38 #define PSIHB_XSCOM_FIR_AND     0x01
  39 #define PSIHB_XSCOM_FIR_OR      0x02
  40 #define PSIHB_XSCOM_FIRMASK_RW  0x03
  41 #define PSIHB_XSCOM_FIRMASK_AND 0x04
  42 #define PSIHB_XSCOM_FIRMASK_OR  0x05
  43 #define PSIHB_XSCOM_FIRACT0     0x06
  44 #define PSIHB_XSCOM_FIRACT1     0x07
  45
  46 /* Host Bridge Base Address Register */
  47 #define PSIHB_XSCOM_BAR         0x0a
  48 #define   PSIHB_BAR_EN                  0x0000000000000001ull
  49
  50 /* FSP Base Address Register */
  51 #define PSIHB_XSCOM_FSPBAR      0x0b
  52
  53 /* PSI Host Bridge Control/Status Register */
  54 #define PSIHB_XSCOM_CR          0x0e
  55 #define   PSIHB_CR_FSP_CMD_ENABLE       0x8000000000000000ull
  56 #define   PSIHB_CR_FSP_MMIO_ENABLE      0x4000000000000000ull
  57 #define   PSIHB_CR_FSP_IRQ_ENABLE       0x1000000000000000ull
  58 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE   0x0800000000000000ull
  59 #define   PSIHB_CR_PSI_LINK_ENABLE      0x0400000000000000ull
  60 #define   PSIHB_CR_FSP_RESET            0x0200000000000000ull
  61 #define   PSIHB_CR_PSIHB_RESET          0x0100000000000000ull
  62 #define   PSIHB_CR_PSI_IRQ              0x0000800000000000ull
  63 #define   PSIHB_CR_FSP_IRQ              0x0000400000000000ull
  64 #define   PSIHB_CR_FSP_LINK_ACTIVE      0x0000200000000000ull
  65 #define   PSIHB_CR_IRQ_CMD_EXPECT       0x0000010000000000ull
  66           /* and more ... */
  67
  68 /* PSIHB Status / Error Mask Register */
  69 #define PSIHB_XSCOM_SEMR        0x0f
  70
  71 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
  72 #define PSIHB_XSCOM_XIVR_FSP    0x10
  73 #define   PSIHB_XIVR_SERVER_SH          40
  74 #define   PSIHB_XIVR_SERVER_MSK         (0xffffull << PSIHB_XIVR_SERVER_SH)
  75 #define   PSIHB_XIVR_PRIO_SH            32
  76 #define   PSIHB_XIVR_PRIO_MSK           (0xffull << PSIHB_XIVR_PRIO_SH)
  77 #define   PSIHB_XIVR_SRC_SH             29
  78 #define   PSIHB_XIVR_SRC_MSK            (0x7ull << PSIHB_XIVR_SRC_SH)
  79 #define   PSIHB_XIVR_PENDING            0x01000000ull
  80
  81 /* PSI Host Bridge Set Control/ Status Register */
  82 #define PSIHB_XSCOM_SCR         0x12
  83
  84 /* PSI Host Bridge Clear Control/ Status Register */
  85 #define PSIHB_XSCOM_CCR         0x13
  86
  87 /* DMA Upper Address Register */
  88 #define PSIHB_XSCOM_DMA_UPADD   0x14
  89
  90 /* Interrupt Status */
  91 #define PSIHB_XSCOM_IRQ_STAT    0x15
  92 #define   PSIHB_IRQ_STAT_OCC            0x0000001000000000ull
  93 #define   PSIHB_IRQ_STAT_FSI            0x0000000800000000ull
  94 #define   PSIHB_IRQ_STAT_LPCI2C         0x0000000400000000ull
  95 #define   PSIHB_IRQ_STAT_LOCERR         0x0000000200000000ull
  96 #define   PSIHB_IRQ_STAT_EXT            0x0000000100000000ull
  97
  98 /* remaining XIVR */
  99 #define PSIHB_XSCOM_XIVR_OCC    0x16
 100 #define PSIHB_XSCOM_XIVR_FSI    0x17
 101 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18
 102 #define PSIHB_XSCOM_XIVR_LOCERR 0x19
 103 #define PSIHB_XSCOM_XIVR_EXT    0x1a
 104
 105 /* Interrupt Requester Source Compare Register */
 106 #define PSIHB_XSCOM_IRSN        0x1b
 107 #define   PSIHB_IRSN_COMP_SH            45
 108 #define   PSIHB_IRSN_COMP_MSK           (0x7ffffull << PSIHB_IRSN_COMP_SH)
 109 #define   PSIHB_IRSN_IRQ_MUX            0x0000000800000000ull
 110 #define   PSIHB_IRSN_IRQ_RESET          0x0000000400000000ull
 111 #define   PSIHB_IRSN_DOWNSTREAM_EN      0x0000000200000000ull
 112 #define   PSIHB_IRSN_UPSTREAM_EN        0x0000000100000000ull
 113 #define   PSIHB_IRSN_COMPMASK_SH        13
 114 #define   PSIHB_IRSN_COMPMASK_MSK       (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
 115
 116 #define PSIHB_BAR_MASK                  0x0003fffffff00000ull
 117 #define PSIHB_FSPBAR_MASK               0x0003ffff00000000ull
 118
 119 #define PSIHB9_BAR_MASK                 0x00fffffffff00000ull
 120 #define PSIHB9_FSPBAR_MASK              0x00ffffff00000000ull
 121
 122 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
 123
 124 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
 125 {
 126     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
 127     MemoryRegion *sysmem = get_system_memory();
 128     uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
 129
 130     psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
 131
 132     /* Update MR, always remove it first */
 133     if (old & PSIHB_BAR_EN) {
 134         memory_region_del_subregion(sysmem, &psi->regs_mr);
 135     }
 136
 137     /* Then add it back if needed */
 138     if (bar & PSIHB_BAR_EN) {
 139         uint64_t addr = bar & ppc->bar_mask;
 140         memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
 141     }
 142 }
 143
 144 static void pnv_psi_update_fsp_mr(PnvPsi *psi)
 145 {
 146     /* TODO: Update FSP MR if/when we support FSP BAR */
 147 }
 148
 149 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
 150 {
 151     uint64_t old = psi->regs[PSIHB_XSCOM_CR];
 152
 153     psi->regs[PSIHB_XSCOM_CR] = cr;
 154
 155     /* Check some bit changes */
 156     if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
 157         pnv_psi_update_fsp_mr(psi);
 158     }
 159 }
 160
 161 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
 162 {
 163     ICSState *ics = &PNV8_PSI(psi)->ics;
 164
 165     /* In this model we ignore the up/down enable bits for now
 166      * as SW doesn't use them (other than setting them at boot).
 167      * We ignore IRQ_MUX, its meaning isn't clear and we don't use
 168      * it and finally we ignore reset (XXX fix that ?)
 169      */
 170     psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
 171                                          PSIHB_IRSN_IRQ_MUX |
 172                                          PSIHB_IRSN_IRQ_RESET |
 173                                          PSIHB_IRSN_DOWNSTREAM_EN |
 174                                          PSIHB_IRSN_UPSTREAM_EN);
 175
 176     /* We ignore the compare mask as well, our ICS emulation is too
 177      * simplistic to make any use if it, and we extract the offset
 178      * from the compare value
 179      */
 180     ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
 181 }
 182
 183 /*
 184  * FSP and PSI interrupts are muxed under the same number.
 185  */
 186 static const uint32_t xivr_regs[] = {
 187     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_XIVR_FSP,
 188     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_XIVR_FSP,
 189     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_XIVR_OCC,
 190     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_XIVR_FSI,
 191     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_XIVR_LPCI2C,
 192     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
 193     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_XIVR_EXT,
 194 };
 195
 196 static const uint32_t stat_regs[] = {
 197     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_CR,
 198     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_CR,
 199     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_IRQ_STAT,
 200     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_IRQ_STAT,
 201     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_IRQ_STAT,
 202     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
 203     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_IRQ_STAT,
 204 };
 205
 206 static const uint64_t stat_bits[] = {
 207     [PSIHB_IRQ_PSI]       = PSIHB_CR_PSI_IRQ,
 208     [PSIHB_IRQ_FSP]       = PSIHB_CR_FSP_IRQ,
 209     [PSIHB_IRQ_OCC]       = PSIHB_IRQ_STAT_OCC,
 210     [PSIHB_IRQ_FSI]       = PSIHB_IRQ_STAT_FSI,
 211     [PSIHB_IRQ_LPC_I2C]   = PSIHB_IRQ_STAT_LPCI2C,
 212     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
 213     [PSIHB_IRQ_EXTERNAL]  = PSIHB_IRQ_STAT_EXT,
 214 };
 215
 216 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
 217 {
 218     PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
 219 }
 220
 221 static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
 222 {
 223     uint32_t xivr_reg;
 224     uint32_t stat_reg;
 225     uint32_t src;
 226     bool masked;
 227
 228     if (irq > PSIHB_IRQ_EXTERNAL) {
 229         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
 230         return;
 231     }
 232
 233     xivr_reg = xivr_regs[irq];
 234     stat_reg = stat_regs[irq];
 235
 236     src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 237     if (state) {
 238         psi->regs[stat_reg] |= stat_bits[irq];
 239         /* TODO: optimization, check mask here. That means
 240          * re-evaluating when unmasking
 241          */
 242         qemu_irq_raise(psi->qirqs[src]);
 243     } else {
 244         psi->regs[stat_reg] &= ~stat_bits[irq];
 245
 246         /* FSP and PSI are muxed so don't lower if either is still set */
 247         if (stat_reg != PSIHB_XSCOM_CR ||
 248             !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
 249             qemu_irq_lower(psi->qirqs[src]);
 250         } else {
 251             state = true;
 252         }
 253     }
 254
 255     /* Note about the emulation of the pending bit: This isn't
 256      * entirely correct. The pending bit should be cleared when the
 257      * EOI has been received. However, we don't have callbacks on EOI
 258      * (especially not under KVM) so no way to emulate that properly,
 259      * so instead we just set that bit as the logical "output" of the
 260      * XIVR (ie pending & !masked)
 261      *
 262      * CLG: We could define a new ICS object with a custom eoi()
 263      * handler to clear the pending bit. But I am not sure this would
 264      * be useful for the software anyhow.
 265      */
 266     masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
 267     if (state && !masked) {
 268         psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
 269     } else {
 270         psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
 271     }
 272 }
 273
 274 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
 275 {
 276     ICSState *ics = &PNV8_PSI(psi)->ics;
 277     uint16_t server;
 278     uint8_t prio;
 279     uint8_t src;
 280
 281     psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
 282             (val & (PSIHB_XIVR_SERVER_MSK |
 283                     PSIHB_XIVR_PRIO_MSK |
 284                     PSIHB_XIVR_SRC_MSK));
 285     val = psi->regs[reg];
 286     server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
 287     prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
 288     src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 289
 290     if (src >= PSI_NUM_INTERRUPTS) {
 291         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
 292         return;
 293     }
 294
 295     /* Remove pending bit if the IRQ is masked */
 296     if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
 297         psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
 298     }
 299
 300     /* The low order 2 bits are the link pointer (Type II interrupts).
 301      * Shift back to get a valid IRQ server.
 302      */
 303     server >>= 2;
 304
 305     /* Now because of source remapping, weird things can happen
 306      * if you change the source number dynamically, our simple ICS
 307      * doesn't deal with remapping. So we just poke a different
 308      * ICS entry based on what source number was written. This will
 309      * do for now but a more accurate implementation would instead
 310      * use a fixed server/prio and a remapper of the generated irq.
 311      */
 312     ics_simple_write_xive(ics, src, server, prio, prio);
 313 }
 314
 315 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
 316 {
 317     uint64_t val = 0xffffffffffffffffull;
 318
 319     switch (offset) {
 320     case PSIHB_XSCOM_FIR_RW:
 321     case PSIHB_XSCOM_FIRACT0:
 322     case PSIHB_XSCOM_FIRACT1:
 323     case PSIHB_XSCOM_BAR:
 324     case PSIHB_XSCOM_FSPBAR:
 325     case PSIHB_XSCOM_CR:
 326     case PSIHB_XSCOM_XIVR_FSP:
 327     case PSIHB_XSCOM_XIVR_OCC:
 328     case PSIHB_XSCOM_XIVR_FSI:
 329     case PSIHB_XSCOM_XIVR_LPCI2C:
 330     case PSIHB_XSCOM_XIVR_LOCERR:
 331     case PSIHB_XSCOM_XIVR_EXT:
 332     case PSIHB_XSCOM_IRQ_STAT:
 333     case PSIHB_XSCOM_SEMR:
 334     case PSIHB_XSCOM_DMA_UPADD:
 335     case PSIHB_XSCOM_IRSN:
 336         val = psi->regs[offset];
 337         break;
 338     default:
 339         qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
 340     }
 341     return val;
 342 }
 343
 344 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
 345                               bool mmio)
 346 {
 347     switch (offset) {
 348     case PSIHB_XSCOM_FIR_RW:
 349     case PSIHB_XSCOM_FIRACT0:
 350     case PSIHB_XSCOM_FIRACT1:
 351     case PSIHB_XSCOM_SEMR:
 352     case PSIHB_XSCOM_DMA_UPADD:
 353         psi->regs[offset] = val;
 354         break;
 355     case PSIHB_XSCOM_FIR_OR:
 356         psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
 357         break;
 358     case PSIHB_XSCOM_FIR_AND:
 359         psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
 360         break;
 361     case PSIHB_XSCOM_BAR:
 362         /* Only XSCOM can write this one */
 363         if (!mmio) {
 364             pnv_psi_set_bar(psi, val);
 365         } else {
 366             qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
 367         }
 368         break;
 369     case PSIHB_XSCOM_FSPBAR:
 370         psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
 371         pnv_psi_update_fsp_mr(psi);
 372         break;
 373     case PSIHB_XSCOM_CR:
 374         pnv_psi_set_cr(psi, val);
 375         break;
 376     case PSIHB_XSCOM_SCR:
 377         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
 378         break;
 379     case PSIHB_XSCOM_CCR:
 380         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
 381         break;
 382     case PSIHB_XSCOM_XIVR_FSP:
 383     case PSIHB_XSCOM_XIVR_OCC:
 384     case PSIHB_XSCOM_XIVR_FSI:
 385     case PSIHB_XSCOM_XIVR_LPCI2C:
 386     case PSIHB_XSCOM_XIVR_LOCERR:
 387     case PSIHB_XSCOM_XIVR_EXT:
 388         pnv_psi_set_xivr(psi, offset, val);
 389         break;
 390     case PSIHB_XSCOM_IRQ_STAT:
 391         /* Read only */
 392         qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
 393         break;
 394     case PSIHB_XSCOM_IRSN:
 395         pnv_psi_set_irsn(psi, val);
 396         break;
 397     default:
 398         qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
 399     }
 400 }
 401
 402 /*
 403  * The values of the registers when accessed through the MMIO region
 404  * follow the relation : xscom = (mmio + 0x50) >> 3
 405  */
 406 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
 407 {
 408     return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
 409 }
 410
 411 static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
 412                               uint64_t val, unsigned size)
 413 {
 414     pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
 415 }
 416
 417 static const MemoryRegionOps psi_mmio_ops = {
 418     .read = pnv_psi_mmio_read,
 419     .write = pnv_psi_mmio_write,
 420     .endianness = DEVICE_BIG_ENDIAN,
 421     .valid = {
 422         .min_access_size = 8,
 423         .max_access_size = 8,
 424     },
 425     .impl = {
 426         .min_access_size = 8,
 427         .max_access_size = 8,
 428     },
 429 };
 430
 431 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
 432 {
 433     return pnv_psi_reg_read(opaque, addr >> 3, false);
 434 }
 435
 436 static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
 437                                 uint64_t val, unsigned size)
 438 {
 439     pnv_psi_reg_write(opaque, addr >> 3, val, false);
 440 }
 441
 442 static const MemoryRegionOps pnv_psi_xscom_ops = {
 443     .read = pnv_psi_xscom_read,
 444     .write = pnv_psi_xscom_write,
 445     .endianness = DEVICE_BIG_ENDIAN,
 446     .valid = {
 447         .min_access_size = 8,
 448         .max_access_size = 8,
 449     },
 450     .impl = {
 451         .min_access_size = 8,
 452         .max_access_size = 8,
 453     }
 454 };
 455
 456 static void pnv_psi_reset(void *dev)
 457 {
 458     PnvPsi *psi = PNV_PSI(dev);
 459
 460     memset(psi->regs, 0x0, sizeof(psi->regs));
 461
 462     psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
 463 }
 464
 465 static void pnv_psi_power8_instance_init(Object *obj)
 466 {
 467     Pnv8Psi *psi8 = PNV8_PSI(obj);
 468
 469     object_initialize_child(obj, "ics-psi",  &psi8->ics, sizeof(psi8->ics),
 470                             TYPE_ICS_SIMPLE, &error_abort, NULL);
 471 }
 472
 473 static const uint8_t irq_to_xivr[] = {
 474     PSIHB_XSCOM_XIVR_FSP,
 475     PSIHB_XSCOM_XIVR_OCC,
 476     PSIHB_XSCOM_XIVR_FSI,
 477     PSIHB_XSCOM_XIVR_LPCI2C,
 478     PSIHB_XSCOM_XIVR_LOCERR,
 479     PSIHB_XSCOM_XIVR_EXT,
 480 };
 481
 482 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
 483 {
 484     PnvPsi *psi = PNV_PSI(dev);
 485     ICSState *ics = &PNV8_PSI(psi)->ics;
 486     Object *obj;
 487     Error *err = NULL;
 488     unsigned int i;
 489
 490     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 491     if (!obj) {
 492         error_setg(errp, "%s: required link 'xics' not found: %s",
 493                    __func__, error_get_pretty(err));
 494         return;
 495     }
 496
 497     /* Create PSI interrupt control source */
 498     object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj,
 499                                    &error_abort);
 500     object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
 501     if (err) {
 502         error_propagate(errp, err);
 503         return;
 504     }
 505     object_property_set_bool(OBJECT(ics), true, "realized",  &err);
 506     if (err) {
 507         error_propagate(errp, err);
 508         return;
 509     }
 510
 511     for (i = 0; i < ics->nr_irqs; i++) {
 512         ics_set_irq_type(ics, i, true);
 513     }
 514
 515     psi->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
 516
 517     /* XSCOM region for PSI registers */
 518     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
 519                 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
 520
 521     /* Initialize MMIO region */
 522     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
 523                           "psihb", PNV_PSIHB_SIZE);
 524
 525     /* Default BAR for MMIO region */
 526     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
 527
 528     /* Default sources in XIVR */
 529     for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
 530         uint8_t xivr = irq_to_xivr[i];
 531         psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
 532             ((uint64_t) i << PSIHB_XIVR_SRC_SH);
 533     }
 534
 535     qemu_register_reset(pnv_psi_reset, dev);
 536 }
 537
 538 static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x";
 539 static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x";
 540
 541 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 542 {
 543     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
 544     char *name;
 545     int offset;
 546     uint32_t reg[] = {
 547         cpu_to_be32(ppc->xscom_pcba),
 548         cpu_to_be32(ppc->xscom_size)
 549     };
 550
 551     name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
 552     offset = fdt_add_subnode(fdt, xscom_offset, name);
 553     _FDT(offset);
 554     g_free(name);
 555
 556     _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
 557     _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
 558     _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
 559     if (ppc->chip_type == PNV_CHIP_POWER9) {
 560         _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9,
 561                          sizeof(compat_p9)));
 562     } else {
 563         _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8,
 564                          sizeof(compat_p8)));
 565     }
 566     return 0;
 567 }
 568
 569 static Property pnv_psi_properties[] = {
 570     DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
 571     DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
 572     DEFINE_PROP_END_OF_LIST(),
 573 };
 574
 575 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
 576 {
 577     DeviceClass *dc = DEVICE_CLASS(klass);
 578     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 579
 580     dc->desc    = "PowerNV PSI Controller POWER8";
 581     dc->realize = pnv_psi_power8_realize;
 582
 583     ppc->chip_type =  PNV_CHIP_POWER8;
 584     ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
 585     ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
 586     ppc->bar_mask   = PSIHB_BAR_MASK;
 587     ppc->irq_set    = pnv_psi_power8_irq_set;
 588 }
 589
 590 static const TypeInfo pnv_psi_power8_info = {
 591     .name          = TYPE_PNV8_PSI,
 592     .parent        = TYPE_PNV_PSI,
 593     .instance_size = sizeof(Pnv8Psi),
 594     .instance_init = pnv_psi_power8_instance_init,
 595     .class_init    = pnv_psi_power8_class_init,
 596 };
 597
 598
 599 /* Common registers */
 600
 601 #define PSIHB9_CR                       0x20
 602 #define PSIHB9_SEMR                     0x28
 603
 604 /* P9 registers */
 605
 606 #define PSIHB9_INTERRUPT_CONTROL        0x58
 607 #define   PSIHB9_IRQ_METHOD             PPC_BIT(0)
 608 #define   PSIHB9_IRQ_RESET              PPC_BIT(1)
 609 #define PSIHB9_ESB_CI_BASE              0x60
 610 #define   PSIHB9_ESB_CI_VALID           1
 611 #define PSIHB9_ESB_NOTIF_ADDR           0x68
 612 #define   PSIHB9_ESB_NOTIF_VALID        1
 613 #define PSIHB9_IVT_OFFSET               0x70
 614 #define   PSIHB9_IVT_OFF_SHIFT          32
 615
 616 #define PSIHB9_IRQ_LEVEL                0x78 /* assertion */
 617 #define   PSIHB9_IRQ_LEVEL_PSI          PPC_BIT(0)
 618 #define   PSIHB9_IRQ_LEVEL_OCC          PPC_BIT(1)
 619 #define   PSIHB9_IRQ_LEVEL_FSI          PPC_BIT(2)
 620 #define   PSIHB9_IRQ_LEVEL_LPCHC        PPC_BIT(3)
 621 #define   PSIHB9_IRQ_LEVEL_LOCAL_ERR    PPC_BIT(4)
 622 #define   PSIHB9_IRQ_LEVEL_GLOBAL_ERR   PPC_BIT(5)
 623 #define   PSIHB9_IRQ_LEVEL_TPM          PPC_BIT(6)
 624 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ1    PPC_BIT(7)
 625 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ2    PPC_BIT(8)
 626 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ3    PPC_BIT(9)
 627 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ4    PPC_BIT(10)
 628 #define   PSIHB9_IRQ_LEVEL_SBE_I2C      PPC_BIT(11)
 629 #define   PSIHB9_IRQ_LEVEL_DIO          PPC_BIT(12)
 630 #define   PSIHB9_IRQ_LEVEL_PSU          PPC_BIT(13)
 631 #define   PSIHB9_IRQ_LEVEL_I2C_C        PPC_BIT(14)
 632 #define   PSIHB9_IRQ_LEVEL_I2C_D        PPC_BIT(15)
 633 #define   PSIHB9_IRQ_LEVEL_I2C_E        PPC_BIT(16)
 634 #define   PSIHB9_IRQ_LEVEL_SBE          PPC_BIT(19)
 635
 636 #define PSIHB9_IRQ_STAT                 0x80 /* P bit */
 637 #define   PSIHB9_IRQ_STAT_PSI           PPC_BIT(0)
 638 #define   PSIHB9_IRQ_STAT_OCC           PPC_BIT(1)
 639 #define   PSIHB9_IRQ_STAT_FSI           PPC_BIT(2)
 640 #define   PSIHB9_IRQ_STAT_LPCHC         PPC_BIT(3)
 641 #define   PSIHB9_IRQ_STAT_LOCAL_ERR     PPC_BIT(4)
 642 #define   PSIHB9_IRQ_STAT_GLOBAL_ERR    PPC_BIT(5)
 643 #define   PSIHB9_IRQ_STAT_TPM           PPC_BIT(6)
 644 #define   PSIHB9_IRQ_STAT_LPC_SIRQ1     PPC_BIT(7)
 645 #define   PSIHB9_IRQ_STAT_LPC_SIRQ2     PPC_BIT(8)
 646 #define   PSIHB9_IRQ_STAT_LPC_SIRQ3     PPC_BIT(9)
 647 #define   PSIHB9_IRQ_STAT_LPC_SIRQ4     PPC_BIT(10)
 648 #define   PSIHB9_IRQ_STAT_SBE_I2C       PPC_BIT(11)
 649 #define   PSIHB9_IRQ_STAT_DIO           PPC_BIT(12)
 650 #define   PSIHB9_IRQ_STAT_PSU           PPC_BIT(13)
 651
 652 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
 653 {
 654     PnvPsi *psi = PNV_PSI(xf);
 655     uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
 656     bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID;
 657     uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID;
 658
 659     uint32_t offset =
 660         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
 661     uint64_t lisn = cpu_to_be64(offset + srcno);
 662
 663     if (valid) {
 664         cpu_physical_memory_write(notify_addr, &lisn, sizeof(lisn));
 665     }
 666 }
 667
 668 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size)
 669 {
 670     PnvPsi *psi = PNV_PSI(opaque);
 671     uint32_t reg = PSIHB_REG(addr);
 672     uint64_t val = -1;
 673
 674     switch (addr) {
 675     case PSIHB9_CR:
 676     case PSIHB9_SEMR:
 677         /* FSP stuff */
 678     case PSIHB9_INTERRUPT_CONTROL:
 679     case PSIHB9_ESB_CI_BASE:
 680     case PSIHB9_ESB_NOTIF_ADDR:
 681     case PSIHB9_IVT_OFFSET:
 682         val = psi->regs[reg];
 683         break;
 684     default:
 685         qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr);
 686     }
 687
 688     return val;
 689 }
 690
 691 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
 692                                   uint64_t val, unsigned size)
 693 {
 694     PnvPsi *psi = PNV_PSI(opaque);
 695     Pnv9Psi *psi9 = PNV9_PSI(psi);
 696     uint32_t reg = PSIHB_REG(addr);
 697     MemoryRegion *sysmem = get_system_memory();
 698
 699     switch (addr) {
 700     case PSIHB9_CR:
 701     case PSIHB9_SEMR:
 702         /* FSP stuff */
 703         break;
 704     case PSIHB9_INTERRUPT_CONTROL:
 705         if (val & PSIHB9_IRQ_RESET) {
 706             device_reset(DEVICE(&psi9->source));
 707         }
 708         psi->regs[reg] = val;
 709         break;
 710
 711     case PSIHB9_ESB_CI_BASE:
 712         if (!(val & PSIHB9_ESB_CI_VALID)) {
 713             if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
 714                 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
 715             }
 716         } else {
 717             if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
 718                 memory_region_add_subregion(sysmem,
 719                                         val & ~PSIHB9_ESB_CI_VALID,
 720                                         &psi9->source.esb_mmio);
 721             }
 722         }
 723         psi->regs[reg] = val;
 724         break;
 725
 726     case PSIHB9_ESB_NOTIF_ADDR:
 727         psi->regs[reg] = val;
 728         break;
 729     case PSIHB9_IVT_OFFSET:
 730         psi->regs[reg] = val;
 731         break;
 732     default:
 733         qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr);
 734     }
 735 }
 736
 737 static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
 738     .read = pnv_psi_p9_mmio_read,
 739     .write = pnv_psi_p9_mmio_write,
 740     .endianness = DEVICE_BIG_ENDIAN,
 741     .valid = {
 742         .min_access_size = 8,
 743         .max_access_size = 8,
 744     },
 745     .impl = {
 746         .min_access_size = 8,
 747         .max_access_size = 8,
 748     },
 749 };
 750
 751 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
 752 {
 753     /* No read are expected */
 754     qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
 755     return -1;
 756 }
 757
 758 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
 759                                 uint64_t val, unsigned size)
 760 {
 761     PnvPsi *psi = PNV_PSI(opaque);
 762
 763     /* XSCOM is only used to set the PSIHB MMIO region */
 764     switch (addr >> 3) {
 765     case PSIHB_XSCOM_BAR:
 766         pnv_psi_set_bar(psi, val);
 767         break;
 768     default:
 769         qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
 770                       addr);
 771     }
 772 }
 773
 774 static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
 775     .read = pnv_psi_p9_xscom_read,
 776     .write = pnv_psi_p9_xscom_write,
 777     .endianness = DEVICE_BIG_ENDIAN,
 778     .valid = {
 779         .min_access_size = 8,
 780         .max_access_size = 8,
 781     },
 782     .impl = {
 783         .min_access_size = 8,
 784         .max_access_size = 8,
 785     }
 786 };
 787
 788 static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
 789 {
 790     uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
 791
 792     if (irq > PSIHB9_NUM_IRQS) {
 793         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
 794         return;
 795     }
 796
 797     if (irq_method & PSIHB9_IRQ_METHOD) {
 798         qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
 799         return;
 800     }
 801
 802     /* Update LSI levels */
 803     if (state) {
 804         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
 805     } else {
 806         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
 807     }
 808
 809     qemu_set_irq(psi->qirqs[irq], state);
 810 }
 811
 812 static void pnv_psi_power9_reset(void *dev)
 813 {
 814     Pnv9Psi *psi = PNV9_PSI(dev);
 815
 816     pnv_psi_reset(dev);
 817
 818     if (memory_region_is_mapped(&psi->source.esb_mmio)) {
 819         memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
 820     }
 821 }
 822
 823 static void pnv_psi_power9_instance_init(Object *obj)
 824 {
 825     Pnv9Psi *psi = PNV9_PSI(obj);
 826
 827     object_initialize_child(obj, "source", &psi->source, sizeof(psi->source),
 828                             TYPE_XIVE_SOURCE, &error_abort, NULL);
 829 }
 830
 831 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
 832 {
 833     PnvPsi *psi = PNV_PSI(dev);
 834     XiveSource *xsrc = &PNV9_PSI(psi)->source;
 835     Error *local_err = NULL;
 836     int i;
 837
 838     /* This is the only device with 4k ESB pages */
 839     object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
 840                             &error_fatal);
 841     object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs",
 842                             &error_fatal);
 843     object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(psi),
 844                                    &error_fatal);
 845     object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
 846     if (local_err) {
 847         error_propagate(errp, local_err);
 848         return;
 849     }
 850
 851     for (i = 0; i < xsrc->nr_irqs; i++) {
 852         xive_source_irq_set_lsi(xsrc, i);
 853     }
 854
 855     psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
 856
 857     /* XSCOM region for PSI registers */
 858     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
 859                 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
 860
 861     /* MMIO region for PSI registers */
 862     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
 863                           "psihb", PNV9_PSIHB_SIZE);
 864
 865     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
 866
 867     qemu_register_reset(pnv_psi_power9_reset, dev);
 868 }
 869
 870 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
 871 {
 872     DeviceClass *dc = DEVICE_CLASS(klass);
 873     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 874     XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
 875
 876     dc->desc    = "PowerNV PSI Controller POWER9";
 877     dc->realize = pnv_psi_power9_realize;
 878
 879     ppc->chip_type  = PNV_CHIP_POWER9;
 880     ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
 881     ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
 882     ppc->bar_mask   = PSIHB9_BAR_MASK;
 883     ppc->irq_set    = pnv_psi_power9_irq_set;
 884
 885     xfc->notify      = pnv_psi_notify;
 886 }
 887
 888 static const TypeInfo pnv_psi_power9_info = {
 889     .name          = TYPE_PNV9_PSI,
 890     .parent        = TYPE_PNV_PSI,
 891     .instance_size = sizeof(Pnv9Psi),
 892     .instance_init = pnv_psi_power9_instance_init,
 893     .class_init    = pnv_psi_power9_class_init,
 894     .interfaces = (InterfaceInfo[]) {
 895             { TYPE_XIVE_NOTIFIER },
 896             { },
 897     },
 898 };
 899
 900 static void pnv_psi_class_init(ObjectClass *klass, void *data)
 901 {
 902     DeviceClass *dc = DEVICE_CLASS(klass);
 903     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 904
 905     xdc->dt_xscom = pnv_psi_dt_xscom;
 906
 907     dc->desc = "PowerNV PSI Controller";
 908     dc->props = pnv_psi_properties;
 909 }
 910
 911 static const TypeInfo pnv_psi_info = {
 912     .name          = TYPE_PNV_PSI,
 913     .parent        = TYPE_SYS_BUS_DEVICE,
 914     .instance_size = sizeof(PnvPsi),
 915     .class_init    = pnv_psi_class_init,
 916     .class_size    = sizeof(PnvPsiClass),
 917     .abstract      = true,
 918     .interfaces    = (InterfaceInfo[]) {
 919         { TYPE_PNV_XSCOM_INTERFACE },
 920         { }
 921     }
 922 };
 923
 924 static void pnv_psi_register_types(void)
 925 {
 926     type_register_static(&pnv_psi_info);
 927     type_register_static(&pnv_psi_power8_info);
 928     type_register_static(&pnv_psi_power9_info);
 929 }
 930
 931 type_init(pnv_psi_register_types);
 932
 933 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
 934 {
 935     PnvPsi *psi = PNV_PSI(psi9);
 936
 937     uint32_t offset =
 938         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
 939
 940     monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
 941                   offset, offset + psi9->source.nr_irqs - 1);
 942     xive_source_pic_print_info(&psi9->source, offset, mon);
 943 }