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Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging
[mirror_qemu.git] / hw / ppc / ppc.c
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu-common.h"
26 #include "cpu.h"
27 #include "hw/hw.h"
28 #include "hw/ppc/ppc.h"
29 #include "hw/ppc/ppc_e500.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/cpus.h"
33 #include "qemu/log.h"
34 #include "qemu/error-report.h"
35 #include "sysemu/kvm.h"
36 #include "kvm_ppc.h"
37 #include "trace.h"
38
39 //#define PPC_DEBUG_IRQ
40 //#define PPC_DEBUG_TB
41
42 #ifdef PPC_DEBUG_IRQ
43 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
44 #else
45 # define LOG_IRQ(...) do { } while (0)
46 #endif
47
48
49 #ifdef PPC_DEBUG_TB
50 # define LOG_TB(...) qemu_log(__VA_ARGS__)
51 #else
52 # define LOG_TB(...) do { } while (0)
53 #endif
54
55 static void cpu_ppc_tb_stop (CPUPPCState *env);
56 static void cpu_ppc_tb_start (CPUPPCState *env);
57
58 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
59 {
60 CPUState *cs = CPU(cpu);
61 CPUPPCState *env = &cpu->env;
62 unsigned int old_pending;
63 bool locked = false;
64
65 /* We may already have the BQL if coming from the reset path */
66 if (!qemu_mutex_iothread_locked()) {
67 locked = true;
68 qemu_mutex_lock_iothread();
69 }
70
71 old_pending = env->pending_interrupts;
72
73 if (level) {
74 env->pending_interrupts |= 1 << n_IRQ;
75 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
76 } else {
77 env->pending_interrupts &= ~(1 << n_IRQ);
78 if (env->pending_interrupts == 0) {
79 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
80 }
81 }
82
83 if (old_pending != env->pending_interrupts) {
84 #ifdef CONFIG_KVM
85 kvmppc_set_interrupt(cpu, n_IRQ, level);
86 #endif
87 }
88
89
90 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
91 "req %08x\n", __func__, env, n_IRQ, level,
92 env->pending_interrupts, CPU(cpu)->interrupt_request);
93
94 if (locked) {
95 qemu_mutex_unlock_iothread();
96 }
97 }
98
99 /* PowerPC 6xx / 7xx internal IRQ controller */
100 static void ppc6xx_set_irq(void *opaque, int pin, int level)
101 {
102 PowerPCCPU *cpu = opaque;
103 CPUPPCState *env = &cpu->env;
104 int cur_level;
105
106 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
107 env, pin, level);
108 cur_level = (env->irq_input_state >> pin) & 1;
109 /* Don't generate spurious events */
110 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
111 CPUState *cs = CPU(cpu);
112
113 switch (pin) {
114 case PPC6xx_INPUT_TBEN:
115 /* Level sensitive - active high */
116 LOG_IRQ("%s: %s the time base\n",
117 __func__, level ? "start" : "stop");
118 if (level) {
119 cpu_ppc_tb_start(env);
120 } else {
121 cpu_ppc_tb_stop(env);
122 }
123 case PPC6xx_INPUT_INT:
124 /* Level sensitive - active high */
125 LOG_IRQ("%s: set the external IRQ state to %d\n",
126 __func__, level);
127 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
128 break;
129 case PPC6xx_INPUT_SMI:
130 /* Level sensitive - active high */
131 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
132 __func__, level);
133 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
134 break;
135 case PPC6xx_INPUT_MCP:
136 /* Negative edge sensitive */
137 /* XXX: TODO: actual reaction may depends on HID0 status
138 * 603/604/740/750: check HID0[EMCP]
139 */
140 if (cur_level == 1 && level == 0) {
141 LOG_IRQ("%s: raise machine check state\n",
142 __func__);
143 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
144 }
145 break;
146 case PPC6xx_INPUT_CKSTP_IN:
147 /* Level sensitive - active low */
148 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
149 /* XXX: Note that the only way to restart the CPU is to reset it */
150 if (level) {
151 LOG_IRQ("%s: stop the CPU\n", __func__);
152 cs->halted = 1;
153 }
154 break;
155 case PPC6xx_INPUT_HRESET:
156 /* Level sensitive - active low */
157 if (level) {
158 LOG_IRQ("%s: reset the CPU\n", __func__);
159 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
160 }
161 break;
162 case PPC6xx_INPUT_SRESET:
163 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
164 __func__, level);
165 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
166 break;
167 default:
168 /* Unknown pin - do nothing */
169 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
170 return;
171 }
172 if (level)
173 env->irq_input_state |= 1 << pin;
174 else
175 env->irq_input_state &= ~(1 << pin);
176 }
177 }
178
179 void ppc6xx_irq_init(PowerPCCPU *cpu)
180 {
181 CPUPPCState *env = &cpu->env;
182
183 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
184 PPC6xx_INPUT_NB);
185 }
186
187 #if defined(TARGET_PPC64)
188 /* PowerPC 970 internal IRQ controller */
189 static void ppc970_set_irq(void *opaque, int pin, int level)
190 {
191 PowerPCCPU *cpu = opaque;
192 CPUPPCState *env = &cpu->env;
193 int cur_level;
194
195 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
196 env, pin, level);
197 cur_level = (env->irq_input_state >> pin) & 1;
198 /* Don't generate spurious events */
199 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
200 CPUState *cs = CPU(cpu);
201
202 switch (pin) {
203 case PPC970_INPUT_INT:
204 /* Level sensitive - active high */
205 LOG_IRQ("%s: set the external IRQ state to %d\n",
206 __func__, level);
207 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
208 break;
209 case PPC970_INPUT_THINT:
210 /* Level sensitive - active high */
211 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
212 level);
213 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
214 break;
215 case PPC970_INPUT_MCP:
216 /* Negative edge sensitive */
217 /* XXX: TODO: actual reaction may depends on HID0 status
218 * 603/604/740/750: check HID0[EMCP]
219 */
220 if (cur_level == 1 && level == 0) {
221 LOG_IRQ("%s: raise machine check state\n",
222 __func__);
223 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
224 }
225 break;
226 case PPC970_INPUT_CKSTP:
227 /* Level sensitive - active low */
228 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
229 if (level) {
230 LOG_IRQ("%s: stop the CPU\n", __func__);
231 cs->halted = 1;
232 } else {
233 LOG_IRQ("%s: restart the CPU\n", __func__);
234 cs->halted = 0;
235 qemu_cpu_kick(cs);
236 }
237 break;
238 case PPC970_INPUT_HRESET:
239 /* Level sensitive - active low */
240 if (level) {
241 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
242 }
243 break;
244 case PPC970_INPUT_SRESET:
245 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
246 __func__, level);
247 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
248 break;
249 case PPC970_INPUT_TBEN:
250 LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
251 level);
252 /* XXX: TODO */
253 break;
254 default:
255 /* Unknown pin - do nothing */
256 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
257 return;
258 }
259 if (level)
260 env->irq_input_state |= 1 << pin;
261 else
262 env->irq_input_state &= ~(1 << pin);
263 }
264 }
265
266 void ppc970_irq_init(PowerPCCPU *cpu)
267 {
268 CPUPPCState *env = &cpu->env;
269
270 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
271 PPC970_INPUT_NB);
272 }
273
274 /* POWER7 internal IRQ controller */
275 static void power7_set_irq(void *opaque, int pin, int level)
276 {
277 PowerPCCPU *cpu = opaque;
278 CPUPPCState *env = &cpu->env;
279
280 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
281 env, pin, level);
282
283 switch (pin) {
284 case POWER7_INPUT_INT:
285 /* Level sensitive - active high */
286 LOG_IRQ("%s: set the external IRQ state to %d\n",
287 __func__, level);
288 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
289 break;
290 default:
291 /* Unknown pin - do nothing */
292 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
293 return;
294 }
295 if (level) {
296 env->irq_input_state |= 1 << pin;
297 } else {
298 env->irq_input_state &= ~(1 << pin);
299 }
300 }
301
302 void ppcPOWER7_irq_init(PowerPCCPU *cpu)
303 {
304 CPUPPCState *env = &cpu->env;
305
306 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
307 POWER7_INPUT_NB);
308 }
309
310 /* POWER9 internal IRQ controller */
311 static void power9_set_irq(void *opaque, int pin, int level)
312 {
313 PowerPCCPU *cpu = opaque;
314 CPUPPCState *env = &cpu->env;
315
316 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
317 env, pin, level);
318
319 switch (pin) {
320 case POWER9_INPUT_INT:
321 /* Level sensitive - active high */
322 LOG_IRQ("%s: set the external IRQ state to %d\n",
323 __func__, level);
324 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
325 break;
326 case POWER9_INPUT_HINT:
327 /* Level sensitive - active high */
328 LOG_IRQ("%s: set the external IRQ state to %d\n",
329 __func__, level);
330 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level);
331 break;
332 default:
333 /* Unknown pin - do nothing */
334 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
335 return;
336 }
337 if (level) {
338 env->irq_input_state |= 1 << pin;
339 } else {
340 env->irq_input_state &= ~(1 << pin);
341 }
342 }
343
344 void ppcPOWER9_irq_init(PowerPCCPU *cpu)
345 {
346 CPUPPCState *env = &cpu->env;
347
348 env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu,
349 POWER9_INPUT_NB);
350 }
351 #endif /* defined(TARGET_PPC64) */
352
353 void ppc40x_core_reset(PowerPCCPU *cpu)
354 {
355 CPUPPCState *env = &cpu->env;
356 target_ulong dbsr;
357
358 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n");
359 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
360 dbsr = env->spr[SPR_40x_DBSR];
361 dbsr &= ~0x00000300;
362 dbsr |= 0x00000100;
363 env->spr[SPR_40x_DBSR] = dbsr;
364 }
365
366 void ppc40x_chip_reset(PowerPCCPU *cpu)
367 {
368 CPUPPCState *env = &cpu->env;
369 target_ulong dbsr;
370
371 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n");
372 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
373 /* XXX: TODO reset all internal peripherals */
374 dbsr = env->spr[SPR_40x_DBSR];
375 dbsr &= ~0x00000300;
376 dbsr |= 0x00000200;
377 env->spr[SPR_40x_DBSR] = dbsr;
378 }
379
380 void ppc40x_system_reset(PowerPCCPU *cpu)
381 {
382 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n");
383 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
384 }
385
386 void store_40x_dbcr0(CPUPPCState *env, uint32_t val)
387 {
388 PowerPCCPU *cpu = ppc_env_get_cpu(env);
389
390 switch ((val >> 28) & 0x3) {
391 case 0x0:
392 /* No action */
393 break;
394 case 0x1:
395 /* Core reset */
396 ppc40x_core_reset(cpu);
397 break;
398 case 0x2:
399 /* Chip reset */
400 ppc40x_chip_reset(cpu);
401 break;
402 case 0x3:
403 /* System reset */
404 ppc40x_system_reset(cpu);
405 break;
406 }
407 }
408
409 /* PowerPC 40x internal IRQ controller */
410 static void ppc40x_set_irq(void *opaque, int pin, int level)
411 {
412 PowerPCCPU *cpu = opaque;
413 CPUPPCState *env = &cpu->env;
414 int cur_level;
415
416 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
417 env, pin, level);
418 cur_level = (env->irq_input_state >> pin) & 1;
419 /* Don't generate spurious events */
420 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
421 CPUState *cs = CPU(cpu);
422
423 switch (pin) {
424 case PPC40x_INPUT_RESET_SYS:
425 if (level) {
426 LOG_IRQ("%s: reset the PowerPC system\n",
427 __func__);
428 ppc40x_system_reset(cpu);
429 }
430 break;
431 case PPC40x_INPUT_RESET_CHIP:
432 if (level) {
433 LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
434 ppc40x_chip_reset(cpu);
435 }
436 break;
437 case PPC40x_INPUT_RESET_CORE:
438 /* XXX: TODO: update DBSR[MRR] */
439 if (level) {
440 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
441 ppc40x_core_reset(cpu);
442 }
443 break;
444 case PPC40x_INPUT_CINT:
445 /* Level sensitive - active high */
446 LOG_IRQ("%s: set the critical IRQ state to %d\n",
447 __func__, level);
448 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
449 break;
450 case PPC40x_INPUT_INT:
451 /* Level sensitive - active high */
452 LOG_IRQ("%s: set the external IRQ state to %d\n",
453 __func__, level);
454 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
455 break;
456 case PPC40x_INPUT_HALT:
457 /* Level sensitive - active low */
458 if (level) {
459 LOG_IRQ("%s: stop the CPU\n", __func__);
460 cs->halted = 1;
461 } else {
462 LOG_IRQ("%s: restart the CPU\n", __func__);
463 cs->halted = 0;
464 qemu_cpu_kick(cs);
465 }
466 break;
467 case PPC40x_INPUT_DEBUG:
468 /* Level sensitive - active high */
469 LOG_IRQ("%s: set the debug pin state to %d\n",
470 __func__, level);
471 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
472 break;
473 default:
474 /* Unknown pin - do nothing */
475 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
476 return;
477 }
478 if (level)
479 env->irq_input_state |= 1 << pin;
480 else
481 env->irq_input_state &= ~(1 << pin);
482 }
483 }
484
485 void ppc40x_irq_init(PowerPCCPU *cpu)
486 {
487 CPUPPCState *env = &cpu->env;
488
489 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
490 cpu, PPC40x_INPUT_NB);
491 }
492
493 /* PowerPC E500 internal IRQ controller */
494 static void ppce500_set_irq(void *opaque, int pin, int level)
495 {
496 PowerPCCPU *cpu = opaque;
497 CPUPPCState *env = &cpu->env;
498 int cur_level;
499
500 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
501 env, pin, level);
502 cur_level = (env->irq_input_state >> pin) & 1;
503 /* Don't generate spurious events */
504 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
505 switch (pin) {
506 case PPCE500_INPUT_MCK:
507 if (level) {
508 LOG_IRQ("%s: reset the PowerPC system\n",
509 __func__);
510 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
511 }
512 break;
513 case PPCE500_INPUT_RESET_CORE:
514 if (level) {
515 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
516 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
517 }
518 break;
519 case PPCE500_INPUT_CINT:
520 /* Level sensitive - active high */
521 LOG_IRQ("%s: set the critical IRQ state to %d\n",
522 __func__, level);
523 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
524 break;
525 case PPCE500_INPUT_INT:
526 /* Level sensitive - active high */
527 LOG_IRQ("%s: set the core IRQ state to %d\n",
528 __func__, level);
529 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
530 break;
531 case PPCE500_INPUT_DEBUG:
532 /* Level sensitive - active high */
533 LOG_IRQ("%s: set the debug pin state to %d\n",
534 __func__, level);
535 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
536 break;
537 default:
538 /* Unknown pin - do nothing */
539 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
540 return;
541 }
542 if (level)
543 env->irq_input_state |= 1 << pin;
544 else
545 env->irq_input_state &= ~(1 << pin);
546 }
547 }
548
549 void ppce500_irq_init(PowerPCCPU *cpu)
550 {
551 CPUPPCState *env = &cpu->env;
552
553 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
554 cpu, PPCE500_INPUT_NB);
555 }
556
557 /* Enable or Disable the E500 EPR capability */
558 void ppce500_set_mpic_proxy(bool enabled)
559 {
560 CPUState *cs;
561
562 CPU_FOREACH(cs) {
563 PowerPCCPU *cpu = POWERPC_CPU(cs);
564
565 cpu->env.mpic_proxy = enabled;
566 if (kvm_enabled()) {
567 kvmppc_set_mpic_proxy(cpu, enabled);
568 }
569 }
570 }
571
572 /*****************************************************************************/
573 /* PowerPC time base and decrementer emulation */
574
575 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
576 {
577 /* TB time in tb periods */
578 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset;
579 }
580
581 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
582 {
583 ppc_tb_t *tb_env = env->tb_env;
584 uint64_t tb;
585
586 if (kvm_enabled()) {
587 return env->spr[SPR_TBL];
588 }
589
590 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
591 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
592
593 return tb;
594 }
595
596 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
597 {
598 ppc_tb_t *tb_env = env->tb_env;
599 uint64_t tb;
600
601 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
602 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
603
604 return tb >> 32;
605 }
606
607 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
608 {
609 if (kvm_enabled()) {
610 return env->spr[SPR_TBU];
611 }
612
613 return _cpu_ppc_load_tbu(env);
614 }
615
616 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
617 int64_t *tb_offsetp, uint64_t value)
618 {
619 *tb_offsetp = value -
620 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
621
622 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
623 __func__, value, *tb_offsetp);
624 }
625
626 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
627 {
628 ppc_tb_t *tb_env = env->tb_env;
629 uint64_t tb;
630
631 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
632 tb &= 0xFFFFFFFF00000000ULL;
633 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
634 &tb_env->tb_offset, tb | (uint64_t)value);
635 }
636
637 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
638 {
639 ppc_tb_t *tb_env = env->tb_env;
640 uint64_t tb;
641
642 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
643 tb &= 0x00000000FFFFFFFFULL;
644 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
645 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
646 }
647
648 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
649 {
650 _cpu_ppc_store_tbu(env, value);
651 }
652
653 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
654 {
655 ppc_tb_t *tb_env = env->tb_env;
656 uint64_t tb;
657
658 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
659 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
660
661 return tb;
662 }
663
664 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
665 {
666 ppc_tb_t *tb_env = env->tb_env;
667 uint64_t tb;
668
669 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
670 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
671
672 return tb >> 32;
673 }
674
675 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
676 {
677 ppc_tb_t *tb_env = env->tb_env;
678 uint64_t tb;
679
680 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
681 tb &= 0xFFFFFFFF00000000ULL;
682 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
683 &tb_env->atb_offset, tb | (uint64_t)value);
684 }
685
686 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
687 {
688 ppc_tb_t *tb_env = env->tb_env;
689 uint64_t tb;
690
691 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
692 tb &= 0x00000000FFFFFFFFULL;
693 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
694 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
695 }
696
697 static void cpu_ppc_tb_stop (CPUPPCState *env)
698 {
699 ppc_tb_t *tb_env = env->tb_env;
700 uint64_t tb, atb, vmclk;
701
702 /* If the time base is already frozen, do nothing */
703 if (tb_env->tb_freq != 0) {
704 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
705 /* Get the time base */
706 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
707 /* Get the alternate time base */
708 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
709 /* Store the time base value (ie compute the current offset) */
710 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
711 /* Store the alternate time base value (compute the current offset) */
712 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
713 /* Set the time base frequency to zero */
714 tb_env->tb_freq = 0;
715 /* Now, the time bases are frozen to tb_offset / atb_offset value */
716 }
717 }
718
719 static void cpu_ppc_tb_start (CPUPPCState *env)
720 {
721 ppc_tb_t *tb_env = env->tb_env;
722 uint64_t tb, atb, vmclk;
723
724 /* If the time base is not frozen, do nothing */
725 if (tb_env->tb_freq == 0) {
726 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
727 /* Get the time base from tb_offset */
728 tb = tb_env->tb_offset;
729 /* Get the alternate time base from atb_offset */
730 atb = tb_env->atb_offset;
731 /* Restore the tb frequency from the decrementer frequency */
732 tb_env->tb_freq = tb_env->decr_freq;
733 /* Store the time base value */
734 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
735 /* Store the alternate time base value */
736 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
737 }
738 }
739
740 bool ppc_decr_clear_on_delivery(CPUPPCState *env)
741 {
742 ppc_tb_t *tb_env = env->tb_env;
743 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL;
744 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED);
745 }
746
747 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
748 {
749 ppc_tb_t *tb_env = env->tb_env;
750 uint32_t decr;
751 int64_t diff;
752
753 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
754 if (diff >= 0) {
755 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
756 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
757 decr = 0;
758 } else {
759 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
760 }
761 LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
762
763 return decr;
764 }
765
766 uint32_t cpu_ppc_load_decr (CPUPPCState *env)
767 {
768 ppc_tb_t *tb_env = env->tb_env;
769
770 if (kvm_enabled()) {
771 return env->spr[SPR_DECR];
772 }
773
774 return _cpu_ppc_load_decr(env, tb_env->decr_next);
775 }
776
777 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
778 {
779 ppc_tb_t *tb_env = env->tb_env;
780
781 return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
782 }
783
784 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
785 {
786 ppc_tb_t *tb_env = env->tb_env;
787 uint64_t diff;
788
789 diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start;
790
791 return tb_env->purr_load +
792 muldiv64(diff, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
793 }
794
795 /* When decrementer expires,
796 * all we need to do is generate or queue a CPU exception
797 */
798 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
799 {
800 /* Raise it */
801 LOG_TB("raise decrementer exception\n");
802 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
803 }
804
805 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu)
806 {
807 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
808 }
809
810 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
811 {
812 CPUPPCState *env = &cpu->env;
813
814 /* Raise it */
815 LOG_TB("raise hv decrementer exception\n");
816
817 /* The architecture specifies that we don't deliver HDEC
818 * interrupts in a PM state. Not only they don't cause a
819 * wakeup but they also get effectively discarded.
820 */
821 if (!env->resume_as_sreset) {
822 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
823 }
824 }
825
826 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu)
827 {
828 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
829 }
830
831 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
832 QEMUTimer *timer,
833 void (*raise_excp)(void *),
834 void (*lower_excp)(PowerPCCPU *),
835 uint32_t decr, uint32_t value)
836 {
837 CPUPPCState *env = &cpu->env;
838 ppc_tb_t *tb_env = env->tb_env;
839 uint64_t now, next;
840
841 LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
842 decr, value);
843
844 if (kvm_enabled()) {
845 /* KVM handles decrementer exceptions, we don't need our own timer */
846 return;
847 }
848
849 /*
850 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC
851 * interrupt.
852 *
853 * If we get a really small DEC value, we can assume that by the time we
854 * handled it we should inject an interrupt already.
855 *
856 * On MSB level based DEC implementations the MSB always means the interrupt
857 * is pending, so raise it on those.
858 *
859 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
860 * an edge interrupt, so raise it here too.
861 */
862 if ((value < 3) ||
863 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && (value & 0x80000000)) ||
864 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && (value & 0x80000000)
865 && !(decr & 0x80000000))) {
866 (*raise_excp)(cpu);
867 return;
868 }
869
870 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
871 if (!(value & 0x80000000) && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) {
872 (*lower_excp)(cpu);
873 }
874
875 /* Calculate the next timer event */
876 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
877 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
878 *nextp = next;
879
880 /* Adjust timer */
881 timer_mod(timer, next);
882 }
883
884 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr,
885 uint32_t value)
886 {
887 ppc_tb_t *tb_env = cpu->env.tb_env;
888
889 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
890 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr,
891 value);
892 }
893
894 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
895 {
896 PowerPCCPU *cpu = ppc_env_get_cpu(env);
897
898 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value);
899 }
900
901 static void cpu_ppc_decr_cb(void *opaque)
902 {
903 PowerPCCPU *cpu = opaque;
904
905 cpu_ppc_decr_excp(cpu);
906 }
907
908 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr,
909 uint32_t value)
910 {
911 ppc_tb_t *tb_env = cpu->env.tb_env;
912
913 if (tb_env->hdecr_timer != NULL) {
914 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
915 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower,
916 hdecr, value);
917 }
918 }
919
920 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
921 {
922 PowerPCCPU *cpu = ppc_env_get_cpu(env);
923
924 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value);
925 }
926
927 static void cpu_ppc_hdecr_cb(void *opaque)
928 {
929 PowerPCCPU *cpu = opaque;
930
931 cpu_ppc_hdecr_excp(cpu);
932 }
933
934 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
935 {
936 ppc_tb_t *tb_env = cpu->env.tb_env;
937
938 tb_env->purr_load = value;
939 tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
940 }
941
942 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
943 {
944 CPUPPCState *env = opaque;
945 PowerPCCPU *cpu = ppc_env_get_cpu(env);
946 ppc_tb_t *tb_env = env->tb_env;
947
948 tb_env->tb_freq = freq;
949 tb_env->decr_freq = freq;
950 /* There is a bug in Linux 2.4 kernels:
951 * if a decrementer exception is pending when it enables msr_ee at startup,
952 * it's not ready to handle it...
953 */
954 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF);
955 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF);
956 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
957 }
958
959 static void timebase_save(PPCTimebase *tb)
960 {
961 uint64_t ticks = cpu_get_host_ticks();
962 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
963
964 if (!first_ppc_cpu->env.tb_env) {
965 error_report("No timebase object");
966 return;
967 }
968
969 /* not used anymore, we keep it for compatibility */
970 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
971 /*
972 * tb_offset is only expected to be changed by QEMU so
973 * there is no need to update it from KVM here
974 */
975 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset;
976 }
977
978 static void timebase_load(PPCTimebase *tb)
979 {
980 CPUState *cpu;
981 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
982 int64_t tb_off_adj, tb_off;
983 unsigned long freq;
984
985 if (!first_ppc_cpu->env.tb_env) {
986 error_report("No timebase object");
987 return;
988 }
989
990 freq = first_ppc_cpu->env.tb_env->tb_freq;
991
992 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks();
993
994 tb_off = first_ppc_cpu->env.tb_env->tb_offset;
995 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off,
996 (tb_off_adj - tb_off) / freq);
997
998 /* Set new offset to all CPUs */
999 CPU_FOREACH(cpu) {
1000 PowerPCCPU *pcpu = POWERPC_CPU(cpu);
1001 pcpu->env.tb_env->tb_offset = tb_off_adj;
1002 #if defined(CONFIG_KVM)
1003 kvm_set_one_reg(cpu, KVM_REG_PPC_TB_OFFSET,
1004 &pcpu->env.tb_env->tb_offset);
1005 #endif
1006 }
1007 }
1008
1009 void cpu_ppc_clock_vm_state_change(void *opaque, int running,
1010 RunState state)
1011 {
1012 PPCTimebase *tb = opaque;
1013
1014 if (running) {
1015 timebase_load(tb);
1016 } else {
1017 timebase_save(tb);
1018 }
1019 }
1020
1021 /*
1022 * When migrating, read the clock just before migration,
1023 * so that the guest clock counts during the events
1024 * between:
1025 *
1026 * * vm_stop()
1027 * *
1028 * * pre_save()
1029 *
1030 * This reduces clock difference on migration from 5s
1031 * to 0.1s (when max_downtime == 5s), because sending the
1032 * final pages of memory (which happens between vm_stop()
1033 * and pre_save()) takes max_downtime.
1034 */
1035 static int timebase_pre_save(void *opaque)
1036 {
1037 PPCTimebase *tb = opaque;
1038
1039 timebase_save(tb);
1040
1041 return 0;
1042 }
1043
1044 const VMStateDescription vmstate_ppc_timebase = {
1045 .name = "timebase",
1046 .version_id = 1,
1047 .minimum_version_id = 1,
1048 .minimum_version_id_old = 1,
1049 .pre_save = timebase_pre_save,
1050 .fields = (VMStateField []) {
1051 VMSTATE_UINT64(guest_timebase, PPCTimebase),
1052 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase),
1053 VMSTATE_END_OF_LIST()
1054 },
1055 };
1056
1057 /* Set up (once) timebase frequency (in Hz) */
1058 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
1059 {
1060 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1061 ppc_tb_t *tb_env;
1062
1063 tb_env = g_malloc0(sizeof(ppc_tb_t));
1064 env->tb_env = tb_env;
1065 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1066 if (env->insns_flags & PPC_SEGMENT_64B) {
1067 /* All Book3S 64bit CPUs implement level based DEC logic */
1068 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
1069 }
1070 /* Create new timer */
1071 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu);
1072 if (env->has_hv_mode) {
1073 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb,
1074 cpu);
1075 } else {
1076 tb_env->hdecr_timer = NULL;
1077 }
1078 cpu_ppc_set_tb_clk(env, freq);
1079
1080 return &cpu_ppc_set_tb_clk;
1081 }
1082
1083 /* Specific helpers for POWER & PowerPC 601 RTC */
1084 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
1085 {
1086 _cpu_ppc_store_tbu(env, value);
1087 }
1088
1089 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
1090 {
1091 return _cpu_ppc_load_tbu(env);
1092 }
1093
1094 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
1095 {
1096 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
1097 }
1098
1099 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
1100 {
1101 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1102 }
1103
1104 /*****************************************************************************/
1105 /* PowerPC 40x timers */
1106
1107 /* PIT, FIT & WDT */
1108 typedef struct ppc40x_timer_t ppc40x_timer_t;
1109 struct ppc40x_timer_t {
1110 uint64_t pit_reload; /* PIT auto-reload value */
1111 uint64_t fit_next; /* Tick for next FIT interrupt */
1112 QEMUTimer *fit_timer;
1113 uint64_t wdt_next; /* Tick for next WDT interrupt */
1114 QEMUTimer *wdt_timer;
1115
1116 /* 405 have the PIT, 440 have a DECR. */
1117 unsigned int decr_excp;
1118 };
1119
1120 /* Fixed interval timer */
1121 static void cpu_4xx_fit_cb (void *opaque)
1122 {
1123 PowerPCCPU *cpu;
1124 CPUPPCState *env;
1125 ppc_tb_t *tb_env;
1126 ppc40x_timer_t *ppc40x_timer;
1127 uint64_t now, next;
1128
1129 env = opaque;
1130 cpu = ppc_env_get_cpu(env);
1131 tb_env = env->tb_env;
1132 ppc40x_timer = tb_env->opaque;
1133 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1134 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
1135 case 0:
1136 next = 1 << 9;
1137 break;
1138 case 1:
1139 next = 1 << 13;
1140 break;
1141 case 2:
1142 next = 1 << 17;
1143 break;
1144 case 3:
1145 next = 1 << 21;
1146 break;
1147 default:
1148 /* Cannot occur, but makes gcc happy */
1149 return;
1150 }
1151 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
1152 if (next == now)
1153 next++;
1154 timer_mod(ppc40x_timer->fit_timer, next);
1155 env->spr[SPR_40x_TSR] |= 1 << 26;
1156 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
1157 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
1158 }
1159 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
1160 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
1161 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1162 }
1163
1164 /* Programmable interval timer */
1165 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
1166 {
1167 ppc40x_timer_t *ppc40x_timer;
1168 uint64_t now, next;
1169
1170 ppc40x_timer = tb_env->opaque;
1171 if (ppc40x_timer->pit_reload <= 1 ||
1172 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
1173 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
1174 /* Stop PIT */
1175 LOG_TB("%s: stop PIT\n", __func__);
1176 timer_del(tb_env->decr_timer);
1177 } else {
1178 LOG_TB("%s: start PIT %016" PRIx64 "\n",
1179 __func__, ppc40x_timer->pit_reload);
1180 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1181 next = now + muldiv64(ppc40x_timer->pit_reload,
1182 NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1183 if (is_excp)
1184 next += tb_env->decr_next - now;
1185 if (next == now)
1186 next++;
1187 timer_mod(tb_env->decr_timer, next);
1188 tb_env->decr_next = next;
1189 }
1190 }
1191
1192 static void cpu_4xx_pit_cb (void *opaque)
1193 {
1194 PowerPCCPU *cpu;
1195 CPUPPCState *env;
1196 ppc_tb_t *tb_env;
1197 ppc40x_timer_t *ppc40x_timer;
1198
1199 env = opaque;
1200 cpu = ppc_env_get_cpu(env);
1201 tb_env = env->tb_env;
1202 ppc40x_timer = tb_env->opaque;
1203 env->spr[SPR_40x_TSR] |= 1 << 27;
1204 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
1205 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
1206 }
1207 start_stop_pit(env, tb_env, 1);
1208 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
1209 "%016" PRIx64 "\n", __func__,
1210 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
1211 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
1212 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
1213 ppc40x_timer->pit_reload);
1214 }
1215
1216 /* Watchdog timer */
1217 static void cpu_4xx_wdt_cb (void *opaque)
1218 {
1219 PowerPCCPU *cpu;
1220 CPUPPCState *env;
1221 ppc_tb_t *tb_env;
1222 ppc40x_timer_t *ppc40x_timer;
1223 uint64_t now, next;
1224
1225 env = opaque;
1226 cpu = ppc_env_get_cpu(env);
1227 tb_env = env->tb_env;
1228 ppc40x_timer = tb_env->opaque;
1229 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1230 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
1231 case 0:
1232 next = 1 << 17;
1233 break;
1234 case 1:
1235 next = 1 << 21;
1236 break;
1237 case 2:
1238 next = 1 << 25;
1239 break;
1240 case 3:
1241 next = 1 << 29;
1242 break;
1243 default:
1244 /* Cannot occur, but makes gcc happy */
1245 return;
1246 }
1247 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1248 if (next == now)
1249 next++;
1250 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
1251 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1252 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
1253 case 0x0:
1254 case 0x1:
1255 timer_mod(ppc40x_timer->wdt_timer, next);
1256 ppc40x_timer->wdt_next = next;
1257 env->spr[SPR_40x_TSR] |= 1U << 31;
1258 break;
1259 case 0x2:
1260 timer_mod(ppc40x_timer->wdt_timer, next);
1261 ppc40x_timer->wdt_next = next;
1262 env->spr[SPR_40x_TSR] |= 1 << 30;
1263 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1264 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1265 }
1266 break;
1267 case 0x3:
1268 env->spr[SPR_40x_TSR] &= ~0x30000000;
1269 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1270 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1271 case 0x0:
1272 /* No reset */
1273 break;
1274 case 0x1: /* Core reset */
1275 ppc40x_core_reset(cpu);
1276 break;
1277 case 0x2: /* Chip reset */
1278 ppc40x_chip_reset(cpu);
1279 break;
1280 case 0x3: /* System reset */
1281 ppc40x_system_reset(cpu);
1282 break;
1283 }
1284 }
1285 }
1286
1287 void store_40x_pit (CPUPPCState *env, target_ulong val)
1288 {
1289 ppc_tb_t *tb_env;
1290 ppc40x_timer_t *ppc40x_timer;
1291
1292 tb_env = env->tb_env;
1293 ppc40x_timer = tb_env->opaque;
1294 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
1295 ppc40x_timer->pit_reload = val;
1296 start_stop_pit(env, tb_env, 0);
1297 }
1298
1299 target_ulong load_40x_pit (CPUPPCState *env)
1300 {
1301 return cpu_ppc_load_decr(env);
1302 }
1303
1304 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1305 {
1306 CPUPPCState *env = opaque;
1307 ppc_tb_t *tb_env = env->tb_env;
1308
1309 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
1310 freq);
1311 tb_env->tb_freq = freq;
1312 tb_env->decr_freq = freq;
1313 /* XXX: we should also update all timers */
1314 }
1315
1316 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1317 unsigned int decr_excp)
1318 {
1319 ppc_tb_t *tb_env;
1320 ppc40x_timer_t *ppc40x_timer;
1321
1322 tb_env = g_malloc0(sizeof(ppc_tb_t));
1323 env->tb_env = tb_env;
1324 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1325 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
1326 tb_env->tb_freq = freq;
1327 tb_env->decr_freq = freq;
1328 tb_env->opaque = ppc40x_timer;
1329 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1330 if (ppc40x_timer != NULL) {
1331 /* We use decr timer for PIT */
1332 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env);
1333 ppc40x_timer->fit_timer =
1334 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env);
1335 ppc40x_timer->wdt_timer =
1336 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env);
1337 ppc40x_timer->decr_excp = decr_excp;
1338 }
1339
1340 return &ppc_40x_set_tb_clk;
1341 }
1342
1343 /*****************************************************************************/
1344 /* Embedded PowerPC Device Control Registers */
1345 typedef struct ppc_dcrn_t ppc_dcrn_t;
1346 struct ppc_dcrn_t {
1347 dcr_read_cb dcr_read;
1348 dcr_write_cb dcr_write;
1349 void *opaque;
1350 };
1351
1352 /* XXX: on 460, DCR addresses are 32 bits wide,
1353 * using DCRIPR to get the 22 upper bits of the DCR address
1354 */
1355 #define DCRN_NB 1024
1356 struct ppc_dcr_t {
1357 ppc_dcrn_t dcrn[DCRN_NB];
1358 int (*read_error)(int dcrn);
1359 int (*write_error)(int dcrn);
1360 };
1361
1362 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1363 {
1364 ppc_dcrn_t *dcr;
1365
1366 if (dcrn < 0 || dcrn >= DCRN_NB)
1367 goto error;
1368 dcr = &dcr_env->dcrn[dcrn];
1369 if (dcr->dcr_read == NULL)
1370 goto error;
1371 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1372
1373 return 0;
1374
1375 error:
1376 if (dcr_env->read_error != NULL)
1377 return (*dcr_env->read_error)(dcrn);
1378
1379 return -1;
1380 }
1381
1382 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1383 {
1384 ppc_dcrn_t *dcr;
1385
1386 if (dcrn < 0 || dcrn >= DCRN_NB)
1387 goto error;
1388 dcr = &dcr_env->dcrn[dcrn];
1389 if (dcr->dcr_write == NULL)
1390 goto error;
1391 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1392
1393 return 0;
1394
1395 error:
1396 if (dcr_env->write_error != NULL)
1397 return (*dcr_env->write_error)(dcrn);
1398
1399 return -1;
1400 }
1401
1402 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1403 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1404 {
1405 ppc_dcr_t *dcr_env;
1406 ppc_dcrn_t *dcr;
1407
1408 dcr_env = env->dcr_env;
1409 if (dcr_env == NULL)
1410 return -1;
1411 if (dcrn < 0 || dcrn >= DCRN_NB)
1412 return -1;
1413 dcr = &dcr_env->dcrn[dcrn];
1414 if (dcr->opaque != NULL ||
1415 dcr->dcr_read != NULL ||
1416 dcr->dcr_write != NULL)
1417 return -1;
1418 dcr->opaque = opaque;
1419 dcr->dcr_read = dcr_read;
1420 dcr->dcr_write = dcr_write;
1421
1422 return 0;
1423 }
1424
1425 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1426 int (*write_error)(int dcrn))
1427 {
1428 ppc_dcr_t *dcr_env;
1429
1430 dcr_env = g_malloc0(sizeof(ppc_dcr_t));
1431 dcr_env->read_error = read_error;
1432 dcr_env->write_error = write_error;
1433 env->dcr_env = dcr_env;
1434
1435 return 0;
1436 }
1437
1438 /*****************************************************************************/
1439 /* Debug port */
1440 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1441 {
1442 addr &= 0xF;
1443 switch (addr) {
1444 case 0:
1445 printf("%c", val);
1446 break;
1447 case 1:
1448 printf("\n");
1449 fflush(stdout);
1450 break;
1451 case 2:
1452 printf("Set loglevel to %04" PRIx32 "\n", val);
1453 qemu_set_log(val | 0x100);
1454 break;
1455 }
1456 }
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