hw/ppc/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/ppc/ppc.h"
  26 #include "ppc405.h"
  27 #include "hw/timer/m48t59.h"
  28 #include "hw/block/flash.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/qtest.h"
  31 #include "block/block.h"
  32 #include "hw/boards.h"
  33 #include "qemu/log.h"
  34 #include "qemu/error-report.h"
  35 #include "hw/loader.h"
  36 #include "sysemu/blockdev.h"
  37 #include "exec/address-spaces.h"
  38
  39 #define BIOS_FILENAME "ppc405_rom.bin"
  40 #define BIOS_SIZE (2048 * 1024)
  41
  42 #define KERNEL_LOAD_ADDR 0x00000000
  43 #define INITRD_LOAD_ADDR 0x01800000
  44
  45 #define USE_FLASH_BIOS
  46
  47 //#define DEBUG_BOARD_INIT
  48
  49 /*****************************************************************************/
  50 /* PPC405EP reference board (IBM) */
  51 /* Standalone board with:
  52  * - PowerPC 405EP CPU
  53  * - SDRAM (0x00000000)
  54  * - Flash (0xFFF80000)
  55  * - SRAM  (0xFFF00000)
  56  * - NVRAM (0xF0000000)
  57  * - FPGA  (0xF0300000)
  58  */
  59 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  60 struct ref405ep_fpga_t {
  61     uint8_t reg0;
  62     uint8_t reg1;
  63 };
  64
  65 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
  66 {
  67     ref405ep_fpga_t *fpga;
  68     uint32_t ret;
  69
  70     fpga = opaque;
  71     switch (addr) {
  72     case 0x0:
  73         ret = fpga->reg0;
  74         break;
  75     case 0x1:
  76         ret = fpga->reg1;
  77         break;
  78     default:
  79         ret = 0;
  80         break;
  81     }
  82
  83     return ret;
  84 }
  85
  86 static void ref405ep_fpga_writeb (void *opaque,
  87                                   hwaddr addr, uint32_t value)
  88 {
  89     ref405ep_fpga_t *fpga;
  90
  91     fpga = opaque;
  92     switch (addr) {
  93     case 0x0:
  94         /* Read only */
  95         break;
  96     case 0x1:
  97         fpga->reg1 = value;
  98         break;
  99     default:
 100         break;
 101     }
 102 }
 103
 104 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
 105 {
 106     uint32_t ret;
 107
 108     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 109     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 110
 111     return ret;
 112 }
 113
 114 static void ref405ep_fpga_writew (void *opaque,
 115                                   hwaddr addr, uint32_t value)
 116 {
 117     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 118     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 119 }
 120
 121 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
 122 {
 123     uint32_t ret;
 124
 125     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 126     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 127     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 128     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 129
 130     return ret;
 131 }
 132
 133 static void ref405ep_fpga_writel (void *opaque,
 134                                   hwaddr addr, uint32_t value)
 135 {
 136     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 137     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 138     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 139     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 140 }
 141
 142 static const MemoryRegionOps ref405ep_fpga_ops = {
 143     .old_mmio = {
 144         .read = {
 145             ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,
 146         },
 147         .write = {
 148             ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,
 149         },
 150     },
 151     .endianness = DEVICE_NATIVE_ENDIAN,
 152 };
 153
 154 static void ref405ep_fpga_reset (void *opaque)
 155 {
 156     ref405ep_fpga_t *fpga;
 157
 158     fpga = opaque;
 159     fpga->reg0 = 0x00;
 160     fpga->reg1 = 0x0F;
 161 }
 162
 163 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
 164 {
 165     ref405ep_fpga_t *fpga;
 166     MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
 167
 168     fpga = g_malloc0(sizeof(ref405ep_fpga_t));
 169     memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
 170                           "fpga", 0x00000100);
 171     memory_region_add_subregion(sysmem, base, fpga_memory);
 172     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 173 }
 174
 175 static void ref405ep_init(MachineState *machine)
 176 {
 177     ram_addr_t ram_size = machine->ram_size;
 178     const char *kernel_filename = machine->kernel_filename;
 179     const char *kernel_cmdline = machine->kernel_cmdline;
 180     const char *initrd_filename = machine->initrd_filename;
 181     char *filename;
 182     ppc4xx_bd_info_t bd;
 183     CPUPPCState *env;
 184     qemu_irq *pic;
 185     MemoryRegion *bios;
 186     MemoryRegion *sram = g_new(MemoryRegion, 1);
 187     ram_addr_t bdloc;
 188     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 189     hwaddr ram_bases[2], ram_sizes[2];
 190     target_ulong sram_size;
 191     long bios_size;
 192     //int phy_addr = 0;
 193     //static int phy_addr = 1;
 194     target_ulong kernel_base, initrd_base;
 195     long kernel_size, initrd_size;
 196     int linux_boot;
 197     int fl_idx, fl_sectors, len;
 198     DriveInfo *dinfo;
 199     MemoryRegion *sysmem = get_system_memory();
 200
 201     /* XXX: fix this */
 202     memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
 203                                          0x08000000);
 204     ram_bases[0] = 0;
 205     ram_sizes[0] = 0x08000000;
 206     memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
 207     ram_bases[1] = 0x00000000;
 208     ram_sizes[1] = 0x00000000;
 209     ram_size = 128 * 1024 * 1024;
 210 #ifdef DEBUG_BOARD_INIT
 211     printf("%s: register cpu\n", __func__);
 212 #endif
 213     env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 214                         33333333, &pic, kernel_filename == NULL ? 0 : 1);
 215     /* allocate SRAM */
 216     sram_size = 512 * 1024;
 217     memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, &error_abort);
 218     vmstate_register_ram_global(sram);
 219     memory_region_add_subregion(sysmem, 0xFFF00000, sram);
 220     /* allocate and load BIOS */
 221 #ifdef DEBUG_BOARD_INIT
 222     printf("%s: register BIOS\n", __func__);
 223 #endif
 224     fl_idx = 0;
 225 #ifdef USE_FLASH_BIOS
 226     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 227     if (dinfo) {
 228         bios_size = bdrv_getlength(dinfo->bdrv);
 229         fl_sectors = (bios_size + 65535) >> 16;
 230 #ifdef DEBUG_BOARD_INIT
 231         printf("Register parallel flash %d size %lx"
 232                " at addr %lx '%s' %d\n",
 233                fl_idx, bios_size, -bios_size,
 234                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 235 #endif
 236         pflash_cfi02_register((uint32_t)(-bios_size),
 237                               NULL, "ef405ep.bios", bios_size,
 238                               dinfo->bdrv, 65536, fl_sectors, 1,
 239                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 240                               1);
 241         fl_idx++;
 242     } else
 243 #endif
 244     {
 245 #ifdef DEBUG_BOARD_INIT
 246         printf("Load BIOS from file\n");
 247 #endif
 248         bios = g_new(MemoryRegion, 1);
 249         memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
 250                                &error_abort);
 251         vmstate_register_ram_global(bios);
 252
 253         if (bios_name == NULL)
 254             bios_name = BIOS_FILENAME;
 255         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 256         if (filename) {
 257             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 258             g_free(filename);
 259             if (bios_size < 0 || bios_size > BIOS_SIZE) {
 260                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 261                 exit(1);
 262             }
 263             bios_size = (bios_size + 0xfff) & ~0xfff;
 264             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 265         } else if (!qtest_enabled() || kernel_filename != NULL) {
 266             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 267             exit(1);
 268         } else {
 269             /* Avoid an uninitialized variable warning */
 270             bios_size = -1;
 271         }
 272         memory_region_set_readonly(bios, true);
 273     }
 274     /* Register FPGA */
 275 #ifdef DEBUG_BOARD_INIT
 276     printf("%s: register FPGA\n", __func__);
 277 #endif
 278     ref405ep_fpga_init(sysmem, 0xF0300000);
 279     /* Register NVRAM */
 280 #ifdef DEBUG_BOARD_INIT
 281     printf("%s: register NVRAM\n", __func__);
 282 #endif
 283     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 284     /* Load kernel */
 285     linux_boot = (kernel_filename != NULL);
 286     if (linux_boot) {
 287 #ifdef DEBUG_BOARD_INIT
 288         printf("%s: load kernel\n", __func__);
 289 #endif
 290         memset(&bd, 0, sizeof(bd));
 291         bd.bi_memstart = 0x00000000;
 292         bd.bi_memsize = ram_size;
 293         bd.bi_flashstart = -bios_size;
 294         bd.bi_flashsize = -bios_size;
 295         bd.bi_flashoffset = 0;
 296         bd.bi_sramstart = 0xFFF00000;
 297         bd.bi_sramsize = sram_size;
 298         bd.bi_bootflags = 0;
 299         bd.bi_intfreq = 133333333;
 300         bd.bi_busfreq = 33333333;
 301         bd.bi_baudrate = 115200;
 302         bd.bi_s_version[0] = 'Q';
 303         bd.bi_s_version[1] = 'M';
 304         bd.bi_s_version[2] = 'U';
 305         bd.bi_s_version[3] = '\0';
 306         bd.bi_r_version[0] = 'Q';
 307         bd.bi_r_version[1] = 'E';
 308         bd.bi_r_version[2] = 'M';
 309         bd.bi_r_version[3] = 'U';
 310         bd.bi_r_version[4] = '\0';
 311         bd.bi_procfreq = 133333333;
 312         bd.bi_plb_busfreq = 33333333;
 313         bd.bi_pci_busfreq = 33333333;
 314         bd.bi_opbfreq = 33333333;
 315         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 316         env->gpr[3] = bdloc;
 317         kernel_base = KERNEL_LOAD_ADDR;
 318         /* now we can load the kernel */
 319         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 320                                           ram_size - kernel_base);
 321         if (kernel_size < 0) {
 322             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 323                     kernel_filename);
 324             exit(1);
 325         }
 326         printf("Load kernel size %ld at " TARGET_FMT_lx,
 327                kernel_size, kernel_base);
 328         /* load initrd */
 329         if (initrd_filename) {
 330             initrd_base = INITRD_LOAD_ADDR;
 331             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 332                                               ram_size - initrd_base);
 333             if (initrd_size < 0) {
 334                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 335                         initrd_filename);
 336                 exit(1);
 337             }
 338         } else {
 339             initrd_base = 0;
 340             initrd_size = 0;
 341         }
 342         env->gpr[4] = initrd_base;
 343         env->gpr[5] = initrd_size;
 344         if (kernel_cmdline != NULL) {
 345             len = strlen(kernel_cmdline);
 346             bdloc -= ((len + 255) & ~255);
 347             cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
 348             env->gpr[6] = bdloc;
 349             env->gpr[7] = bdloc + len;
 350         } else {
 351             env->gpr[6] = 0;
 352             env->gpr[7] = 0;
 353         }
 354         env->nip = KERNEL_LOAD_ADDR;
 355     } else {
 356         kernel_base = 0;
 357         kernel_size = 0;
 358         initrd_base = 0;
 359         initrd_size = 0;
 360         bdloc = 0;
 361     }
 362 #ifdef DEBUG_BOARD_INIT
 363     printf("bdloc " RAM_ADDR_FMT "\n", bdloc);
 364     printf("%s: Done\n", __func__);
 365 #endif
 366 }
 367
 368 static QEMUMachine ref405ep_machine = {
 369     .name = "ref405ep",
 370     .desc = "ref405ep",
 371     .init = ref405ep_init,
 372 };
 373
 374 /*****************************************************************************/
 375 /* AMCC Taihu evaluation board */
 376 /* - PowerPC 405EP processor
 377  * - SDRAM               128 MB at 0x00000000
 378  * - Boot flash          2 MB   at 0xFFE00000
 379  * - Application flash   32 MB  at 0xFC000000
 380  * - 2 serial ports
 381  * - 2 ethernet PHY
 382  * - 1 USB 1.1 device    0x50000000
 383  * - 1 LCD display       0x50100000
 384  * - 1 CPLD              0x50100000
 385  * - 1 I2C EEPROM
 386  * - 1 I2C thermal sensor
 387  * - a set of LEDs
 388  * - bit-bang SPI port using GPIOs
 389  * - 1 EBC interface connector 0 0x50200000
 390  * - 1 cardbus controller + expansion slot.
 391  * - 1 PCI expansion slot.
 392  */
 393 typedef struct taihu_cpld_t taihu_cpld_t;
 394 struct taihu_cpld_t {
 395     uint8_t reg0;
 396     uint8_t reg1;
 397 };
 398
 399 static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
 400 {
 401     taihu_cpld_t *cpld;
 402     uint32_t ret;
 403
 404     cpld = opaque;
 405     switch (addr) {
 406     case 0x0:
 407         ret = cpld->reg0;
 408         break;
 409     case 0x1:
 410         ret = cpld->reg1;
 411         break;
 412     default:
 413         ret = 0;
 414         break;
 415     }
 416
 417     return ret;
 418 }
 419
 420 static void taihu_cpld_writeb (void *opaque,
 421                                hwaddr addr, uint32_t value)
 422 {
 423     taihu_cpld_t *cpld;
 424
 425     cpld = opaque;
 426     switch (addr) {
 427     case 0x0:
 428         /* Read only */
 429         break;
 430     case 0x1:
 431         cpld->reg1 = value;
 432         break;
 433     default:
 434         break;
 435     }
 436 }
 437
 438 static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr)
 439 {
 440     uint32_t ret;
 441
 442     ret = taihu_cpld_readb(opaque, addr) << 8;
 443     ret |= taihu_cpld_readb(opaque, addr + 1);
 444
 445     return ret;
 446 }
 447
 448 static void taihu_cpld_writew (void *opaque,
 449                                hwaddr addr, uint32_t value)
 450 {
 451     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 452     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 453 }
 454
 455 static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr)
 456 {
 457     uint32_t ret;
 458
 459     ret = taihu_cpld_readb(opaque, addr) << 24;
 460     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 461     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 462     ret |= taihu_cpld_readb(opaque, addr + 3);
 463
 464     return ret;
 465 }
 466
 467 static void taihu_cpld_writel (void *opaque,
 468                                hwaddr addr, uint32_t value)
 469 {
 470     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 471     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 472     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 473     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 474 }
 475
 476 static const MemoryRegionOps taihu_cpld_ops = {
 477     .old_mmio = {
 478         .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, },
 479         .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, },
 480     },
 481     .endianness = DEVICE_NATIVE_ENDIAN,
 482 };
 483
 484 static void taihu_cpld_reset (void *opaque)
 485 {
 486     taihu_cpld_t *cpld;
 487
 488     cpld = opaque;
 489     cpld->reg0 = 0x01;
 490     cpld->reg1 = 0x80;
 491 }
 492
 493 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
 494 {
 495     taihu_cpld_t *cpld;
 496     MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
 497
 498     cpld = g_malloc0(sizeof(taihu_cpld_t));
 499     memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
 500     memory_region_add_subregion(sysmem, base, cpld_memory);
 501     qemu_register_reset(&taihu_cpld_reset, cpld);
 502 }
 503
 504 static void taihu_405ep_init(MachineState *machine)
 505 {
 506     ram_addr_t ram_size = machine->ram_size;
 507     const char *kernel_filename = machine->kernel_filename;
 508     const char *initrd_filename = machine->initrd_filename;
 509     char *filename;
 510     qemu_irq *pic;
 511     MemoryRegion *sysmem = get_system_memory();
 512     MemoryRegion *bios;
 513     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 514     MemoryRegion *ram = g_malloc0(sizeof(*ram));
 515     hwaddr ram_bases[2], ram_sizes[2];
 516     long bios_size;
 517     target_ulong kernel_base, initrd_base;
 518     long kernel_size, initrd_size;
 519     int linux_boot;
 520     int fl_idx, fl_sectors;
 521     DriveInfo *dinfo;
 522
 523     /* RAM is soldered to the board so the size cannot be changed */
 524     ram_size = 0x08000000;
 525     memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
 526                                          ram_size);
 527
 528     ram_bases[0] = 0;
 529     ram_sizes[0] = 0x04000000;
 530     memory_region_init_alias(&ram_memories[0], NULL,
 531                              "taihu_405ep.ram-0", ram, ram_bases[0],
 532                              ram_sizes[0]);
 533     ram_bases[1] = 0x04000000;
 534     ram_sizes[1] = 0x04000000;
 535     memory_region_init_alias(&ram_memories[1], NULL,
 536                              "taihu_405ep.ram-1", ram, ram_bases[1],
 537                              ram_sizes[1]);
 538 #ifdef DEBUG_BOARD_INIT
 539     printf("%s: register cpu\n", __func__);
 540 #endif
 541     ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 542                   33333333, &pic, kernel_filename == NULL ? 0 : 1);
 543     /* allocate and load BIOS */
 544 #ifdef DEBUG_BOARD_INIT
 545     printf("%s: register BIOS\n", __func__);
 546 #endif
 547     fl_idx = 0;
 548 #if defined(USE_FLASH_BIOS)
 549     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 550     if (dinfo) {
 551         bios_size = bdrv_getlength(dinfo->bdrv);
 552         /* XXX: should check that size is 2MB */
 553         //        bios_size = 2 * 1024 * 1024;
 554         fl_sectors = (bios_size + 65535) >> 16;
 555 #ifdef DEBUG_BOARD_INIT
 556         printf("Register parallel flash %d size %lx"
 557                " at addr %lx '%s' %d\n",
 558                fl_idx, bios_size, -bios_size,
 559                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 560 #endif
 561         pflash_cfi02_register((uint32_t)(-bios_size),
 562                               NULL, "taihu_405ep.bios", bios_size,
 563                               dinfo->bdrv, 65536, fl_sectors, 1,
 564                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 565                               1);
 566         fl_idx++;
 567     } else
 568 #endif
 569     {
 570 #ifdef DEBUG_BOARD_INIT
 571         printf("Load BIOS from file\n");
 572 #endif
 573         if (bios_name == NULL)
 574             bios_name = BIOS_FILENAME;
 575         bios = g_new(MemoryRegion, 1);
 576         memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
 577                                &error_abort);
 578         vmstate_register_ram_global(bios);
 579         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 580         if (filename) {
 581             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 582             g_free(filename);
 583             if (bios_size < 0 || bios_size > BIOS_SIZE) {
 584                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 585                 exit(1);
 586             }
 587             bios_size = (bios_size + 0xfff) & ~0xfff;
 588             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 589         } else if (!qtest_enabled()) {
 590             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 591             exit(1);
 592         }
 593         memory_region_set_readonly(bios, true);
 594     }
 595     /* Register Linux flash */
 596     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 597     if (dinfo) {
 598         bios_size = bdrv_getlength(dinfo->bdrv);
 599         /* XXX: should check that size is 32MB */
 600         bios_size = 32 * 1024 * 1024;
 601         fl_sectors = (bios_size + 65535) >> 16;
 602 #ifdef DEBUG_BOARD_INIT
 603         printf("Register parallel flash %d size %lx"
 604                " at addr " TARGET_FMT_lx " '%s'\n",
 605                fl_idx, bios_size, (target_ulong)0xfc000000,
 606                bdrv_get_device_name(dinfo->bdrv));
 607 #endif
 608         pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
 609                               dinfo->bdrv, 65536, fl_sectors, 1,
 610                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 611                               1);
 612         fl_idx++;
 613     }
 614     /* Register CLPD & LCD display */
 615 #ifdef DEBUG_BOARD_INIT
 616     printf("%s: register CPLD\n", __func__);
 617 #endif
 618     taihu_cpld_init(sysmem, 0x50100000);
 619     /* Load kernel */
 620     linux_boot = (kernel_filename != NULL);
 621     if (linux_boot) {
 622 #ifdef DEBUG_BOARD_INIT
 623         printf("%s: load kernel\n", __func__);
 624 #endif
 625         kernel_base = KERNEL_LOAD_ADDR;
 626         /* now we can load the kernel */
 627         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 628                                           ram_size - kernel_base);
 629         if (kernel_size < 0) {
 630             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 631                     kernel_filename);
 632             exit(1);
 633         }
 634         /* load initrd */
 635         if (initrd_filename) {
 636             initrd_base = INITRD_LOAD_ADDR;
 637             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 638                                               ram_size - initrd_base);
 639             if (initrd_size < 0) {
 640                 fprintf(stderr,
 641                         "qemu: could not load initial ram disk '%s'\n",
 642                         initrd_filename);
 643                 exit(1);
 644             }
 645         } else {
 646             initrd_base = 0;
 647             initrd_size = 0;
 648         }
 649     } else {
 650         kernel_base = 0;
 651         kernel_size = 0;
 652         initrd_base = 0;
 653         initrd_size = 0;
 654     }
 655 #ifdef DEBUG_BOARD_INIT
 656     printf("%s: Done\n", __func__);
 657 #endif
 658 }
 659
 660 static QEMUMachine taihu_machine = {
 661     .name = "taihu",
 662     .desc = "taihu",
 663     .init = taihu_405ep_init,
 664 };
 665
 666 static void ppc405_machine_init(void)
 667 {
 668     qemu_register_machine(&ref405ep_machine);
 669     qemu_register_machine(&taihu_machine);
 670 }
 671
 672 machine_init(ppc405_machine_init);