hw/ppc/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/ppc/ppc.h"
  27 #include "ppc405.h"
  28 #include "hw/timer/m48t59.h"
  29 #include "hw/block/flash.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/qtest.h"
  32 #include "sysemu/block-backend.h"
  33 #include "hw/boards.h"
  34 #include "qemu/log.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/loader.h"
  37 #include "sysemu/block-backend.h"
  38 #include "sysemu/blockdev.h"
  39 #include "exec/address-spaces.h"
  40
  41 #define BIOS_FILENAME "ppc405_rom.bin"
  42 #define BIOS_SIZE (2048 * 1024)
  43
  44 #define KERNEL_LOAD_ADDR 0x00000000
  45 #define INITRD_LOAD_ADDR 0x01800000
  46
  47 #define USE_FLASH_BIOS
  48
  49 //#define DEBUG_BOARD_INIT
  50
  51 /*****************************************************************************/
  52 /* PPC405EP reference board (IBM) */
  53 /* Standalone board with:
  54  * - PowerPC 405EP CPU
  55  * - SDRAM (0x00000000)
  56  * - Flash (0xFFF80000)
  57  * - SRAM  (0xFFF00000)
  58  * - NVRAM (0xF0000000)
  59  * - FPGA  (0xF0300000)
  60  */
  61 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  62 struct ref405ep_fpga_t {
  63     uint8_t reg0;
  64     uint8_t reg1;
  65 };
  66
  67 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
  68 {
  69     ref405ep_fpga_t *fpga;
  70     uint32_t ret;
  71
  72     fpga = opaque;
  73     switch (addr) {
  74     case 0x0:
  75         ret = fpga->reg0;
  76         break;
  77     case 0x1:
  78         ret = fpga->reg1;
  79         break;
  80     default:
  81         ret = 0;
  82         break;
  83     }
  84
  85     return ret;
  86 }
  87
  88 static void ref405ep_fpga_writeb (void *opaque,
  89                                   hwaddr addr, uint32_t value)
  90 {
  91     ref405ep_fpga_t *fpga;
  92
  93     fpga = opaque;
  94     switch (addr) {
  95     case 0x0:
  96         /* Read only */
  97         break;
  98     case 0x1:
  99         fpga->reg1 = value;
 100         break;
 101     default:
 102         break;
 103     }
 104 }
 105
 106 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
 107 {
 108     uint32_t ret;
 109
 110     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 111     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 112
 113     return ret;
 114 }
 115
 116 static void ref405ep_fpga_writew (void *opaque,
 117                                   hwaddr addr, uint32_t value)
 118 {
 119     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 120     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 121 }
 122
 123 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
 124 {
 125     uint32_t ret;
 126
 127     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 128     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 129     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 130     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 131
 132     return ret;
 133 }
 134
 135 static void ref405ep_fpga_writel (void *opaque,
 136                                   hwaddr addr, uint32_t value)
 137 {
 138     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 139     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 140     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 141     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 142 }
 143
 144 static const MemoryRegionOps ref405ep_fpga_ops = {
 145     .old_mmio = {
 146         .read = {
 147             ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,
 148         },
 149         .write = {
 150             ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,
 151         },
 152     },
 153     .endianness = DEVICE_NATIVE_ENDIAN,
 154 };
 155
 156 static void ref405ep_fpga_reset (void *opaque)
 157 {
 158     ref405ep_fpga_t *fpga;
 159
 160     fpga = opaque;
 161     fpga->reg0 = 0x00;
 162     fpga->reg1 = 0x0F;
 163 }
 164
 165 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
 166 {
 167     ref405ep_fpga_t *fpga;
 168     MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
 169
 170     fpga = g_malloc0(sizeof(ref405ep_fpga_t));
 171     memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
 172                           "fpga", 0x00000100);
 173     memory_region_add_subregion(sysmem, base, fpga_memory);
 174     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 175 }
 176
 177 static void ref405ep_init(MachineState *machine)
 178 {
 179     ram_addr_t ram_size = machine->ram_size;
 180     const char *kernel_filename = machine->kernel_filename;
 181     const char *kernel_cmdline = machine->kernel_cmdline;
 182     const char *initrd_filename = machine->initrd_filename;
 183     char *filename;
 184     ppc4xx_bd_info_t bd;
 185     CPUPPCState *env;
 186     qemu_irq *pic;
 187     MemoryRegion *bios;
 188     MemoryRegion *sram = g_new(MemoryRegion, 1);
 189     ram_addr_t bdloc;
 190     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 191     hwaddr ram_bases[2], ram_sizes[2];
 192     target_ulong sram_size;
 193     long bios_size;
 194     //int phy_addr = 0;
 195     //static int phy_addr = 1;
 196     target_ulong kernel_base, initrd_base;
 197     long kernel_size, initrd_size;
 198     int linux_boot;
 199     int fl_idx, fl_sectors, len;
 200     DriveInfo *dinfo;
 201     MemoryRegion *sysmem = get_system_memory();
 202
 203     /* XXX: fix this */
 204     memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
 205                                          0x08000000);
 206     ram_bases[0] = 0;
 207     ram_sizes[0] = 0x08000000;
 208     memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
 209     ram_bases[1] = 0x00000000;
 210     ram_sizes[1] = 0x00000000;
 211     ram_size = 128 * 1024 * 1024;
 212 #ifdef DEBUG_BOARD_INIT
 213     printf("%s: register cpu\n", __func__);
 214 #endif
 215     env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 216                         33333333, &pic, kernel_filename == NULL ? 0 : 1);
 217     /* allocate SRAM */
 218     sram_size = 512 * 1024;
 219     memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
 220                            &error_fatal);
 221     vmstate_register_ram_global(sram);
 222     memory_region_add_subregion(sysmem, 0xFFF00000, sram);
 223     /* allocate and load BIOS */
 224 #ifdef DEBUG_BOARD_INIT
 225     printf("%s: register BIOS\n", __func__);
 226 #endif
 227     fl_idx = 0;
 228 #ifdef USE_FLASH_BIOS
 229     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 230     if (dinfo) {
 231         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 232
 233         bios_size = blk_getlength(blk);
 234         fl_sectors = (bios_size + 65535) >> 16;
 235 #ifdef DEBUG_BOARD_INIT
 236         printf("Register parallel flash %d size %lx"
 237                " at addr %lx '%s' %d\n",
 238                fl_idx, bios_size, -bios_size,
 239                blk_name(blk), fl_sectors);
 240 #endif
 241         pflash_cfi02_register((uint32_t)(-bios_size),
 242                               NULL, "ef405ep.bios", bios_size,
 243                               blk, 65536, fl_sectors, 1,
 244                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 245                               1);
 246         fl_idx++;
 247     } else
 248 #endif
 249     {
 250 #ifdef DEBUG_BOARD_INIT
 251         printf("Load BIOS from file\n");
 252 #endif
 253         bios = g_new(MemoryRegion, 1);
 254         memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
 255                                &error_fatal);
 256         vmstate_register_ram_global(bios);
 257
 258         if (bios_name == NULL)
 259             bios_name = BIOS_FILENAME;
 260         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 261         if (filename) {
 262             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 263             g_free(filename);
 264             if (bios_size < 0 || bios_size > BIOS_SIZE) {
 265                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 266                 exit(1);
 267             }
 268             bios_size = (bios_size + 0xfff) & ~0xfff;
 269             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 270         } else if (!qtest_enabled() || kernel_filename != NULL) {
 271             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 272             exit(1);
 273         } else {
 274             /* Avoid an uninitialized variable warning */
 275             bios_size = -1;
 276         }
 277         memory_region_set_readonly(bios, true);
 278     }
 279     /* Register FPGA */
 280 #ifdef DEBUG_BOARD_INIT
 281     printf("%s: register FPGA\n", __func__);
 282 #endif
 283     ref405ep_fpga_init(sysmem, 0xF0300000);
 284     /* Register NVRAM */
 285 #ifdef DEBUG_BOARD_INIT
 286     printf("%s: register NVRAM\n", __func__);
 287 #endif
 288     m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
 289     /* Load kernel */
 290     linux_boot = (kernel_filename != NULL);
 291     if (linux_boot) {
 292 #ifdef DEBUG_BOARD_INIT
 293         printf("%s: load kernel\n", __func__);
 294 #endif
 295         memset(&bd, 0, sizeof(bd));
 296         bd.bi_memstart = 0x00000000;
 297         bd.bi_memsize = ram_size;
 298         bd.bi_flashstart = -bios_size;
 299         bd.bi_flashsize = -bios_size;
 300         bd.bi_flashoffset = 0;
 301         bd.bi_sramstart = 0xFFF00000;
 302         bd.bi_sramsize = sram_size;
 303         bd.bi_bootflags = 0;
 304         bd.bi_intfreq = 133333333;
 305         bd.bi_busfreq = 33333333;
 306         bd.bi_baudrate = 115200;
 307         bd.bi_s_version[0] = 'Q';
 308         bd.bi_s_version[1] = 'M';
 309         bd.bi_s_version[2] = 'U';
 310         bd.bi_s_version[3] = '\0';
 311         bd.bi_r_version[0] = 'Q';
 312         bd.bi_r_version[1] = 'E';
 313         bd.bi_r_version[2] = 'M';
 314         bd.bi_r_version[3] = 'U';
 315         bd.bi_r_version[4] = '\0';
 316         bd.bi_procfreq = 133333333;
 317         bd.bi_plb_busfreq = 33333333;
 318         bd.bi_pci_busfreq = 33333333;
 319         bd.bi_opbfreq = 33333333;
 320         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 321         env->gpr[3] = bdloc;
 322         kernel_base = KERNEL_LOAD_ADDR;
 323         /* now we can load the kernel */
 324         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 325                                           ram_size - kernel_base);
 326         if (kernel_size < 0) {
 327             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 328                     kernel_filename);
 329             exit(1);
 330         }
 331         printf("Load kernel size %ld at " TARGET_FMT_lx,
 332                kernel_size, kernel_base);
 333         /* load initrd */
 334         if (initrd_filename) {
 335             initrd_base = INITRD_LOAD_ADDR;
 336             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 337                                               ram_size - initrd_base);
 338             if (initrd_size < 0) {
 339                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 340                         initrd_filename);
 341                 exit(1);
 342             }
 343         } else {
 344             initrd_base = 0;
 345             initrd_size = 0;
 346         }
 347         env->gpr[4] = initrd_base;
 348         env->gpr[5] = initrd_size;
 349         if (kernel_cmdline != NULL) {
 350             len = strlen(kernel_cmdline);
 351             bdloc -= ((len + 255) & ~255);
 352             cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
 353             env->gpr[6] = bdloc;
 354             env->gpr[7] = bdloc + len;
 355         } else {
 356             env->gpr[6] = 0;
 357             env->gpr[7] = 0;
 358         }
 359         env->nip = KERNEL_LOAD_ADDR;
 360     } else {
 361         kernel_base = 0;
 362         kernel_size = 0;
 363         initrd_base = 0;
 364         initrd_size = 0;
 365         bdloc = 0;
 366     }
 367 #ifdef DEBUG_BOARD_INIT
 368     printf("bdloc " RAM_ADDR_FMT "\n", bdloc);
 369     printf("%s: Done\n", __func__);
 370 #endif
 371 }
 372
 373 static void ref405ep_class_init(ObjectClass *oc, void *data)
 374 {
 375     MachineClass *mc = MACHINE_CLASS(oc);
 376
 377     mc->desc = "ref405ep";
 378     mc->init = ref405ep_init;
 379 }
 380
 381 static const TypeInfo ref405ep_type = {
 382     .name = MACHINE_TYPE_NAME("ref405ep"),
 383     .parent = TYPE_MACHINE,
 384     .class_init = ref405ep_class_init,
 385 };
 386
 387 /*****************************************************************************/
 388 /* AMCC Taihu evaluation board */
 389 /* - PowerPC 405EP processor
 390  * - SDRAM               128 MB at 0x00000000
 391  * - Boot flash          2 MB   at 0xFFE00000
 392  * - Application flash   32 MB  at 0xFC000000
 393  * - 2 serial ports
 394  * - 2 ethernet PHY
 395  * - 1 USB 1.1 device    0x50000000
 396  * - 1 LCD display       0x50100000
 397  * - 1 CPLD              0x50100000
 398  * - 1 I2C EEPROM
 399  * - 1 I2C thermal sensor
 400  * - a set of LEDs
 401  * - bit-bang SPI port using GPIOs
 402  * - 1 EBC interface connector 0 0x50200000
 403  * - 1 cardbus controller + expansion slot.
 404  * - 1 PCI expansion slot.
 405  */
 406 typedef struct taihu_cpld_t taihu_cpld_t;
 407 struct taihu_cpld_t {
 408     uint8_t reg0;
 409     uint8_t reg1;
 410 };
 411
 412 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
 413 {
 414     taihu_cpld_t *cpld;
 415     uint32_t ret;
 416
 417     cpld = opaque;
 418     switch (addr) {
 419     case 0x0:
 420         ret = cpld->reg0;
 421         break;
 422     case 0x1:
 423         ret = cpld->reg1;
 424         break;
 425     default:
 426         ret = 0;
 427         break;
 428     }
 429
 430     return ret;
 431 }
 432
 433 static void taihu_cpld_write(void *opaque, hwaddr addr,
 434                              uint64_t value, unsigned size)
 435 {
 436     taihu_cpld_t *cpld;
 437
 438     cpld = opaque;
 439     switch (addr) {
 440     case 0x0:
 441         /* Read only */
 442         break;
 443     case 0x1:
 444         cpld->reg1 = value;
 445         break;
 446     default:
 447         break;
 448     }
 449 }
 450
 451 static const MemoryRegionOps taihu_cpld_ops = {
 452     .read = taihu_cpld_read,
 453     .write = taihu_cpld_write,
 454     .impl = {
 455         .min_access_size = 1,
 456         .max_access_size = 1,
 457     },
 458     .endianness = DEVICE_NATIVE_ENDIAN,
 459 };
 460
 461 static void taihu_cpld_reset (void *opaque)
 462 {
 463     taihu_cpld_t *cpld;
 464
 465     cpld = opaque;
 466     cpld->reg0 = 0x01;
 467     cpld->reg1 = 0x80;
 468 }
 469
 470 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
 471 {
 472     taihu_cpld_t *cpld;
 473     MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
 474
 475     cpld = g_malloc0(sizeof(taihu_cpld_t));
 476     memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
 477     memory_region_add_subregion(sysmem, base, cpld_memory);
 478     qemu_register_reset(&taihu_cpld_reset, cpld);
 479 }
 480
 481 static void taihu_405ep_init(MachineState *machine)
 482 {
 483     ram_addr_t ram_size = machine->ram_size;
 484     const char *kernel_filename = machine->kernel_filename;
 485     const char *initrd_filename = machine->initrd_filename;
 486     char *filename;
 487     qemu_irq *pic;
 488     MemoryRegion *sysmem = get_system_memory();
 489     MemoryRegion *bios;
 490     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 491     MemoryRegion *ram = g_malloc0(sizeof(*ram));
 492     hwaddr ram_bases[2], ram_sizes[2];
 493     long bios_size;
 494     target_ulong kernel_base, initrd_base;
 495     long kernel_size, initrd_size;
 496     int linux_boot;
 497     int fl_idx, fl_sectors;
 498     DriveInfo *dinfo;
 499
 500     /* RAM is soldered to the board so the size cannot be changed */
 501     ram_size = 0x08000000;
 502     memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
 503                                          ram_size);
 504
 505     ram_bases[0] = 0;
 506     ram_sizes[0] = 0x04000000;
 507     memory_region_init_alias(&ram_memories[0], NULL,
 508                              "taihu_405ep.ram-0", ram, ram_bases[0],
 509                              ram_sizes[0]);
 510     ram_bases[1] = 0x04000000;
 511     ram_sizes[1] = 0x04000000;
 512     memory_region_init_alias(&ram_memories[1], NULL,
 513                              "taihu_405ep.ram-1", ram, ram_bases[1],
 514                              ram_sizes[1]);
 515 #ifdef DEBUG_BOARD_INIT
 516     printf("%s: register cpu\n", __func__);
 517 #endif
 518     ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 519                   33333333, &pic, kernel_filename == NULL ? 0 : 1);
 520     /* allocate and load BIOS */
 521 #ifdef DEBUG_BOARD_INIT
 522     printf("%s: register BIOS\n", __func__);
 523 #endif
 524     fl_idx = 0;
 525 #if defined(USE_FLASH_BIOS)
 526     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 527     if (dinfo) {
 528         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 529
 530         bios_size = blk_getlength(blk);
 531         /* XXX: should check that size is 2MB */
 532         //        bios_size = 2 * 1024 * 1024;
 533         fl_sectors = (bios_size + 65535) >> 16;
 534 #ifdef DEBUG_BOARD_INIT
 535         printf("Register parallel flash %d size %lx"
 536                " at addr %lx '%s' %d\n",
 537                fl_idx, bios_size, -bios_size,
 538                blk_name(blk), fl_sectors);
 539 #endif
 540         pflash_cfi02_register((uint32_t)(-bios_size),
 541                               NULL, "taihu_405ep.bios", bios_size,
 542                               blk, 65536, fl_sectors, 1,
 543                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 544                               1);
 545         fl_idx++;
 546     } else
 547 #endif
 548     {
 549 #ifdef DEBUG_BOARD_INIT
 550         printf("Load BIOS from file\n");
 551 #endif
 552         if (bios_name == NULL)
 553             bios_name = BIOS_FILENAME;
 554         bios = g_new(MemoryRegion, 1);
 555         memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
 556                                &error_fatal);
 557         vmstate_register_ram_global(bios);
 558         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 559         if (filename) {
 560             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 561             g_free(filename);
 562             if (bios_size < 0 || bios_size > BIOS_SIZE) {
 563                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 564                 exit(1);
 565             }
 566             bios_size = (bios_size + 0xfff) & ~0xfff;
 567             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 568         } else if (!qtest_enabled()) {
 569             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 570             exit(1);
 571         }
 572         memory_region_set_readonly(bios, true);
 573     }
 574     /* Register Linux flash */
 575     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 576     if (dinfo) {
 577         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 578
 579         bios_size = blk_getlength(blk);
 580         /* XXX: should check that size is 32MB */
 581         bios_size = 32 * 1024 * 1024;
 582         fl_sectors = (bios_size + 65535) >> 16;
 583 #ifdef DEBUG_BOARD_INIT
 584         printf("Register parallel flash %d size %lx"
 585                " at addr " TARGET_FMT_lx " '%s'\n",
 586                fl_idx, bios_size, (target_ulong)0xfc000000,
 587                blk_name(blk));
 588 #endif
 589         pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
 590                               blk, 65536, fl_sectors, 1,
 591                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 592                               1);
 593         fl_idx++;
 594     }
 595     /* Register CLPD & LCD display */
 596 #ifdef DEBUG_BOARD_INIT
 597     printf("%s: register CPLD\n", __func__);
 598 #endif
 599     taihu_cpld_init(sysmem, 0x50100000);
 600     /* Load kernel */
 601     linux_boot = (kernel_filename != NULL);
 602     if (linux_boot) {
 603 #ifdef DEBUG_BOARD_INIT
 604         printf("%s: load kernel\n", __func__);
 605 #endif
 606         kernel_base = KERNEL_LOAD_ADDR;
 607         /* now we can load the kernel */
 608         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 609                                           ram_size - kernel_base);
 610         if (kernel_size < 0) {
 611             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 612                     kernel_filename);
 613             exit(1);
 614         }
 615         /* load initrd */
 616         if (initrd_filename) {
 617             initrd_base = INITRD_LOAD_ADDR;
 618             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 619                                               ram_size - initrd_base);
 620             if (initrd_size < 0) {
 621                 fprintf(stderr,
 622                         "qemu: could not load initial ram disk '%s'\n",
 623                         initrd_filename);
 624                 exit(1);
 625             }
 626         } else {
 627             initrd_base = 0;
 628             initrd_size = 0;
 629         }
 630     } else {
 631         kernel_base = 0;
 632         kernel_size = 0;
 633         initrd_base = 0;
 634         initrd_size = 0;
 635     }
 636 #ifdef DEBUG_BOARD_INIT
 637     printf("%s: Done\n", __func__);
 638 #endif
 639 }
 640
 641 static void taihu_class_init(ObjectClass *oc, void *data)
 642 {
 643     MachineClass *mc = MACHINE_CLASS(oc);
 644
 645     mc->desc = "taihu";
 646     mc->init = taihu_405ep_init;
 647 }
 648
 649 static const TypeInfo taihu_type = {
 650     .name = MACHINE_TYPE_NAME("taihu"),
 651     .parent = TYPE_MACHINE,
 652     .class_init = taihu_class_init,
 653 };
 654
 655 static void ppc405_machine_init(void)
 656 {
 657     type_register_static(&ref405ep_type);
 658     type_register_static(&taihu_type);
 659 }
 660
 661 machine_init(ppc405_machine_init)