hw/ppc/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/hw.h"
  29 #include "hw/ppc/ppc.h"
  30 #include "ppc405.h"
  31 #include "hw/timer/m48t59.h"
  32 #include "hw/block/flash.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/qtest.h"
  35 #include "sysemu/block-backend.h"
  36 #include "hw/boards.h"
  37 #include "qemu/log.h"
  38 #include "qemu/error-report.h"
  39 #include "hw/loader.h"
  40 #include "sysemu/blockdev.h"
  41 #include "exec/address-spaces.h"
  42
  43 #define BIOS_FILENAME "ppc405_rom.bin"
  44 #define BIOS_SIZE (2048 * 1024)
  45
  46 #define KERNEL_LOAD_ADDR 0x00000000
  47 #define INITRD_LOAD_ADDR 0x01800000
  48
  49 #define USE_FLASH_BIOS
  50
  51 //#define DEBUG_BOARD_INIT
  52
  53 /*****************************************************************************/
  54 /* PPC405EP reference board (IBM) */
  55 /* Standalone board with:
  56  * - PowerPC 405EP CPU
  57  * - SDRAM (0x00000000)
  58  * - Flash (0xFFF80000)
  59  * - SRAM  (0xFFF00000)
  60  * - NVRAM (0xF0000000)
  61  * - FPGA  (0xF0300000)
  62  */
  63 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  64 struct ref405ep_fpga_t {
  65     uint8_t reg0;
  66     uint8_t reg1;
  67 };
  68
  69 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
  70 {
  71     ref405ep_fpga_t *fpga;
  72     uint32_t ret;
  73
  74     fpga = opaque;
  75     switch (addr) {
  76     case 0x0:
  77         ret = fpga->reg0;
  78         break;
  79     case 0x1:
  80         ret = fpga->reg1;
  81         break;
  82     default:
  83         ret = 0;
  84         break;
  85     }
  86
  87     return ret;
  88 }
  89
  90 static void ref405ep_fpga_writeb (void *opaque,
  91                                   hwaddr addr, uint32_t value)
  92 {
  93     ref405ep_fpga_t *fpga;
  94
  95     fpga = opaque;
  96     switch (addr) {
  97     case 0x0:
  98         /* Read only */
  99         break;
 100     case 0x1:
 101         fpga->reg1 = value;
 102         break;
 103     default:
 104         break;
 105     }
 106 }
 107
 108 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
 109 {
 110     uint32_t ret;
 111
 112     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 113     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 114
 115     return ret;
 116 }
 117
 118 static void ref405ep_fpga_writew (void *opaque,
 119                                   hwaddr addr, uint32_t value)
 120 {
 121     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 122     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 123 }
 124
 125 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
 126 {
 127     uint32_t ret;
 128
 129     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 130     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 131     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 132     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 133
 134     return ret;
 135 }
 136
 137 static void ref405ep_fpga_writel (void *opaque,
 138                                   hwaddr addr, uint32_t value)
 139 {
 140     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 141     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 142     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 143     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 144 }
 145
 146 static const MemoryRegionOps ref405ep_fpga_ops = {
 147     .old_mmio = {
 148         .read = {
 149             ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,
 150         },
 151         .write = {
 152             ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,
 153         },
 154     },
 155     .endianness = DEVICE_NATIVE_ENDIAN,
 156 };
 157
 158 static void ref405ep_fpga_reset (void *opaque)
 159 {
 160     ref405ep_fpga_t *fpga;
 161
 162     fpga = opaque;
 163     fpga->reg0 = 0x00;
 164     fpga->reg1 = 0x0F;
 165 }
 166
 167 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
 168 {
 169     ref405ep_fpga_t *fpga;
 170     MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
 171
 172     fpga = g_malloc0(sizeof(ref405ep_fpga_t));
 173     memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
 174                           "fpga", 0x00000100);
 175     memory_region_add_subregion(sysmem, base, fpga_memory);
 176     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 177 }
 178
 179 static void ref405ep_init(MachineState *machine)
 180 {
 181     ram_addr_t ram_size = machine->ram_size;
 182     const char *kernel_filename = machine->kernel_filename;
 183     const char *kernel_cmdline = machine->kernel_cmdline;
 184     const char *initrd_filename = machine->initrd_filename;
 185     char *filename;
 186     ppc4xx_bd_info_t bd;
 187     CPUPPCState *env;
 188     qemu_irq *pic;
 189     MemoryRegion *bios;
 190     MemoryRegion *sram = g_new(MemoryRegion, 1);
 191     ram_addr_t bdloc;
 192     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 193     hwaddr ram_bases[2], ram_sizes[2];
 194     target_ulong sram_size;
 195     long bios_size;
 196     //int phy_addr = 0;
 197     //static int phy_addr = 1;
 198     target_ulong kernel_base, initrd_base;
 199     long kernel_size, initrd_size;
 200     int linux_boot;
 201     int fl_idx, fl_sectors, len;
 202     DriveInfo *dinfo;
 203     MemoryRegion *sysmem = get_system_memory();
 204
 205 #ifdef TARGET_PPCEMB
 206     if (!qtest_enabled()) {
 207         warn_report("qemu-system-ppcemb is deprecated, "
 208                     "please use qemu-system-ppc instead.");
 209     }
 210 #endif
 211
 212     /* XXX: fix this */
 213     memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
 214                                          0x08000000);
 215     ram_bases[0] = 0;
 216     ram_sizes[0] = 0x08000000;
 217     memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
 218     ram_bases[1] = 0x00000000;
 219     ram_sizes[1] = 0x00000000;
 220     ram_size = 128 * 1024 * 1024;
 221 #ifdef DEBUG_BOARD_INIT
 222     printf("%s: register cpu\n", __func__);
 223 #endif
 224     env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 225                         33333333, &pic, kernel_filename == NULL ? 0 : 1);
 226     /* allocate SRAM */
 227     sram_size = 512 * 1024;
 228     memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
 229                            &error_fatal);
 230     memory_region_add_subregion(sysmem, 0xFFF00000, sram);
 231     /* allocate and load BIOS */
 232 #ifdef DEBUG_BOARD_INIT
 233     printf("%s: register BIOS\n", __func__);
 234 #endif
 235     fl_idx = 0;
 236 #ifdef USE_FLASH_BIOS
 237     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 238     if (dinfo) {
 239         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 240
 241         bios_size = blk_getlength(blk);
 242         fl_sectors = (bios_size + 65535) >> 16;
 243 #ifdef DEBUG_BOARD_INIT
 244         printf("Register parallel flash %d size %lx"
 245                " at addr %lx '%s' %d\n",
 246                fl_idx, bios_size, -bios_size,
 247                blk_name(blk), fl_sectors);
 248 #endif
 249         pflash_cfi02_register((uint32_t)(-bios_size),
 250                               NULL, "ef405ep.bios", bios_size,
 251                               blk, 65536, fl_sectors, 1,
 252                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 253                               1);
 254         fl_idx++;
 255     } else
 256 #endif
 257     {
 258 #ifdef DEBUG_BOARD_INIT
 259         printf("Load BIOS from file\n");
 260 #endif
 261         bios = g_new(MemoryRegion, 1);
 262         memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
 263                                &error_fatal);
 264
 265         if (bios_name == NULL)
 266             bios_name = BIOS_FILENAME;
 267         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 268         if (filename) {
 269             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 270             g_free(filename);
 271             if (bios_size < 0 || bios_size > BIOS_SIZE) {
 272                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 273                 exit(1);
 274             }
 275             bios_size = (bios_size + 0xfff) & ~0xfff;
 276             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 277         } else if (!qtest_enabled() || kernel_filename != NULL) {
 278             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 279             exit(1);
 280         } else {
 281             /* Avoid an uninitialized variable warning */
 282             bios_size = -1;
 283         }
 284         memory_region_set_readonly(bios, true);
 285     }
 286     /* Register FPGA */
 287 #ifdef DEBUG_BOARD_INIT
 288     printf("%s: register FPGA\n", __func__);
 289 #endif
 290     ref405ep_fpga_init(sysmem, 0xF0300000);
 291     /* Register NVRAM */
 292 #ifdef DEBUG_BOARD_INIT
 293     printf("%s: register NVRAM\n", __func__);
 294 #endif
 295     m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
 296     /* Load kernel */
 297     linux_boot = (kernel_filename != NULL);
 298     if (linux_boot) {
 299 #ifdef DEBUG_BOARD_INIT
 300         printf("%s: load kernel\n", __func__);
 301 #endif
 302         memset(&bd, 0, sizeof(bd));
 303         bd.bi_memstart = 0x00000000;
 304         bd.bi_memsize = ram_size;
 305         bd.bi_flashstart = -bios_size;
 306         bd.bi_flashsize = -bios_size;
 307         bd.bi_flashoffset = 0;
 308         bd.bi_sramstart = 0xFFF00000;
 309         bd.bi_sramsize = sram_size;
 310         bd.bi_bootflags = 0;
 311         bd.bi_intfreq = 133333333;
 312         bd.bi_busfreq = 33333333;
 313         bd.bi_baudrate = 115200;
 314         bd.bi_s_version[0] = 'Q';
 315         bd.bi_s_version[1] = 'M';
 316         bd.bi_s_version[2] = 'U';
 317         bd.bi_s_version[3] = '\0';
 318         bd.bi_r_version[0] = 'Q';
 319         bd.bi_r_version[1] = 'E';
 320         bd.bi_r_version[2] = 'M';
 321         bd.bi_r_version[3] = 'U';
 322         bd.bi_r_version[4] = '\0';
 323         bd.bi_procfreq = 133333333;
 324         bd.bi_plb_busfreq = 33333333;
 325         bd.bi_pci_busfreq = 33333333;
 326         bd.bi_opbfreq = 33333333;
 327         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 328         env->gpr[3] = bdloc;
 329         kernel_base = KERNEL_LOAD_ADDR;
 330         /* now we can load the kernel */
 331         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 332                                           ram_size - kernel_base);
 333         if (kernel_size < 0) {
 334             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 335                     kernel_filename);
 336             exit(1);
 337         }
 338         printf("Load kernel size %ld at " TARGET_FMT_lx,
 339                kernel_size, kernel_base);
 340         /* load initrd */
 341         if (initrd_filename) {
 342             initrd_base = INITRD_LOAD_ADDR;
 343             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 344                                               ram_size - initrd_base);
 345             if (initrd_size < 0) {
 346                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 347                         initrd_filename);
 348                 exit(1);
 349             }
 350         } else {
 351             initrd_base = 0;
 352             initrd_size = 0;
 353         }
 354         env->gpr[4] = initrd_base;
 355         env->gpr[5] = initrd_size;
 356         if (kernel_cmdline != NULL) {
 357             len = strlen(kernel_cmdline);
 358             bdloc -= ((len + 255) & ~255);
 359             cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
 360             env->gpr[6] = bdloc;
 361             env->gpr[7] = bdloc + len;
 362         } else {
 363             env->gpr[6] = 0;
 364             env->gpr[7] = 0;
 365         }
 366         env->nip = KERNEL_LOAD_ADDR;
 367     } else {
 368         kernel_base = 0;
 369         kernel_size = 0;
 370         initrd_base = 0;
 371         initrd_size = 0;
 372         bdloc = 0;
 373     }
 374 #ifdef DEBUG_BOARD_INIT
 375     printf("bdloc " RAM_ADDR_FMT "\n", bdloc);
 376     printf("%s: Done\n", __func__);
 377 #endif
 378 }
 379
 380 static void ref405ep_class_init(ObjectClass *oc, void *data)
 381 {
 382     MachineClass *mc = MACHINE_CLASS(oc);
 383
 384     mc->desc = "ref405ep";
 385     mc->init = ref405ep_init;
 386 }
 387
 388 static const TypeInfo ref405ep_type = {
 389     .name = MACHINE_TYPE_NAME("ref405ep"),
 390     .parent = TYPE_MACHINE,
 391     .class_init = ref405ep_class_init,
 392 };
 393
 394 /*****************************************************************************/
 395 /* AMCC Taihu evaluation board */
 396 /* - PowerPC 405EP processor
 397  * - SDRAM               128 MB at 0x00000000
 398  * - Boot flash          2 MB   at 0xFFE00000
 399  * - Application flash   32 MB  at 0xFC000000
 400  * - 2 serial ports
 401  * - 2 ethernet PHY
 402  * - 1 USB 1.1 device    0x50000000
 403  * - 1 LCD display       0x50100000
 404  * - 1 CPLD              0x50100000
 405  * - 1 I2C EEPROM
 406  * - 1 I2C thermal sensor
 407  * - a set of LEDs
 408  * - bit-bang SPI port using GPIOs
 409  * - 1 EBC interface connector 0 0x50200000
 410  * - 1 cardbus controller + expansion slot.
 411  * - 1 PCI expansion slot.
 412  */
 413 typedef struct taihu_cpld_t taihu_cpld_t;
 414 struct taihu_cpld_t {
 415     uint8_t reg0;
 416     uint8_t reg1;
 417 };
 418
 419 static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
 420 {
 421     taihu_cpld_t *cpld;
 422     uint32_t ret;
 423
 424     cpld = opaque;
 425     switch (addr) {
 426     case 0x0:
 427         ret = cpld->reg0;
 428         break;
 429     case 0x1:
 430         ret = cpld->reg1;
 431         break;
 432     default:
 433         ret = 0;
 434         break;
 435     }
 436
 437     return ret;
 438 }
 439
 440 static void taihu_cpld_write(void *opaque, hwaddr addr,
 441                              uint64_t value, unsigned size)
 442 {
 443     taihu_cpld_t *cpld;
 444
 445     cpld = opaque;
 446     switch (addr) {
 447     case 0x0:
 448         /* Read only */
 449         break;
 450     case 0x1:
 451         cpld->reg1 = value;
 452         break;
 453     default:
 454         break;
 455     }
 456 }
 457
 458 static const MemoryRegionOps taihu_cpld_ops = {
 459     .read = taihu_cpld_read,
 460     .write = taihu_cpld_write,
 461     .impl = {
 462         .min_access_size = 1,
 463         .max_access_size = 1,
 464     },
 465     .endianness = DEVICE_NATIVE_ENDIAN,
 466 };
 467
 468 static void taihu_cpld_reset (void *opaque)
 469 {
 470     taihu_cpld_t *cpld;
 471
 472     cpld = opaque;
 473     cpld->reg0 = 0x01;
 474     cpld->reg1 = 0x80;
 475 }
 476
 477 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
 478 {
 479     taihu_cpld_t *cpld;
 480     MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
 481
 482     cpld = g_malloc0(sizeof(taihu_cpld_t));
 483     memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
 484     memory_region_add_subregion(sysmem, base, cpld_memory);
 485     qemu_register_reset(&taihu_cpld_reset, cpld);
 486 }
 487
 488 static void taihu_405ep_init(MachineState *machine)
 489 {
 490     ram_addr_t ram_size = machine->ram_size;
 491     const char *kernel_filename = machine->kernel_filename;
 492     const char *initrd_filename = machine->initrd_filename;
 493     char *filename;
 494     qemu_irq *pic;
 495     MemoryRegion *sysmem = get_system_memory();
 496     MemoryRegion *bios;
 497     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 498     MemoryRegion *ram = g_malloc0(sizeof(*ram));
 499     hwaddr ram_bases[2], ram_sizes[2];
 500     long bios_size;
 501     target_ulong kernel_base, initrd_base;
 502     long kernel_size, initrd_size;
 503     int linux_boot;
 504     int fl_idx, fl_sectors;
 505     DriveInfo *dinfo;
 506
 507 #ifdef TARGET_PPCEMB
 508     if (!qtest_enabled()) {
 509         warn_report("qemu-system-ppcemb is deprecated, "
 510                     "please use qemu-system-ppc instead.");
 511     }
 512 #endif
 513
 514     /* RAM is soldered to the board so the size cannot be changed */
 515     ram_size = 0x08000000;
 516     memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
 517                                          ram_size);
 518
 519     ram_bases[0] = 0;
 520     ram_sizes[0] = 0x04000000;
 521     memory_region_init_alias(&ram_memories[0], NULL,
 522                              "taihu_405ep.ram-0", ram, ram_bases[0],
 523                              ram_sizes[0]);
 524     ram_bases[1] = 0x04000000;
 525     ram_sizes[1] = 0x04000000;
 526     memory_region_init_alias(&ram_memories[1], NULL,
 527                              "taihu_405ep.ram-1", ram, ram_bases[1],
 528                              ram_sizes[1]);
 529 #ifdef DEBUG_BOARD_INIT
 530     printf("%s: register cpu\n", __func__);
 531 #endif
 532     ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 533                   33333333, &pic, kernel_filename == NULL ? 0 : 1);
 534     /* allocate and load BIOS */
 535 #ifdef DEBUG_BOARD_INIT
 536     printf("%s: register BIOS\n", __func__);
 537 #endif
 538     fl_idx = 0;
 539 #if defined(USE_FLASH_BIOS)
 540     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 541     if (dinfo) {
 542         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 543
 544         bios_size = blk_getlength(blk);
 545         /* XXX: should check that size is 2MB */
 546         //        bios_size = 2 * 1024 * 1024;
 547         fl_sectors = (bios_size + 65535) >> 16;
 548 #ifdef DEBUG_BOARD_INIT
 549         printf("Register parallel flash %d size %lx"
 550                " at addr %lx '%s' %d\n",
 551                fl_idx, bios_size, -bios_size,
 552                blk_name(blk), fl_sectors);
 553 #endif
 554         pflash_cfi02_register((uint32_t)(-bios_size),
 555                               NULL, "taihu_405ep.bios", bios_size,
 556                               blk, 65536, fl_sectors, 1,
 557                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 558                               1);
 559         fl_idx++;
 560     } else
 561 #endif
 562     {
 563 #ifdef DEBUG_BOARD_INIT
 564         printf("Load BIOS from file\n");
 565 #endif
 566         if (bios_name == NULL)
 567             bios_name = BIOS_FILENAME;
 568         bios = g_new(MemoryRegion, 1);
 569         memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
 570                                &error_fatal);
 571         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 572         if (filename) {
 573             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 574             g_free(filename);
 575             if (bios_size < 0 || bios_size > BIOS_SIZE) {
 576                 error_report("Could not load PowerPC BIOS '%s'", bios_name);
 577                 exit(1);
 578             }
 579             bios_size = (bios_size + 0xfff) & ~0xfff;
 580             memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 581         } else if (!qtest_enabled()) {
 582             error_report("Could not load PowerPC BIOS '%s'", bios_name);
 583             exit(1);
 584         }
 585         memory_region_set_readonly(bios, true);
 586     }
 587     /* Register Linux flash */
 588     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 589     if (dinfo) {
 590         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 591
 592         bios_size = blk_getlength(blk);
 593         /* XXX: should check that size is 32MB */
 594         bios_size = 32 * 1024 * 1024;
 595         fl_sectors = (bios_size + 65535) >> 16;
 596 #ifdef DEBUG_BOARD_INIT
 597         printf("Register parallel flash %d size %lx"
 598                " at addr " TARGET_FMT_lx " '%s'\n",
 599                fl_idx, bios_size, (target_ulong)0xfc000000,
 600                blk_name(blk));
 601 #endif
 602         pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
 603                               blk, 65536, fl_sectors, 1,
 604                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 605                               1);
 606         fl_idx++;
 607     }
 608     /* Register CLPD & LCD display */
 609 #ifdef DEBUG_BOARD_INIT
 610     printf("%s: register CPLD\n", __func__);
 611 #endif
 612     taihu_cpld_init(sysmem, 0x50100000);
 613     /* Load kernel */
 614     linux_boot = (kernel_filename != NULL);
 615     if (linux_boot) {
 616 #ifdef DEBUG_BOARD_INIT
 617         printf("%s: load kernel\n", __func__);
 618 #endif
 619         kernel_base = KERNEL_LOAD_ADDR;
 620         /* now we can load the kernel */
 621         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 622                                           ram_size - kernel_base);
 623         if (kernel_size < 0) {
 624             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 625                     kernel_filename);
 626             exit(1);
 627         }
 628         /* load initrd */
 629         if (initrd_filename) {
 630             initrd_base = INITRD_LOAD_ADDR;
 631             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 632                                               ram_size - initrd_base);
 633             if (initrd_size < 0) {
 634                 fprintf(stderr,
 635                         "qemu: could not load initial ram disk '%s'\n",
 636                         initrd_filename);
 637                 exit(1);
 638             }
 639         } else {
 640             initrd_base = 0;
 641             initrd_size = 0;
 642         }
 643     } else {
 644         kernel_base = 0;
 645         kernel_size = 0;
 646         initrd_base = 0;
 647         initrd_size = 0;
 648     }
 649 #ifdef DEBUG_BOARD_INIT
 650     printf("%s: Done\n", __func__);
 651 #endif
 652 }
 653
 654 static void taihu_class_init(ObjectClass *oc, void *data)
 655 {
 656     MachineClass *mc = MACHINE_CLASS(oc);
 657
 658     mc->desc = "taihu";
 659     mc->init = taihu_405ep_init;
 660 }
 661
 662 static const TypeInfo taihu_type = {
 663     .name = MACHINE_TYPE_NAME("taihu"),
 664     .parent = TYPE_MACHINE,
 665     .class_init = taihu_class_init,
 666 };
 667
 668 static void ppc405_machine_init(void)
 669 {
 670     type_register_static(&ref405ep_type);
 671     type_register_static(&taihu_type);
 672 }
 673
 674 type_init(ppc405_machine_init)