2 * QEMU PowerPC 405 evaluation boards emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/ppc/ppc.h"
27 #include "hw/timer/m48t59.h"
28 #include "hw/block/flash.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/qtest.h"
31 #include "block/block.h"
32 #include "hw/boards.h"
34 #include "qemu/error-report.h"
35 #include "hw/loader.h"
36 #include "sysemu/blockdev.h"
37 #include "exec/address-spaces.h"
39 #define BIOS_FILENAME "ppc405_rom.bin"
40 #define BIOS_SIZE (2048 * 1024)
42 #define KERNEL_LOAD_ADDR 0x00000000
43 #define INITRD_LOAD_ADDR 0x01800000
45 #define USE_FLASH_BIOS
47 //#define DEBUG_BOARD_INIT
49 /*****************************************************************************/
50 /* PPC405EP reference board (IBM) */
51 /* Standalone board with:
53 * - SDRAM (0x00000000)
54 * - Flash (0xFFF80000)
56 * - NVRAM (0xF0000000)
59 typedef struct ref405ep_fpga_t ref405ep_fpga_t
;
60 struct ref405ep_fpga_t
{
65 static uint32_t ref405ep_fpga_readb (void *opaque
, hwaddr addr
)
67 ref405ep_fpga_t
*fpga
;
86 static void ref405ep_fpga_writeb (void *opaque
,
87 hwaddr addr
, uint32_t value
)
89 ref405ep_fpga_t
*fpga
;
104 static uint32_t ref405ep_fpga_readw (void *opaque
, hwaddr addr
)
108 ret
= ref405ep_fpga_readb(opaque
, addr
) << 8;
109 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 1);
114 static void ref405ep_fpga_writew (void *opaque
,
115 hwaddr addr
, uint32_t value
)
117 ref405ep_fpga_writeb(opaque
, addr
, (value
>> 8) & 0xFF);
118 ref405ep_fpga_writeb(opaque
, addr
+ 1, value
& 0xFF);
121 static uint32_t ref405ep_fpga_readl (void *opaque
, hwaddr addr
)
125 ret
= ref405ep_fpga_readb(opaque
, addr
) << 24;
126 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 1) << 16;
127 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 2) << 8;
128 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 3);
133 static void ref405ep_fpga_writel (void *opaque
,
134 hwaddr addr
, uint32_t value
)
136 ref405ep_fpga_writeb(opaque
, addr
, (value
>> 24) & 0xFF);
137 ref405ep_fpga_writeb(opaque
, addr
+ 1, (value
>> 16) & 0xFF);
138 ref405ep_fpga_writeb(opaque
, addr
+ 2, (value
>> 8) & 0xFF);
139 ref405ep_fpga_writeb(opaque
, addr
+ 3, value
& 0xFF);
142 static const MemoryRegionOps ref405ep_fpga_ops
= {
145 ref405ep_fpga_readb
, ref405ep_fpga_readw
, ref405ep_fpga_readl
,
148 ref405ep_fpga_writeb
, ref405ep_fpga_writew
, ref405ep_fpga_writel
,
151 .endianness
= DEVICE_NATIVE_ENDIAN
,
154 static void ref405ep_fpga_reset (void *opaque
)
156 ref405ep_fpga_t
*fpga
;
163 static void ref405ep_fpga_init(MemoryRegion
*sysmem
, uint32_t base
)
165 ref405ep_fpga_t
*fpga
;
166 MemoryRegion
*fpga_memory
= g_new(MemoryRegion
, 1);
168 fpga
= g_malloc0(sizeof(ref405ep_fpga_t
));
169 memory_region_init_io(fpga_memory
, NULL
, &ref405ep_fpga_ops
, fpga
,
171 memory_region_add_subregion(sysmem
, base
, fpga_memory
);
172 qemu_register_reset(&ref405ep_fpga_reset
, fpga
);
175 static void ref405ep_init(QEMUMachineInitArgs
*args
)
177 ram_addr_t ram_size
= args
->ram_size
;
178 const char *kernel_filename
= args
->kernel_filename
;
179 const char *kernel_cmdline
= args
->kernel_cmdline
;
180 const char *initrd_filename
= args
->initrd_filename
;
186 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
188 MemoryRegion
*ram_memories
= g_malloc(2 * sizeof(*ram_memories
));
189 hwaddr ram_bases
[2], ram_sizes
[2];
190 target_ulong sram_size
;
193 //static int phy_addr = 1;
194 target_ulong kernel_base
, initrd_base
;
195 long kernel_size
, initrd_size
;
197 int fl_idx
, fl_sectors
, len
;
199 MemoryRegion
*sysmem
= get_system_memory();
202 memory_region_init_ram(&ram_memories
[0], NULL
, "ef405ep.ram", 0x08000000);
203 vmstate_register_ram_global(&ram_memories
[0]);
205 ram_sizes
[0] = 0x08000000;
206 memory_region_init(&ram_memories
[1], NULL
, "ef405ep.ram1", 0);
207 ram_bases
[1] = 0x00000000;
208 ram_sizes
[1] = 0x00000000;
209 ram_size
= 128 * 1024 * 1024;
210 #ifdef DEBUG_BOARD_INIT
211 printf("%s: register cpu\n", __func__
);
213 env
= ppc405ep_init(sysmem
, ram_memories
, ram_bases
, ram_sizes
,
214 33333333, &pic
, kernel_filename
== NULL
? 0 : 1);
216 sram_size
= 512 * 1024;
217 memory_region_init_ram(sram
, NULL
, "ef405ep.sram", sram_size
);
218 vmstate_register_ram_global(sram
);
219 memory_region_add_subregion(sysmem
, 0xFFF00000, sram
);
220 /* allocate and load BIOS */
221 #ifdef DEBUG_BOARD_INIT
222 printf("%s: register BIOS\n", __func__
);
225 #ifdef USE_FLASH_BIOS
226 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
228 bios_size
= bdrv_getlength(dinfo
->bdrv
);
229 fl_sectors
= (bios_size
+ 65535) >> 16;
230 #ifdef DEBUG_BOARD_INIT
231 printf("Register parallel flash %d size %lx"
232 " at addr %lx '%s' %d\n",
233 fl_idx
, bios_size
, -bios_size
,
234 bdrv_get_device_name(dinfo
->bdrv
), fl_sectors
);
236 pflash_cfi02_register((uint32_t)(-bios_size
),
237 NULL
, "ef405ep.bios", bios_size
,
238 dinfo
->bdrv
, 65536, fl_sectors
, 1,
239 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
245 #ifdef DEBUG_BOARD_INIT
246 printf("Load BIOS from file\n");
248 bios
= g_new(MemoryRegion
, 1);
249 memory_region_init_ram(bios
, NULL
, "ef405ep.bios", BIOS_SIZE
);
250 vmstate_register_ram_global(bios
);
251 if (bios_name
== NULL
)
252 bios_name
= BIOS_FILENAME
;
253 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
255 bios_size
= load_image(filename
, memory_region_get_ram_ptr(bios
));
257 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
258 error_report("Could not load PowerPC BIOS '%s'", bios_name
);
261 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
262 memory_region_add_subregion(sysmem
, (uint32_t)(-bios_size
), bios
);
263 } else if (!qtest_enabled() || kernel_filename
!= NULL
) {
264 error_report("Could not load PowerPC BIOS '%s'", bios_name
);
267 /* Avoid an uninitialized variable warning */
270 memory_region_set_readonly(bios
, true);
273 #ifdef DEBUG_BOARD_INIT
274 printf("%s: register FPGA\n", __func__
);
276 ref405ep_fpga_init(sysmem
, 0xF0300000);
278 #ifdef DEBUG_BOARD_INIT
279 printf("%s: register NVRAM\n", __func__
);
281 m48t59_init(NULL
, 0xF0000000, 0, 8192, 8);
283 linux_boot
= (kernel_filename
!= NULL
);
285 #ifdef DEBUG_BOARD_INIT
286 printf("%s: load kernel\n", __func__
);
288 memset(&bd
, 0, sizeof(bd
));
289 bd
.bi_memstart
= 0x00000000;
290 bd
.bi_memsize
= ram_size
;
291 bd
.bi_flashstart
= -bios_size
;
292 bd
.bi_flashsize
= -bios_size
;
293 bd
.bi_flashoffset
= 0;
294 bd
.bi_sramstart
= 0xFFF00000;
295 bd
.bi_sramsize
= sram_size
;
297 bd
.bi_intfreq
= 133333333;
298 bd
.bi_busfreq
= 33333333;
299 bd
.bi_baudrate
= 115200;
300 bd
.bi_s_version
[0] = 'Q';
301 bd
.bi_s_version
[1] = 'M';
302 bd
.bi_s_version
[2] = 'U';
303 bd
.bi_s_version
[3] = '\0';
304 bd
.bi_r_version
[0] = 'Q';
305 bd
.bi_r_version
[1] = 'E';
306 bd
.bi_r_version
[2] = 'M';
307 bd
.bi_r_version
[3] = 'U';
308 bd
.bi_r_version
[4] = '\0';
309 bd
.bi_procfreq
= 133333333;
310 bd
.bi_plb_busfreq
= 33333333;
311 bd
.bi_pci_busfreq
= 33333333;
312 bd
.bi_opbfreq
= 33333333;
313 bdloc
= ppc405_set_bootinfo(env
, &bd
, 0x00000001);
315 kernel_base
= KERNEL_LOAD_ADDR
;
316 /* now we can load the kernel */
317 kernel_size
= load_image_targphys(kernel_filename
, kernel_base
,
318 ram_size
- kernel_base
);
319 if (kernel_size
< 0) {
320 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
324 printf("Load kernel size %ld at " TARGET_FMT_lx
,
325 kernel_size
, kernel_base
);
327 if (initrd_filename
) {
328 initrd_base
= INITRD_LOAD_ADDR
;
329 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
330 ram_size
- initrd_base
);
331 if (initrd_size
< 0) {
332 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
340 env
->gpr
[4] = initrd_base
;
341 env
->gpr
[5] = initrd_size
;
342 if (kernel_cmdline
!= NULL
) {
343 len
= strlen(kernel_cmdline
);
344 bdloc
-= ((len
+ 255) & ~255);
345 cpu_physical_memory_write(bdloc
, kernel_cmdline
, len
+ 1);
347 env
->gpr
[7] = bdloc
+ len
;
352 env
->nip
= KERNEL_LOAD_ADDR
;
360 #ifdef DEBUG_BOARD_INIT
361 printf("bdloc " RAM_ADDR_FMT
"\n", bdloc
);
362 printf("%s: Done\n", __func__
);
366 static QEMUMachine ref405ep_machine
= {
369 .init
= ref405ep_init
,
370 DEFAULT_MACHINE_OPTIONS
,
373 /*****************************************************************************/
374 /* AMCC Taihu evaluation board */
375 /* - PowerPC 405EP processor
376 * - SDRAM 128 MB at 0x00000000
377 * - Boot flash 2 MB at 0xFFE00000
378 * - Application flash 32 MB at 0xFC000000
381 * - 1 USB 1.1 device 0x50000000
382 * - 1 LCD display 0x50100000
383 * - 1 CPLD 0x50100000
385 * - 1 I2C thermal sensor
387 * - bit-bang SPI port using GPIOs
388 * - 1 EBC interface connector 0 0x50200000
389 * - 1 cardbus controller + expansion slot.
390 * - 1 PCI expansion slot.
392 typedef struct taihu_cpld_t taihu_cpld_t
;
393 struct taihu_cpld_t
{
398 static uint32_t taihu_cpld_readb (void *opaque
, hwaddr addr
)
419 static void taihu_cpld_writeb (void *opaque
,
420 hwaddr addr
, uint32_t value
)
437 static uint32_t taihu_cpld_readw (void *opaque
, hwaddr addr
)
441 ret
= taihu_cpld_readb(opaque
, addr
) << 8;
442 ret
|= taihu_cpld_readb(opaque
, addr
+ 1);
447 static void taihu_cpld_writew (void *opaque
,
448 hwaddr addr
, uint32_t value
)
450 taihu_cpld_writeb(opaque
, addr
, (value
>> 8) & 0xFF);
451 taihu_cpld_writeb(opaque
, addr
+ 1, value
& 0xFF);
454 static uint32_t taihu_cpld_readl (void *opaque
, hwaddr addr
)
458 ret
= taihu_cpld_readb(opaque
, addr
) << 24;
459 ret
|= taihu_cpld_readb(opaque
, addr
+ 1) << 16;
460 ret
|= taihu_cpld_readb(opaque
, addr
+ 2) << 8;
461 ret
|= taihu_cpld_readb(opaque
, addr
+ 3);
466 static void taihu_cpld_writel (void *opaque
,
467 hwaddr addr
, uint32_t value
)
469 taihu_cpld_writel(opaque
, addr
, (value
>> 24) & 0xFF);
470 taihu_cpld_writel(opaque
, addr
+ 1, (value
>> 16) & 0xFF);
471 taihu_cpld_writel(opaque
, addr
+ 2, (value
>> 8) & 0xFF);
472 taihu_cpld_writeb(opaque
, addr
+ 3, value
& 0xFF);
475 static const MemoryRegionOps taihu_cpld_ops
= {
477 .read
= { taihu_cpld_readb
, taihu_cpld_readw
, taihu_cpld_readl
, },
478 .write
= { taihu_cpld_writeb
, taihu_cpld_writew
, taihu_cpld_writel
, },
480 .endianness
= DEVICE_NATIVE_ENDIAN
,
483 static void taihu_cpld_reset (void *opaque
)
492 static void taihu_cpld_init(MemoryRegion
*sysmem
, uint32_t base
)
495 MemoryRegion
*cpld_memory
= g_new(MemoryRegion
, 1);
497 cpld
= g_malloc0(sizeof(taihu_cpld_t
));
498 memory_region_init_io(cpld_memory
, NULL
, &taihu_cpld_ops
, cpld
, "cpld", 0x100);
499 memory_region_add_subregion(sysmem
, base
, cpld_memory
);
500 qemu_register_reset(&taihu_cpld_reset
, cpld
);
503 static void taihu_405ep_init(QEMUMachineInitArgs
*args
)
505 ram_addr_t ram_size
= args
->ram_size
;
506 const char *kernel_filename
= args
->kernel_filename
;
507 const char *initrd_filename
= args
->initrd_filename
;
510 MemoryRegion
*sysmem
= get_system_memory();
512 MemoryRegion
*ram_memories
= g_malloc(2 * sizeof(*ram_memories
));
513 hwaddr ram_bases
[2], ram_sizes
[2];
515 target_ulong kernel_base
, initrd_base
;
516 long kernel_size
, initrd_size
;
518 int fl_idx
, fl_sectors
;
521 /* RAM is soldered to the board so the size cannot be changed */
522 memory_region_init_ram(&ram_memories
[0], NULL
,
523 "taihu_405ep.ram-0", 0x04000000);
524 vmstate_register_ram_global(&ram_memories
[0]);
526 ram_sizes
[0] = 0x04000000;
527 memory_region_init_ram(&ram_memories
[1], NULL
,
528 "taihu_405ep.ram-1", 0x04000000);
529 vmstate_register_ram_global(&ram_memories
[1]);
530 ram_bases
[1] = 0x04000000;
531 ram_sizes
[1] = 0x04000000;
532 ram_size
= 0x08000000;
533 #ifdef DEBUG_BOARD_INIT
534 printf("%s: register cpu\n", __func__
);
536 ppc405ep_init(sysmem
, ram_memories
, ram_bases
, ram_sizes
,
537 33333333, &pic
, kernel_filename
== NULL
? 0 : 1);
538 /* allocate and load BIOS */
539 #ifdef DEBUG_BOARD_INIT
540 printf("%s: register BIOS\n", __func__
);
543 #if defined(USE_FLASH_BIOS)
544 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
546 bios_size
= bdrv_getlength(dinfo
->bdrv
);
547 /* XXX: should check that size is 2MB */
548 // bios_size = 2 * 1024 * 1024;
549 fl_sectors
= (bios_size
+ 65535) >> 16;
550 #ifdef DEBUG_BOARD_INIT
551 printf("Register parallel flash %d size %lx"
552 " at addr %lx '%s' %d\n",
553 fl_idx
, bios_size
, -bios_size
,
554 bdrv_get_device_name(dinfo
->bdrv
), fl_sectors
);
556 pflash_cfi02_register((uint32_t)(-bios_size
),
557 NULL
, "taihu_405ep.bios", bios_size
,
558 dinfo
->bdrv
, 65536, fl_sectors
, 1,
559 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
565 #ifdef DEBUG_BOARD_INIT
566 printf("Load BIOS from file\n");
568 if (bios_name
== NULL
)
569 bios_name
= BIOS_FILENAME
;
570 bios
= g_new(MemoryRegion
, 1);
571 memory_region_init_ram(bios
, NULL
, "taihu_405ep.bios", BIOS_SIZE
);
572 vmstate_register_ram_global(bios
);
573 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
575 bios_size
= load_image(filename
, memory_region_get_ram_ptr(bios
));
577 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
578 error_report("Could not load PowerPC BIOS '%s'", bios_name
);
581 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
582 memory_region_add_subregion(sysmem
, (uint32_t)(-bios_size
), bios
);
583 } else if (!qtest_enabled()) {
584 error_report("Could not load PowerPC BIOS '%s'", bios_name
);
587 memory_region_set_readonly(bios
, true);
589 /* Register Linux flash */
590 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
592 bios_size
= bdrv_getlength(dinfo
->bdrv
);
593 /* XXX: should check that size is 32MB */
594 bios_size
= 32 * 1024 * 1024;
595 fl_sectors
= (bios_size
+ 65535) >> 16;
596 #ifdef DEBUG_BOARD_INIT
597 printf("Register parallel flash %d size %lx"
598 " at addr " TARGET_FMT_lx
" '%s'\n",
599 fl_idx
, bios_size
, (target_ulong
)0xfc000000,
600 bdrv_get_device_name(dinfo
->bdrv
));
602 pflash_cfi02_register(0xfc000000, NULL
, "taihu_405ep.flash", bios_size
,
603 dinfo
->bdrv
, 65536, fl_sectors
, 1,
604 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
608 /* Register CLPD & LCD display */
609 #ifdef DEBUG_BOARD_INIT
610 printf("%s: register CPLD\n", __func__
);
612 taihu_cpld_init(sysmem
, 0x50100000);
614 linux_boot
= (kernel_filename
!= NULL
);
616 #ifdef DEBUG_BOARD_INIT
617 printf("%s: load kernel\n", __func__
);
619 kernel_base
= KERNEL_LOAD_ADDR
;
620 /* now we can load the kernel */
621 kernel_size
= load_image_targphys(kernel_filename
, kernel_base
,
622 ram_size
- kernel_base
);
623 if (kernel_size
< 0) {
624 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
629 if (initrd_filename
) {
630 initrd_base
= INITRD_LOAD_ADDR
;
631 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
632 ram_size
- initrd_base
);
633 if (initrd_size
< 0) {
635 "qemu: could not load initial ram disk '%s'\n",
649 #ifdef DEBUG_BOARD_INIT
650 printf("%s: Done\n", __func__
);
654 static QEMUMachine taihu_machine
= {
657 .init
= taihu_405ep_init
,
658 DEFAULT_MACHINE_OPTIONS
,
661 static void ppc405_machine_init(void)
663 qemu_register_machine(&ref405ep_machine
);
664 qemu_register_machine(&taihu_machine
);
667 machine_init(ppc405_machine_init
);