hw/ppc/ppc440_uc.c

   1 /*
   2  * QEMU PowerPC 440 embedded processors emulation
   3  *
   4  * Copyright (c) 2012 François Revol
   5  * Copyright (c) 2016-2019 BALATON Zoltan
   6  *
   7  * This work is licensed under the GNU GPL license version 2 or later.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qemu/units.h"
  13 #include "qemu/error-report.h"
  14 #include "qapi/error.h"
  15 #include "qemu/log.h"
  16 #include "qemu/module.h"
  17 #include "hw/irq.h"
  18 #include "exec/memory.h"
  19 #include "hw/ppc/ppc4xx.h"
  20 #include "hw/qdev-properties.h"
  21 #include "hw/pci/pci.h"
  22 #include "sysemu/block-backend.h"
  23 #include "sysemu/reset.h"
  24 #include "ppc440.h"
  25 #include "qom/object.h"
  26 #include "trace.h"
  27
  28 /*****************************************************************************/
  29 /* L2 Cache as SRAM */
  30 /* FIXME:fix names */
  31 enum {
  32     DCR_L2CACHE_BASE  = 0x30,
  33     DCR_L2CACHE_CFG   = DCR_L2CACHE_BASE,
  34     DCR_L2CACHE_CMD,
  35     DCR_L2CACHE_ADDR,
  36     DCR_L2CACHE_DATA,
  37     DCR_L2CACHE_STAT,
  38     DCR_L2CACHE_CVER,
  39     DCR_L2CACHE_SNP0,
  40     DCR_L2CACHE_SNP1,
  41     DCR_L2CACHE_END   = DCR_L2CACHE_SNP1,
  42 };
  43
  44 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
  45 enum {
  46     DCR_ISRAM0_BASE   = 0x20,
  47     DCR_ISRAM0_SB0CR  = DCR_ISRAM0_BASE,
  48     DCR_ISRAM0_SB1CR,
  49     DCR_ISRAM0_SB2CR,
  50     DCR_ISRAM0_SB3CR,
  51     DCR_ISRAM0_BEAR,
  52     DCR_ISRAM0_BESR0,
  53     DCR_ISRAM0_BESR1,
  54     DCR_ISRAM0_PMEG,
  55     DCR_ISRAM0_CID,
  56     DCR_ISRAM0_REVID,
  57     DCR_ISRAM0_DPC,
  58     DCR_ISRAM0_END    = DCR_ISRAM0_DPC
  59 };
  60
  61 enum {
  62     DCR_ISRAM1_BASE   = 0xb0,
  63     DCR_ISRAM1_SB0CR  = DCR_ISRAM1_BASE,
  64     /* single bank */
  65     DCR_ISRAM1_BEAR   = DCR_ISRAM1_BASE + 0x04,
  66     DCR_ISRAM1_BESR0,
  67     DCR_ISRAM1_BESR1,
  68     DCR_ISRAM1_PMEG,
  69     DCR_ISRAM1_CID,
  70     DCR_ISRAM1_REVID,
  71     DCR_ISRAM1_DPC,
  72     DCR_ISRAM1_END    = DCR_ISRAM1_DPC
  73 };
  74
  75 typedef struct ppc4xx_l2sram_t {
  76     MemoryRegion bank[4];
  77     uint32_t l2cache[8];
  78     uint32_t isram0[11];
  79 } ppc4xx_l2sram_t;
  80
  81 #ifdef MAP_L2SRAM
  82 static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram,
  83                                    uint32_t isarc, uint32_t isacntl,
  84                                    uint32_t dsarc, uint32_t dsacntl)
  85 {
  86     if (l2sram->isarc != isarc ||
  87         (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
  88         if (l2sram->isacntl & 0x80000000) {
  89             /* Unmap previously assigned memory region */
  90             memory_region_del_subregion(get_system_memory(),
  91                                         &l2sram->isarc_ram);
  92         }
  93         if (isacntl & 0x80000000) {
  94             /* Map new instruction memory region */
  95             memory_region_add_subregion(get_system_memory(), isarc,
  96                                         &l2sram->isarc_ram);
  97         }
  98     }
  99     if (l2sram->dsarc != dsarc ||
 100         (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
 101         if (l2sram->dsacntl & 0x80000000) {
 102             /* Beware not to unmap the region we just mapped */
 103             if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) {
 104                 /* Unmap previously assigned memory region */
 105                 memory_region_del_subregion(get_system_memory(),
 106                                             &l2sram->dsarc_ram);
 107             }
 108         }
 109         if (dsacntl & 0x80000000) {
 110             /* Beware not to remap the region we just mapped */
 111             if (!(isacntl & 0x80000000) || dsarc != isarc) {
 112                 /* Map new data memory region */
 113                 memory_region_add_subregion(get_system_memory(), dsarc,
 114                                             &l2sram->dsarc_ram);
 115             }
 116         }
 117     }
 118 }
 119 #endif
 120
 121 static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
 122 {
 123     ppc4xx_l2sram_t *l2sram = opaque;
 124     uint32_t ret = 0;
 125
 126     switch (dcrn) {
 127     case DCR_L2CACHE_CFG:
 128     case DCR_L2CACHE_CMD:
 129     case DCR_L2CACHE_ADDR:
 130     case DCR_L2CACHE_DATA:
 131     case DCR_L2CACHE_STAT:
 132     case DCR_L2CACHE_CVER:
 133     case DCR_L2CACHE_SNP0:
 134     case DCR_L2CACHE_SNP1:
 135         ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE];
 136         break;
 137
 138     case DCR_ISRAM0_SB0CR:
 139     case DCR_ISRAM0_SB1CR:
 140     case DCR_ISRAM0_SB2CR:
 141     case DCR_ISRAM0_SB3CR:
 142     case DCR_ISRAM0_BEAR:
 143     case DCR_ISRAM0_BESR0:
 144     case DCR_ISRAM0_BESR1:
 145     case DCR_ISRAM0_PMEG:
 146     case DCR_ISRAM0_CID:
 147     case DCR_ISRAM0_REVID:
 148     case DCR_ISRAM0_DPC:
 149         ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
 150         break;
 151
 152     default:
 153         break;
 154     }
 155
 156     return ret;
 157 }
 158
 159 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val)
 160 {
 161     /*ppc4xx_l2sram_t *l2sram = opaque;*/
 162     /* FIXME: Actually handle L2 cache mapping */
 163
 164     switch (dcrn) {
 165     case DCR_L2CACHE_CFG:
 166     case DCR_L2CACHE_CMD:
 167     case DCR_L2CACHE_ADDR:
 168     case DCR_L2CACHE_DATA:
 169     case DCR_L2CACHE_STAT:
 170     case DCR_L2CACHE_CVER:
 171     case DCR_L2CACHE_SNP0:
 172     case DCR_L2CACHE_SNP1:
 173         /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
 174         break;
 175
 176     case DCR_ISRAM0_SB0CR:
 177     case DCR_ISRAM0_SB1CR:
 178     case DCR_ISRAM0_SB2CR:
 179     case DCR_ISRAM0_SB3CR:
 180     case DCR_ISRAM0_BEAR:
 181     case DCR_ISRAM0_BESR0:
 182     case DCR_ISRAM0_BESR1:
 183     case DCR_ISRAM0_PMEG:
 184     case DCR_ISRAM0_CID:
 185     case DCR_ISRAM0_REVID:
 186     case DCR_ISRAM0_DPC:
 187         /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
 188         break;
 189
 190     case DCR_ISRAM1_SB0CR:
 191     case DCR_ISRAM1_BEAR:
 192     case DCR_ISRAM1_BESR0:
 193     case DCR_ISRAM1_BESR1:
 194     case DCR_ISRAM1_PMEG:
 195     case DCR_ISRAM1_CID:
 196     case DCR_ISRAM1_REVID:
 197     case DCR_ISRAM1_DPC:
 198         /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
 199         break;
 200     }
 201     /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
 202 }
 203
 204 static void l2sram_reset(void *opaque)
 205 {
 206     ppc4xx_l2sram_t *l2sram = opaque;
 207
 208     memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache));
 209     l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000;
 210     memset(l2sram->isram0, 0, sizeof(l2sram->isram0));
 211     /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
 212 }
 213
 214 void ppc4xx_l2sram_init(CPUPPCState *env)
 215 {
 216     ppc4xx_l2sram_t *l2sram;
 217
 218     l2sram = g_malloc0(sizeof(*l2sram));
 219     /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
 220     memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0",
 221                            64 * KiB, &error_abort);
 222     memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1",
 223                            64 * KiB, &error_abort);
 224     memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2",
 225                            64 * KiB, &error_abort);
 226     memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3",
 227                            64 * KiB, &error_abort);
 228     qemu_register_reset(&l2sram_reset, l2sram);
 229     ppc_dcr_register(env, DCR_L2CACHE_CFG,
 230                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 231     ppc_dcr_register(env, DCR_L2CACHE_CMD,
 232                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 233     ppc_dcr_register(env, DCR_L2CACHE_ADDR,
 234                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 235     ppc_dcr_register(env, DCR_L2CACHE_DATA,
 236                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 237     ppc_dcr_register(env, DCR_L2CACHE_STAT,
 238                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 239     ppc_dcr_register(env, DCR_L2CACHE_CVER,
 240                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 241     ppc_dcr_register(env, DCR_L2CACHE_SNP0,
 242                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 243     ppc_dcr_register(env, DCR_L2CACHE_SNP1,
 244                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 245
 246     ppc_dcr_register(env, DCR_ISRAM0_SB0CR,
 247                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 248     ppc_dcr_register(env, DCR_ISRAM0_SB1CR,
 249                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 250     ppc_dcr_register(env, DCR_ISRAM0_SB2CR,
 251                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 252     ppc_dcr_register(env, DCR_ISRAM0_SB3CR,
 253                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 254     ppc_dcr_register(env, DCR_ISRAM0_PMEG,
 255                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 256     ppc_dcr_register(env, DCR_ISRAM0_DPC,
 257                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 258
 259     ppc_dcr_register(env, DCR_ISRAM1_SB0CR,
 260                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 261     ppc_dcr_register(env, DCR_ISRAM1_PMEG,
 262                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 263     ppc_dcr_register(env, DCR_ISRAM1_DPC,
 264                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 265 }
 266
 267 /*****************************************************************************/
 268 /* Clocking Power on Reset */
 269 enum {
 270     CPR0_CFGADDR = 0xC,
 271     CPR0_CFGDATA = 0xD,
 272
 273     CPR0_PLLD = 0x060,
 274     CPR0_PLBED = 0x080,
 275     CPR0_OPBD = 0x0C0,
 276     CPR0_PERD = 0x0E0,
 277     CPR0_AHBD = 0x100,
 278 };
 279
 280 typedef struct ppc4xx_cpr_t {
 281     uint32_t addr;
 282 } ppc4xx_cpr_t;
 283
 284 static uint32_t dcr_read_cpr(void *opaque, int dcrn)
 285 {
 286     ppc4xx_cpr_t *cpr = opaque;
 287     uint32_t ret = 0;
 288
 289     switch (dcrn) {
 290     case CPR0_CFGADDR:
 291         ret = cpr->addr;
 292         break;
 293     case CPR0_CFGDATA:
 294         switch (cpr->addr) {
 295         case CPR0_PLLD:
 296             ret = (0xb5 << 24) | (1 << 16) | (9 << 8);
 297             break;
 298         case CPR0_PLBED:
 299             ret = (5 << 24);
 300             break;
 301         case CPR0_OPBD:
 302             ret = (2 << 24);
 303             break;
 304         case CPR0_PERD:
 305         case CPR0_AHBD:
 306             ret = (1 << 24);
 307             break;
 308         default:
 309             break;
 310         }
 311         break;
 312     default:
 313         break;
 314     }
 315
 316     return ret;
 317 }
 318
 319 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val)
 320 {
 321     ppc4xx_cpr_t *cpr = opaque;
 322
 323     switch (dcrn) {
 324     case CPR0_CFGADDR:
 325         cpr->addr = val;
 326         break;
 327     case CPR0_CFGDATA:
 328         break;
 329     default:
 330         break;
 331     }
 332 }
 333
 334 static void ppc4xx_cpr_reset(void *opaque)
 335 {
 336     ppc4xx_cpr_t *cpr = opaque;
 337
 338     cpr->addr = 0;
 339 }
 340
 341 void ppc4xx_cpr_init(CPUPPCState *env)
 342 {
 343     ppc4xx_cpr_t *cpr;
 344
 345     cpr = g_malloc0(sizeof(*cpr));
 346     ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr);
 347     ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr);
 348     qemu_register_reset(ppc4xx_cpr_reset, cpr);
 349 }
 350
 351 /*****************************************************************************/
 352 /* System DCRs */
 353 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t;
 354 struct ppc4xx_sdr_t {
 355     uint32_t addr;
 356 };
 357
 358 enum {
 359     SDR0_CFGADDR = 0x00e,
 360     SDR0_CFGDATA,
 361     SDR0_STRP0 = 0x020,
 362     SDR0_STRP1,
 363     SDR0_102 = 0x66,
 364     SDR0_103,
 365     SDR0_128 = 0x80,
 366     SDR0_ECID3 = 0x083,
 367     SDR0_DDR0 = 0x0e1,
 368     SDR0_USB0 = 0x320,
 369 };
 370
 371 enum {
 372     PESDR0_LOOP = 0x303,
 373     PESDR0_RCSSET,
 374     PESDR0_RCSSTS,
 375     PESDR0_RSTSTA = 0x310,
 376     PESDR1_LOOP = 0x343,
 377     PESDR1_RCSSET,
 378     PESDR1_RCSSTS,
 379     PESDR1_RSTSTA = 0x365,
 380 };
 381
 382 #define SDR0_DDR0_DDRM_ENCODE(n)  ((((unsigned long)(n)) & 0x03) << 29)
 383 #define SDR0_DDR0_DDRM_DDR1       0x20000000
 384 #define SDR0_DDR0_DDRM_DDR2       0x40000000
 385
 386 static uint32_t dcr_read_sdr(void *opaque, int dcrn)
 387 {
 388     ppc4xx_sdr_t *sdr = opaque;
 389     uint32_t ret = 0;
 390
 391     switch (dcrn) {
 392     case SDR0_CFGADDR:
 393         ret = sdr->addr;
 394         break;
 395     case SDR0_CFGDATA:
 396         switch (sdr->addr) {
 397         case SDR0_STRP0:
 398             ret = (0xb5 << 8) | (1 << 4) | 9;
 399             break;
 400         case SDR0_STRP1:
 401             ret = (5 << 29) | (2 << 26) | (1 << 24);
 402             break;
 403         case SDR0_ECID3:
 404             ret = 1 << 20; /* No Security/Kasumi support */
 405             break;
 406         case SDR0_DDR0:
 407             ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
 408             break;
 409         case PESDR0_RCSSET:
 410         case PESDR1_RCSSET:
 411             ret = (1 << 24) | (1 << 16);
 412             break;
 413         case PESDR0_RCSSTS:
 414         case PESDR1_RCSSTS:
 415             ret = (1 << 16) | (1 << 12);
 416             break;
 417         case PESDR0_RSTSTA:
 418         case PESDR1_RSTSTA:
 419             ret = 1;
 420             break;
 421         case PESDR0_LOOP:
 422         case PESDR1_LOOP:
 423             ret = 1 << 12;
 424             break;
 425         default:
 426             break;
 427         }
 428         break;
 429     default:
 430         break;
 431     }
 432
 433     return ret;
 434 }
 435
 436 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val)
 437 {
 438     ppc4xx_sdr_t *sdr = opaque;
 439
 440     switch (dcrn) {
 441     case SDR0_CFGADDR:
 442         sdr->addr = val;
 443         break;
 444     case SDR0_CFGDATA:
 445         switch (sdr->addr) {
 446         case 0x00: /* B0CR */
 447             break;
 448         default:
 449             break;
 450         }
 451         break;
 452     default:
 453         break;
 454     }
 455 }
 456
 457 static void sdr_reset(void *opaque)
 458 {
 459     ppc4xx_sdr_t *sdr = opaque;
 460
 461     sdr->addr = 0;
 462 }
 463
 464 void ppc4xx_sdr_init(CPUPPCState *env)
 465 {
 466     ppc4xx_sdr_t *sdr;
 467
 468     sdr = g_malloc0(sizeof(*sdr));
 469     qemu_register_reset(&sdr_reset, sdr);
 470     ppc_dcr_register(env, SDR0_CFGADDR,
 471                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 472     ppc_dcr_register(env, SDR0_CFGDATA,
 473                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 474     ppc_dcr_register(env, SDR0_102,
 475                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 476     ppc_dcr_register(env, SDR0_103,
 477                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 478     ppc_dcr_register(env, SDR0_128,
 479                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 480     ppc_dcr_register(env, SDR0_USB0,
 481                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 482 }
 483
 484 /*****************************************************************************/
 485 /* SDRAM controller */
 486 typedef struct ppc440_sdram_t {
 487     uint32_t addr;
 488     int nbanks;
 489     Ppc4xxSdramBank bank[4];
 490 } ppc440_sdram_t;
 491
 492 enum {
 493     SDRAM0_CFGADDR = 0x10,
 494     SDRAM0_CFGDATA,
 495     SDRAM_R0BAS = 0x40,
 496     SDRAM_R1BAS,
 497     SDRAM_R2BAS,
 498     SDRAM_R3BAS,
 499     SDRAM_CONF1HB = 0x45,
 500     SDRAM_PLBADDULL = 0x4a,
 501     SDRAM_CONF1LL = 0x4b,
 502     SDRAM_CONFPATHB = 0x4f,
 503     SDRAM_PLBADDUHB = 0x50,
 504 };
 505
 506 static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
 507 {
 508     uint32_t bcr;
 509
 510     switch (ram_size) {
 511     case (8 * MiB):
 512         bcr = 0xffc0;
 513         break;
 514     case (16 * MiB):
 515         bcr = 0xff80;
 516         break;
 517     case (32 * MiB):
 518         bcr = 0xff00;
 519         break;
 520     case (64 * MiB):
 521         bcr = 0xfe00;
 522         break;
 523     case (128 * MiB):
 524         bcr = 0xfc00;
 525         break;
 526     case (256 * MiB):
 527         bcr = 0xf800;
 528         break;
 529     case (512 * MiB):
 530         bcr = 0xf000;
 531         break;
 532     case (1 * GiB):
 533         bcr = 0xe000;
 534         break;
 535     case (2 * GiB):
 536         bcr = 0xc000;
 537         break;
 538     case (4 * GiB):
 539         bcr = 0x8000;
 540         break;
 541     default:
 542         error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
 543         return 0;
 544     }
 545     bcr |= ram_base >> 2 & 0xffe00000;
 546     bcr |= 1;
 547
 548     return bcr;
 549 }
 550
 551 static inline hwaddr sdram_base(uint32_t bcr)
 552 {
 553     return (bcr & 0xffe00000) << 2;
 554 }
 555
 556 static uint64_t sdram_size(uint32_t bcr)
 557 {
 558     uint64_t size;
 559     int sh;
 560
 561     sh = 1024 - ((bcr >> 6) & 0x3ff);
 562     size = 8 * MiB * sh;
 563
 564     return size;
 565 }
 566
 567 static void sdram_bank_map(Ppc4xxSdramBank *bank)
 568 {
 569     memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
 570     memory_region_add_subregion(&bank->container, 0, &bank->ram);
 571     memory_region_add_subregion(get_system_memory(), bank->base,
 572                                 &bank->container);
 573 }
 574
 575 static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
 576 {
 577     memory_region_del_subregion(get_system_memory(), &bank->container);
 578     memory_region_del_subregion(&bank->container, &bank->ram);
 579     object_unparent(OBJECT(&bank->container));
 580 }
 581
 582 static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
 583                           uint32_t bcr, int enabled)
 584 {
 585     if (sdram->bank[i].bcr & 1) {
 586         /* First unmap RAM if enabled */
 587         trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
 588                                  sdram_size(sdram->bank[i].bcr));
 589         sdram_bank_unmap(&sdram->bank[i]);
 590     }
 591     sdram->bank[i].bcr = bcr & 0xffe0ffc1;
 592     if (enabled && (bcr & 1)) {
 593         trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
 594         sdram_bank_map(&sdram->bank[i]);
 595     }
 596 }
 597
 598 static void sdram_map_bcr(ppc440_sdram_t *sdram)
 599 {
 600     int i;
 601
 602     for (i = 0; i < sdram->nbanks; i++) {
 603         if (sdram->bank[i].size != 0) {
 604             sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
 605                                               sdram->bank[i].size), 1);
 606         } else {
 607             sdram_set_bcr(sdram, i, 0, 0);
 608         }
 609     }
 610 }
 611
 612 static uint32_t dcr_read_sdram(void *opaque, int dcrn)
 613 {
 614     ppc440_sdram_t *sdram = opaque;
 615     uint32_t ret = 0;
 616
 617     switch (dcrn) {
 618     case SDRAM_R0BAS:
 619     case SDRAM_R1BAS:
 620     case SDRAM_R2BAS:
 621     case SDRAM_R3BAS:
 622         if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
 623             ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
 624                             sdram->bank[dcrn - SDRAM_R0BAS].size);
 625         }
 626         break;
 627     case SDRAM_CONF1HB:
 628     case SDRAM_CONF1LL:
 629     case SDRAM_CONFPATHB:
 630     case SDRAM_PLBADDULL:
 631     case SDRAM_PLBADDUHB:
 632         break;
 633     case SDRAM0_CFGADDR:
 634         ret = sdram->addr;
 635         break;
 636     case SDRAM0_CFGDATA:
 637         switch (sdram->addr) {
 638         case 0x14: /* SDRAM_MCSTAT (405EX) */
 639         case 0x1F:
 640             ret = 0x80000000;
 641             break;
 642         case 0x21: /* SDRAM_MCOPT2 */
 643             ret = 0x08000000;
 644             break;
 645         case 0x40: /* SDRAM_MB0CF */
 646             ret = 0x00008001;
 647             break;
 648         case 0x7A: /* SDRAM_DLCR */
 649             ret = 0x02000000;
 650             break;
 651         case 0xE1: /* SDR0_DDR0 */
 652             ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
 653             break;
 654         default:
 655             break;
 656         }
 657         break;
 658     default:
 659         break;
 660     }
 661
 662     return ret;
 663 }
 664
 665 static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
 666 {
 667     ppc440_sdram_t *sdram = opaque;
 668
 669     switch (dcrn) {
 670     case SDRAM_R0BAS:
 671     case SDRAM_R1BAS:
 672     case SDRAM_R2BAS:
 673     case SDRAM_R3BAS:
 674     case SDRAM_CONF1HB:
 675     case SDRAM_CONF1LL:
 676     case SDRAM_CONFPATHB:
 677     case SDRAM_PLBADDULL:
 678     case SDRAM_PLBADDUHB:
 679         break;
 680     case SDRAM0_CFGADDR:
 681         sdram->addr = val;
 682         break;
 683     case SDRAM0_CFGDATA:
 684         switch (sdram->addr) {
 685         case 0x00: /* B0CR */
 686             break;
 687         default:
 688             break;
 689         }
 690         break;
 691     default:
 692         break;
 693     }
 694 }
 695
 696 static void sdram_reset(void *opaque)
 697 {
 698     ppc440_sdram_t *sdram = opaque;
 699
 700     sdram->addr = 0;
 701 }
 702
 703 void ppc440_sdram_init(CPUPPCState *env, int nbanks,
 704                        Ppc4xxSdramBank *ram_banks,
 705                        int do_init)
 706 {
 707     ppc440_sdram_t *sdram;
 708     int i;
 709
 710     sdram = g_malloc0(sizeof(*sdram));
 711     sdram->nbanks = nbanks;
 712     for (i = 0; i < nbanks; i++) {
 713         sdram->bank[i].ram = ram_banks[i].ram;
 714         sdram->bank[i].base = ram_banks[i].base;
 715         sdram->bank[i].size = ram_banks[i].size;
 716     }
 717     qemu_register_reset(&sdram_reset, sdram);
 718     ppc_dcr_register(env, SDRAM0_CFGADDR,
 719                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 720     ppc_dcr_register(env, SDRAM0_CFGDATA,
 721                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 722     if (do_init) {
 723         sdram_map_bcr(sdram);
 724     }
 725
 726     ppc_dcr_register(env, SDRAM_R0BAS,
 727                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 728     ppc_dcr_register(env, SDRAM_R1BAS,
 729                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 730     ppc_dcr_register(env, SDRAM_R2BAS,
 731                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 732     ppc_dcr_register(env, SDRAM_R3BAS,
 733                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 734     ppc_dcr_register(env, SDRAM_CONF1HB,
 735                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 736     ppc_dcr_register(env, SDRAM_PLBADDULL,
 737                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 738     ppc_dcr_register(env, SDRAM_CONF1LL,
 739                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 740     ppc_dcr_register(env, SDRAM_CONFPATHB,
 741                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 742     ppc_dcr_register(env, SDRAM_PLBADDUHB,
 743                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 744 }
 745
 746 /*****************************************************************************/
 747 /* PLB to AHB bridge */
 748 enum {
 749     AHB_TOP    = 0xA4,
 750     AHB_BOT    = 0xA5,
 751 };
 752
 753 typedef struct ppc4xx_ahb_t {
 754     uint32_t top;
 755     uint32_t bot;
 756 } ppc4xx_ahb_t;
 757
 758 static uint32_t dcr_read_ahb(void *opaque, int dcrn)
 759 {
 760     ppc4xx_ahb_t *ahb = opaque;
 761     uint32_t ret = 0;
 762
 763     switch (dcrn) {
 764     case AHB_TOP:
 765         ret = ahb->top;
 766         break;
 767     case AHB_BOT:
 768         ret = ahb->bot;
 769         break;
 770     default:
 771         break;
 772     }
 773
 774     return ret;
 775 }
 776
 777 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val)
 778 {
 779     ppc4xx_ahb_t *ahb = opaque;
 780
 781     switch (dcrn) {
 782     case AHB_TOP:
 783         ahb->top = val;
 784         break;
 785     case AHB_BOT:
 786         ahb->bot = val;
 787         break;
 788     }
 789 }
 790
 791 static void ppc4xx_ahb_reset(void *opaque)
 792 {
 793     ppc4xx_ahb_t *ahb = opaque;
 794
 795     /* No error */
 796     ahb->top = 0;
 797     ahb->bot = 0;
 798 }
 799
 800 void ppc4xx_ahb_init(CPUPPCState *env)
 801 {
 802     ppc4xx_ahb_t *ahb;
 803
 804     ahb = g_malloc0(sizeof(*ahb));
 805     ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb);
 806     ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb);
 807     qemu_register_reset(ppc4xx_ahb_reset, ahb);
 808 }
 809
 810 /*****************************************************************************/
 811 /* DMA controller */
 812
 813 #define DMA0_CR_CE  (1 << 31)
 814 #define DMA0_CR_PW  (1 << 26 | 1 << 25)
 815 #define DMA0_CR_DAI (1 << 24)
 816 #define DMA0_CR_SAI (1 << 23)
 817 #define DMA0_CR_DEC (1 << 2)
 818
 819 enum {
 820     DMA0_CR  = 0x00,
 821     DMA0_CT,
 822     DMA0_SAH,
 823     DMA0_SAL,
 824     DMA0_DAH,
 825     DMA0_DAL,
 826     DMA0_SGH,
 827     DMA0_SGL,
 828
 829     DMA0_SR  = 0x20,
 830     DMA0_SGC = 0x23,
 831     DMA0_SLP = 0x25,
 832     DMA0_POL = 0x26,
 833 };
 834
 835 typedef struct {
 836     uint32_t cr;
 837     uint32_t ct;
 838     uint64_t sa;
 839     uint64_t da;
 840     uint64_t sg;
 841 } PPC4xxDmaChnl;
 842
 843 typedef struct {
 844     int base;
 845     PPC4xxDmaChnl ch[4];
 846     uint32_t sr;
 847 } PPC4xxDmaState;
 848
 849 static uint32_t dcr_read_dma(void *opaque, int dcrn)
 850 {
 851     PPC4xxDmaState *dma = opaque;
 852     uint32_t val = 0;
 853     int addr = dcrn - dma->base;
 854     int chnl = addr / 8;
 855
 856     switch (addr) {
 857     case 0x00 ... 0x1f:
 858         switch (addr % 8) {
 859         case DMA0_CR:
 860             val = dma->ch[chnl].cr;
 861             break;
 862         case DMA0_CT:
 863             val = dma->ch[chnl].ct;
 864             break;
 865         case DMA0_SAH:
 866             val = dma->ch[chnl].sa >> 32;
 867             break;
 868         case DMA0_SAL:
 869             val = dma->ch[chnl].sa;
 870             break;
 871         case DMA0_DAH:
 872             val = dma->ch[chnl].da >> 32;
 873             break;
 874         case DMA0_DAL:
 875             val = dma->ch[chnl].da;
 876             break;
 877         case DMA0_SGH:
 878             val = dma->ch[chnl].sg >> 32;
 879             break;
 880         case DMA0_SGL:
 881             val = dma->ch[chnl].sg;
 882             break;
 883         }
 884         break;
 885     case DMA0_SR:
 886         val = dma->sr;
 887         break;
 888     default:
 889         qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
 890                       __func__, dcrn, chnl, addr);
 891     }
 892
 893     return val;
 894 }
 895
 896 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
 897 {
 898     PPC4xxDmaState *dma = opaque;
 899     int addr = dcrn - dma->base;
 900     int chnl = addr / 8;
 901
 902     switch (addr) {
 903     case 0x00 ... 0x1f:
 904         switch (addr % 8) {
 905         case DMA0_CR:
 906             dma->ch[chnl].cr = val;
 907             if (val & DMA0_CR_CE) {
 908                 int count = dma->ch[chnl].ct & 0xffff;
 909
 910                 if (count) {
 911                     int width, i, sidx, didx;
 912                     uint8_t *rptr, *wptr;
 913                     hwaddr rlen, wlen;
 914                     hwaddr xferlen;
 915
 916                     sidx = didx = 0;
 917                     width = 1 << ((val & DMA0_CR_PW) >> 25);
 918                     xferlen = count * width;
 919                     wlen = rlen = xferlen;
 920                     rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen,
 921                                                    false);
 922                     wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen,
 923                                                    true);
 924                     if (rptr && rlen == xferlen && wptr && wlen == xferlen) {
 925                         if (!(val & DMA0_CR_DEC) &&
 926                             val & DMA0_CR_SAI && val & DMA0_CR_DAI) {
 927                             /* optimise common case */
 928                             memmove(wptr, rptr, count * width);
 929                             sidx = didx = count * width;
 930                         } else {
 931                             /* do it the slow way */
 932                             for (sidx = didx = i = 0; i < count; i++) {
 933                                 uint64_t v = ldn_le_p(rptr + sidx, width);
 934                                 stn_le_p(wptr + didx, width, v);
 935                                 if (val & DMA0_CR_SAI) {
 936                                     sidx += width;
 937                                 }
 938                                 if (val & DMA0_CR_DAI) {
 939                                     didx += width;
 940                                 }
 941                             }
 942                         }
 943                     }
 944                     if (wptr) {
 945                         cpu_physical_memory_unmap(wptr, wlen, 1, didx);
 946                     }
 947                     if (rptr) {
 948                         cpu_physical_memory_unmap(rptr, rlen, 0, sidx);
 949                     }
 950                 }
 951             }
 952             break;
 953         case DMA0_CT:
 954             dma->ch[chnl].ct = val;
 955             break;
 956         case DMA0_SAH:
 957             dma->ch[chnl].sa &= 0xffffffffULL;
 958             dma->ch[chnl].sa |= (uint64_t)val << 32;
 959             break;
 960         case DMA0_SAL:
 961             dma->ch[chnl].sa &= 0xffffffff00000000ULL;
 962             dma->ch[chnl].sa |= val;
 963             break;
 964         case DMA0_DAH:
 965             dma->ch[chnl].da &= 0xffffffffULL;
 966             dma->ch[chnl].da |= (uint64_t)val << 32;
 967             break;
 968         case DMA0_DAL:
 969             dma->ch[chnl].da &= 0xffffffff00000000ULL;
 970             dma->ch[chnl].da |= val;
 971             break;
 972         case DMA0_SGH:
 973             dma->ch[chnl].sg &= 0xffffffffULL;
 974             dma->ch[chnl].sg |= (uint64_t)val << 32;
 975             break;
 976         case DMA0_SGL:
 977             dma->ch[chnl].sg &= 0xffffffff00000000ULL;
 978             dma->ch[chnl].sg |= val;
 979             break;
 980         }
 981         break;
 982     case DMA0_SR:
 983         dma->sr &= ~val;
 984         break;
 985     default:
 986         qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
 987                       __func__, dcrn, chnl, addr);
 988     }
 989 }
 990
 991 static void ppc4xx_dma_reset(void *opaque)
 992 {
 993     PPC4xxDmaState *dma = opaque;
 994     int dma_base = dma->base;
 995
 996     memset(dma, 0, sizeof(*dma));
 997     dma->base = dma_base;
 998 }
 999
1000 void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
1001 {
1002     PPC4xxDmaState *dma;
1003     int i;
1004
1005     dma = g_malloc0(sizeof(*dma));
1006     dma->base = dcr_base;
1007     qemu_register_reset(&ppc4xx_dma_reset, dma);
1008     for (i = 0; i < 4; i++) {
1009         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR,
1010                          dma, &dcr_read_dma, &dcr_write_dma);
1011         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT,
1012                          dma, &dcr_read_dma, &dcr_write_dma);
1013         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH,
1014                          dma, &dcr_read_dma, &dcr_write_dma);
1015         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL,
1016                          dma, &dcr_read_dma, &dcr_write_dma);
1017         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH,
1018                          dma, &dcr_read_dma, &dcr_write_dma);
1019         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL,
1020                          dma, &dcr_read_dma, &dcr_write_dma);
1021         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH,
1022                          dma, &dcr_read_dma, &dcr_write_dma);
1023         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL,
1024                          dma, &dcr_read_dma, &dcr_write_dma);
1025     }
1026     ppc_dcr_register(env, dcr_base + DMA0_SR,
1027                      dma, &dcr_read_dma, &dcr_write_dma);
1028     ppc_dcr_register(env, dcr_base + DMA0_SGC,
1029                      dma, &dcr_read_dma, &dcr_write_dma);
1030     ppc_dcr_register(env, dcr_base + DMA0_SLP,
1031                      dma, &dcr_read_dma, &dcr_write_dma);
1032     ppc_dcr_register(env, dcr_base + DMA0_POL,
1033                      dma, &dcr_read_dma, &dcr_write_dma);
1034 }
1035
1036 /*****************************************************************************/
1037 /* PCI Express controller */
1038 /*
1039  * FIXME: This is not complete and does not work, only implemented partially
1040  * to allow firmware and guests to find an empty bus. Cards should use PCI.
1041  */
1042 #include "hw/pci/pcie_host.h"
1043
1044 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
1045 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST)
1046
1047 struct PPC460EXPCIEState {
1048     PCIExpressHost host;
1049
1050     MemoryRegion iomem;
1051     qemu_irq irq[4];
1052     int32_t dcrn_base;
1053
1054     uint64_t cfg_base;
1055     uint32_t cfg_mask;
1056     uint64_t msg_base;
1057     uint32_t msg_mask;
1058     uint64_t omr1_base;
1059     uint64_t omr1_mask;
1060     uint64_t omr2_base;
1061     uint64_t omr2_mask;
1062     uint64_t omr3_base;
1063     uint64_t omr3_mask;
1064     uint64_t reg_base;
1065     uint32_t reg_mask;
1066     uint32_t special;
1067     uint32_t cfg;
1068 };
1069
1070 #define DCRN_PCIE0_BASE 0x100
1071 #define DCRN_PCIE1_BASE 0x120
1072
1073 enum {
1074     PEGPL_CFGBAH = 0x0,
1075     PEGPL_CFGBAL,
1076     PEGPL_CFGMSK,
1077     PEGPL_MSGBAH,
1078     PEGPL_MSGBAL,
1079     PEGPL_MSGMSK,
1080     PEGPL_OMR1BAH,
1081     PEGPL_OMR1BAL,
1082     PEGPL_OMR1MSKH,
1083     PEGPL_OMR1MSKL,
1084     PEGPL_OMR2BAH,
1085     PEGPL_OMR2BAL,
1086     PEGPL_OMR2MSKH,
1087     PEGPL_OMR2MSKL,
1088     PEGPL_OMR3BAH,
1089     PEGPL_OMR3BAL,
1090     PEGPL_OMR3MSKH,
1091     PEGPL_OMR3MSKL,
1092     PEGPL_REGBAH,
1093     PEGPL_REGBAL,
1094     PEGPL_REGMSK,
1095     PEGPL_SPECIAL,
1096     PEGPL_CFG,
1097 };
1098
1099 static uint32_t dcr_read_pcie(void *opaque, int dcrn)
1100 {
1101     PPC460EXPCIEState *state = opaque;
1102     uint32_t ret = 0;
1103
1104     switch (dcrn - state->dcrn_base) {
1105     case PEGPL_CFGBAH:
1106         ret = state->cfg_base >> 32;
1107         break;
1108     case PEGPL_CFGBAL:
1109         ret = state->cfg_base;
1110         break;
1111     case PEGPL_CFGMSK:
1112         ret = state->cfg_mask;
1113         break;
1114     case PEGPL_MSGBAH:
1115         ret = state->msg_base >> 32;
1116         break;
1117     case PEGPL_MSGBAL:
1118         ret = state->msg_base;
1119         break;
1120     case PEGPL_MSGMSK:
1121         ret = state->msg_mask;
1122         break;
1123     case PEGPL_OMR1BAH:
1124         ret = state->omr1_base >> 32;
1125         break;
1126     case PEGPL_OMR1BAL:
1127         ret = state->omr1_base;
1128         break;
1129     case PEGPL_OMR1MSKH:
1130         ret = state->omr1_mask >> 32;
1131         break;
1132     case PEGPL_OMR1MSKL:
1133         ret = state->omr1_mask;
1134         break;
1135     case PEGPL_OMR2BAH:
1136         ret = state->omr2_base >> 32;
1137         break;
1138     case PEGPL_OMR2BAL:
1139         ret = state->omr2_base;
1140         break;
1141     case PEGPL_OMR2MSKH:
1142         ret = state->omr2_mask >> 32;
1143         break;
1144     case PEGPL_OMR2MSKL:
1145         ret = state->omr3_mask;
1146         break;
1147     case PEGPL_OMR3BAH:
1148         ret = state->omr3_base >> 32;
1149         break;
1150     case PEGPL_OMR3BAL:
1151         ret = state->omr3_base;
1152         break;
1153     case PEGPL_OMR3MSKH:
1154         ret = state->omr3_mask >> 32;
1155         break;
1156     case PEGPL_OMR3MSKL:
1157         ret = state->omr3_mask;
1158         break;
1159     case PEGPL_REGBAH:
1160         ret = state->reg_base >> 32;
1161         break;
1162     case PEGPL_REGBAL:
1163         ret = state->reg_base;
1164         break;
1165     case PEGPL_REGMSK:
1166         ret = state->reg_mask;
1167         break;
1168     case PEGPL_SPECIAL:
1169         ret = state->special;
1170         break;
1171     case PEGPL_CFG:
1172         ret = state->cfg;
1173         break;
1174     }
1175
1176     return ret;
1177 }
1178
1179 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val)
1180 {
1181     PPC460EXPCIEState *s = opaque;
1182     uint64_t size;
1183
1184     switch (dcrn - s->dcrn_base) {
1185     case PEGPL_CFGBAH:
1186         s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff);
1187         break;
1188     case PEGPL_CFGBAL:
1189         s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val;
1190         break;
1191     case PEGPL_CFGMSK:
1192         s->cfg_mask = val;
1193         size = ~(val & 0xfffffffe) + 1;
1194         /*
1195          * Firmware sets this register to E0000001. Why we are not sure,
1196          * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is
1197          * ignored.
1198          */
1199         if (size > PCIE_MMCFG_SIZE_MAX) {
1200             size = PCIE_MMCFG_SIZE_MAX;
1201         }
1202         pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size);
1203         break;
1204     case PEGPL_MSGBAH:
1205         s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff);
1206         break;
1207     case PEGPL_MSGBAL:
1208         s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val;
1209         break;
1210     case PEGPL_MSGMSK:
1211         s->msg_mask = val;
1212         break;
1213     case PEGPL_OMR1BAH:
1214         s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff);
1215         break;
1216     case PEGPL_OMR1BAL:
1217         s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val;
1218         break;
1219     case PEGPL_OMR1MSKH:
1220         s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff);
1221         break;
1222     case PEGPL_OMR1MSKL:
1223         s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val;
1224         break;
1225     case PEGPL_OMR2BAH:
1226         s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff);
1227         break;
1228     case PEGPL_OMR2BAL:
1229         s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val;
1230         break;
1231     case PEGPL_OMR2MSKH:
1232         s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff);
1233         break;
1234     case PEGPL_OMR2MSKL:
1235         s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val;
1236         break;
1237     case PEGPL_OMR3BAH:
1238         s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff);
1239         break;
1240     case PEGPL_OMR3BAL:
1241         s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val;
1242         break;
1243     case PEGPL_OMR3MSKH:
1244         s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff);
1245         break;
1246     case PEGPL_OMR3MSKL:
1247         s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val;
1248         break;
1249     case PEGPL_REGBAH:
1250         s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff);
1251         break;
1252     case PEGPL_REGBAL:
1253         s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val;
1254         break;
1255     case PEGPL_REGMSK:
1256         s->reg_mask = val;
1257         /* FIXME: how is size encoded? */
1258         size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1);
1259         break;
1260     case PEGPL_SPECIAL:
1261         s->special = val;
1262         break;
1263     case PEGPL_CFG:
1264         s->cfg = val;
1265         break;
1266     }
1267 }
1268
1269 static void ppc460ex_set_irq(void *opaque, int irq_num, int level)
1270 {
1271        PPC460EXPCIEState *s = opaque;
1272        qemu_set_irq(s->irq[irq_num], level);
1273 }
1274
1275 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp)
1276 {
1277     PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev);
1278     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
1279     int i, id;
1280     char buf[16];
1281
1282     switch (s->dcrn_base) {
1283     case DCRN_PCIE0_BASE:
1284         id = 0;
1285         break;
1286     case DCRN_PCIE1_BASE:
1287         id = 1;
1288         break;
1289     default:
1290         error_setg(errp, "invalid PCIe DCRN base");
1291         return;
1292     }
1293     snprintf(buf, sizeof(buf), "pcie%d-io", id);
1294     memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX);
1295     for (i = 0; i < 4; i++) {
1296         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1297     }
1298     snprintf(buf, sizeof(buf), "pcie.%d", id);
1299     pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq,
1300                                 pci_swizzle_map_irq_fn, s, &s->iomem,
1301                                 get_system_io(), 0, 4, TYPE_PCIE_BUS);
1302 }
1303
1304 static Property ppc460ex_pcie_props[] = {
1305     DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1),
1306     DEFINE_PROP_END_OF_LIST(),
1307 };
1308
1309 static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data)
1310 {
1311     DeviceClass *dc = DEVICE_CLASS(klass);
1312
1313     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1314     dc->realize = ppc460ex_pcie_realize;
1315     device_class_set_props(dc, ppc460ex_pcie_props);
1316     dc->hotpluggable = false;
1317 }
1318
1319 static const TypeInfo ppc460ex_pcie_host_info = {
1320     .name = TYPE_PPC460EX_PCIE_HOST,
1321     .parent = TYPE_PCIE_HOST_BRIDGE,
1322     .instance_size = sizeof(PPC460EXPCIEState),
1323     .class_init = ppc460ex_pcie_class_init,
1324 };
1325
1326 static void ppc460ex_pcie_register(void)
1327 {
1328     type_register_static(&ppc460ex_pcie_host_info);
1329 }
1330
1331 type_init(ppc460ex_pcie_register)
1332
1333 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env)
1334 {
1335     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s,
1336                      &dcr_read_pcie, &dcr_write_pcie);
1337     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s,
1338                      &dcr_read_pcie, &dcr_write_pcie);
1339     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s,
1340                      &dcr_read_pcie, &dcr_write_pcie);
1341     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s,
1342                      &dcr_read_pcie, &dcr_write_pcie);
1343     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s,
1344                      &dcr_read_pcie, &dcr_write_pcie);
1345     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s,
1346                      &dcr_read_pcie, &dcr_write_pcie);
1347     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s,
1348                      &dcr_read_pcie, &dcr_write_pcie);
1349     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s,
1350                      &dcr_read_pcie, &dcr_write_pcie);
1351     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s,
1352                      &dcr_read_pcie, &dcr_write_pcie);
1353     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s,
1354                      &dcr_read_pcie, &dcr_write_pcie);
1355     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s,
1356                      &dcr_read_pcie, &dcr_write_pcie);
1357     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s,
1358                      &dcr_read_pcie, &dcr_write_pcie);
1359     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s,
1360                      &dcr_read_pcie, &dcr_write_pcie);
1361     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s,
1362                      &dcr_read_pcie, &dcr_write_pcie);
1363     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s,
1364                      &dcr_read_pcie, &dcr_write_pcie);
1365     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s,
1366                      &dcr_read_pcie, &dcr_write_pcie);
1367     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s,
1368                      &dcr_read_pcie, &dcr_write_pcie);
1369     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s,
1370                      &dcr_read_pcie, &dcr_write_pcie);
1371     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s,
1372                      &dcr_read_pcie, &dcr_write_pcie);
1373     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s,
1374                      &dcr_read_pcie, &dcr_write_pcie);
1375     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s,
1376                      &dcr_read_pcie, &dcr_write_pcie);
1377     ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s,
1378                      &dcr_read_pcie, &dcr_write_pcie);
1379     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s,
1380                      &dcr_read_pcie, &dcr_write_pcie);
1381 }
1382
1383 void ppc460ex_pcie_init(CPUPPCState *env)
1384 {
1385     DeviceState *dev;
1386
1387     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
1388     qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
1389     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1390     ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
1391
1392     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
1393     qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
1394     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1395     ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
1396 }