hw/ppc/ppc440_uc.c

   1 /*
   2  * QEMU PowerPC 440 embedded processors emulation
   3  *
   4  * Copyright (c) 2012 François Revol
   5  * Copyright (c) 2016-2019 BALATON Zoltan
   6  *
   7  * This work is licensed under the GNU GPL license version 2 or later.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qemu/units.h"
  13 #include "qemu/error-report.h"
  14 #include "qapi/error.h"
  15 #include "qemu/log.h"
  16 #include "qemu/module.h"
  17 #include "hw/irq.h"
  18 #include "exec/memory.h"
  19 #include "cpu.h"
  20 #include "hw/ppc/ppc4xx.h"
  21 #include "hw/qdev-properties.h"
  22 #include "hw/pci/pci.h"
  23 #include "sysemu/block-backend.h"
  24 #include "sysemu/reset.h"
  25 #include "ppc440.h"
  26 #include "qom/object.h"
  27 #include "trace.h"
  28
  29 /*****************************************************************************/
  30 /* L2 Cache as SRAM */
  31 /* FIXME:fix names */
  32 enum {
  33     DCR_L2CACHE_BASE  = 0x30,
  34     DCR_L2CACHE_CFG   = DCR_L2CACHE_BASE,
  35     DCR_L2CACHE_CMD,
  36     DCR_L2CACHE_ADDR,
  37     DCR_L2CACHE_DATA,
  38     DCR_L2CACHE_STAT,
  39     DCR_L2CACHE_CVER,
  40     DCR_L2CACHE_SNP0,
  41     DCR_L2CACHE_SNP1,
  42     DCR_L2CACHE_END   = DCR_L2CACHE_SNP1,
  43 };
  44
  45 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
  46 enum {
  47     DCR_ISRAM0_BASE   = 0x20,
  48     DCR_ISRAM0_SB0CR  = DCR_ISRAM0_BASE,
  49     DCR_ISRAM0_SB1CR,
  50     DCR_ISRAM0_SB2CR,
  51     DCR_ISRAM0_SB3CR,
  52     DCR_ISRAM0_BEAR,
  53     DCR_ISRAM0_BESR0,
  54     DCR_ISRAM0_BESR1,
  55     DCR_ISRAM0_PMEG,
  56     DCR_ISRAM0_CID,
  57     DCR_ISRAM0_REVID,
  58     DCR_ISRAM0_DPC,
  59     DCR_ISRAM0_END    = DCR_ISRAM0_DPC
  60 };
  61
  62 enum {
  63     DCR_ISRAM1_BASE   = 0xb0,
  64     DCR_ISRAM1_SB0CR  = DCR_ISRAM1_BASE,
  65     /* single bank */
  66     DCR_ISRAM1_BEAR   = DCR_ISRAM1_BASE + 0x04,
  67     DCR_ISRAM1_BESR0,
  68     DCR_ISRAM1_BESR1,
  69     DCR_ISRAM1_PMEG,
  70     DCR_ISRAM1_CID,
  71     DCR_ISRAM1_REVID,
  72     DCR_ISRAM1_DPC,
  73     DCR_ISRAM1_END    = DCR_ISRAM1_DPC
  74 };
  75
  76 typedef struct ppc4xx_l2sram_t {
  77     MemoryRegion bank[4];
  78     uint32_t l2cache[8];
  79     uint32_t isram0[11];
  80 } ppc4xx_l2sram_t;
  81
  82 #ifdef MAP_L2SRAM
  83 static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram,
  84                                    uint32_t isarc, uint32_t isacntl,
  85                                    uint32_t dsarc, uint32_t dsacntl)
  86 {
  87     if (l2sram->isarc != isarc ||
  88         (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
  89         if (l2sram->isacntl & 0x80000000) {
  90             /* Unmap previously assigned memory region */
  91             memory_region_del_subregion(get_system_memory(),
  92                                         &l2sram->isarc_ram);
  93         }
  94         if (isacntl & 0x80000000) {
  95             /* Map new instruction memory region */
  96             memory_region_add_subregion(get_system_memory(), isarc,
  97                                         &l2sram->isarc_ram);
  98         }
  99     }
 100     if (l2sram->dsarc != dsarc ||
 101         (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
 102         if (l2sram->dsacntl & 0x80000000) {
 103             /* Beware not to unmap the region we just mapped */
 104             if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) {
 105                 /* Unmap previously assigned memory region */
 106                 memory_region_del_subregion(get_system_memory(),
 107                                             &l2sram->dsarc_ram);
 108             }
 109         }
 110         if (dsacntl & 0x80000000) {
 111             /* Beware not to remap the region we just mapped */
 112             if (!(isacntl & 0x80000000) || dsarc != isarc) {
 113                 /* Map new data memory region */
 114                 memory_region_add_subregion(get_system_memory(), dsarc,
 115                                             &l2sram->dsarc_ram);
 116             }
 117         }
 118     }
 119 }
 120 #endif
 121
 122 static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
 123 {
 124     ppc4xx_l2sram_t *l2sram = opaque;
 125     uint32_t ret = 0;
 126
 127     switch (dcrn) {
 128     case DCR_L2CACHE_CFG:
 129     case DCR_L2CACHE_CMD:
 130     case DCR_L2CACHE_ADDR:
 131     case DCR_L2CACHE_DATA:
 132     case DCR_L2CACHE_STAT:
 133     case DCR_L2CACHE_CVER:
 134     case DCR_L2CACHE_SNP0:
 135     case DCR_L2CACHE_SNP1:
 136         ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE];
 137         break;
 138
 139     case DCR_ISRAM0_SB0CR:
 140     case DCR_ISRAM0_SB1CR:
 141     case DCR_ISRAM0_SB2CR:
 142     case DCR_ISRAM0_SB3CR:
 143     case DCR_ISRAM0_BEAR:
 144     case DCR_ISRAM0_BESR0:
 145     case DCR_ISRAM0_BESR1:
 146     case DCR_ISRAM0_PMEG:
 147     case DCR_ISRAM0_CID:
 148     case DCR_ISRAM0_REVID:
 149     case DCR_ISRAM0_DPC:
 150         ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
 151         break;
 152
 153     default:
 154         break;
 155     }
 156
 157     return ret;
 158 }
 159
 160 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val)
 161 {
 162     /*ppc4xx_l2sram_t *l2sram = opaque;*/
 163     /* FIXME: Actually handle L2 cache mapping */
 164
 165     switch (dcrn) {
 166     case DCR_L2CACHE_CFG:
 167     case DCR_L2CACHE_CMD:
 168     case DCR_L2CACHE_ADDR:
 169     case DCR_L2CACHE_DATA:
 170     case DCR_L2CACHE_STAT:
 171     case DCR_L2CACHE_CVER:
 172     case DCR_L2CACHE_SNP0:
 173     case DCR_L2CACHE_SNP1:
 174         /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
 175         break;
 176
 177     case DCR_ISRAM0_SB0CR:
 178     case DCR_ISRAM0_SB1CR:
 179     case DCR_ISRAM0_SB2CR:
 180     case DCR_ISRAM0_SB3CR:
 181     case DCR_ISRAM0_BEAR:
 182     case DCR_ISRAM0_BESR0:
 183     case DCR_ISRAM0_BESR1:
 184     case DCR_ISRAM0_PMEG:
 185     case DCR_ISRAM0_CID:
 186     case DCR_ISRAM0_REVID:
 187     case DCR_ISRAM0_DPC:
 188         /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
 189         break;
 190
 191     case DCR_ISRAM1_SB0CR:
 192     case DCR_ISRAM1_BEAR:
 193     case DCR_ISRAM1_BESR0:
 194     case DCR_ISRAM1_BESR1:
 195     case DCR_ISRAM1_PMEG:
 196     case DCR_ISRAM1_CID:
 197     case DCR_ISRAM1_REVID:
 198     case DCR_ISRAM1_DPC:
 199         /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
 200         break;
 201     }
 202     /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
 203 }
 204
 205 static void l2sram_reset(void *opaque)
 206 {
 207     ppc4xx_l2sram_t *l2sram = opaque;
 208
 209     memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache));
 210     l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000;
 211     memset(l2sram->isram0, 0, sizeof(l2sram->isram0));
 212     /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
 213 }
 214
 215 void ppc4xx_l2sram_init(CPUPPCState *env)
 216 {
 217     ppc4xx_l2sram_t *l2sram;
 218
 219     l2sram = g_malloc0(sizeof(*l2sram));
 220     /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
 221     memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0",
 222                            64 * KiB, &error_abort);
 223     memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1",
 224                            64 * KiB, &error_abort);
 225     memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2",
 226                            64 * KiB, &error_abort);
 227     memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3",
 228                            64 * KiB, &error_abort);
 229     qemu_register_reset(&l2sram_reset, l2sram);
 230     ppc_dcr_register(env, DCR_L2CACHE_CFG,
 231                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 232     ppc_dcr_register(env, DCR_L2CACHE_CMD,
 233                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 234     ppc_dcr_register(env, DCR_L2CACHE_ADDR,
 235                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 236     ppc_dcr_register(env, DCR_L2CACHE_DATA,
 237                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 238     ppc_dcr_register(env, DCR_L2CACHE_STAT,
 239                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 240     ppc_dcr_register(env, DCR_L2CACHE_CVER,
 241                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 242     ppc_dcr_register(env, DCR_L2CACHE_SNP0,
 243                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 244     ppc_dcr_register(env, DCR_L2CACHE_SNP1,
 245                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 246
 247     ppc_dcr_register(env, DCR_ISRAM0_SB0CR,
 248                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 249     ppc_dcr_register(env, DCR_ISRAM0_SB1CR,
 250                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 251     ppc_dcr_register(env, DCR_ISRAM0_SB2CR,
 252                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 253     ppc_dcr_register(env, DCR_ISRAM0_SB3CR,
 254                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 255     ppc_dcr_register(env, DCR_ISRAM0_PMEG,
 256                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 257     ppc_dcr_register(env, DCR_ISRAM0_DPC,
 258                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 259
 260     ppc_dcr_register(env, DCR_ISRAM1_SB0CR,
 261                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 262     ppc_dcr_register(env, DCR_ISRAM1_PMEG,
 263                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 264     ppc_dcr_register(env, DCR_ISRAM1_DPC,
 265                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 266 }
 267
 268 /*****************************************************************************/
 269 /* Clocking Power on Reset */
 270 enum {
 271     CPR0_CFGADDR = 0xC,
 272     CPR0_CFGDATA = 0xD,
 273
 274     CPR0_PLLD = 0x060,
 275     CPR0_PLBED = 0x080,
 276     CPR0_OPBD = 0x0C0,
 277     CPR0_PERD = 0x0E0,
 278     CPR0_AHBD = 0x100,
 279 };
 280
 281 typedef struct ppc4xx_cpr_t {
 282     uint32_t addr;
 283 } ppc4xx_cpr_t;
 284
 285 static uint32_t dcr_read_cpr(void *opaque, int dcrn)
 286 {
 287     ppc4xx_cpr_t *cpr = opaque;
 288     uint32_t ret = 0;
 289
 290     switch (dcrn) {
 291     case CPR0_CFGADDR:
 292         ret = cpr->addr;
 293         break;
 294     case CPR0_CFGDATA:
 295         switch (cpr->addr) {
 296         case CPR0_PLLD:
 297             ret = (0xb5 << 24) | (1 << 16) | (9 << 8);
 298             break;
 299         case CPR0_PLBED:
 300             ret = (5 << 24);
 301             break;
 302         case CPR0_OPBD:
 303             ret = (2 << 24);
 304             break;
 305         case CPR0_PERD:
 306         case CPR0_AHBD:
 307             ret = (1 << 24);
 308             break;
 309         default:
 310             break;
 311         }
 312         break;
 313     default:
 314         break;
 315     }
 316
 317     return ret;
 318 }
 319
 320 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val)
 321 {
 322     ppc4xx_cpr_t *cpr = opaque;
 323
 324     switch (dcrn) {
 325     case CPR0_CFGADDR:
 326         cpr->addr = val;
 327         break;
 328     case CPR0_CFGDATA:
 329         break;
 330     default:
 331         break;
 332     }
 333 }
 334
 335 static void ppc4xx_cpr_reset(void *opaque)
 336 {
 337     ppc4xx_cpr_t *cpr = opaque;
 338
 339     cpr->addr = 0;
 340 }
 341
 342 void ppc4xx_cpr_init(CPUPPCState *env)
 343 {
 344     ppc4xx_cpr_t *cpr;
 345
 346     cpr = g_malloc0(sizeof(*cpr));
 347     ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr);
 348     ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr);
 349     qemu_register_reset(ppc4xx_cpr_reset, cpr);
 350 }
 351
 352 /*****************************************************************************/
 353 /* System DCRs */
 354 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t;
 355 struct ppc4xx_sdr_t {
 356     uint32_t addr;
 357 };
 358
 359 enum {
 360     SDR0_CFGADDR = 0x00e,
 361     SDR0_CFGDATA,
 362     SDR0_STRP0 = 0x020,
 363     SDR0_STRP1,
 364     SDR0_102 = 0x66,
 365     SDR0_103,
 366     SDR0_128 = 0x80,
 367     SDR0_ECID3 = 0x083,
 368     SDR0_DDR0 = 0x0e1,
 369     SDR0_USB0 = 0x320,
 370 };
 371
 372 enum {
 373     PESDR0_LOOP = 0x303,
 374     PESDR0_RCSSET,
 375     PESDR0_RCSSTS,
 376     PESDR0_RSTSTA = 0x310,
 377     PESDR1_LOOP = 0x343,
 378     PESDR1_RCSSET,
 379     PESDR1_RCSSTS,
 380     PESDR1_RSTSTA = 0x365,
 381 };
 382
 383 static uint32_t dcr_read_sdr(void *opaque, int dcrn)
 384 {
 385     ppc4xx_sdr_t *sdr = opaque;
 386     uint32_t ret = 0;
 387
 388     switch (dcrn) {
 389     case SDR0_CFGADDR:
 390         ret = sdr->addr;
 391         break;
 392     case SDR0_CFGDATA:
 393         switch (sdr->addr) {
 394         case SDR0_STRP0:
 395             ret = (0xb5 << 8) | (1 << 4) | 9;
 396             break;
 397         case SDR0_STRP1:
 398             ret = (5 << 29) | (2 << 26) | (1 << 24);
 399             break;
 400         case SDR0_ECID3:
 401             ret = 1 << 20; /* No Security/Kasumi support */
 402             break;
 403         case SDR0_DDR0:
 404             ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
 405             break;
 406         case PESDR0_RCSSET:
 407         case PESDR1_RCSSET:
 408             ret = (1 << 24) | (1 << 16);
 409             break;
 410         case PESDR0_RCSSTS:
 411         case PESDR1_RCSSTS:
 412             ret = (1 << 16) | (1 << 12);
 413             break;
 414         case PESDR0_RSTSTA:
 415         case PESDR1_RSTSTA:
 416             ret = 1;
 417             break;
 418         case PESDR0_LOOP:
 419         case PESDR1_LOOP:
 420             ret = 1 << 12;
 421             break;
 422         default:
 423             break;
 424         }
 425         break;
 426     default:
 427         break;
 428     }
 429
 430     return ret;
 431 }
 432
 433 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val)
 434 {
 435     ppc4xx_sdr_t *sdr = opaque;
 436
 437     switch (dcrn) {
 438     case SDR0_CFGADDR:
 439         sdr->addr = val;
 440         break;
 441     case SDR0_CFGDATA:
 442         switch (sdr->addr) {
 443         case 0x00: /* B0CR */
 444             break;
 445         default:
 446             break;
 447         }
 448         break;
 449     default:
 450         break;
 451     }
 452 }
 453
 454 static void sdr_reset(void *opaque)
 455 {
 456     ppc4xx_sdr_t *sdr = opaque;
 457
 458     sdr->addr = 0;
 459 }
 460
 461 void ppc4xx_sdr_init(CPUPPCState *env)
 462 {
 463     ppc4xx_sdr_t *sdr;
 464
 465     sdr = g_malloc0(sizeof(*sdr));
 466     qemu_register_reset(&sdr_reset, sdr);
 467     ppc_dcr_register(env, SDR0_CFGADDR,
 468                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 469     ppc_dcr_register(env, SDR0_CFGDATA,
 470                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 471     ppc_dcr_register(env, SDR0_102,
 472                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 473     ppc_dcr_register(env, SDR0_103,
 474                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 475     ppc_dcr_register(env, SDR0_128,
 476                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 477     ppc_dcr_register(env, SDR0_USB0,
 478                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 479 }
 480
 481 /*****************************************************************************/
 482 /* SDRAM controller */
 483 enum {
 484     SDRAM0_CFGADDR = 0x10,
 485     SDRAM0_CFGDATA,
 486     SDRAM_R0BAS = 0x40,
 487     SDRAM_R1BAS,
 488     SDRAM_R2BAS,
 489     SDRAM_R3BAS,
 490     SDRAM_CONF1HB = 0x45,
 491     SDRAM_PLBADDULL = 0x4a,
 492     SDRAM_CONF1LL = 0x4b,
 493     SDRAM_CONFPATHB = 0x4f,
 494     SDRAM_PLBADDUHB = 0x50,
 495 };
 496
 497 static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
 498 {
 499     uint32_t bcr;
 500
 501     switch (ram_size) {
 502     case 8 * MiB:
 503         bcr = 0xffc0;
 504         break;
 505     case 16 * MiB:
 506         bcr = 0xff80;
 507         break;
 508     case 32 * MiB:
 509         bcr = 0xff00;
 510         break;
 511     case 64 * MiB:
 512         bcr = 0xfe00;
 513         break;
 514     case 128 * MiB:
 515         bcr = 0xfc00;
 516         break;
 517     case 256 * MiB:
 518         bcr = 0xf800;
 519         break;
 520     case 512 * MiB:
 521         bcr = 0xf000;
 522         break;
 523     case 1 * GiB:
 524         bcr = 0xe000;
 525         break;
 526     case 2 * GiB:
 527         bcr = 0xc000;
 528         break;
 529     case 4 * GiB:
 530         bcr = 0x8000;
 531         break;
 532     default:
 533         error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
 534         return 0;
 535     }
 536     bcr |= ram_base >> 2 & 0xffe00000;
 537     bcr |= 1;
 538
 539     return bcr;
 540 }
 541
 542 static inline hwaddr sdram_ddr2_base(uint32_t bcr)
 543 {
 544     return (bcr & 0xffe00000) << 2;
 545 }
 546
 547 static uint64_t sdram_ddr2_size(uint32_t bcr)
 548 {
 549     uint64_t size;
 550     int sh;
 551
 552     sh = 1024 - ((bcr >> 6) & 0x3ff);
 553     size = 8 * MiB * sh;
 554
 555     return size;
 556 }
 557
 558 static void sdram_bank_map(Ppc4xxSdramBank *bank)
 559 {
 560     memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
 561     memory_region_add_subregion(&bank->container, 0, &bank->ram);
 562     memory_region_add_subregion(get_system_memory(), bank->base,
 563                                 &bank->container);
 564 }
 565
 566 static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
 567 {
 568     memory_region_del_subregion(get_system_memory(), &bank->container);
 569     memory_region_del_subregion(&bank->container, &bank->ram);
 570     object_unparent(OBJECT(&bank->container));
 571 }
 572
 573 static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
 574                                uint32_t bcr, int enabled)
 575 {
 576     if (sdram->bank[i].bcr & 1) {
 577         /* First unmap RAM if enabled */
 578         trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
 579                                  sdram_ddr2_size(sdram->bank[i].bcr));
 580         sdram_bank_unmap(&sdram->bank[i]);
 581     }
 582     sdram->bank[i].bcr = bcr & 0xffe0ffc1;
 583     if (enabled && (bcr & 1)) {
 584         trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
 585         sdram_bank_map(&sdram->bank[i]);
 586     }
 587 }
 588
 589 static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
 590 {
 591     int i;
 592
 593     for (i = 0; i < sdram->nbanks; i++) {
 594         if (sdram->bank[i].size) {
 595             sdram_ddr2_set_bcr(sdram, i,
 596                                sdram_ddr2_bcr(sdram->bank[i].base,
 597                                               sdram->bank[i].size), 1);
 598         } else {
 599             sdram_ddr2_set_bcr(sdram, i, 0, 0);
 600         }
 601     }
 602 }
 603
 604 static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
 605 {
 606     int i;
 607
 608     for (i = 0; i < sdram->nbanks; i++) {
 609         if (sdram->bank[i].size) {
 610             sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
 611         }
 612     }
 613 }
 614
 615 static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
 616 {
 617     Ppc4xxSdramDdr2State *sdram = opaque;
 618     uint32_t ret = 0;
 619
 620     switch (dcrn) {
 621     case SDRAM_R0BAS:
 622     case SDRAM_R1BAS:
 623     case SDRAM_R2BAS:
 624     case SDRAM_R3BAS:
 625         if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
 626             ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
 627                                  sdram->bank[dcrn - SDRAM_R0BAS].size);
 628         }
 629         break;
 630     case SDRAM_CONF1HB:
 631     case SDRAM_CONF1LL:
 632     case SDRAM_CONFPATHB:
 633     case SDRAM_PLBADDULL:
 634     case SDRAM_PLBADDUHB:
 635         break;
 636     case SDRAM0_CFGADDR:
 637         ret = sdram->addr;
 638         break;
 639     case SDRAM0_CFGDATA:
 640         switch (sdram->addr) {
 641         case 0x14: /* SDRAM_MCSTAT (405EX) */
 642         case 0x1F:
 643             ret = 0x80000000;
 644             break;
 645         case 0x21: /* SDRAM_MCOPT2 */
 646             ret = sdram->mcopt2;
 647             break;
 648         case 0x40: /* SDRAM_MB0CF */
 649             ret = 0x00008001;
 650             break;
 651         case 0x7A: /* SDRAM_DLCR */
 652             ret = 0x02000000;
 653             break;
 654         case 0xE1: /* SDR0_DDR0 */
 655             ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
 656             break;
 657         default:
 658             break;
 659         }
 660         break;
 661     default:
 662         break;
 663     }
 664
 665     return ret;
 666 }
 667
 668 #define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
 669
 670 static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
 671 {
 672     Ppc4xxSdramDdr2State *sdram = opaque;
 673
 674     switch (dcrn) {
 675     case SDRAM_R0BAS:
 676     case SDRAM_R1BAS:
 677     case SDRAM_R2BAS:
 678     case SDRAM_R3BAS:
 679     case SDRAM_CONF1HB:
 680     case SDRAM_CONF1LL:
 681     case SDRAM_CONFPATHB:
 682     case SDRAM_PLBADDULL:
 683     case SDRAM_PLBADDUHB:
 684         break;
 685     case SDRAM0_CFGADDR:
 686         sdram->addr = val;
 687         break;
 688     case SDRAM0_CFGDATA:
 689         switch (sdram->addr) {
 690         case 0x00: /* B0CR */
 691             break;
 692         case 0x21: /* SDRAM_MCOPT2 */
 693             if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
 694                 (val & SDRAM_DDR2_MCOPT2_DCEN)) {
 695                 trace_ppc4xx_sdram_enable("enable");
 696                 /* validate all RAM mappings */
 697                 sdram_ddr2_map_bcr(sdram);
 698                 sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
 699             } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
 700                        !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
 701                 trace_ppc4xx_sdram_enable("disable");
 702                 /* invalidate all RAM mappings */
 703                 sdram_ddr2_unmap_bcr(sdram);
 704                 sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
 705             }
 706             break;
 707         default:
 708             break;
 709         }
 710         break;
 711     default:
 712         break;
 713     }
 714 }
 715
 716 static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
 717 {
 718     Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
 719
 720     sdram->addr = 0;
 721     sdram->mcopt2 = 0;
 722 }
 723
 724 static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
 725 {
 726     Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
 727     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 728     /*
 729      * SoC also has 4 GiB but that causes problem with 32 bit
 730      * builds (4*GiB overflows the 32 bit ram_addr_t).
 731      */
 732     const ram_addr_t valid_bank_sizes[] = {
 733         2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB,
 734         64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
 735     };
 736
 737     if (s->nbanks < 1 || s->nbanks > 4) {
 738         error_setg(errp, "Invalid number of RAM banks");
 739         return;
 740     }
 741     if (!s->dram_mr) {
 742         error_setg(errp, "Missing dram memory region");
 743         return;
 744     }
 745     ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
 746
 747     ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
 748                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 749     ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
 750                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 751
 752     ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
 753                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 754     ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
 755                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 756     ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
 757                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 758     ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
 759                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 760     ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
 761                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 762     ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
 763                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 764     ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
 765                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 766     ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
 767                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 768     ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
 769                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 770 }
 771
 772 static Property ppc4xx_sdram_ddr2_props[] = {
 773     DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
 774                      MemoryRegion *),
 775     DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
 776     DEFINE_PROP_END_OF_LIST(),
 777 };
 778
 779 static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
 780 {
 781     DeviceClass *dc = DEVICE_CLASS(oc);
 782
 783     dc->realize = ppc4xx_sdram_ddr2_realize;
 784     dc->reset = ppc4xx_sdram_ddr2_reset;
 785     /* Reason: only works as function of a ppc4xx SoC */
 786     dc->user_creatable = false;
 787     device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
 788 }
 789
 790 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
 791 {
 792     sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
 793     sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
 794 }
 795
 796 static const TypeInfo ppc4xx_types[] = {
 797     {
 798         .name           = TYPE_PPC4xx_SDRAM_DDR2,
 799         .parent         = TYPE_PPC4xx_DCR_DEVICE,
 800         .instance_size  = sizeof(Ppc4xxSdramDdr2State),
 801         .class_init     = ppc4xx_sdram_ddr2_class_init,
 802     }
 803 };
 804 DEFINE_TYPES(ppc4xx_types)
 805
 806 /*****************************************************************************/
 807 /* PLB to AHB bridge */
 808 enum {
 809     AHB_TOP    = 0xA4,
 810     AHB_BOT    = 0xA5,
 811 };
 812
 813 typedef struct ppc4xx_ahb_t {
 814     uint32_t top;
 815     uint32_t bot;
 816 } ppc4xx_ahb_t;
 817
 818 static uint32_t dcr_read_ahb(void *opaque, int dcrn)
 819 {
 820     ppc4xx_ahb_t *ahb = opaque;
 821     uint32_t ret = 0;
 822
 823     switch (dcrn) {
 824     case AHB_TOP:
 825         ret = ahb->top;
 826         break;
 827     case AHB_BOT:
 828         ret = ahb->bot;
 829         break;
 830     default:
 831         break;
 832     }
 833
 834     return ret;
 835 }
 836
 837 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val)
 838 {
 839     ppc4xx_ahb_t *ahb = opaque;
 840
 841     switch (dcrn) {
 842     case AHB_TOP:
 843         ahb->top = val;
 844         break;
 845     case AHB_BOT:
 846         ahb->bot = val;
 847         break;
 848     }
 849 }
 850
 851 static void ppc4xx_ahb_reset(void *opaque)
 852 {
 853     ppc4xx_ahb_t *ahb = opaque;
 854
 855     /* No error */
 856     ahb->top = 0;
 857     ahb->bot = 0;
 858 }
 859
 860 void ppc4xx_ahb_init(CPUPPCState *env)
 861 {
 862     ppc4xx_ahb_t *ahb;
 863
 864     ahb = g_malloc0(sizeof(*ahb));
 865     ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb);
 866     ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb);
 867     qemu_register_reset(ppc4xx_ahb_reset, ahb);
 868 }
 869
 870 /*****************************************************************************/
 871 /* DMA controller */
 872
 873 #define DMA0_CR_CE  (1 << 31)
 874 #define DMA0_CR_PW  (1 << 26 | 1 << 25)
 875 #define DMA0_CR_DAI (1 << 24)
 876 #define DMA0_CR_SAI (1 << 23)
 877 #define DMA0_CR_DEC (1 << 2)
 878
 879 enum {
 880     DMA0_CR  = 0x00,
 881     DMA0_CT,
 882     DMA0_SAH,
 883     DMA0_SAL,
 884     DMA0_DAH,
 885     DMA0_DAL,
 886     DMA0_SGH,
 887     DMA0_SGL,
 888
 889     DMA0_SR  = 0x20,
 890     DMA0_SGC = 0x23,
 891     DMA0_SLP = 0x25,
 892     DMA0_POL = 0x26,
 893 };
 894
 895 typedef struct {
 896     uint32_t cr;
 897     uint32_t ct;
 898     uint64_t sa;
 899     uint64_t da;
 900     uint64_t sg;
 901 } PPC4xxDmaChnl;
 902
 903 typedef struct {
 904     int base;
 905     PPC4xxDmaChnl ch[4];
 906     uint32_t sr;
 907 } PPC4xxDmaState;
 908
 909 static uint32_t dcr_read_dma(void *opaque, int dcrn)
 910 {
 911     PPC4xxDmaState *dma = opaque;
 912     uint32_t val = 0;
 913     int addr = dcrn - dma->base;
 914     int chnl = addr / 8;
 915
 916     switch (addr) {
 917     case 0x00 ... 0x1f:
 918         switch (addr % 8) {
 919         case DMA0_CR:
 920             val = dma->ch[chnl].cr;
 921             break;
 922         case DMA0_CT:
 923             val = dma->ch[chnl].ct;
 924             break;
 925         case DMA0_SAH:
 926             val = dma->ch[chnl].sa >> 32;
 927             break;
 928         case DMA0_SAL:
 929             val = dma->ch[chnl].sa;
 930             break;
 931         case DMA0_DAH:
 932             val = dma->ch[chnl].da >> 32;
 933             break;
 934         case DMA0_DAL:
 935             val = dma->ch[chnl].da;
 936             break;
 937         case DMA0_SGH:
 938             val = dma->ch[chnl].sg >> 32;
 939             break;
 940         case DMA0_SGL:
 941             val = dma->ch[chnl].sg;
 942             break;
 943         }
 944         break;
 945     case DMA0_SR:
 946         val = dma->sr;
 947         break;
 948     default:
 949         qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
 950                       __func__, dcrn, chnl, addr);
 951     }
 952
 953     return val;
 954 }
 955
 956 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
 957 {
 958     PPC4xxDmaState *dma = opaque;
 959     int addr = dcrn - dma->base;
 960     int chnl = addr / 8;
 961
 962     switch (addr) {
 963     case 0x00 ... 0x1f:
 964         switch (addr % 8) {
 965         case DMA0_CR:
 966             dma->ch[chnl].cr = val;
 967             if (val & DMA0_CR_CE) {
 968                 int count = dma->ch[chnl].ct & 0xffff;
 969
 970                 if (count) {
 971                     int width, i, sidx, didx;
 972                     uint8_t *rptr, *wptr;
 973                     hwaddr rlen, wlen;
 974                     hwaddr xferlen;
 975
 976                     sidx = didx = 0;
 977                     width = 1 << ((val & DMA0_CR_PW) >> 25);
 978                     xferlen = count * width;
 979                     wlen = rlen = xferlen;
 980                     rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen,
 981                                                    false);
 982                     wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen,
 983                                                    true);
 984                     if (rptr && rlen == xferlen && wptr && wlen == xferlen) {
 985                         if (!(val & DMA0_CR_DEC) &&
 986                             val & DMA0_CR_SAI && val & DMA0_CR_DAI) {
 987                             /* optimise common case */
 988                             memmove(wptr, rptr, count * width);
 989                             sidx = didx = count * width;
 990                         } else {
 991                             /* do it the slow way */
 992                             for (sidx = didx = i = 0; i < count; i++) {
 993                                 uint64_t v = ldn_le_p(rptr + sidx, width);
 994                                 stn_le_p(wptr + didx, width, v);
 995                                 if (val & DMA0_CR_SAI) {
 996                                     sidx += width;
 997                                 }
 998                                 if (val & DMA0_CR_DAI) {
 999                                     didx += width;
1000                                 }
1001                             }
1002                         }
1003                     }
1004                     if (wptr) {
1005                         cpu_physical_memory_unmap(wptr, wlen, 1, didx);
1006                     }
1007                     if (rptr) {
1008                         cpu_physical_memory_unmap(rptr, rlen, 0, sidx);
1009                     }
1010                 }
1011             }
1012             break;
1013         case DMA0_CT:
1014             dma->ch[chnl].ct = val;
1015             break;
1016         case DMA0_SAH:
1017             dma->ch[chnl].sa &= 0xffffffffULL;
1018             dma->ch[chnl].sa |= (uint64_t)val << 32;
1019             break;
1020         case DMA0_SAL:
1021             dma->ch[chnl].sa &= 0xffffffff00000000ULL;
1022             dma->ch[chnl].sa |= val;
1023             break;
1024         case DMA0_DAH:
1025             dma->ch[chnl].da &= 0xffffffffULL;
1026             dma->ch[chnl].da |= (uint64_t)val << 32;
1027             break;
1028         case DMA0_DAL:
1029             dma->ch[chnl].da &= 0xffffffff00000000ULL;
1030             dma->ch[chnl].da |= val;
1031             break;
1032         case DMA0_SGH:
1033             dma->ch[chnl].sg &= 0xffffffffULL;
1034             dma->ch[chnl].sg |= (uint64_t)val << 32;
1035             break;
1036         case DMA0_SGL:
1037             dma->ch[chnl].sg &= 0xffffffff00000000ULL;
1038             dma->ch[chnl].sg |= val;
1039             break;
1040         }
1041         break;
1042     case DMA0_SR:
1043         dma->sr &= ~val;
1044         break;
1045     default:
1046         qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
1047                       __func__, dcrn, chnl, addr);
1048     }
1049 }
1050
1051 static void ppc4xx_dma_reset(void *opaque)
1052 {
1053     PPC4xxDmaState *dma = opaque;
1054     int dma_base = dma->base;
1055
1056     memset(dma, 0, sizeof(*dma));
1057     dma->base = dma_base;
1058 }
1059
1060 void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
1061 {
1062     PPC4xxDmaState *dma;
1063     int i;
1064
1065     dma = g_malloc0(sizeof(*dma));
1066     dma->base = dcr_base;
1067     qemu_register_reset(&ppc4xx_dma_reset, dma);
1068     for (i = 0; i < 4; i++) {
1069         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR,
1070                          dma, &dcr_read_dma, &dcr_write_dma);
1071         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT,
1072                          dma, &dcr_read_dma, &dcr_write_dma);
1073         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH,
1074                          dma, &dcr_read_dma, &dcr_write_dma);
1075         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL,
1076                          dma, &dcr_read_dma, &dcr_write_dma);
1077         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH,
1078                          dma, &dcr_read_dma, &dcr_write_dma);
1079         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL,
1080                          dma, &dcr_read_dma, &dcr_write_dma);
1081         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH,
1082                          dma, &dcr_read_dma, &dcr_write_dma);
1083         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL,
1084                          dma, &dcr_read_dma, &dcr_write_dma);
1085     }
1086     ppc_dcr_register(env, dcr_base + DMA0_SR,
1087                      dma, &dcr_read_dma, &dcr_write_dma);
1088     ppc_dcr_register(env, dcr_base + DMA0_SGC,
1089                      dma, &dcr_read_dma, &dcr_write_dma);
1090     ppc_dcr_register(env, dcr_base + DMA0_SLP,
1091                      dma, &dcr_read_dma, &dcr_write_dma);
1092     ppc_dcr_register(env, dcr_base + DMA0_POL,
1093                      dma, &dcr_read_dma, &dcr_write_dma);
1094 }
1095
1096 /*****************************************************************************/
1097 /* PCI Express controller */
1098 /*
1099  * FIXME: This is not complete and does not work, only implemented partially
1100  * to allow firmware and guests to find an empty bus. Cards should use PCI.
1101  */
1102 #include "hw/pci/pcie_host.h"
1103
1104 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
1105 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST)
1106
1107 struct PPC460EXPCIEState {
1108     PCIExpressHost host;
1109
1110     MemoryRegion iomem;
1111     qemu_irq irq[4];
1112     int32_t dcrn_base;
1113
1114     uint64_t cfg_base;
1115     uint32_t cfg_mask;
1116     uint64_t msg_base;
1117     uint32_t msg_mask;
1118     uint64_t omr1_base;
1119     uint64_t omr1_mask;
1120     uint64_t omr2_base;
1121     uint64_t omr2_mask;
1122     uint64_t omr3_base;
1123     uint64_t omr3_mask;
1124     uint64_t reg_base;
1125     uint32_t reg_mask;
1126     uint32_t special;
1127     uint32_t cfg;
1128 };
1129
1130 #define DCRN_PCIE0_BASE 0x100
1131 #define DCRN_PCIE1_BASE 0x120
1132
1133 enum {
1134     PEGPL_CFGBAH = 0x0,
1135     PEGPL_CFGBAL,
1136     PEGPL_CFGMSK,
1137     PEGPL_MSGBAH,
1138     PEGPL_MSGBAL,
1139     PEGPL_MSGMSK,
1140     PEGPL_OMR1BAH,
1141     PEGPL_OMR1BAL,
1142     PEGPL_OMR1MSKH,
1143     PEGPL_OMR1MSKL,
1144     PEGPL_OMR2BAH,
1145     PEGPL_OMR2BAL,
1146     PEGPL_OMR2MSKH,
1147     PEGPL_OMR2MSKL,
1148     PEGPL_OMR3BAH,
1149     PEGPL_OMR3BAL,
1150     PEGPL_OMR3MSKH,
1151     PEGPL_OMR3MSKL,
1152     PEGPL_REGBAH,
1153     PEGPL_REGBAL,
1154     PEGPL_REGMSK,
1155     PEGPL_SPECIAL,
1156     PEGPL_CFG,
1157 };
1158
1159 static uint32_t dcr_read_pcie(void *opaque, int dcrn)
1160 {
1161     PPC460EXPCIEState *state = opaque;
1162     uint32_t ret = 0;
1163
1164     switch (dcrn - state->dcrn_base) {
1165     case PEGPL_CFGBAH:
1166         ret = state->cfg_base >> 32;
1167         break;
1168     case PEGPL_CFGBAL:
1169         ret = state->cfg_base;
1170         break;
1171     case PEGPL_CFGMSK:
1172         ret = state->cfg_mask;
1173         break;
1174     case PEGPL_MSGBAH:
1175         ret = state->msg_base >> 32;
1176         break;
1177     case PEGPL_MSGBAL:
1178         ret = state->msg_base;
1179         break;
1180     case PEGPL_MSGMSK:
1181         ret = state->msg_mask;
1182         break;
1183     case PEGPL_OMR1BAH:
1184         ret = state->omr1_base >> 32;
1185         break;
1186     case PEGPL_OMR1BAL:
1187         ret = state->omr1_base;
1188         break;
1189     case PEGPL_OMR1MSKH:
1190         ret = state->omr1_mask >> 32;
1191         break;
1192     case PEGPL_OMR1MSKL:
1193         ret = state->omr1_mask;
1194         break;
1195     case PEGPL_OMR2BAH:
1196         ret = state->omr2_base >> 32;
1197         break;
1198     case PEGPL_OMR2BAL:
1199         ret = state->omr2_base;
1200         break;
1201     case PEGPL_OMR2MSKH:
1202         ret = state->omr2_mask >> 32;
1203         break;
1204     case PEGPL_OMR2MSKL:
1205         ret = state->omr3_mask;
1206         break;
1207     case PEGPL_OMR3BAH:
1208         ret = state->omr3_base >> 32;
1209         break;
1210     case PEGPL_OMR3BAL:
1211         ret = state->omr3_base;
1212         break;
1213     case PEGPL_OMR3MSKH:
1214         ret = state->omr3_mask >> 32;
1215         break;
1216     case PEGPL_OMR3MSKL:
1217         ret = state->omr3_mask;
1218         break;
1219     case PEGPL_REGBAH:
1220         ret = state->reg_base >> 32;
1221         break;
1222     case PEGPL_REGBAL:
1223         ret = state->reg_base;
1224         break;
1225     case PEGPL_REGMSK:
1226         ret = state->reg_mask;
1227         break;
1228     case PEGPL_SPECIAL:
1229         ret = state->special;
1230         break;
1231     case PEGPL_CFG:
1232         ret = state->cfg;
1233         break;
1234     }
1235
1236     return ret;
1237 }
1238
1239 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val)
1240 {
1241     PPC460EXPCIEState *s = opaque;
1242     uint64_t size;
1243
1244     switch (dcrn - s->dcrn_base) {
1245     case PEGPL_CFGBAH:
1246         s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff);
1247         break;
1248     case PEGPL_CFGBAL:
1249         s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val;
1250         break;
1251     case PEGPL_CFGMSK:
1252         s->cfg_mask = val;
1253         size = ~(val & 0xfffffffe) + 1;
1254         /*
1255          * Firmware sets this register to E0000001. Why we are not sure,
1256          * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is
1257          * ignored.
1258          */
1259         if (size > PCIE_MMCFG_SIZE_MAX) {
1260             size = PCIE_MMCFG_SIZE_MAX;
1261         }
1262         pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size);
1263         break;
1264     case PEGPL_MSGBAH:
1265         s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff);
1266         break;
1267     case PEGPL_MSGBAL:
1268         s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val;
1269         break;
1270     case PEGPL_MSGMSK:
1271         s->msg_mask = val;
1272         break;
1273     case PEGPL_OMR1BAH:
1274         s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff);
1275         break;
1276     case PEGPL_OMR1BAL:
1277         s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val;
1278         break;
1279     case PEGPL_OMR1MSKH:
1280         s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff);
1281         break;
1282     case PEGPL_OMR1MSKL:
1283         s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val;
1284         break;
1285     case PEGPL_OMR2BAH:
1286         s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff);
1287         break;
1288     case PEGPL_OMR2BAL:
1289         s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val;
1290         break;
1291     case PEGPL_OMR2MSKH:
1292         s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff);
1293         break;
1294     case PEGPL_OMR2MSKL:
1295         s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val;
1296         break;
1297     case PEGPL_OMR3BAH:
1298         s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff);
1299         break;
1300     case PEGPL_OMR3BAL:
1301         s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val;
1302         break;
1303     case PEGPL_OMR3MSKH:
1304         s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff);
1305         break;
1306     case PEGPL_OMR3MSKL:
1307         s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val;
1308         break;
1309     case PEGPL_REGBAH:
1310         s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff);
1311         break;
1312     case PEGPL_REGBAL:
1313         s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val;
1314         break;
1315     case PEGPL_REGMSK:
1316         s->reg_mask = val;
1317         /* FIXME: how is size encoded? */
1318         size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1);
1319         break;
1320     case PEGPL_SPECIAL:
1321         s->special = val;
1322         break;
1323     case PEGPL_CFG:
1324         s->cfg = val;
1325         break;
1326     }
1327 }
1328
1329 static void ppc460ex_set_irq(void *opaque, int irq_num, int level)
1330 {
1331        PPC460EXPCIEState *s = opaque;
1332        qemu_set_irq(s->irq[irq_num], level);
1333 }
1334
1335 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp)
1336 {
1337     PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev);
1338     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
1339     int i, id;
1340     char buf[16];
1341
1342     switch (s->dcrn_base) {
1343     case DCRN_PCIE0_BASE:
1344         id = 0;
1345         break;
1346     case DCRN_PCIE1_BASE:
1347         id = 1;
1348         break;
1349     default:
1350         error_setg(errp, "invalid PCIe DCRN base");
1351         return;
1352     }
1353     snprintf(buf, sizeof(buf), "pcie%d-io", id);
1354     memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX);
1355     for (i = 0; i < 4; i++) {
1356         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1357     }
1358     snprintf(buf, sizeof(buf), "pcie.%d", id);
1359     pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq,
1360                                 pci_swizzle_map_irq_fn, s, &s->iomem,
1361                                 get_system_io(), 0, 4, TYPE_PCIE_BUS);
1362 }
1363
1364 static Property ppc460ex_pcie_props[] = {
1365     DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1),
1366     DEFINE_PROP_END_OF_LIST(),
1367 };
1368
1369 static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data)
1370 {
1371     DeviceClass *dc = DEVICE_CLASS(klass);
1372
1373     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1374     dc->realize = ppc460ex_pcie_realize;
1375     device_class_set_props(dc, ppc460ex_pcie_props);
1376     dc->hotpluggable = false;
1377 }
1378
1379 static const TypeInfo ppc460ex_pcie_host_info = {
1380     .name = TYPE_PPC460EX_PCIE_HOST,
1381     .parent = TYPE_PCIE_HOST_BRIDGE,
1382     .instance_size = sizeof(PPC460EXPCIEState),
1383     .class_init = ppc460ex_pcie_class_init,
1384 };
1385
1386 static void ppc460ex_pcie_register(void)
1387 {
1388     type_register_static(&ppc460ex_pcie_host_info);
1389 }
1390
1391 type_init(ppc460ex_pcie_register)
1392
1393 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env)
1394 {
1395     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s,
1396                      &dcr_read_pcie, &dcr_write_pcie);
1397     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s,
1398                      &dcr_read_pcie, &dcr_write_pcie);
1399     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s,
1400                      &dcr_read_pcie, &dcr_write_pcie);
1401     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s,
1402                      &dcr_read_pcie, &dcr_write_pcie);
1403     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s,
1404                      &dcr_read_pcie, &dcr_write_pcie);
1405     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s,
1406                      &dcr_read_pcie, &dcr_write_pcie);
1407     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s,
1408                      &dcr_read_pcie, &dcr_write_pcie);
1409     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s,
1410                      &dcr_read_pcie, &dcr_write_pcie);
1411     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s,
1412                      &dcr_read_pcie, &dcr_write_pcie);
1413     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s,
1414                      &dcr_read_pcie, &dcr_write_pcie);
1415     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s,
1416                      &dcr_read_pcie, &dcr_write_pcie);
1417     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s,
1418                      &dcr_read_pcie, &dcr_write_pcie);
1419     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s,
1420                      &dcr_read_pcie, &dcr_write_pcie);
1421     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s,
1422                      &dcr_read_pcie, &dcr_write_pcie);
1423     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s,
1424                      &dcr_read_pcie, &dcr_write_pcie);
1425     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s,
1426                      &dcr_read_pcie, &dcr_write_pcie);
1427     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s,
1428                      &dcr_read_pcie, &dcr_write_pcie);
1429     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s,
1430                      &dcr_read_pcie, &dcr_write_pcie);
1431     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s,
1432                      &dcr_read_pcie, &dcr_write_pcie);
1433     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s,
1434                      &dcr_read_pcie, &dcr_write_pcie);
1435     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s,
1436                      &dcr_read_pcie, &dcr_write_pcie);
1437     ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s,
1438                      &dcr_read_pcie, &dcr_write_pcie);
1439     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s,
1440                      &dcr_read_pcie, &dcr_write_pcie);
1441 }
1442
1443 void ppc460ex_pcie_init(CPUPPCState *env)
1444 {
1445     DeviceState *dev;
1446
1447     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
1448     qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
1449     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1450     ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
1451
1452     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
1453     qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
1454     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1455     ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
1456 }