hw/ppc/ppc4xx_devs.c

   1 /*
   2  * QEMU PowerPC 4xx embedded processors shared devices emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "cpu.h"
  26 #include "hw/hw.h"
  27 #include "hw/ppc/ppc.h"
  28 #include "hw/ppc/ppc4xx.h"
  29 #include "hw/boards.h"
  30 #include "qemu/log.h"
  31 #include "exec/address-spaces.h"
  32
  33 #define DEBUG_UIC
  34
  35
  36 #ifdef DEBUG_UIC
  37 #  define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
  38 #else
  39 #  define LOG_UIC(...) do { } while (0)
  40 #endif
  41
  42 static void ppc4xx_reset(void *opaque)
  43 {
  44     PowerPCCPU *cpu = opaque;
  45
  46     cpu_reset(CPU(cpu));
  47 }
  48
  49 /*****************************************************************************/
  50 /* Generic PowerPC 4xx processor instantiation */
  51 PowerPCCPU *ppc4xx_init(const char *cpu_model,
  52                         clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  53                         uint32_t sysclk)
  54 {
  55     PowerPCCPU *cpu;
  56     CPUPPCState *env;
  57
  58     /* init CPUs */
  59     cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
  60     if (cpu == NULL) {
  61         fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
  62                 cpu_model);
  63         exit(1);
  64     }
  65     env = &cpu->env;
  66
  67     cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
  68     cpu_clk->opaque = env;
  69     /* Set time-base frequency to sysclk */
  70     tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
  71     tb_clk->opaque = env;
  72     ppc_dcr_init(env, NULL, NULL);
  73     /* Register qemu callbacks */
  74     qemu_register_reset(ppc4xx_reset, cpu);
  75
  76     return cpu;
  77 }
  78
  79 /*****************************************************************************/
  80 /* "Universal" Interrupt controller */
  81 enum {
  82     DCR_UICSR  = 0x000,
  83     DCR_UICSRS = 0x001,
  84     DCR_UICER  = 0x002,
  85     DCR_UICCR  = 0x003,
  86     DCR_UICPR  = 0x004,
  87     DCR_UICTR  = 0x005,
  88     DCR_UICMSR = 0x006,
  89     DCR_UICVR  = 0x007,
  90     DCR_UICVCR = 0x008,
  91     DCR_UICMAX = 0x009,
  92 };
  93
  94 #define UIC_MAX_IRQ 32
  95 typedef struct ppcuic_t ppcuic_t;
  96 struct ppcuic_t {
  97     uint32_t dcr_base;
  98     int use_vectors;
  99     uint32_t level;  /* Remembers the state of level-triggered interrupts. */
 100     uint32_t uicsr;  /* Status register */
 101     uint32_t uicer;  /* Enable register */
 102     uint32_t uiccr;  /* Critical register */
 103     uint32_t uicpr;  /* Polarity register */
 104     uint32_t uictr;  /* Triggering register */
 105     uint32_t uicvcr; /* Vector configuration register */
 106     uint32_t uicvr;
 107     qemu_irq *irqs;
 108 };
 109
 110 static void ppcuic_trigger_irq (ppcuic_t *uic)
 111 {
 112     uint32_t ir, cr;
 113     int start, end, inc, i;
 114
 115     /* Trigger interrupt if any is pending */
 116     ir = uic->uicsr & uic->uicer & (~uic->uiccr);
 117     cr = uic->uicsr & uic->uicer & uic->uiccr;
 118     LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
 119                 " uiccr %08" PRIx32 "\n"
 120                 "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
 121                 __func__, uic->uicsr, uic->uicer, uic->uiccr,
 122                 uic->uicsr & uic->uicer, ir, cr);
 123     if (ir != 0x0000000) {
 124         LOG_UIC("Raise UIC interrupt\n");
 125         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
 126     } else {
 127         LOG_UIC("Lower UIC interrupt\n");
 128         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
 129     }
 130     /* Trigger critical interrupt if any is pending and update vector */
 131     if (cr != 0x0000000) {
 132         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
 133         if (uic->use_vectors) {
 134             /* Compute critical IRQ vector */
 135             if (uic->uicvcr & 1) {
 136                 start = 31;
 137                 end = 0;
 138                 inc = -1;
 139             } else {
 140                 start = 0;
 141                 end = 31;
 142                 inc = 1;
 143             }
 144             uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
 145             for (i = start; i <= end; i += inc) {
 146                 if (cr & (1 << i)) {
 147                     uic->uicvr += (i - start) * 512 * inc;
 148                     break;
 149                 }
 150             }
 151         }
 152         LOG_UIC("Raise UIC critical interrupt - "
 153                     "vector %08" PRIx32 "\n", uic->uicvr);
 154     } else {
 155         LOG_UIC("Lower UIC critical interrupt\n");
 156         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
 157         uic->uicvr = 0x00000000;
 158     }
 159 }
 160
 161 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
 162 {
 163     ppcuic_t *uic;
 164     uint32_t mask, sr;
 165
 166     uic = opaque;
 167     mask = 1U << (31-irq_num);
 168     LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
 169                 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
 170                 __func__, irq_num, level,
 171                 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
 172     if (irq_num < 0 || irq_num > 31)
 173         return;
 174     sr = uic->uicsr;
 175
 176     /* Update status register */
 177     if (uic->uictr & mask) {
 178         /* Edge sensitive interrupt */
 179         if (level == 1)
 180             uic->uicsr |= mask;
 181     } else {
 182         /* Level sensitive interrupt */
 183         if (level == 1) {
 184             uic->uicsr |= mask;
 185             uic->level |= mask;
 186         } else {
 187             uic->uicsr &= ~mask;
 188             uic->level &= ~mask;
 189         }
 190     }
 191     LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
 192                 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
 193     if (sr != uic->uicsr)
 194         ppcuic_trigger_irq(uic);
 195 }
 196
 197 static uint32_t dcr_read_uic (void *opaque, int dcrn)
 198 {
 199     ppcuic_t *uic;
 200     uint32_t ret;
 201
 202     uic = opaque;
 203     dcrn -= uic->dcr_base;
 204     switch (dcrn) {
 205     case DCR_UICSR:
 206     case DCR_UICSRS:
 207         ret = uic->uicsr;
 208         break;
 209     case DCR_UICER:
 210         ret = uic->uicer;
 211         break;
 212     case DCR_UICCR:
 213         ret = uic->uiccr;
 214         break;
 215     case DCR_UICPR:
 216         ret = uic->uicpr;
 217         break;
 218     case DCR_UICTR:
 219         ret = uic->uictr;
 220         break;
 221     case DCR_UICMSR:
 222         ret = uic->uicsr & uic->uicer;
 223         break;
 224     case DCR_UICVR:
 225         if (!uic->use_vectors)
 226             goto no_read;
 227         ret = uic->uicvr;
 228         break;
 229     case DCR_UICVCR:
 230         if (!uic->use_vectors)
 231             goto no_read;
 232         ret = uic->uicvcr;
 233         break;
 234     default:
 235     no_read:
 236         ret = 0x00000000;
 237         break;
 238     }
 239
 240     return ret;
 241 }
 242
 243 static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
 244 {
 245     ppcuic_t *uic;
 246
 247     uic = opaque;
 248     dcrn -= uic->dcr_base;
 249     LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
 250     switch (dcrn) {
 251     case DCR_UICSR:
 252         uic->uicsr &= ~val;
 253         uic->uicsr |= uic->level;
 254         ppcuic_trigger_irq(uic);
 255         break;
 256     case DCR_UICSRS:
 257         uic->uicsr |= val;
 258         ppcuic_trigger_irq(uic);
 259         break;
 260     case DCR_UICER:
 261         uic->uicer = val;
 262         ppcuic_trigger_irq(uic);
 263         break;
 264     case DCR_UICCR:
 265         uic->uiccr = val;
 266         ppcuic_trigger_irq(uic);
 267         break;
 268     case DCR_UICPR:
 269         uic->uicpr = val;
 270         break;
 271     case DCR_UICTR:
 272         uic->uictr = val;
 273         ppcuic_trigger_irq(uic);
 274         break;
 275     case DCR_UICMSR:
 276         break;
 277     case DCR_UICVR:
 278         break;
 279     case DCR_UICVCR:
 280         uic->uicvcr = val & 0xFFFFFFFD;
 281         ppcuic_trigger_irq(uic);
 282         break;
 283     }
 284 }
 285
 286 static void ppcuic_reset (void *opaque)
 287 {
 288     ppcuic_t *uic;
 289
 290     uic = opaque;
 291     uic->uiccr = 0x00000000;
 292     uic->uicer = 0x00000000;
 293     uic->uicpr = 0x00000000;
 294     uic->uicsr = 0x00000000;
 295     uic->uictr = 0x00000000;
 296     if (uic->use_vectors) {
 297         uic->uicvcr = 0x00000000;
 298         uic->uicvr = 0x0000000;
 299     }
 300 }
 301
 302 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
 303                        uint32_t dcr_base, int has_ssr, int has_vr)
 304 {
 305     ppcuic_t *uic;
 306     int i;
 307
 308     uic = g_malloc0(sizeof(ppcuic_t));
 309     uic->dcr_base = dcr_base;
 310     uic->irqs = irqs;
 311     if (has_vr)
 312         uic->use_vectors = 1;
 313     for (i = 0; i < DCR_UICMAX; i++) {
 314         ppc_dcr_register(env, dcr_base + i, uic,
 315                          &dcr_read_uic, &dcr_write_uic);
 316     }
 317     qemu_register_reset(ppcuic_reset, uic);
 318
 319     return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
 320 }
 321
 322 /*****************************************************************************/
 323 /* SDRAM controller */
 324 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
 325 struct ppc4xx_sdram_t {
 326     uint32_t addr;
 327     int nbanks;
 328     MemoryRegion containers[4]; /* used for clipping */
 329     MemoryRegion *ram_memories;
 330     hwaddr ram_bases[4];
 331     hwaddr ram_sizes[4];
 332     uint32_t besr0;
 333     uint32_t besr1;
 334     uint32_t bear;
 335     uint32_t cfg;
 336     uint32_t status;
 337     uint32_t rtr;
 338     uint32_t pmit;
 339     uint32_t bcr[4];
 340     uint32_t tr;
 341     uint32_t ecccfg;
 342     uint32_t eccesr;
 343     qemu_irq irq;
 344 };
 345
 346 enum {
 347     SDRAM0_CFGADDR = 0x010,
 348     SDRAM0_CFGDATA = 0x011,
 349 };
 350
 351 /* XXX: TOFIX: some patches have made this code become inconsistent:
 352  *      there are type inconsistencies, mixing hwaddr, target_ulong
 353  *      and uint32_t
 354  */
 355 static uint32_t sdram_bcr (hwaddr ram_base,
 356                            hwaddr ram_size)
 357 {
 358     uint32_t bcr;
 359
 360     switch (ram_size) {
 361     case (4 * 1024 * 1024):
 362         bcr = 0x00000000;
 363         break;
 364     case (8 * 1024 * 1024):
 365         bcr = 0x00020000;
 366         break;
 367     case (16 * 1024 * 1024):
 368         bcr = 0x00040000;
 369         break;
 370     case (32 * 1024 * 1024):
 371         bcr = 0x00060000;
 372         break;
 373     case (64 * 1024 * 1024):
 374         bcr = 0x00080000;
 375         break;
 376     case (128 * 1024 * 1024):
 377         bcr = 0x000A0000;
 378         break;
 379     case (256 * 1024 * 1024):
 380         bcr = 0x000C0000;
 381         break;
 382     default:
 383         printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
 384                ram_size);
 385         return 0x00000000;
 386     }
 387     bcr |= ram_base & 0xFF800000;
 388     bcr |= 1;
 389
 390     return bcr;
 391 }
 392
 393 static inline hwaddr sdram_base(uint32_t bcr)
 394 {
 395     return bcr & 0xFF800000;
 396 }
 397
 398 static target_ulong sdram_size (uint32_t bcr)
 399 {
 400     target_ulong size;
 401     int sh;
 402
 403     sh = (bcr >> 17) & 0x7;
 404     if (sh == 7)
 405         size = -1;
 406     else
 407         size = (4 * 1024 * 1024) << sh;
 408
 409     return size;
 410 }
 411
 412 static void sdram_set_bcr(ppc4xx_sdram_t *sdram,
 413                           uint32_t *bcrp, uint32_t bcr, int enabled)
 414 {
 415     unsigned n = bcrp - sdram->bcr;
 416
 417     if (*bcrp & 0x00000001) {
 418         /* Unmap RAM */
 419 #ifdef DEBUG_SDRAM
 420         printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 421                __func__, sdram_base(*bcrp), sdram_size(*bcrp));
 422 #endif
 423         memory_region_del_subregion(get_system_memory(),
 424                                     &sdram->containers[n]);
 425         memory_region_del_subregion(&sdram->containers[n],
 426                                     &sdram->ram_memories[n]);
 427         object_unparent(OBJECT(&sdram->containers[n]));
 428     }
 429     *bcrp = bcr & 0xFFDEE001;
 430     if (enabled && (bcr & 0x00000001)) {
 431 #ifdef DEBUG_SDRAM
 432         printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 433                __func__, sdram_base(bcr), sdram_size(bcr));
 434 #endif
 435         memory_region_init(&sdram->containers[n], NULL, "sdram-containers",
 436                            sdram_size(bcr));
 437         memory_region_add_subregion(&sdram->containers[n], 0,
 438                                     &sdram->ram_memories[n]);
 439         memory_region_add_subregion(get_system_memory(),
 440                                     sdram_base(bcr),
 441                                     &sdram->containers[n]);
 442     }
 443 }
 444
 445 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
 446 {
 447     int i;
 448
 449     for (i = 0; i < sdram->nbanks; i++) {
 450         if (sdram->ram_sizes[i] != 0) {
 451             sdram_set_bcr(sdram,
 452                           &sdram->bcr[i],
 453                           sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
 454                           1);
 455         } else {
 456             sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0);
 457         }
 458     }
 459 }
 460
 461 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
 462 {
 463     int i;
 464
 465     for (i = 0; i < sdram->nbanks; i++) {
 466 #ifdef DEBUG_SDRAM
 467         printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 468                __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
 469 #endif
 470         memory_region_del_subregion(get_system_memory(),
 471                                     &sdram->ram_memories[i]);
 472     }
 473 }
 474
 475 static uint32_t dcr_read_sdram (void *opaque, int dcrn)
 476 {
 477     ppc4xx_sdram_t *sdram;
 478     uint32_t ret;
 479
 480     sdram = opaque;
 481     switch (dcrn) {
 482     case SDRAM0_CFGADDR:
 483         ret = sdram->addr;
 484         break;
 485     case SDRAM0_CFGDATA:
 486         switch (sdram->addr) {
 487         case 0x00: /* SDRAM_BESR0 */
 488             ret = sdram->besr0;
 489             break;
 490         case 0x08: /* SDRAM_BESR1 */
 491             ret = sdram->besr1;
 492             break;
 493         case 0x10: /* SDRAM_BEAR */
 494             ret = sdram->bear;
 495             break;
 496         case 0x20: /* SDRAM_CFG */
 497             ret = sdram->cfg;
 498             break;
 499         case 0x24: /* SDRAM_STATUS */
 500             ret = sdram->status;
 501             break;
 502         case 0x30: /* SDRAM_RTR */
 503             ret = sdram->rtr;
 504             break;
 505         case 0x34: /* SDRAM_PMIT */
 506             ret = sdram->pmit;
 507             break;
 508         case 0x40: /* SDRAM_B0CR */
 509             ret = sdram->bcr[0];
 510             break;
 511         case 0x44: /* SDRAM_B1CR */
 512             ret = sdram->bcr[1];
 513             break;
 514         case 0x48: /* SDRAM_B2CR */
 515             ret = sdram->bcr[2];
 516             break;
 517         case 0x4C: /* SDRAM_B3CR */
 518             ret = sdram->bcr[3];
 519             break;
 520         case 0x80: /* SDRAM_TR */
 521             ret = -1; /* ? */
 522             break;
 523         case 0x94: /* SDRAM_ECCCFG */
 524             ret = sdram->ecccfg;
 525             break;
 526         case 0x98: /* SDRAM_ECCESR */
 527             ret = sdram->eccesr;
 528             break;
 529         default: /* Error */
 530             ret = -1;
 531             break;
 532         }
 533         break;
 534     default:
 535         /* Avoid gcc warning */
 536         ret = 0x00000000;
 537         break;
 538     }
 539
 540     return ret;
 541 }
 542
 543 static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
 544 {
 545     ppc4xx_sdram_t *sdram;
 546
 547     sdram = opaque;
 548     switch (dcrn) {
 549     case SDRAM0_CFGADDR:
 550         sdram->addr = val;
 551         break;
 552     case SDRAM0_CFGDATA:
 553         switch (sdram->addr) {
 554         case 0x00: /* SDRAM_BESR0 */
 555             sdram->besr0 &= ~val;
 556             break;
 557         case 0x08: /* SDRAM_BESR1 */
 558             sdram->besr1 &= ~val;
 559             break;
 560         case 0x10: /* SDRAM_BEAR */
 561             sdram->bear = val;
 562             break;
 563         case 0x20: /* SDRAM_CFG */
 564             val &= 0xFFE00000;
 565             if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
 566 #ifdef DEBUG_SDRAM
 567                 printf("%s: enable SDRAM controller\n", __func__);
 568 #endif
 569                 /* validate all RAM mappings */
 570                 sdram_map_bcr(sdram);
 571                 sdram->status &= ~0x80000000;
 572             } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
 573 #ifdef DEBUG_SDRAM
 574                 printf("%s: disable SDRAM controller\n", __func__);
 575 #endif
 576                 /* invalidate all RAM mappings */
 577                 sdram_unmap_bcr(sdram);
 578                 sdram->status |= 0x80000000;
 579             }
 580             if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
 581                 sdram->status |= 0x40000000;
 582             else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
 583                 sdram->status &= ~0x40000000;
 584             sdram->cfg = val;
 585             break;
 586         case 0x24: /* SDRAM_STATUS */
 587             /* Read-only register */
 588             break;
 589         case 0x30: /* SDRAM_RTR */
 590             sdram->rtr = val & 0x3FF80000;
 591             break;
 592         case 0x34: /* SDRAM_PMIT */
 593             sdram->pmit = (val & 0xF8000000) | 0x07C00000;
 594             break;
 595         case 0x40: /* SDRAM_B0CR */
 596             sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000);
 597             break;
 598         case 0x44: /* SDRAM_B1CR */
 599             sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000);
 600             break;
 601         case 0x48: /* SDRAM_B2CR */
 602             sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000);
 603             break;
 604         case 0x4C: /* SDRAM_B3CR */
 605             sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000);
 606             break;
 607         case 0x80: /* SDRAM_TR */
 608             sdram->tr = val & 0x018FC01F;
 609             break;
 610         case 0x94: /* SDRAM_ECCCFG */
 611             sdram->ecccfg = val & 0x00F00000;
 612             break;
 613         case 0x98: /* SDRAM_ECCESR */
 614             val &= 0xFFF0F000;
 615             if (sdram->eccesr == 0 && val != 0)
 616                 qemu_irq_raise(sdram->irq);
 617             else if (sdram->eccesr != 0 && val == 0)
 618                 qemu_irq_lower(sdram->irq);
 619             sdram->eccesr = val;
 620             break;
 621         default: /* Error */
 622             break;
 623         }
 624         break;
 625     }
 626 }
 627
 628 static void sdram_reset (void *opaque)
 629 {
 630     ppc4xx_sdram_t *sdram;
 631
 632     sdram = opaque;
 633     sdram->addr = 0x00000000;
 634     sdram->bear = 0x00000000;
 635     sdram->besr0 = 0x00000000; /* No error */
 636     sdram->besr1 = 0x00000000; /* No error */
 637     sdram->cfg = 0x00000000;
 638     sdram->ecccfg = 0x00000000; /* No ECC */
 639     sdram->eccesr = 0x00000000; /* No error */
 640     sdram->pmit = 0x07C00000;
 641     sdram->rtr = 0x05F00000;
 642     sdram->tr = 0x00854009;
 643     /* We pre-initialize RAM banks */
 644     sdram->status = 0x00000000;
 645     sdram->cfg = 0x00800000;
 646 }
 647
 648 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
 649                         MemoryRegion *ram_memories,
 650                         hwaddr *ram_bases,
 651                         hwaddr *ram_sizes,
 652                         int do_init)
 653 {
 654     ppc4xx_sdram_t *sdram;
 655
 656     sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
 657     sdram->irq = irq;
 658     sdram->nbanks = nbanks;
 659     sdram->ram_memories = ram_memories;
 660     memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
 661     memcpy(sdram->ram_bases, ram_bases,
 662            nbanks * sizeof(hwaddr));
 663     memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
 664     memcpy(sdram->ram_sizes, ram_sizes,
 665            nbanks * sizeof(hwaddr));
 666     qemu_register_reset(&sdram_reset, sdram);
 667     ppc_dcr_register(env, SDRAM0_CFGADDR,
 668                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 669     ppc_dcr_register(env, SDRAM0_CFGDATA,
 670                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 671     if (do_init)
 672         sdram_map_bcr(sdram);
 673 }
 674
 675 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
 676  *
 677  * sdram_bank_sizes[] must be 0-terminated.
 678  *
 679  * The 4xx SDRAM controller supports a small number of banks, and each bank
 680  * must be one of a small set of sizes. The number of banks and the supported
 681  * sizes varies by SoC. */
 682 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
 683                                MemoryRegion ram_memories[],
 684                                hwaddr ram_bases[],
 685                                hwaddr ram_sizes[],
 686                                const unsigned int sdram_bank_sizes[])
 687 {
 688     MemoryRegion *ram = g_malloc0(sizeof(*ram));
 689     ram_addr_t size_left = ram_size;
 690     ram_addr_t base = 0;
 691     unsigned int bank_size;
 692     int i;
 693     int j;
 694
 695     for (i = 0; i < nr_banks; i++) {
 696         for (j = 0; sdram_bank_sizes[j] != 0; j++) {
 697             bank_size = sdram_bank_sizes[j];
 698             if (bank_size <= size_left) {
 699                 size_left -= bank_size;
 700             }
 701         }
 702         if (!size_left) {
 703             /* No need to use the remaining banks. */
 704             break;
 705         }
 706     }
 707
 708     ram_size -= size_left;
 709     if (size_left) {
 710         printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
 711                (int)(ram_size >> 20));
 712     }
 713
 714     memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size);
 715
 716     size_left = ram_size;
 717     for (i = 0; i < nr_banks && size_left; i++) {
 718         for (j = 0; sdram_bank_sizes[j] != 0; j++) {
 719             bank_size = sdram_bank_sizes[j];
 720
 721             if (bank_size <= size_left) {
 722                 char name[32];
 723                 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
 724                 memory_region_init_alias(&ram_memories[i], NULL, name, ram,
 725                                          base, bank_size);
 726                 ram_bases[i] = base;
 727                 ram_sizes[i] = bank_size;
 728                 base += bank_size;
 729                 size_left -= bank_size;
 730                 break;
 731             }
 732         }
 733     }
 734
 735     return ram_size;
 736 }
 737
 738 /*****************************************************************************/
 739 /* MAL */
 740
 741 enum {
 742     MAL0_CFG      = 0x180,
 743     MAL0_ESR      = 0x181,
 744     MAL0_IER      = 0x182,
 745     MAL0_TXCASR   = 0x184,
 746     MAL0_TXCARR   = 0x185,
 747     MAL0_TXEOBISR = 0x186,
 748     MAL0_TXDEIR   = 0x187,
 749     MAL0_RXCASR   = 0x190,
 750     MAL0_RXCARR   = 0x191,
 751     MAL0_RXEOBISR = 0x192,
 752     MAL0_RXDEIR   = 0x193,
 753     MAL0_TXCTP0R  = 0x1A0,
 754     MAL0_RXCTP0R  = 0x1C0,
 755     MAL0_RCBS0    = 0x1E0,
 756     MAL0_RCBS1    = 0x1E1,
 757 };
 758
 759 typedef struct ppc4xx_mal_t ppc4xx_mal_t;
 760 struct ppc4xx_mal_t {
 761     qemu_irq irqs[4];
 762     uint32_t cfg;
 763     uint32_t esr;
 764     uint32_t ier;
 765     uint32_t txcasr;
 766     uint32_t txcarr;
 767     uint32_t txeobisr;
 768     uint32_t txdeir;
 769     uint32_t rxcasr;
 770     uint32_t rxcarr;
 771     uint32_t rxeobisr;
 772     uint32_t rxdeir;
 773     uint32_t *txctpr;
 774     uint32_t *rxctpr;
 775     uint32_t *rcbs;
 776     uint8_t  txcnum;
 777     uint8_t  rxcnum;
 778 };
 779
 780 static void ppc4xx_mal_reset(void *opaque)
 781 {
 782     ppc4xx_mal_t *mal;
 783
 784     mal = opaque;
 785     mal->cfg = 0x0007C000;
 786     mal->esr = 0x00000000;
 787     mal->ier = 0x00000000;
 788     mal->rxcasr = 0x00000000;
 789     mal->rxdeir = 0x00000000;
 790     mal->rxeobisr = 0x00000000;
 791     mal->txcasr = 0x00000000;
 792     mal->txdeir = 0x00000000;
 793     mal->txeobisr = 0x00000000;
 794 }
 795
 796 static uint32_t dcr_read_mal(void *opaque, int dcrn)
 797 {
 798     ppc4xx_mal_t *mal;
 799     uint32_t ret;
 800
 801     mal = opaque;
 802     switch (dcrn) {
 803     case MAL0_CFG:
 804         ret = mal->cfg;
 805         break;
 806     case MAL0_ESR:
 807         ret = mal->esr;
 808         break;
 809     case MAL0_IER:
 810         ret = mal->ier;
 811         break;
 812     case MAL0_TXCASR:
 813         ret = mal->txcasr;
 814         break;
 815     case MAL0_TXCARR:
 816         ret = mal->txcarr;
 817         break;
 818     case MAL0_TXEOBISR:
 819         ret = mal->txeobisr;
 820         break;
 821     case MAL0_TXDEIR:
 822         ret = mal->txdeir;
 823         break;
 824     case MAL0_RXCASR:
 825         ret = mal->rxcasr;
 826         break;
 827     case MAL0_RXCARR:
 828         ret = mal->rxcarr;
 829         break;
 830     case MAL0_RXEOBISR:
 831         ret = mal->rxeobisr;
 832         break;
 833     case MAL0_RXDEIR:
 834         ret = mal->rxdeir;
 835         break;
 836     default:
 837         ret = 0;
 838         break;
 839     }
 840     if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
 841         ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
 842     }
 843     if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
 844         ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
 845     }
 846     if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
 847         ret = mal->rcbs[dcrn - MAL0_RCBS0];
 848     }
 849
 850     return ret;
 851 }
 852
 853 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
 854 {
 855     ppc4xx_mal_t *mal;
 856
 857     mal = opaque;
 858     switch (dcrn) {
 859     case MAL0_CFG:
 860         if (val & 0x80000000) {
 861             ppc4xx_mal_reset(mal);
 862         }
 863         mal->cfg = val & 0x00FFC087;
 864         break;
 865     case MAL0_ESR:
 866         /* Read/clear */
 867         mal->esr &= ~val;
 868         break;
 869     case MAL0_IER:
 870         mal->ier = val & 0x0000001F;
 871         break;
 872     case MAL0_TXCASR:
 873         mal->txcasr = val & 0xF0000000;
 874         break;
 875     case MAL0_TXCARR:
 876         mal->txcarr = val & 0xF0000000;
 877         break;
 878     case MAL0_TXEOBISR:
 879         /* Read/clear */
 880         mal->txeobisr &= ~val;
 881         break;
 882     case MAL0_TXDEIR:
 883         /* Read/clear */
 884         mal->txdeir &= ~val;
 885         break;
 886     case MAL0_RXCASR:
 887         mal->rxcasr = val & 0xC0000000;
 888         break;
 889     case MAL0_RXCARR:
 890         mal->rxcarr = val & 0xC0000000;
 891         break;
 892     case MAL0_RXEOBISR:
 893         /* Read/clear */
 894         mal->rxeobisr &= ~val;
 895         break;
 896     case MAL0_RXDEIR:
 897         /* Read/clear */
 898         mal->rxdeir &= ~val;
 899         break;
 900     }
 901     if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
 902         mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
 903     }
 904     if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
 905         mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
 906     }
 907     if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
 908         mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
 909     }
 910 }
 911
 912 void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
 913                      qemu_irq irqs[4])
 914 {
 915     ppc4xx_mal_t *mal;
 916     int i;
 917
 918     assert(txcnum <= 32 && rxcnum <= 32);
 919     mal = g_malloc0(sizeof(*mal));
 920     mal->txcnum = txcnum;
 921     mal->rxcnum = rxcnum;
 922     mal->txctpr = g_new0(uint32_t, txcnum);
 923     mal->rxctpr = g_new0(uint32_t, rxcnum);
 924     mal->rcbs = g_new0(uint32_t, rxcnum);
 925     for (i = 0; i < 4; i++) {
 926         mal->irqs[i] = irqs[i];
 927     }
 928     qemu_register_reset(&ppc4xx_mal_reset, mal);
 929     ppc_dcr_register(env, MAL0_CFG,
 930                      mal, &dcr_read_mal, &dcr_write_mal);
 931     ppc_dcr_register(env, MAL0_ESR,
 932                      mal, &dcr_read_mal, &dcr_write_mal);
 933     ppc_dcr_register(env, MAL0_IER,
 934                      mal, &dcr_read_mal, &dcr_write_mal);
 935     ppc_dcr_register(env, MAL0_TXCASR,
 936                      mal, &dcr_read_mal, &dcr_write_mal);
 937     ppc_dcr_register(env, MAL0_TXCARR,
 938                      mal, &dcr_read_mal, &dcr_write_mal);
 939     ppc_dcr_register(env, MAL0_TXEOBISR,
 940                      mal, &dcr_read_mal, &dcr_write_mal);
 941     ppc_dcr_register(env, MAL0_TXDEIR,
 942                      mal, &dcr_read_mal, &dcr_write_mal);
 943     ppc_dcr_register(env, MAL0_RXCASR,
 944                      mal, &dcr_read_mal, &dcr_write_mal);
 945     ppc_dcr_register(env, MAL0_RXCARR,
 946                      mal, &dcr_read_mal, &dcr_write_mal);
 947     ppc_dcr_register(env, MAL0_RXEOBISR,
 948                      mal, &dcr_read_mal, &dcr_write_mal);
 949     ppc_dcr_register(env, MAL0_RXDEIR,
 950                      mal, &dcr_read_mal, &dcr_write_mal);
 951     for (i = 0; i < txcnum; i++) {
 952         ppc_dcr_register(env, MAL0_TXCTP0R + i,
 953                          mal, &dcr_read_mal, &dcr_write_mal);
 954     }
 955     for (i = 0; i < rxcnum; i++) {
 956         ppc_dcr_register(env, MAL0_RXCTP0R + i,
 957                          mal, &dcr_read_mal, &dcr_write_mal);
 958     }
 959     for (i = 0; i < rxcnum; i++) {
 960         ppc_dcr_register(env, MAL0_RCBS0 + i,
 961                          mal, &dcr_read_mal, &dcr_write_mal);
 962     }
 963 }