hw/ppc/ppc4xx_devs.c

   1 /*
   2  * QEMU PowerPC 4xx embedded processors shared devices emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "sysemu/reset.h"
  28 #include "cpu.h"
  29 #include "hw/irq.h"
  30 #include "hw/ppc/ppc.h"
  31 #include "hw/ppc/ppc4xx.h"
  32 #include "hw/qdev-properties.h"
  33 #include "qemu/log.h"
  34 #include "exec/address-spaces.h"
  35 #include "qemu/error-report.h"
  36 #include "qapi/error.h"
  37 #include "trace.h"
  38
  39 /*****************************************************************************/
  40 /* SDRAM controller */
  41 enum {
  42     SDRAM0_CFGADDR = 0x010,
  43     SDRAM0_CFGDATA = 0x011,
  44 };
  45
  46 /*
  47  * XXX: TOFIX: some patches have made this code become inconsistent:
  48  *      there are type inconsistencies, mixing hwaddr, target_ulong
  49  *      and uint32_t
  50  */
  51 static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
  52 {
  53     uint32_t bcr;
  54
  55     switch (ram_size) {
  56     case 4 * MiB:
  57         bcr = 0;
  58         break;
  59     case 8 * MiB:
  60         bcr = 0x20000;
  61         break;
  62     case 16 * MiB:
  63         bcr = 0x40000;
  64         break;
  65     case 32 * MiB:
  66         bcr = 0x60000;
  67         break;
  68     case 64 * MiB:
  69         bcr = 0x80000;
  70         break;
  71     case 128 * MiB:
  72         bcr = 0xA0000;
  73         break;
  74     case 256 * MiB:
  75         bcr = 0xC0000;
  76         break;
  77     default:
  78         qemu_log_mask(LOG_GUEST_ERROR,
  79                       "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
  80                       ram_size);
  81         return 0;
  82     }
  83     bcr |= ram_base & 0xFF800000;
  84     bcr |= 1;
  85
  86     return bcr;
  87 }
  88
  89 static inline hwaddr sdram_ddr_base(uint32_t bcr)
  90 {
  91     return bcr & 0xFF800000;
  92 }
  93
  94 static target_ulong sdram_ddr_size(uint32_t bcr)
  95 {
  96     target_ulong size;
  97     int sh;
  98
  99     sh = (bcr >> 17) & 0x7;
 100     if (sh == 7) {
 101         size = -1;
 102     } else {
 103         size = (4 * MiB) << sh;
 104     }
 105
 106     return size;
 107 }
 108
 109 static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
 110                               uint32_t bcr, int enabled)
 111 {
 112     if (sdram->bank[i].bcr & 1) {
 113         /* Unmap RAM */
 114         trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
 115                                  sdram_ddr_size(sdram->bank[i].bcr));
 116         memory_region_del_subregion(get_system_memory(),
 117                                     &sdram->bank[i].container);
 118         memory_region_del_subregion(&sdram->bank[i].container,
 119                                     &sdram->bank[i].ram);
 120         object_unparent(OBJECT(&sdram->bank[i].container));
 121     }
 122     sdram->bank[i].bcr = bcr & 0xFFDEE001;
 123     if (enabled && (bcr & 1)) {
 124         trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
 125         memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
 126                            sdram_ddr_size(bcr));
 127         memory_region_add_subregion(&sdram->bank[i].container, 0,
 128                                     &sdram->bank[i].ram);
 129         memory_region_add_subregion(get_system_memory(),
 130                                     sdram_ddr_base(bcr),
 131                                     &sdram->bank[i].container);
 132     }
 133 }
 134
 135 static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
 136 {
 137     int i;
 138
 139     for (i = 0; i < sdram->nbanks; i++) {
 140         if (sdram->bank[i].size != 0) {
 141             sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
 142                                                       sdram->bank[i].size), 1);
 143         } else {
 144             sdram_ddr_set_bcr(sdram, i, 0, 0);
 145         }
 146     }
 147 }
 148
 149 static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
 150 {
 151     int i;
 152
 153     for (i = 0; i < sdram->nbanks; i++) {
 154         trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
 155                                  sdram_ddr_size(sdram->bank[i].bcr));
 156         memory_region_del_subregion(get_system_memory(),
 157                                     &sdram->bank[i].ram);
 158     }
 159 }
 160
 161 static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
 162 {
 163     Ppc4xxSdramDdrState *sdram = opaque;
 164     uint32_t ret;
 165
 166     switch (dcrn) {
 167     case SDRAM0_CFGADDR:
 168         ret = sdram->addr;
 169         break;
 170     case SDRAM0_CFGDATA:
 171         switch (sdram->addr) {
 172         case 0x00: /* SDRAM_BESR0 */
 173             ret = sdram->besr0;
 174             break;
 175         case 0x08: /* SDRAM_BESR1 */
 176             ret = sdram->besr1;
 177             break;
 178         case 0x10: /* SDRAM_BEAR */
 179             ret = sdram->bear;
 180             break;
 181         case 0x20: /* SDRAM_CFG */
 182             ret = sdram->cfg;
 183             break;
 184         case 0x24: /* SDRAM_STATUS */
 185             ret = sdram->status;
 186             break;
 187         case 0x30: /* SDRAM_RTR */
 188             ret = sdram->rtr;
 189             break;
 190         case 0x34: /* SDRAM_PMIT */
 191             ret = sdram->pmit;
 192             break;
 193         case 0x40: /* SDRAM_B0CR */
 194             ret = sdram->bank[0].bcr;
 195             break;
 196         case 0x44: /* SDRAM_B1CR */
 197             ret = sdram->bank[1].bcr;
 198             break;
 199         case 0x48: /* SDRAM_B2CR */
 200             ret = sdram->bank[2].bcr;
 201             break;
 202         case 0x4C: /* SDRAM_B3CR */
 203             ret = sdram->bank[3].bcr;
 204             break;
 205         case 0x80: /* SDRAM_TR */
 206             ret = -1; /* ? */
 207             break;
 208         case 0x94: /* SDRAM_ECCCFG */
 209             ret = sdram->ecccfg;
 210             break;
 211         case 0x98: /* SDRAM_ECCESR */
 212             ret = sdram->eccesr;
 213             break;
 214         default: /* Error */
 215             ret = -1;
 216             break;
 217         }
 218         break;
 219     default:
 220         /* Avoid gcc warning */
 221         ret = 0;
 222         break;
 223     }
 224
 225     return ret;
 226 }
 227
 228 static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
 229 {
 230     Ppc4xxSdramDdrState *sdram = opaque;
 231
 232     switch (dcrn) {
 233     case SDRAM0_CFGADDR:
 234         sdram->addr = val;
 235         break;
 236     case SDRAM0_CFGDATA:
 237         switch (sdram->addr) {
 238         case 0x00: /* SDRAM_BESR0 */
 239             sdram->besr0 &= ~val;
 240             break;
 241         case 0x08: /* SDRAM_BESR1 */
 242             sdram->besr1 &= ~val;
 243             break;
 244         case 0x10: /* SDRAM_BEAR */
 245             sdram->bear = val;
 246             break;
 247         case 0x20: /* SDRAM_CFG */
 248             val &= 0xFFE00000;
 249             if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
 250                 trace_ppc4xx_sdram_enable("enable");
 251                 /* validate all RAM mappings */
 252                 sdram_ddr_map_bcr(sdram);
 253                 sdram->status &= ~0x80000000;
 254             } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
 255                 trace_ppc4xx_sdram_enable("disable");
 256                 /* invalidate all RAM mappings */
 257                 sdram_ddr_unmap_bcr(sdram);
 258                 sdram->status |= 0x80000000;
 259             }
 260             if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
 261                 sdram->status |= 0x40000000;
 262             } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) {
 263                 sdram->status &= ~0x40000000;
 264             }
 265             sdram->cfg = val;
 266             break;
 267         case 0x24: /* SDRAM_STATUS */
 268             /* Read-only register */
 269             break;
 270         case 0x30: /* SDRAM_RTR */
 271             sdram->rtr = val & 0x3FF80000;
 272             break;
 273         case 0x34: /* SDRAM_PMIT */
 274             sdram->pmit = (val & 0xF8000000) | 0x07C00000;
 275             break;
 276         case 0x40: /* SDRAM_B0CR */
 277             sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
 278             break;
 279         case 0x44: /* SDRAM_B1CR */
 280             sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
 281             break;
 282         case 0x48: /* SDRAM_B2CR */
 283             sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
 284             break;
 285         case 0x4C: /* SDRAM_B3CR */
 286             sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
 287             break;
 288         case 0x80: /* SDRAM_TR */
 289             sdram->tr = val & 0x018FC01F;
 290             break;
 291         case 0x94: /* SDRAM_ECCCFG */
 292             sdram->ecccfg = val & 0x00F00000;
 293             break;
 294         case 0x98: /* SDRAM_ECCESR */
 295             val &= 0xFFF0F000;
 296             if (sdram->eccesr == 0 && val != 0) {
 297                 qemu_irq_raise(sdram->irq);
 298             } else if (sdram->eccesr != 0 && val == 0) {
 299                 qemu_irq_lower(sdram->irq);
 300             }
 301             sdram->eccesr = val;
 302             break;
 303         default: /* Error */
 304             break;
 305         }
 306         break;
 307     }
 308 }
 309
 310 static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
 311 {
 312     Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
 313
 314     sdram->addr = 0;
 315     sdram->bear = 0;
 316     sdram->besr0 = 0; /* No error */
 317     sdram->besr1 = 0; /* No error */
 318     sdram->cfg = 0;
 319     sdram->ecccfg = 0; /* No ECC */
 320     sdram->eccesr = 0; /* No error */
 321     sdram->pmit = 0x07C00000;
 322     sdram->rtr = 0x05F00000;
 323     sdram->tr = 0x00854009;
 324     /* We pre-initialize RAM banks */
 325     sdram->status = 0;
 326     sdram->cfg = 0x00800000;
 327 }
 328
 329 static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
 330 {
 331     Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
 332     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 333     const ram_addr_t valid_bank_sizes[] = {
 334         256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
 335     };
 336
 337     if (s->nbanks < 1 || s->nbanks > 4) {
 338         error_setg(errp, "Invalid number of RAM banks");
 339         return;
 340     }
 341     if (!s->dram_mr) {
 342         error_setg(errp, "Missing dram memory region");
 343         return;
 344     }
 345     ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
 346
 347     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 348
 349     ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
 350                         s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
 351     ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
 352                         s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
 353 }
 354
 355 static Property ppc4xx_sdram_ddr_props[] = {
 356     DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
 357                      MemoryRegion *),
 358     DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
 359     DEFINE_PROP_END_OF_LIST(),
 360 };
 361
 362 static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
 363 {
 364     DeviceClass *dc = DEVICE_CLASS(oc);
 365
 366     dc->realize = ppc4xx_sdram_ddr_realize;
 367     dc->reset = ppc4xx_sdram_ddr_reset;
 368     /* Reason: only works as function of a ppc4xx SoC */
 369     dc->user_creatable = false;
 370     device_class_set_props(dc, ppc4xx_sdram_ddr_props);
 371 }
 372
 373 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
 374 {
 375     sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
 376     sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
 377 }
 378
 379 /*
 380  * Split RAM between SDRAM banks.
 381  *
 382  * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
 383  * and must be 0-terminated.
 384  *
 385  * The 4xx SDRAM controller supports a small number of banks, and each bank
 386  * must be one of a small set of sizes. The number of banks and the supported
 387  * sizes varies by SoC.
 388  */
 389 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
 390                         Ppc4xxSdramBank ram_banks[],
 391                         const ram_addr_t sdram_bank_sizes[])
 392 {
 393     ram_addr_t size_left = memory_region_size(ram);
 394     ram_addr_t base = 0;
 395     ram_addr_t bank_size;
 396     int i;
 397     int j;
 398
 399     for (i = 0; i < nr_banks; i++) {
 400         for (j = 0; sdram_bank_sizes[j] != 0; j++) {
 401             bank_size = sdram_bank_sizes[j];
 402             if (bank_size <= size_left) {
 403                 char name[32];
 404
 405                 ram_banks[i].base = base;
 406                 ram_banks[i].size = bank_size;
 407                 base += bank_size;
 408                 size_left -= bank_size;
 409                 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
 410                 memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
 411                                          ram_banks[i].base, ram_banks[i].size);
 412                 break;
 413             }
 414         }
 415         if (!size_left) {
 416             /* No need to use the remaining banks. */
 417             break;
 418         }
 419     }
 420
 421     if (size_left) {
 422         ram_addr_t used_size = memory_region_size(ram) - size_left;
 423         GString *s = g_string_new(NULL);
 424
 425         for (i = 0; sdram_bank_sizes[i]; i++) {
 426             g_string_append_printf(s, "%" PRIi64 "%s",
 427                                    sdram_bank_sizes[i] / MiB,
 428                                    sdram_bank_sizes[i + 1] ? ", " : "");
 429         }
 430         error_report("at most %d bank%s of %s MiB each supported",
 431                      nr_banks, nr_banks == 1 ? "" : "s", s->str);
 432         error_printf("Possible valid RAM size: %" PRIi64 " MiB\n",
 433             used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
 434
 435         g_string_free(s, true);
 436         exit(EXIT_FAILURE);
 437     }
 438 }
 439
 440 /*****************************************************************************/
 441 /* MAL */
 442
 443 enum {
 444     MAL0_CFG      = 0x180,
 445     MAL0_ESR      = 0x181,
 446     MAL0_IER      = 0x182,
 447     MAL0_TXCASR   = 0x184,
 448     MAL0_TXCARR   = 0x185,
 449     MAL0_TXEOBISR = 0x186,
 450     MAL0_TXDEIR   = 0x187,
 451     MAL0_RXCASR   = 0x190,
 452     MAL0_RXCARR   = 0x191,
 453     MAL0_RXEOBISR = 0x192,
 454     MAL0_RXDEIR   = 0x193,
 455     MAL0_TXCTP0R  = 0x1A0,
 456     MAL0_RXCTP0R  = 0x1C0,
 457     MAL0_RCBS0    = 0x1E0,
 458     MAL0_RCBS1    = 0x1E1,
 459 };
 460
 461 static void ppc4xx_mal_reset(DeviceState *dev)
 462 {
 463     Ppc4xxMalState *mal = PPC4xx_MAL(dev);
 464
 465     mal->cfg = 0x0007C000;
 466     mal->esr = 0x00000000;
 467     mal->ier = 0x00000000;
 468     mal->rxcasr = 0x00000000;
 469     mal->rxdeir = 0x00000000;
 470     mal->rxeobisr = 0x00000000;
 471     mal->txcasr = 0x00000000;
 472     mal->txdeir = 0x00000000;
 473     mal->txeobisr = 0x00000000;
 474 }
 475
 476 static uint32_t dcr_read_mal(void *opaque, int dcrn)
 477 {
 478     Ppc4xxMalState *mal = opaque;
 479     uint32_t ret;
 480
 481     switch (dcrn) {
 482     case MAL0_CFG:
 483         ret = mal->cfg;
 484         break;
 485     case MAL0_ESR:
 486         ret = mal->esr;
 487         break;
 488     case MAL0_IER:
 489         ret = mal->ier;
 490         break;
 491     case MAL0_TXCASR:
 492         ret = mal->txcasr;
 493         break;
 494     case MAL0_TXCARR:
 495         ret = mal->txcarr;
 496         break;
 497     case MAL0_TXEOBISR:
 498         ret = mal->txeobisr;
 499         break;
 500     case MAL0_TXDEIR:
 501         ret = mal->txdeir;
 502         break;
 503     case MAL0_RXCASR:
 504         ret = mal->rxcasr;
 505         break;
 506     case MAL0_RXCARR:
 507         ret = mal->rxcarr;
 508         break;
 509     case MAL0_RXEOBISR:
 510         ret = mal->rxeobisr;
 511         break;
 512     case MAL0_RXDEIR:
 513         ret = mal->rxdeir;
 514         break;
 515     default:
 516         ret = 0;
 517         break;
 518     }
 519     if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
 520         ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
 521     }
 522     if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
 523         ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
 524     }
 525     if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
 526         ret = mal->rcbs[dcrn - MAL0_RCBS0];
 527     }
 528
 529     return ret;
 530 }
 531
 532 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
 533 {
 534     Ppc4xxMalState *mal = opaque;
 535
 536     switch (dcrn) {
 537     case MAL0_CFG:
 538         if (val & 0x80000000) {
 539             ppc4xx_mal_reset(DEVICE(mal));
 540         }
 541         mal->cfg = val & 0x00FFC087;
 542         break;
 543     case MAL0_ESR:
 544         /* Read/clear */
 545         mal->esr &= ~val;
 546         break;
 547     case MAL0_IER:
 548         mal->ier = val & 0x0000001F;
 549         break;
 550     case MAL0_TXCASR:
 551         mal->txcasr = val & 0xF0000000;
 552         break;
 553     case MAL0_TXCARR:
 554         mal->txcarr = val & 0xF0000000;
 555         break;
 556     case MAL0_TXEOBISR:
 557         /* Read/clear */
 558         mal->txeobisr &= ~val;
 559         break;
 560     case MAL0_TXDEIR:
 561         /* Read/clear */
 562         mal->txdeir &= ~val;
 563         break;
 564     case MAL0_RXCASR:
 565         mal->rxcasr = val & 0xC0000000;
 566         break;
 567     case MAL0_RXCARR:
 568         mal->rxcarr = val & 0xC0000000;
 569         break;
 570     case MAL0_RXEOBISR:
 571         /* Read/clear */
 572         mal->rxeobisr &= ~val;
 573         break;
 574     case MAL0_RXDEIR:
 575         /* Read/clear */
 576         mal->rxdeir &= ~val;
 577         break;
 578     }
 579     if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
 580         mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
 581     }
 582     if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
 583         mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
 584     }
 585     if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
 586         mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
 587     }
 588 }
 589
 590 static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
 591 {
 592     Ppc4xxMalState *mal = PPC4xx_MAL(dev);
 593     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 594     int i;
 595
 596     if (mal->txcnum > 32 || mal->rxcnum > 32) {
 597         error_setg(errp, "invalid TXC/RXC number");
 598         return;
 599     }
 600
 601     mal->txctpr = g_new0(uint32_t, mal->txcnum);
 602     mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
 603     mal->rcbs = g_new0(uint32_t, mal->rxcnum);
 604
 605     for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
 606         sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]);
 607     }
 608
 609     ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal);
 610     ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal);
 611     ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal);
 612     ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal);
 613     ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal);
 614     ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
 615     ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
 616     ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal);
 617     ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal);
 618     ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
 619     ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
 620     for (i = 0; i < mal->txcnum; i++) {
 621         ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i,
 622                             mal, &dcr_read_mal, &dcr_write_mal);
 623     }
 624     for (i = 0; i < mal->rxcnum; i++) {
 625         ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i,
 626                             mal, &dcr_read_mal, &dcr_write_mal);
 627     }
 628     for (i = 0; i < mal->rxcnum; i++) {
 629         ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i,
 630                             mal, &dcr_read_mal, &dcr_write_mal);
 631     }
 632 }
 633
 634 static void ppc4xx_mal_finalize(Object *obj)
 635 {
 636     Ppc4xxMalState *mal = PPC4xx_MAL(obj);
 637
 638     g_free(mal->rcbs);
 639     g_free(mal->rxctpr);
 640     g_free(mal->txctpr);
 641 }
 642
 643 static Property ppc4xx_mal_properties[] = {
 644     DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
 645     DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
 646     DEFINE_PROP_END_OF_LIST(),
 647 };
 648
 649 static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
 650 {
 651     DeviceClass *dc = DEVICE_CLASS(oc);
 652
 653     dc->realize = ppc4xx_mal_realize;
 654     dc->reset = ppc4xx_mal_reset;
 655     /* Reason: only works as function of a ppc4xx SoC */
 656     dc->user_creatable = false;
 657     device_class_set_props(dc, ppc4xx_mal_properties);
 658 }
 659
 660 /*****************************************************************************/
 661 /* Peripheral local bus arbitrer */
 662 enum {
 663     PLB3A0_ACR = 0x077,
 664     PLB4A0_ACR = 0x081,
 665     PLB0_BESR  = 0x084,
 666     PLB0_BEAR  = 0x086,
 667     PLB0_ACR   = 0x087,
 668     PLB4A1_ACR = 0x089,
 669 };
 670
 671 static uint32_t dcr_read_plb(void *opaque, int dcrn)
 672 {
 673     Ppc4xxPlbState *plb = opaque;
 674     uint32_t ret;
 675
 676     switch (dcrn) {
 677     case PLB0_ACR:
 678         ret = plb->acr;
 679         break;
 680     case PLB0_BEAR:
 681         ret = plb->bear;
 682         break;
 683     case PLB0_BESR:
 684         ret = plb->besr;
 685         break;
 686     default:
 687         /* Avoid gcc warning */
 688         ret = 0;
 689         break;
 690     }
 691
 692     return ret;
 693 }
 694
 695 static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
 696 {
 697     Ppc4xxPlbState *plb = opaque;
 698
 699     switch (dcrn) {
 700     case PLB0_ACR:
 701         /*
 702          * We don't care about the actual parameters written as
 703          * we don't manage any priorities on the bus
 704          */
 705         plb->acr = val & 0xF8000000;
 706         break;
 707     case PLB0_BEAR:
 708         /* Read only */
 709         break;
 710     case PLB0_BESR:
 711         /* Write-clear */
 712         plb->besr &= ~val;
 713         break;
 714     }
 715 }
 716
 717 static void ppc405_plb_reset(DeviceState *dev)
 718 {
 719     Ppc4xxPlbState *plb = PPC4xx_PLB(dev);
 720
 721     plb->acr = 0x00000000;
 722     plb->bear = 0x00000000;
 723     plb->besr = 0x00000000;
 724 }
 725
 726 static void ppc405_plb_realize(DeviceState *dev, Error **errp)
 727 {
 728     Ppc4xxPlbState *plb = PPC4xx_PLB(dev);
 729     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 730
 731     ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
 732     ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
 733     ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
 734     ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
 735     ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
 736     ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
 737 }
 738
 739 static void ppc405_plb_class_init(ObjectClass *oc, void *data)
 740 {
 741     DeviceClass *dc = DEVICE_CLASS(oc);
 742
 743     dc->realize = ppc405_plb_realize;
 744     dc->reset = ppc405_plb_reset;
 745     /* Reason: only works as function of a ppc4xx SoC */
 746     dc->user_creatable = false;
 747 }
 748
 749 /*****************************************************************************/
 750 /* Peripheral controller */
 751 enum {
 752     EBC0_CFGADDR = 0x012,
 753     EBC0_CFGDATA = 0x013,
 754 };
 755
 756 static uint32_t dcr_read_ebc(void *opaque, int dcrn)
 757 {
 758     Ppc4xxEbcState *ebc = opaque;
 759     uint32_t ret;
 760
 761     switch (dcrn) {
 762     case EBC0_CFGADDR:
 763         ret = ebc->addr;
 764         break;
 765     case EBC0_CFGDATA:
 766         switch (ebc->addr) {
 767         case 0x00: /* B0CR */
 768             ret = ebc->bcr[0];
 769             break;
 770         case 0x01: /* B1CR */
 771             ret = ebc->bcr[1];
 772             break;
 773         case 0x02: /* B2CR */
 774             ret = ebc->bcr[2];
 775             break;
 776         case 0x03: /* B3CR */
 777             ret = ebc->bcr[3];
 778             break;
 779         case 0x04: /* B4CR */
 780             ret = ebc->bcr[4];
 781             break;
 782         case 0x05: /* B5CR */
 783             ret = ebc->bcr[5];
 784             break;
 785         case 0x06: /* B6CR */
 786             ret = ebc->bcr[6];
 787             break;
 788         case 0x07: /* B7CR */
 789             ret = ebc->bcr[7];
 790             break;
 791         case 0x10: /* B0AP */
 792             ret = ebc->bap[0];
 793             break;
 794         case 0x11: /* B1AP */
 795             ret = ebc->bap[1];
 796             break;
 797         case 0x12: /* B2AP */
 798             ret = ebc->bap[2];
 799             break;
 800         case 0x13: /* B3AP */
 801             ret = ebc->bap[3];
 802             break;
 803         case 0x14: /* B4AP */
 804             ret = ebc->bap[4];
 805             break;
 806         case 0x15: /* B5AP */
 807             ret = ebc->bap[5];
 808             break;
 809         case 0x16: /* B6AP */
 810             ret = ebc->bap[6];
 811             break;
 812         case 0x17: /* B7AP */
 813             ret = ebc->bap[7];
 814             break;
 815         case 0x20: /* BEAR */
 816             ret = ebc->bear;
 817             break;
 818         case 0x21: /* BESR0 */
 819             ret = ebc->besr0;
 820             break;
 821         case 0x22: /* BESR1 */
 822             ret = ebc->besr1;
 823             break;
 824         case 0x23: /* CFG */
 825             ret = ebc->cfg;
 826             break;
 827         default:
 828             ret = 0x00000000;
 829             break;
 830         }
 831         break;
 832     default:
 833         ret = 0x00000000;
 834         break;
 835     }
 836
 837     return ret;
 838 }
 839
 840 static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
 841 {
 842     Ppc4xxEbcState *ebc = opaque;
 843
 844     switch (dcrn) {
 845     case EBC0_CFGADDR:
 846         ebc->addr = val;
 847         break;
 848     case EBC0_CFGDATA:
 849         switch (ebc->addr) {
 850         case 0x00: /* B0CR */
 851             break;
 852         case 0x01: /* B1CR */
 853             break;
 854         case 0x02: /* B2CR */
 855             break;
 856         case 0x03: /* B3CR */
 857             break;
 858         case 0x04: /* B4CR */
 859             break;
 860         case 0x05: /* B5CR */
 861             break;
 862         case 0x06: /* B6CR */
 863             break;
 864         case 0x07: /* B7CR */
 865             break;
 866         case 0x10: /* B0AP */
 867             break;
 868         case 0x11: /* B1AP */
 869             break;
 870         case 0x12: /* B2AP */
 871             break;
 872         case 0x13: /* B3AP */
 873             break;
 874         case 0x14: /* B4AP */
 875             break;
 876         case 0x15: /* B5AP */
 877             break;
 878         case 0x16: /* B6AP */
 879             break;
 880         case 0x17: /* B7AP */
 881             break;
 882         case 0x20: /* BEAR */
 883             break;
 884         case 0x21: /* BESR0 */
 885             break;
 886         case 0x22: /* BESR1 */
 887             break;
 888         case 0x23: /* CFG */
 889             break;
 890         default:
 891             break;
 892         }
 893         break;
 894     default:
 895         break;
 896     }
 897 }
 898
 899 static void ppc405_ebc_reset(DeviceState *dev)
 900 {
 901     Ppc4xxEbcState *ebc = PPC4xx_EBC(dev);
 902     int i;
 903
 904     ebc->addr = 0x00000000;
 905     ebc->bap[0] = 0x7F8FFE80;
 906     ebc->bcr[0] = 0xFFE28000;
 907     for (i = 0; i < 8; i++) {
 908         ebc->bap[i] = 0x00000000;
 909         ebc->bcr[i] = 0x00000000;
 910     }
 911     ebc->besr0 = 0x00000000;
 912     ebc->besr1 = 0x00000000;
 913     ebc->cfg = 0x80400000;
 914 }
 915
 916 static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
 917 {
 918     Ppc4xxEbcState *ebc = PPC4xx_EBC(dev);
 919     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 920
 921     ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc);
 922     ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc);
 923 }
 924
 925 static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
 926 {
 927     DeviceClass *dc = DEVICE_CLASS(oc);
 928
 929     dc->realize = ppc405_ebc_realize;
 930     dc->reset = ppc405_ebc_reset;
 931     /* Reason: only works as function of a ppc4xx SoC */
 932     dc->user_creatable = false;
 933 }
 934
 935 /* PPC4xx_DCR_DEVICE */
 936
 937 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
 938                          dcr_read_cb dcr_read, dcr_write_cb dcr_write)
 939 {
 940     assert(dev->cpu);
 941     ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write);
 942 }
 943
 944 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
 945                         Error **errp)
 946 {
 947     object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
 948     return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
 949 }
 950
 951 static Property ppc4xx_dcr_properties[] = {
 952     DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
 953                      PowerPCCPU *),
 954     DEFINE_PROP_END_OF_LIST(),
 955 };
 956
 957 static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
 958 {
 959     DeviceClass *dc = DEVICE_CLASS(oc);
 960
 961     device_class_set_props(dc, ppc4xx_dcr_properties);
 962 }
 963
 964 static const TypeInfo ppc4xx_types[] = {
 965     {
 966         .name           = TYPE_PPC4xx_SDRAM_DDR,
 967         .parent         = TYPE_PPC4xx_DCR_DEVICE,
 968         .instance_size  = sizeof(Ppc4xxSdramDdrState),
 969         .class_init     = ppc4xx_sdram_ddr_class_init,
 970     }, {
 971         .name           = TYPE_PPC4xx_MAL,
 972         .parent         = TYPE_PPC4xx_DCR_DEVICE,
 973         .instance_size  = sizeof(Ppc4xxMalState),
 974         .instance_finalize = ppc4xx_mal_finalize,
 975         .class_init     = ppc4xx_mal_class_init,
 976     }, {
 977         .name           = TYPE_PPC4xx_PLB,
 978         .parent         = TYPE_PPC4xx_DCR_DEVICE,
 979         .instance_size  = sizeof(Ppc4xxPlbState),
 980         .class_init     = ppc405_plb_class_init,
 981     }, {
 982         .name           = TYPE_PPC4xx_EBC,
 983         .parent         = TYPE_PPC4xx_DCR_DEVICE,
 984         .instance_size  = sizeof(Ppc4xxEbcState),
 985         .class_init     = ppc405_ebc_class_init,
 986     }, {
 987         .name           = TYPE_PPC4xx_DCR_DEVICE,
 988         .parent         = TYPE_SYS_BUS_DEVICE,
 989         .instance_size  = sizeof(Ppc4xxDcrDeviceState),
 990         .class_init     = ppc4xx_dcr_class_init,
 991         .abstract       = true,
 992     }
 993 };
 994
 995 DEFINE_TYPES(ppc4xx_types)