hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  * Copyright (c) 2017 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "cpu.h"
  28 #include "hw/rtc/m48t59.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/block/fdc.h"
  31 #include "net/net.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/isa/isa.h"
  34 #include "hw/pci/pci.h"
  35 #include "hw/pci/pci_host.h"
  36 #include "hw/ppc/ppc.h"
  37 #include "hw/boards.h"
  38 #include "qemu/error-report.h"
  39 #include "qemu/log.h"
  40 #include "hw/irq.h"
  41 #include "hw/loader.h"
  42 #include "hw/rtc/mc146818rtc.h"
  43 #include "hw/isa/pc87312.h"
  44 #include "hw/qdev-properties.h"
  45 #include "sysemu/arch_init.h"
  46 #include "sysemu/kvm.h"
  47 #include "sysemu/qtest.h"
  48 #include "sysemu/reset.h"
  49 #include "exec/address-spaces.h"
  50 #include "trace.h"
  51 #include "elf.h"
  52 #include "qemu/units.h"
  53 #include "kvm_ppc.h"
  54
  55 /* SMP is not enabled, for now */
  56 #define MAX_CPUS 1
  57
  58 #define MAX_IDE_BUS 2
  59
  60 #define CFG_ADDR 0xf0000510
  61
  62 #define KERNEL_LOAD_ADDR 0x01000000
  63 #define INITRD_LOAD_ADDR 0x01800000
  64
  65 #define NVRAM_SIZE        0x2000
  66
  67 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  68                             Error **errp)
  69 {
  70     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  71 }
  72
  73 static void ppc_prep_reset(void *opaque)
  74 {
  75     PowerPCCPU *cpu = opaque;
  76
  77     cpu_reset(CPU(cpu));
  78 }
  79
  80
  81 /*****************************************************************************/
  82 /* NVRAM helpers */
  83 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
  84 {
  85     NvramClass *k = NVRAM_GET_CLASS(nvram);
  86     return (k->read)(nvram, addr);
  87 }
  88
  89 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
  90 {
  91     NvramClass *k = NVRAM_GET_CLASS(nvram);
  92     (k->write)(nvram, addr, val);
  93 }
  94
  95 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
  96 {
  97     nvram_write(nvram, addr, value);
  98 }
  99
 100 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
 101 {
 102     return nvram_read(nvram, addr);
 103 }
 104
 105 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
 106 {
 107     nvram_write(nvram, addr, value >> 8);
 108     nvram_write(nvram, addr + 1, value & 0xFF);
 109 }
 110
 111 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
 112 {
 113     uint16_t tmp;
 114
 115     tmp = nvram_read(nvram, addr) << 8;
 116     tmp |= nvram_read(nvram, addr + 1);
 117
 118     return tmp;
 119 }
 120
 121 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
 122 {
 123     nvram_write(nvram, addr, value >> 24);
 124     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
 125     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
 126     nvram_write(nvram, addr + 3, value & 0xFF);
 127 }
 128
 129 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
 130                              uint32_t max)
 131 {
 132     int i;
 133
 134     for (i = 0; i < max && str[i] != '\0'; i++) {
 135         nvram_write(nvram, addr + i, str[i]);
 136     }
 137     nvram_write(nvram, addr + i, str[i]);
 138     nvram_write(nvram, addr + max - 1, '\0');
 139 }
 140
 141 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 142 {
 143     uint16_t tmp;
 144     uint16_t pd, pd1, pd2;
 145
 146     tmp = prev >> 8;
 147     pd = prev ^ value;
 148     pd1 = pd & 0x000F;
 149     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 150     tmp ^= (pd1 << 3) | (pd1 << 8);
 151     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 152
 153     return tmp;
 154 }
 155
 156 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
 157 {
 158     uint32_t i;
 159     uint16_t crc = 0xFFFF;
 160     int odd;
 161
 162     odd = count & 1;
 163     count &= ~1;
 164     for (i = 0; i != count; i++) {
 165         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 166     }
 167     if (odd) {
 168         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 169     }
 170
 171     return crc;
 172 }
 173
 174 #define CMDLINE_ADDR 0x017ff000
 175
 176 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
 177                           const char *arch,
 178                           uint32_t RAM_size, int boot_device,
 179                           uint32_t kernel_image, uint32_t kernel_size,
 180                           const char *cmdline,
 181                           uint32_t initrd_image, uint32_t initrd_size,
 182                           uint32_t NVRAM_image,
 183                           int width, int height, int depth)
 184 {
 185     uint16_t crc;
 186
 187     /* Set parameters for Open Hack'Ware BIOS */
 188     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 189     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 190     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 191     NVRAM_set_string(nvram, 0x20, arch, 16);
 192     NVRAM_set_lword(nvram,  0x30, RAM_size);
 193     NVRAM_set_byte(nvram,   0x34, boot_device);
 194     NVRAM_set_lword(nvram,  0x38, kernel_image);
 195     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 196     if (cmdline) {
 197         /* XXX: put the cmdline in NVRAM too ? */
 198         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
 199                          cmdline);
 200         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 201         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 202     } else {
 203         NVRAM_set_lword(nvram,  0x40, 0);
 204         NVRAM_set_lword(nvram,  0x44, 0);
 205     }
 206     NVRAM_set_lword(nvram,  0x48, initrd_image);
 207     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 208     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 209
 210     NVRAM_set_word(nvram,   0x54, width);
 211     NVRAM_set_word(nvram,   0x56, height);
 212     NVRAM_set_word(nvram,   0x58, depth);
 213     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 214     NVRAM_set_word(nvram,   0xFC, crc);
 215
 216     return 0;
 217 }
 218
 219 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
 220 {
 221     uint16_t checksum = *(uint16_t *)opaque;
 222     ISADevice *rtc;
 223
 224     if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
 225         rtc = ISA_DEVICE(dev);
 226         rtc_set_memory(rtc, 0x2e, checksum & 0xff);
 227         rtc_set_memory(rtc, 0x3e, checksum & 0xff);
 228         rtc_set_memory(rtc, 0x2f, checksum >> 8);
 229         rtc_set_memory(rtc, 0x3f, checksum >> 8);
 230
 231         object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
 232                                   "date", NULL);
 233     }
 234     return 0;
 235 }
 236
 237 static void ibm_40p_init(MachineState *machine)
 238 {
 239     CPUPPCState *env = NULL;
 240     uint16_t cmos_checksum;
 241     PowerPCCPU *cpu;
 242     DeviceState *dev, *i82378_dev;
 243     SysBusDevice *pcihost, *s;
 244     Nvram *m48t59 = NULL;
 245     PCIBus *pci_bus;
 246     ISABus *isa_bus;
 247     void *fw_cfg;
 248     int i;
 249     uint32_t kernel_base = 0, initrd_base = 0;
 250     long kernel_size = 0, initrd_size = 0;
 251     char boot_device;
 252
 253     /* init CPU */
 254     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 255     env = &cpu->env;
 256     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 257         error_report("only 6xx bus is supported on this machine");
 258         exit(1);
 259     }
 260
 261     if (env->flags & POWERPC_FLAG_RTC_CLK) {
 262         /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 263         cpu_ppc_tb_init(env, 7812500UL);
 264     } else {
 265         /* Set time-base frequency to 100 Mhz */
 266         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 267     }
 268     qemu_register_reset(ppc_prep_reset, cpu);
 269
 270     /* PCI host */
 271     dev = qdev_create(NULL, "raven-pcihost");
 272     if (!bios_name) {
 273         bios_name = "openbios-ppc";
 274     }
 275     qdev_prop_set_string(dev, "bios-name", bios_name);
 276     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 277     pcihost = SYS_BUS_DEVICE(dev);
 278     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 279     qdev_init_nofail(dev);
 280     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
 281     if (!pci_bus) {
 282         error_report("could not create PCI host controller");
 283         exit(1);
 284     }
 285
 286     /* PCI -> ISA bridge */
 287     i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
 288     qdev_connect_gpio_out(i82378_dev, 0,
 289                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 290     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
 291     isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
 292
 293     /* Memory controller */
 294     dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
 295     qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
 296     qdev_init_nofail(dev);
 297
 298     /* RTC */
 299     dev = DEVICE(isa_create(isa_bus, TYPE_MC146818_RTC));
 300     qdev_prop_set_int32(dev, "base_year", 1900);
 301     qdev_init_nofail(dev);
 302
 303     /* initialize CMOS checksums */
 304     cmos_checksum = 0x6aa9;
 305     qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
 306                        &cmos_checksum);
 307
 308     /* add some more devices */
 309     if (defaults_enabled()) {
 310         m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
 311
 312         dev = DEVICE(isa_create(isa_bus, "cs4231a"));
 313         qdev_prop_set_uint32(dev, "iobase", 0x830);
 314         qdev_prop_set_uint32(dev, "irq", 10);
 315         qdev_init_nofail(dev);
 316
 317         dev = DEVICE(isa_create(isa_bus, "pc87312"));
 318         qdev_prop_set_uint32(dev, "config", 12);
 319         qdev_init_nofail(dev);
 320
 321         dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
 322         qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
 323         qdev_prop_set_uint32(dev, "equipment", 0xc0);
 324         qdev_init_nofail(dev);
 325
 326         dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
 327                                        "lsi53c810"));
 328         lsi53c8xx_handle_legacy_cmdline(dev);
 329         qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
 330
 331         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
 332         pci_vga_init(pci_bus);
 333
 334         for (i = 0; i < nb_nics; i++) {
 335             pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
 336                                 i == 0 ? "3" : NULL);
 337         }
 338     }
 339
 340     /* Prepare firmware configuration for OpenBIOS */
 341     dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
 342     fw_cfg = FW_CFG(dev);
 343     qdev_prop_set_uint32(dev, "data_width", 1);
 344     qdev_prop_set_bit(dev, "dma_enabled", false);
 345     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
 346                               OBJECT(fw_cfg), NULL);
 347     qdev_init_nofail(dev);
 348     s = SYS_BUS_DEVICE(dev);
 349     sysbus_mmio_map(s, 0, CFG_ADDR);
 350     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
 351
 352     if (machine->kernel_filename) {
 353         /* load kernel */
 354         kernel_base = KERNEL_LOAD_ADDR;
 355         kernel_size = load_image_targphys(machine->kernel_filename,
 356                                           kernel_base,
 357                                           machine->ram_size - kernel_base);
 358         if (kernel_size < 0) {
 359             error_report("could not load kernel '%s'",
 360                          machine->kernel_filename);
 361             exit(1);
 362         }
 363         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 364         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 365         /* load initrd */
 366         if (machine->initrd_filename) {
 367             initrd_base = INITRD_LOAD_ADDR;
 368             initrd_size = load_image_targphys(machine->initrd_filename,
 369                                               initrd_base,
 370                                               machine->ram_size - initrd_base);
 371             if (initrd_size < 0) {
 372                 error_report("could not load initial ram disk '%s'",
 373                              machine->initrd_filename);
 374                 exit(1);
 375             }
 376             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 377             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 378         }
 379         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 380             fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 381             pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
 382                              machine->kernel_cmdline);
 383             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
 384                               machine->kernel_cmdline);
 385             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 386                            strlen(machine->kernel_cmdline) + 1);
 387         }
 388         boot_device = 'm';
 389     } else {
 390         boot_device = machine->boot_order[0];
 391     }
 392
 393     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 394     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
 395     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
 396
 397     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 398     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 399     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 400
 401     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 402     if (kvm_enabled()) {
 403         uint8_t *hypercall;
 404
 405         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 406         hypercall = g_malloc(16);
 407         kvmppc_get_hypercall(env, hypercall, 16);
 408         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 409         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 410     } else {
 411         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
 412     }
 413     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
 414     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 415
 416     /* Prepare firmware configuration for Open Hack'Ware */
 417     if (m48t59) {
 418         PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
 419                              boot_device,
 420                              kernel_base, kernel_size,
 421                              machine->kernel_cmdline,
 422                              initrd_base, initrd_size,
 423                              /* XXX: need an option to load a NVRAM image */
 424                              0,
 425                              graphic_width, graphic_height, graphic_depth);
 426     }
 427 }
 428
 429 static void ibm_40p_machine_init(MachineClass *mc)
 430 {
 431     mc->desc = "IBM RS/6000 7020 (40p)",
 432     mc->init = ibm_40p_init;
 433     mc->max_cpus = 1;
 434     mc->default_ram_size = 128 * MiB;
 435     mc->block_default_type = IF_SCSI;
 436     mc->default_boot_order = "c";
 437     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
 438     mc->default_display = "std";
 439 }
 440
 441 DEFINE_MACHINE("40p", ibm_40p_machine_init)