hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  * Copyright (c) 2017 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "cpu.h"
  27 #include "hw/hw.h"
  28 #include "hw/timer/m48t59.h"
  29 #include "hw/i386/pc.h"
  30 #include "hw/char/serial.h"
  31 #include "hw/block/fdc.h"
  32 #include "net/net.h"
  33 #include "sysemu/sysemu.h"
  34 #include "hw/isa/isa.h"
  35 #include "hw/pci/pci.h"
  36 #include "hw/pci/pci_host.h"
  37 #include "hw/ppc/ppc.h"
  38 #include "hw/boards.h"
  39 #include "qemu/error-report.h"
  40 #include "qemu/log.h"
  41 #include "hw/ide.h"
  42 #include "hw/loader.h"
  43 #include "hw/timer/mc146818rtc.h"
  44 #include "hw/input/i8042.h"
  45 #include "hw/isa/pc87312.h"
  46 #include "hw/net/ne2000-isa.h"
  47 #include "sysemu/arch_init.h"
  48 #include "sysemu/kvm.h"
  49 #include "sysemu/qtest.h"
  50 #include "exec/address-spaces.h"
  51 #include "trace.h"
  52 #include "elf.h"
  53 #include "qemu/units.h"
  54 #include "kvm_ppc.h"
  55
  56 /* SMP is not enabled, for now */
  57 #define MAX_CPUS 1
  58
  59 #define MAX_IDE_BUS 2
  60
  61 #define CFG_ADDR 0xf0000510
  62
  63 #define BIOS_SIZE (1 * MiB)
  64 #define BIOS_FILENAME "ppc_rom.bin"
  65 #define KERNEL_LOAD_ADDR 0x01000000
  66 #define INITRD_LOAD_ADDR 0x01800000
  67
  68 /* Constants for devices init */
  69 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  70 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  71 static const int ide_irq[2] = { 13, 13 };
  72
  73 #define NE2000_NB_MAX 6
  74
  75 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  76 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  77
  78 /* ISA IO ports bridge */
  79 #define PPC_IO_BASE 0x80000000
  80
  81 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
  82 typedef struct sysctrl_t {
  83     qemu_irq reset_irq;
  84     Nvram *nvram;
  85     uint8_t state;
  86     uint8_t syscontrol;
  87     int contiguous_map;
  88     qemu_irq contiguous_map_irq;
  89     int endian;
  90 } sysctrl_t;
  91
  92 enum {
  93     STATE_HARDFILE = 0x01,
  94 };
  95
  96 static sysctrl_t *sysctrl;
  97
  98 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
  99 {
 100     sysctrl_t *sysctrl = opaque;
 101
 102     trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
 103     switch (addr) {
 104     case 0x0092:
 105         /* Special port 92 */
 106         /* Check soft reset asked */
 107         if (val & 0x01) {
 108             qemu_irq_raise(sysctrl->reset_irq);
 109         } else {
 110             qemu_irq_lower(sysctrl->reset_irq);
 111         }
 112         /* Check LE mode */
 113         if (val & 0x02) {
 114             sysctrl->endian = 1;
 115         } else {
 116             sysctrl->endian = 0;
 117         }
 118         break;
 119     case 0x0800:
 120         /* Motorola CPU configuration register : read-only */
 121         break;
 122     case 0x0802:
 123         /* Motorola base module feature register : read-only */
 124         break;
 125     case 0x0803:
 126         /* Motorola base module status register : read-only */
 127         break;
 128     case 0x0808:
 129         /* Hardfile light register */
 130         if (val & 1)
 131             sysctrl->state |= STATE_HARDFILE;
 132         else
 133             sysctrl->state &= ~STATE_HARDFILE;
 134         break;
 135     case 0x0810:
 136         /* Password protect 1 register */
 137         if (sysctrl->nvram != NULL) {
 138             NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 139             (k->toggle_lock)(sysctrl->nvram, 1);
 140         }
 141         break;
 142     case 0x0812:
 143         /* Password protect 2 register */
 144         if (sysctrl->nvram != NULL) {
 145             NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 146             (k->toggle_lock)(sysctrl->nvram, 2);
 147         }
 148         break;
 149     case 0x0814:
 150         /* L2 invalidate register */
 151         //        tlb_flush(first_cpu, 1);
 152         break;
 153     case 0x081C:
 154         /* system control register */
 155         sysctrl->syscontrol = val & 0x0F;
 156         break;
 157     case 0x0850:
 158         /* I/O map type register */
 159         sysctrl->contiguous_map = val & 0x01;
 160         qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
 161         break;
 162     default:
 163         printf("ERROR: unaffected IO port write: %04" PRIx32
 164                " => %02" PRIx32"\n", addr, val);
 165         break;
 166     }
 167 }
 168
 169 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 170 {
 171     sysctrl_t *sysctrl = opaque;
 172     uint32_t retval = 0xFF;
 173
 174     switch (addr) {
 175     case 0x0092:
 176         /* Special port 92 */
 177         retval = sysctrl->endian << 1;
 178         break;
 179     case 0x0800:
 180         /* Motorola CPU configuration register */
 181         retval = 0xEF; /* MPC750 */
 182         break;
 183     case 0x0802:
 184         /* Motorola Base module feature register */
 185         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 186         break;
 187     case 0x0803:
 188         /* Motorola base module status register */
 189         retval = 0xE0; /* Standard MPC750 */
 190         break;
 191     case 0x080C:
 192         /* Equipment present register:
 193          *  no L2 cache
 194          *  no upgrade processor
 195          *  no cards in PCI slots
 196          *  SCSI fuse is bad
 197          */
 198         retval = 0x3C;
 199         break;
 200     case 0x0810:
 201         /* Motorola base module extended feature register */
 202         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 203         break;
 204     case 0x0814:
 205         /* L2 invalidate: don't care */
 206         break;
 207     case 0x0818:
 208         /* Keylock */
 209         retval = 0x00;
 210         break;
 211     case 0x081C:
 212         /* system control register
 213          * 7 - 6 / 1 - 0: L2 cache enable
 214          */
 215         retval = sysctrl->syscontrol;
 216         break;
 217     case 0x0823:
 218         /* */
 219         retval = 0x03; /* no L2 cache */
 220         break;
 221     case 0x0850:
 222         /* I/O map type register */
 223         retval = sysctrl->contiguous_map;
 224         break;
 225     default:
 226         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 227         break;
 228     }
 229     trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
 230
 231     return retval;
 232 }
 233
 234
 235 #define NVRAM_SIZE        0x2000
 236
 237 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 238                             Error **errp)
 239 {
 240     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 241 }
 242
 243 static void ppc_prep_reset(void *opaque)
 244 {
 245     PowerPCCPU *cpu = opaque;
 246
 247     cpu_reset(CPU(cpu));
 248 }
 249
 250 static const MemoryRegionPortio prep_portio_list[] = {
 251     /* System control ports */
 252     { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 253     { 0x0800, 0x52, 1,
 254       .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 255     /* Special port to get debug messages from Open-Firmware */
 256     { 0x0F00, 4, 1, .write = PPC_debug_write, },
 257     PORTIO_END_OF_LIST(),
 258 };
 259
 260 static PortioList prep_port_list;
 261
 262 /*****************************************************************************/
 263 /* NVRAM helpers */
 264 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
 265 {
 266     NvramClass *k = NVRAM_GET_CLASS(nvram);
 267     return (k->read)(nvram, addr);
 268 }
 269
 270 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
 271 {
 272     NvramClass *k = NVRAM_GET_CLASS(nvram);
 273     (k->write)(nvram, addr, val);
 274 }
 275
 276 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
 277 {
 278     nvram_write(nvram, addr, value);
 279 }
 280
 281 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
 282 {
 283     return nvram_read(nvram, addr);
 284 }
 285
 286 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
 287 {
 288     nvram_write(nvram, addr, value >> 8);
 289     nvram_write(nvram, addr + 1, value & 0xFF);
 290 }
 291
 292 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
 293 {
 294     uint16_t tmp;
 295
 296     tmp = nvram_read(nvram, addr) << 8;
 297     tmp |= nvram_read(nvram, addr + 1);
 298
 299     return tmp;
 300 }
 301
 302 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
 303 {
 304     nvram_write(nvram, addr, value >> 24);
 305     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
 306     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
 307     nvram_write(nvram, addr + 3, value & 0xFF);
 308 }
 309
 310 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
 311                              uint32_t max)
 312 {
 313     int i;
 314
 315     for (i = 0; i < max && str[i] != '\0'; i++) {
 316         nvram_write(nvram, addr + i, str[i]);
 317     }
 318     nvram_write(nvram, addr + i, str[i]);
 319     nvram_write(nvram, addr + max - 1, '\0');
 320 }
 321
 322 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 323 {
 324     uint16_t tmp;
 325     uint16_t pd, pd1, pd2;
 326
 327     tmp = prev >> 8;
 328     pd = prev ^ value;
 329     pd1 = pd & 0x000F;
 330     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 331     tmp ^= (pd1 << 3) | (pd1 << 8);
 332     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 333
 334     return tmp;
 335 }
 336
 337 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
 338 {
 339     uint32_t i;
 340     uint16_t crc = 0xFFFF;
 341     int odd;
 342
 343     odd = count & 1;
 344     count &= ~1;
 345     for (i = 0; i != count; i++) {
 346         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 347     }
 348     if (odd) {
 349         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 350     }
 351
 352     return crc;
 353 }
 354
 355 #define CMDLINE_ADDR 0x017ff000
 356
 357 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
 358                           const char *arch,
 359                           uint32_t RAM_size, int boot_device,
 360                           uint32_t kernel_image, uint32_t kernel_size,
 361                           const char *cmdline,
 362                           uint32_t initrd_image, uint32_t initrd_size,
 363                           uint32_t NVRAM_image,
 364                           int width, int height, int depth)
 365 {
 366     uint16_t crc;
 367
 368     /* Set parameters for Open Hack'Ware BIOS */
 369     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 370     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 371     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 372     NVRAM_set_string(nvram, 0x20, arch, 16);
 373     NVRAM_set_lword(nvram,  0x30, RAM_size);
 374     NVRAM_set_byte(nvram,   0x34, boot_device);
 375     NVRAM_set_lword(nvram,  0x38, kernel_image);
 376     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 377     if (cmdline) {
 378         /* XXX: put the cmdline in NVRAM too ? */
 379         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
 380                          cmdline);
 381         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 382         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 383     } else {
 384         NVRAM_set_lword(nvram,  0x40, 0);
 385         NVRAM_set_lword(nvram,  0x44, 0);
 386     }
 387     NVRAM_set_lword(nvram,  0x48, initrd_image);
 388     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 389     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 390
 391     NVRAM_set_word(nvram,   0x54, width);
 392     NVRAM_set_word(nvram,   0x56, height);
 393     NVRAM_set_word(nvram,   0x58, depth);
 394     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 395     NVRAM_set_word(nvram,   0xFC, crc);
 396
 397     return 0;
 398 }
 399
 400 /* PowerPC PREP hardware initialisation */
 401 static void ppc_prep_init(MachineState *machine)
 402 {
 403     ram_addr_t ram_size = machine->ram_size;
 404     const char *kernel_filename = machine->kernel_filename;
 405     const char *kernel_cmdline = machine->kernel_cmdline;
 406     const char *initrd_filename = machine->initrd_filename;
 407     const char *boot_device = machine->boot_order;
 408     MemoryRegion *sysmem = get_system_memory();
 409     PowerPCCPU *cpu = NULL;
 410     CPUPPCState *env = NULL;
 411     Nvram *m48t59;
 412 #if 0
 413     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 414 #endif
 415     int linux_boot, i, nb_nics1;
 416     MemoryRegion *ram = g_new(MemoryRegion, 1);
 417     uint32_t kernel_base, initrd_base;
 418     long kernel_size, initrd_size;
 419     DeviceState *dev;
 420     PCIHostState *pcihost;
 421     PCIBus *pci_bus;
 422     PCIDevice *pci;
 423     ISABus *isa_bus;
 424     ISADevice *isa;
 425     int ppc_boot_device;
 426     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 427
 428     sysctrl = g_malloc0(sizeof(sysctrl_t));
 429
 430     linux_boot = (kernel_filename != NULL);
 431
 432     /* init CPUs */
 433     for (i = 0; i < smp_cpus; i++) {
 434         cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 435         env = &cpu->env;
 436
 437         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 438             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 439             cpu_ppc_tb_init(env, 7812500UL);
 440         } else {
 441             /* Set time-base frequency to 100 Mhz */
 442             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 443         }
 444         qemu_register_reset(ppc_prep_reset, cpu);
 445     }
 446
 447     /* allocate RAM */
 448     memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
 449     memory_region_add_subregion(sysmem, 0, ram);
 450
 451     if (linux_boot) {
 452         kernel_base = KERNEL_LOAD_ADDR;
 453         /* now we can load the kernel */
 454         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 455                                           ram_size - kernel_base);
 456         if (kernel_size < 0) {
 457             error_report("could not load kernel '%s'", kernel_filename);
 458             exit(1);
 459         }
 460         /* load initrd */
 461         if (initrd_filename) {
 462             initrd_base = INITRD_LOAD_ADDR;
 463             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 464                                               ram_size - initrd_base);
 465             if (initrd_size < 0) {
 466                 error_report("could not load initial ram disk '%s'",
 467                              initrd_filename);
 468                 exit(1);
 469             }
 470         } else {
 471             initrd_base = 0;
 472             initrd_size = 0;
 473         }
 474         ppc_boot_device = 'm';
 475     } else {
 476         kernel_base = 0;
 477         kernel_size = 0;
 478         initrd_base = 0;
 479         initrd_size = 0;
 480         ppc_boot_device = '\0';
 481         /* For now, OHW cannot boot from the network. */
 482         for (i = 0; boot_device[i] != '\0'; i++) {
 483             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 484                 ppc_boot_device = boot_device[i];
 485                 break;
 486             }
 487         }
 488         if (ppc_boot_device == '\0') {
 489             error_report("No valid boot device for Mac99 machine");
 490             exit(1);
 491         }
 492     }
 493
 494     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 495         error_report("Only 6xx bus is supported on PREP machine");
 496         exit(1);
 497     }
 498
 499     dev = qdev_create(NULL, "raven-pcihost");
 500     if (bios_name == NULL) {
 501         bios_name = BIOS_FILENAME;
 502     }
 503     qdev_prop_set_string(dev, "bios-name", bios_name);
 504     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 505     pcihost = PCI_HOST_BRIDGE(dev);
 506     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 507     qdev_init_nofail(dev);
 508     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 509     if (pci_bus == NULL) {
 510         error_report("Couldn't create PCI host controller");
 511         exit(1);
 512     }
 513     sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
 514
 515     /* PCI -> ISA bridge */
 516     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 517     cpu = POWERPC_CPU(first_cpu);
 518     qdev_connect_gpio_out(&pci->qdev, 0,
 519                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 520     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 521     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 522     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 523     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 524     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
 525
 526     /* Super I/O (parallel + serial ports) */
 527     isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO);
 528     dev = DEVICE(isa);
 529     qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
 530     qdev_init_nofail(dev);
 531
 532     /* init basic PC hardware */
 533     pci_vga_init(pci_bus);
 534
 535     nb_nics1 = nb_nics;
 536     if (nb_nics1 > NE2000_NB_MAX)
 537         nb_nics1 = NE2000_NB_MAX;
 538     for(i = 0; i < nb_nics1; i++) {
 539         if (nd_table[i].model == NULL) {
 540             nd_table[i].model = g_strdup("ne2k_isa");
 541         }
 542         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 543             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 544                             &nd_table[i]);
 545         } else {
 546             pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 547         }
 548     }
 549
 550     ide_drive_get(hd, ARRAY_SIZE(hd));
 551     for(i = 0; i < MAX_IDE_BUS; i++) {
 552         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 553                      hd[2 * i],
 554                      hd[2 * i + 1]);
 555     }
 556
 557     cpu = POWERPC_CPU(first_cpu);
 558     sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
 559
 560     portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
 561     portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
 562
 563     /*
 564      * PowerPC control and status register group: unimplemented,
 565      * would be at address 0xFEFF0000.
 566      */
 567
 568     if (machine_usb(machine)) {
 569         pci_create_simple(pci_bus, -1, "pci-ohci");
 570     }
 571
 572     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
 573     if (m48t59 == NULL)
 574         return;
 575     sysctrl->nvram = m48t59;
 576
 577     /* Initialise NVRAM */
 578     PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
 579                          ppc_boot_device,
 580                          kernel_base, kernel_size,
 581                          kernel_cmdline,
 582                          initrd_base, initrd_size,
 583                          /* XXX: need an option to load a NVRAM image */
 584                          0,
 585                          graphic_width, graphic_height, graphic_depth);
 586 }
 587
 588 static void prep_machine_init(MachineClass *mc)
 589 {
 590     mc->desc = "PowerPC PREP platform";
 591     mc->init = ppc_prep_init;
 592     mc->block_default_type = IF_IDE;
 593     mc->max_cpus = MAX_CPUS;
 594     mc->default_boot_order = "cad";
 595     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602");
 596     mc->default_display = "std";
 597 }
 598
 599 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
 600 {
 601     uint16_t checksum = *(uint16_t *)opaque;
 602     ISADevice *rtc;
 603
 604     if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) {
 605         rtc = ISA_DEVICE(dev);
 606         rtc_set_memory(rtc, 0x2e, checksum & 0xff);
 607         rtc_set_memory(rtc, 0x3e, checksum & 0xff);
 608         rtc_set_memory(rtc, 0x2f, checksum >> 8);
 609         rtc_set_memory(rtc, 0x3f, checksum >> 8);
 610     }
 611     return 0;
 612 }
 613
 614 static void ibm_40p_init(MachineState *machine)
 615 {
 616     CPUPPCState *env = NULL;
 617     uint16_t cmos_checksum;
 618     PowerPCCPU *cpu;
 619     DeviceState *dev;
 620     SysBusDevice *pcihost;
 621     Nvram *m48t59 = NULL;
 622     PCIBus *pci_bus;
 623     ISABus *isa_bus;
 624     void *fw_cfg;
 625     int i;
 626     uint32_t kernel_base = 0, initrd_base = 0;
 627     long kernel_size = 0, initrd_size = 0;
 628     char boot_device;
 629
 630     /* init CPU */
 631     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 632     env = &cpu->env;
 633     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 634         error_report("only 6xx bus is supported on this machine");
 635         exit(1);
 636     }
 637
 638     if (env->flags & POWERPC_FLAG_RTC_CLK) {
 639         /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 640         cpu_ppc_tb_init(env, 7812500UL);
 641     } else {
 642         /* Set time-base frequency to 100 Mhz */
 643         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 644     }
 645     qemu_register_reset(ppc_prep_reset, cpu);
 646
 647     /* PCI host */
 648     dev = qdev_create(NULL, "raven-pcihost");
 649     if (!bios_name) {
 650         bios_name = BIOS_FILENAME;
 651     }
 652     qdev_prop_set_string(dev, "bios-name", bios_name);
 653     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 654     pcihost = SYS_BUS_DEVICE(dev);
 655     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 656     qdev_init_nofail(dev);
 657     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
 658     if (!pci_bus) {
 659         error_report("could not create PCI host controller");
 660         exit(1);
 661     }
 662
 663     /* PCI -> ISA bridge */
 664     dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
 665     qdev_connect_gpio_out(dev, 0,
 666                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 667     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
 668     sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
 669     sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
 670     sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
 671     isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
 672
 673     /* Memory controller */
 674     dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
 675     qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
 676     qdev_init_nofail(dev);
 677
 678     /* initialize CMOS checksums */
 679     cmos_checksum = 0x6aa9;
 680     qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
 681                        &cmos_checksum);
 682
 683     /* add some more devices */
 684     if (defaults_enabled()) {
 685         m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
 686
 687         dev = DEVICE(isa_create(isa_bus, "cs4231a"));
 688         qdev_prop_set_uint32(dev, "iobase", 0x830);
 689         qdev_prop_set_uint32(dev, "irq", 10);
 690         qdev_init_nofail(dev);
 691
 692         dev = DEVICE(isa_create(isa_bus, "pc87312"));
 693         qdev_prop_set_uint32(dev, "config", 12);
 694         qdev_init_nofail(dev);
 695
 696         dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
 697         qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
 698         qdev_prop_set_uint32(dev, "equipment", 0xc0);
 699         qdev_init_nofail(dev);
 700
 701         lsi53c810_create(pci_bus, PCI_DEVFN(1, 0));
 702
 703         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
 704         pci_vga_init(pci_bus);
 705
 706         for (i = 0; i < nb_nics; i++) {
 707             pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
 708                                 i == 0 ? "3" : NULL);
 709         }
 710     }
 711
 712     /* Prepare firmware configuration for OpenBIOS */
 713     fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
 714
 715     if (machine->kernel_filename) {
 716         /* load kernel */
 717         kernel_base = KERNEL_LOAD_ADDR;
 718         kernel_size = load_image_targphys(machine->kernel_filename,
 719                                           kernel_base,
 720                                           machine->ram_size - kernel_base);
 721         if (kernel_size < 0) {
 722             error_report("could not load kernel '%s'",
 723                          machine->kernel_filename);
 724             exit(1);
 725         }
 726         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 727         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 728         /* load initrd */
 729         if (machine->initrd_filename) {
 730             initrd_base = INITRD_LOAD_ADDR;
 731             initrd_size = load_image_targphys(machine->initrd_filename,
 732                                               initrd_base,
 733                                               machine->ram_size - initrd_base);
 734             if (initrd_size < 0) {
 735                 error_report("could not load initial ram disk '%s'",
 736                              machine->initrd_filename);
 737                 exit(1);
 738             }
 739             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 740             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 741         }
 742         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 743             fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 744             pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
 745                              machine->kernel_cmdline);
 746             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
 747                               machine->kernel_cmdline);
 748             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 749                            strlen(machine->kernel_cmdline) + 1);
 750         }
 751         boot_device = 'm';
 752     } else {
 753         boot_device = machine->boot_order[0];
 754     }
 755
 756     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 757     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
 758     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
 759
 760     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 761     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 762     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 763
 764     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 765     if (kvm_enabled()) {
 766 #ifdef CONFIG_KVM
 767         uint8_t *hypercall;
 768
 769         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 770         hypercall = g_malloc(16);
 771         kvmppc_get_hypercall(env, hypercall, 16);
 772         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 773         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 774 #endif
 775     } else {
 776         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
 777     }
 778     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
 779     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 780
 781     /* Prepare firmware configuration for Open Hack'Ware */
 782     if (m48t59) {
 783         PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
 784                              boot_device,
 785                              kernel_base, kernel_size,
 786                              machine->kernel_cmdline,
 787                              initrd_base, initrd_size,
 788                              /* XXX: need an option to load a NVRAM image */
 789                              0,
 790                              graphic_width, graphic_height, graphic_depth);
 791     }
 792 }
 793
 794 static void ibm_40p_machine_init(MachineClass *mc)
 795 {
 796     mc->desc = "IBM RS/6000 7020 (40p)",
 797     mc->init = ibm_40p_init;
 798     mc->max_cpus = 1;
 799     mc->default_ram_size = 128 * MiB;
 800     mc->block_default_type = IF_SCSI;
 801     mc->default_boot_order = "c";
 802     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
 803     mc->default_display = "std";
 804 }
 805
 806 DEFINE_MACHINE("40p", ibm_40p_machine_init)
 807 DEFINE_MACHINE("prep", prep_machine_init)