2 * QEMU PReP System I/O emulation
4 * Copyright (c) 2017 Hervé Poussineau
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/isa/isa.h"
27 #include "exec/address-spaces.h"
28 #include "qemu/error-report.h" /* for error_report() */
29 #include "qemu/module.h"
30 #include "sysemu/sysemu.h" /* for vm_stop() */
34 #define TYPE_PREP_SYSTEMIO "prep-systemio"
35 #define PREP_SYSTEMIO(obj) \
36 OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO)
38 /* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
39 #define PREP_BIT(n) (1 << (7 - (n)))
41 typedef struct PrepSystemIoState
{
43 MemoryRegion ppc_parity_mem
;
45 qemu_irq non_contiguous_io_map_irq
;
46 uint8_t sreset
; /* 0x0092 */
47 uint8_t equipment
; /* 0x080c */
48 uint8_t system_control
; /* 0x081c */
49 uint8_t iomap_type
; /* 0x0850 */
50 uint8_t ibm_planar_id
; /* 0x0852 */
51 qemu_irq softreset_irq
;
55 /* PORT 0092 -- Special Port 92 (Read/Write) */
58 PORT0092_SOFTRESET
= PREP_BIT(7),
59 PORT0092_LE_MODE
= PREP_BIT(6),
62 static void prep_port0092_write(void *opaque
, uint32_t addr
, uint32_t val
)
64 PrepSystemIoState
*s
= opaque
;
66 trace_prep_systemio_write(addr
, val
);
68 s
->sreset
= val
& PORT0092_SOFTRESET
;
69 qemu_set_irq(s
->softreset_irq
, s
->sreset
);
71 if ((val
& PORT0092_LE_MODE
) != 0) {
72 /* XXX Not supported yet */
73 error_report("little-endian mode not supported");
74 vm_stop(RUN_STATE_PAUSED
);
80 static uint32_t prep_port0092_read(void *opaque
, uint32_t addr
)
82 PrepSystemIoState
*s
= opaque
;
83 trace_prep_systemio_read(addr
, s
->sreset
);
87 /* PORT 0808 -- Hardfile Light Register (Write Only) */
90 PORT0808_HARDFILE_LIGHT_ON
= PREP_BIT(7),
93 static void prep_port0808_write(void *opaque
, uint32_t addr
, uint32_t val
)
95 trace_prep_systemio_write(addr
, val
);
98 /* PORT 0810 -- Password Protect 1 Register (Write Only) */
100 /* reset by port 0x4D in the SIO */
101 static void prep_port0810_write(void *opaque
, uint32_t addr
, uint32_t val
)
103 trace_prep_systemio_write(addr
, val
);
106 /* PORT 0812 -- Password Protect 2 Register (Write Only) */
108 /* reset by port 0x4D in the SIO */
109 static void prep_port0812_write(void *opaque
, uint32_t addr
, uint32_t val
)
111 trace_prep_systemio_write(addr
, val
);
114 /* PORT 0814 -- L2 Invalidate Register (Write Only) */
116 static void prep_port0814_write(void *opaque
, uint32_t addr
, uint32_t val
)
118 trace_prep_systemio_write(addr
, val
);
121 /* PORT 0818 -- Reserved for Keylock (Read Only) */
124 PORT0818_KEYLOCK_SIGNAL_HIGH
= PREP_BIT(7),
127 static uint32_t prep_port0818_read(void *opaque
, uint32_t addr
)
130 trace_prep_systemio_read(addr
, val
);
134 /* PORT 080C -- Equipment */
137 PORT080C_SCSIFUSE
= PREP_BIT(1),
138 PORT080C_L2_COPYBACK
= PREP_BIT(4),
139 PORT080C_L2_256
= PREP_BIT(5),
140 PORT080C_UPGRADE_CPU
= PREP_BIT(6),
141 PORT080C_L2
= PREP_BIT(7),
144 static uint32_t prep_port080c_read(void *opaque
, uint32_t addr
)
146 PrepSystemIoState
*s
= opaque
;
147 trace_prep_systemio_read(addr
, s
->equipment
);
151 /* PORT 081C -- System Control Register (Read/Write) */
154 PORT081C_FLOPPY_MOTOR_INHIBIT
= PREP_BIT(3),
155 PORT081C_MASK_TEA
= PREP_BIT(2),
156 PORT081C_L2_UPDATE_INHIBIT
= PREP_BIT(1),
157 PORT081C_L2_CACHEMISS_INHIBIT
= PREP_BIT(0),
160 static void prep_port081c_write(void *opaque
, uint32_t addr
, uint32_t val
)
162 static const uint8_t mask
= PORT081C_FLOPPY_MOTOR_INHIBIT
|
164 PORT081C_L2_UPDATE_INHIBIT
|
165 PORT081C_L2_CACHEMISS_INHIBIT
;
166 PrepSystemIoState
*s
= opaque
;
167 trace_prep_systemio_write(addr
, val
);
168 s
->system_control
= val
& mask
;
171 static uint32_t prep_port081c_read(void *opaque
, uint32_t addr
)
173 PrepSystemIoState
*s
= opaque
;
174 trace_prep_systemio_read(addr
, s
->system_control
);
175 return s
->system_control
;
178 /* System Board Identification */
180 static uint32_t prep_port0852_read(void *opaque
, uint32_t addr
)
182 PrepSystemIoState
*s
= opaque
;
183 trace_prep_systemio_read(addr
, s
->ibm_planar_id
);
184 return s
->ibm_planar_id
;
187 /* PORT 0850 -- I/O Map Type Register (Read/Write) */
190 PORT0850_IOMAP_NONCONTIGUOUS
= PREP_BIT(7),
193 static uint32_t prep_port0850_read(void *opaque
, uint32_t addr
)
195 PrepSystemIoState
*s
= opaque
;
196 trace_prep_systemio_read(addr
, s
->iomap_type
);
197 return s
->iomap_type
;
200 static void prep_port0850_write(void *opaque
, uint32_t addr
, uint32_t val
)
202 PrepSystemIoState
*s
= opaque
;
204 trace_prep_systemio_write(addr
, val
);
205 qemu_set_irq(s
->non_contiguous_io_map_irq
,
206 val
& PORT0850_IOMAP_NONCONTIGUOUS
);
207 s
->iomap_type
= val
& PORT0850_IOMAP_NONCONTIGUOUS
;
210 static const MemoryRegionPortio ppc_io800_port_list
[] = {
211 { 0x092, 1, 1, .read
= prep_port0092_read
,
212 .write
= prep_port0092_write
, },
213 { 0x808, 1, 1, .write
= prep_port0808_write
, },
214 { 0x80c, 1, 1, .read
= prep_port080c_read
, },
215 { 0x810, 1, 1, .write
= prep_port0810_write
, },
216 { 0x812, 1, 1, .write
= prep_port0812_write
, },
217 { 0x814, 1, 1, .write
= prep_port0814_write
, },
218 { 0x818, 1, 1, .read
= prep_port0818_read
},
219 { 0x81c, 1, 1, .read
= prep_port081c_read
,
220 .write
= prep_port081c_write
, },
221 { 0x850, 1, 1, .read
= prep_port0850_read
,
222 .write
= prep_port0850_write
, },
223 { 0x852, 1, 1, .read
= prep_port0852_read
, },
227 static uint64_t ppc_parity_error_readl(void *opaque
, hwaddr addr
,
231 trace_prep_systemio_read((unsigned int)addr
, val
);
235 static const MemoryRegionOps ppc_parity_error_ops
= {
236 .read
= ppc_parity_error_readl
,
238 .min_access_size
= 4,
239 .max_access_size
= 4,
243 static void prep_systemio_realize(DeviceState
*dev
, Error
**errp
)
245 ISADevice
*isa
= ISA_DEVICE(dev
);
246 PrepSystemIoState
*s
= PREP_SYSTEMIO(dev
);
249 qdev_init_gpio_out(dev
, &s
->non_contiguous_io_map_irq
, 1);
250 s
->iomap_type
= PORT0850_IOMAP_NONCONTIGUOUS
;
251 qemu_set_irq(s
->non_contiguous_io_map_irq
,
252 s
->iomap_type
& PORT0850_IOMAP_NONCONTIGUOUS
);
253 cpu
= POWERPC_CPU(first_cpu
);
254 s
->softreset_irq
= cpu
->env
.irq_inputs
[PPC6xx_INPUT_HRESET
];
256 isa_register_portio_list(isa
, &s
->portio
, 0x0, ppc_io800_port_list
, s
,
259 memory_region_init_io(&s
->ppc_parity_mem
, OBJECT(dev
),
260 &ppc_parity_error_ops
, s
, "ppc-parity", 0x4);
261 memory_region_add_subregion(get_system_memory(), 0xbfffeff0,
265 static const VMStateDescription vmstate_prep_systemio
= {
266 .name
= "prep_systemio",
268 .minimum_version_id
= 1,
269 .fields
= (VMStateField
[]) {
270 VMSTATE_UINT8(sreset
, PrepSystemIoState
),
271 VMSTATE_UINT8(system_control
, PrepSystemIoState
),
272 VMSTATE_UINT8(iomap_type
, PrepSystemIoState
),
273 VMSTATE_END_OF_LIST()
277 static Property prep_systemio_properties
[] = {
278 DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState
, ibm_planar_id
, 0),
279 DEFINE_PROP_UINT8("equipment", PrepSystemIoState
, equipment
, 0),
280 DEFINE_PROP_END_OF_LIST()
283 static void prep_systemio_class_initfn(ObjectClass
*klass
, void *data
)
285 DeviceClass
*dc
= DEVICE_CLASS(klass
);
287 dc
->realize
= prep_systemio_realize
;
288 dc
->vmsd
= &vmstate_prep_systemio
;
289 dc
->props
= prep_systemio_properties
;
292 static TypeInfo prep_systemio800_info
= {
293 .name
= TYPE_PREP_SYSTEMIO
,
294 .parent
= TYPE_ISA_DEVICE
,
295 .instance_size
= sizeof(PrepSystemIoState
),
296 .class_init
= prep_systemio_class_initfn
,
299 static void prep_systemio_register_types(void)
301 type_register_static(&prep_systemio800_info
);
304 type_init(prep_systemio_register_types
)