hw/ppc/sam460ex.c

   1 /*
   2  * QEMU aCube Sam460ex board emulation
   3  *
   4  * Copyright (c) 2012 François Revol
   5  * Copyright (c) 2016-2019 BALATON Zoltan
   6  *
   7  * This file is derived from hw/ppc440_bamboo.c,
   8  * the copyright for that material belongs to the original owners.
   9  *
  10  * This work is licensed under the GNU GPL license version 2 or later.
  11  *
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/units.h"
  16 #include "qemu-common.h"
  17 #include "qemu/error-report.h"
  18 #include "qapi/error.h"
  19 #include "hw/hw.h"
  20 #include "hw/boards.h"
  21 #include "sysemu/kvm.h"
  22 #include "kvm_ppc.h"
  23 #include "sysemu/device_tree.h"
  24 #include "sysemu/block-backend.h"
  25 #include "hw/loader.h"
  26 #include "elf.h"
  27 #include "exec/address-spaces.h"
  28 #include "exec/memory.h"
  29 #include "ppc440.h"
  30 #include "ppc405.h"
  31 #include "hw/block/flash.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/qtest.h"
  34 #include "hw/sysbus.h"
  35 #include "hw/char/serial.h"
  36 #include "hw/i2c/ppc4xx_i2c.h"
  37 #include "hw/i2c/smbus.h"
  38 #include "hw/usb/hcd-ehci.h"
  39 #include "hw/ppc/fdt.h"
  40
  41 #include <libfdt.h>
  42
  43 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
  44 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
  45 /* to extract the official U-Boot bin from the updater: */
  46 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
  47      if=updater/updater-460 of=u-boot-sam460-20100605.bin */
  48
  49 /* from Sam460 U-Boot include/configs/Sam460ex.h */
  50 #define FLASH_BASE             0xfff00000
  51 #define FLASH_BASE_H           0x4
  52 #define FLASH_SIZE             (1 * MiB)
  53 #define UBOOT_LOAD_BASE        0xfff80000
  54 #define UBOOT_SIZE             0x00080000
  55 #define UBOOT_ENTRY            0xfffffffc
  56
  57 /* from U-Boot */
  58 #define EPAPR_MAGIC           (0x45504150)
  59 #define KERNEL_ADDR           0x1000000
  60 #define FDT_ADDR              0x1800000
  61 #define RAMDISK_ADDR          0x1900000
  62
  63 /* Sam460ex IRQ MAP:
  64    IRQ0  = ETH_INT
  65    IRQ1  = FPGA_INT
  66    IRQ2  = PCI_INT (PCIA, PCIB, PCIC, PCIB)
  67    IRQ3  = FPGA_INT2
  68    IRQ11 = RTC_INT
  69    IRQ12 = SM502_INT
  70 */
  71
  72 #define CPU_FREQ 1150000000
  73 #define PLB_FREQ 230000000
  74 #define OPB_FREQ 115000000
  75 #define EBC_FREQ 115000000
  76 #define UART_FREQ 11059200
  77 #define SDRAM_NR_BANKS 4
  78
  79 /* The SoC could also handle 4 GiB but firmware does not work with that. */
  80 /* Maybe it overflows a signed 32 bit number somewhere? */
  81 static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
  82     2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
  83     32 * MiB, 0
  84 };
  85
  86 struct boot_info {
  87     uint32_t dt_base;
  88     uint32_t dt_size;
  89     uint32_t entry;
  90 };
  91
  92 static int sam460ex_load_uboot(void)
  93 {
  94     DriveInfo *dinfo;
  95     BlockBackend *blk = NULL;
  96     hwaddr base = FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32);
  97     long bios_size = FLASH_SIZE;
  98     int fl_sectors;
  99
 100     dinfo = drive_get(IF_PFLASH, 0, 0);
 101     if (dinfo) {
 102         blk = blk_by_legacy_dinfo(dinfo);
 103         bios_size = blk_getlength(blk);
 104     }
 105     fl_sectors = (bios_size + 65535) >> 16;
 106
 107     if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size,
 108                                blk, 64 * KiB, fl_sectors,
 109                                1, 0x89, 0x18, 0x0000, 0x0, 1)) {
 110         error_report("Error registering flash memory");
 111         /* XXX: return an error instead? */
 112         exit(1);
 113     }
 114
 115     if (!blk) {
 116         /*error_report("No flash image given with the 'pflash' parameter,"
 117                 " using default u-boot image");*/
 118         base = UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32);
 119         rom_add_file_fixed(UBOOT_FILENAME, base, -1);
 120     }
 121
 122     return 0;
 123 }
 124
 125 static int sam460ex_load_device_tree(hwaddr addr,
 126                                      uint32_t ramsize,
 127                                      hwaddr initrd_base,
 128                                      hwaddr initrd_size,
 129                                      const char *kernel_cmdline)
 130 {
 131     uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
 132     char *filename;
 133     int fdt_size;
 134     void *fdt;
 135     uint32_t tb_freq = CPU_FREQ;
 136     uint32_t clock_freq = CPU_FREQ;
 137     int offset;
 138
 139     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
 140     if (!filename) {
 141         error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE);
 142         exit(1);
 143     }
 144     fdt = load_device_tree(filename, &fdt_size);
 145     if (!fdt) {
 146         error_report("Couldn't load dtb file `%s'", filename);
 147         g_free(filename);
 148         exit(1);
 149     }
 150     g_free(filename);
 151
 152     /* Manipulate device tree in memory. */
 153
 154     qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
 155                      sizeof(mem_reg_property));
 156
 157     /* default FDT doesn't have a /chosen node... */
 158     qemu_fdt_add_subnode(fdt, "/chosen");
 159
 160     qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base);
 161
 162     qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 163                           (initrd_base + initrd_size));
 164
 165     qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
 166
 167     /* Copy data from the host device tree into the guest. Since the guest can
 168      * directly access the timebase without host involvement, we must expose
 169      * the correct frequencies. */
 170     if (kvm_enabled()) {
 171         tb_freq = kvmppc_get_tbfreq();
 172         clock_freq = kvmppc_get_clockfreq();
 173     }
 174
 175     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
 176                               clock_freq);
 177     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
 178                               tb_freq);
 179
 180     /* Remove cpm node if it exists (it is not emulated) */
 181     offset = fdt_path_offset(fdt, "/cpm");
 182     if (offset >= 0) {
 183         _FDT(fdt_nop_node(fdt, offset));
 184     }
 185
 186     /* set serial port clocks */
 187     offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
 188     while (offset >= 0) {
 189         _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ));
 190         offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
 191     }
 192
 193     /* some more clocks */
 194     qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency",
 195                               PLB_FREQ);
 196     qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency",
 197                               OPB_FREQ);
 198     qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency",
 199                               EBC_FREQ);
 200
 201     rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 202     g_free(fdt);
 203
 204     return fdt_size;
 205 }
 206
 207 /* Create reset TLB entries for BookE, mapping only the flash memory.  */
 208 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
 209 {
 210     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 211
 212     /* on reset the flash is mapped by a shadow TLB,
 213      * but since we don't implement them we need to use
 214      * the same values U-Boot will use to avoid a fault.
 215      */
 216     tlb->attr = 0;
 217     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 218     tlb->size = 0x10000000; /* up to 0xffffffff  */
 219     tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
 220     tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
 221     tlb->PID = 0;
 222 }
 223
 224 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
 225 static void mmubooke_create_initial_mapping(CPUPPCState *env,
 226                                      target_ulong va,
 227                                      hwaddr pa)
 228 {
 229     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 230
 231     tlb->attr = 0;
 232     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 233     tlb->size = 1 << 31; /* up to 0x80000000  */
 234     tlb->EPN = va & TARGET_PAGE_MASK;
 235     tlb->RPN = pa & TARGET_PAGE_MASK;
 236     tlb->PID = 0;
 237 }
 238
 239 static void main_cpu_reset(void *opaque)
 240 {
 241     PowerPCCPU *cpu = opaque;
 242     CPUPPCState *env = &cpu->env;
 243     struct boot_info *bi = env->load_info;
 244
 245     cpu_reset(CPU(cpu));
 246
 247     /* either we have a kernel to boot or we jump to U-Boot */
 248     if (bi->entry != UBOOT_ENTRY) {
 249         env->gpr[1] = (16 * MiB) - 8;
 250         env->gpr[3] = FDT_ADDR;
 251         env->nip = bi->entry;
 252
 253         /* Create a mapping for the kernel.  */
 254         mmubooke_create_initial_mapping(env, 0, 0);
 255         env->gpr[6] = tswap32(EPAPR_MAGIC);
 256         env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */
 257
 258     } else {
 259         env->nip = UBOOT_ENTRY;
 260         mmubooke_create_initial_mapping_uboot(env);
 261     }
 262 }
 263
 264 static void sam460ex_init(MachineState *machine)
 265 {
 266     MemoryRegion *address_space_mem = get_system_memory();
 267     MemoryRegion *isa = g_new(MemoryRegion, 1);
 268     MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
 269     hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
 270     hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
 271     MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
 272     qemu_irq *irqs, *uic[4];
 273     PCIBus *pci_bus;
 274     PowerPCCPU *cpu;
 275     CPUPPCState *env;
 276     I2CBus *i2c;
 277     hwaddr entry = UBOOT_ENTRY;
 278     hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
 279     target_long initrd_size = 0;
 280     DeviceState *dev;
 281     SysBusDevice *sbdev;
 282     struct boot_info *boot_info;
 283     uint8_t *spd_data;
 284     Error *err = NULL;
 285     int success;
 286
 287     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 288     env = &cpu->env;
 289     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 290         error_report("Only MMU model BookE is supported by this machine.");
 291         exit(1);
 292     }
 293
 294     qemu_register_reset(main_cpu_reset, cpu);
 295     boot_info = g_malloc0(sizeof(*boot_info));
 296     env->load_info = boot_info;
 297
 298     ppc_booke_timers_init(cpu, CPU_FREQ, 0);
 299     ppc_dcr_init(env, NULL, NULL);
 300
 301     /* PLB arbitrer */
 302     ppc4xx_plb_init(env);
 303
 304     /* interrupt controllers */
 305     irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
 306     irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
 307     irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
 308     uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1);
 309     uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1);
 310     uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1);
 311     uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
 312
 313     /* SDRAM controller */
 314     /* put all RAM on first bank because board has one slot
 315      * and firmware only checks that */
 316     machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
 317                                    ram_memories, ram_bases, ram_sizes,
 318                                    ppc460ex_sdram_bank_sizes);
 319
 320     /* FIXME: does 460EX have ECC interrupts? */
 321     ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
 322                       ram_bases, ram_sizes, 1);
 323
 324     /* IIC controllers and devices */
 325     dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
 326     i2c = PPC4xx_I2C(dev)->bus;
 327     /* SPD EEPROM on RAM module */
 328     spd_data = spd_data_generate(DDR2, ram_sizes[0], &err);
 329     if (err) {
 330         warn_report_err(err);
 331     }
 332     if (spd_data) {
 333         spd_data[20] = 4; /* SO-DIMM module */
 334         smbus_eeprom_init_one(i2c, 0x50, spd_data);
 335     }
 336     /* RTC */
 337     i2c_create_slave(i2c, "m41t80", 0x68);
 338
 339     dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
 340
 341     /* External bus controller */
 342     ppc405_ebc_init(env);
 343
 344     /* CPR */
 345     ppc4xx_cpr_init(env);
 346
 347     /* PLB to AHB bridge */
 348     ppc4xx_ahb_init(env);
 349
 350     /* System DCRs */
 351     ppc4xx_sdr_init(env);
 352
 353     /* MAL */
 354     ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
 355
 356     /* DMA */
 357     ppc4xx_dma_init(env, 0x200);
 358
 359     /* 256K of L2 cache as memory */
 360     ppc4xx_l2sram_init(env);
 361     /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
 362     memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
 363                            &error_abort);
 364     memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
 365
 366     /* USB */
 367     sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
 368     dev = qdev_create(NULL, "sysbus-ohci");
 369     qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
 370     qdev_prop_set_uint32(dev, "num-ports", 6);
 371     qdev_init_nofail(dev);
 372     sbdev = SYS_BUS_DEVICE(dev);
 373     sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
 374     sysbus_connect_irq(sbdev, 0, uic[2][30]);
 375     usb_create_simple(usb_bus_find(-1), "usb-kbd");
 376     usb_create_simple(usb_bus_find(-1), "usb-mouse");
 377
 378     /* PCI bus */
 379     ppc460ex_pcie_init(env);
 380     /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
 381     dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0]);
 382     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 383     if (!pci_bus) {
 384         error_report("couldn't create PCI controller!");
 385         exit(1);
 386     }
 387     memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
 388                              0, 0x10000);
 389     memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
 390
 391     /* PCI devices */
 392     pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
 393     /* SoC has a single SATA port but we don't emulate that yet
 394      * However, firmware and usual clients have driver for SiI311x
 395      * so add one for convenience by default */
 396     if (defaults_enabled()) {
 397         pci_create_simple(pci_bus, -1, "sii3112");
 398     }
 399
 400     /* SoC has 4 UARTs
 401      * but board has only one wired and two are present in fdt */
 402     if (serial_hd(0) != NULL) {
 403         serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1],
 404                        PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
 405                        DEVICE_BIG_ENDIAN);
 406     }
 407     if (serial_hd(1) != NULL) {
 408         serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1],
 409                        PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
 410                        DEVICE_BIG_ENDIAN);
 411     }
 412
 413     /* Load U-Boot image. */
 414     if (!machine->kernel_filename) {
 415         success = sam460ex_load_uboot();
 416         if (success < 0) {
 417             error_report("could not load firmware");
 418             exit(1);
 419         }
 420     }
 421
 422     /* Load kernel. */
 423     if (machine->kernel_filename) {
 424         success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
 425                               NULL, NULL, NULL);
 426         if (success < 0) {
 427             uint64_t elf_entry, elf_lowaddr;
 428
 429             success = load_elf(machine->kernel_filename, NULL, NULL, &elf_entry,
 430                                &elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 431             entry = elf_entry;
 432             loadaddr = elf_lowaddr;
 433         }
 434         /* XXX try again as binary */
 435         if (success < 0) {
 436             error_report("could not load kernel '%s'",
 437                     machine->kernel_filename);
 438             exit(1);
 439         }
 440     }
 441
 442     /* Load initrd. */
 443     if (machine->initrd_filename) {
 444         initrd_size = load_image_targphys(machine->initrd_filename,
 445                                           RAMDISK_ADDR,
 446                                           machine->ram_size - RAMDISK_ADDR);
 447         if (initrd_size < 0) {
 448             error_report("could not load ram disk '%s' at %x",
 449                     machine->initrd_filename, RAMDISK_ADDR);
 450             exit(1);
 451         }
 452     }
 453
 454     /* If we're loading a kernel directly, we must load the device tree too. */
 455     if (machine->kernel_filename) {
 456         int dt_size;
 457
 458         dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
 459                                     RAMDISK_ADDR, initrd_size,
 460                                     machine->kernel_cmdline);
 461
 462         boot_info->dt_base = FDT_ADDR;
 463         boot_info->dt_size = dt_size;
 464     }
 465
 466     boot_info->entry = entry;
 467 }
 468
 469 static void sam460ex_machine_init(MachineClass *mc)
 470 {
 471     mc->desc = "aCube Sam460ex";
 472     mc->init = sam460ex_init;
 473     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
 474     mc->default_ram_size = 512 * MiB;
 475 }
 476
 477 DEFINE_MACHINE("sam460ex", sam460ex_machine_init)