2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
32 #include "sysemu/qtest.h"
35 #include "hw/fw-path-provider.h"
38 #include "sysemu/device_tree.h"
39 #include "sysemu/cpus.h"
40 #include "sysemu/hw_accel.h"
42 #include "migration/misc.h"
43 #include "migration/global_state.h"
44 #include "migration/register.h"
45 #include "mmu-hash64.h"
46 #include "mmu-book3s-v3.h"
47 #include "cpu-models.h"
50 #include "hw/boards.h"
51 #include "hw/ppc/ppc.h"
52 #include "hw/loader.h"
54 #include "hw/ppc/fdt.h"
55 #include "hw/ppc/spapr.h"
56 #include "hw/ppc/spapr_vio.h"
57 #include "hw/pci-host/spapr.h"
58 #include "hw/pci/msi.h"
60 #include "hw/pci/pci.h"
61 #include "hw/scsi/scsi.h"
62 #include "hw/virtio/virtio-scsi.h"
63 #include "hw/virtio/vhost-scsi-common.h"
65 #include "exec/address-spaces.h"
66 #include "exec/ram_addr.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
72 #include "hw/intc/intc.h"
74 #include "qemu/cutils.h"
75 #include "hw/ppc/spapr_cpu_core.h"
76 #include "hw/mem/memory-device.h"
80 /* SLOF memory layout:
82 * SLOF raw image loaded at 0, copies its romfs right below the flat
83 * device-tree, then position SLOF itself 31M below that
85 * So we set FW_OVERHEAD to 40MB which should account for all of that
88 * We load our kernel at 4M, leaving space for SLOF initial image
90 #define FDT_MAX_SIZE 0x100000
91 #define RTAS_MAX_SIZE 0x10000
92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
93 #define FW_MAX_SIZE 0x400000
94 #define FW_FILE_NAME "slof.bin"
95 #define FW_OVERHEAD 0x2800000
96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
98 #define MIN_RMA_SLOF 128UL
100 #define PHANDLE_INTC 0x00001111
102 /* These two functions implement the VCPU id numbering: one to compute them
103 * all and one to identify thread 0 of a VCORE. Any change to the first one
104 * is likely to have an impact on the second one, so let's keep them close.
106 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
110 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
112 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
116 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
119 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
121 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
122 * and newer QEMUs don't even have them. In both cases, we don't want
123 * to send anything on the wire.
128 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
129 .name
= "icp/server",
131 .minimum_version_id
= 1,
132 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
133 .fields
= (VMStateField
[]) {
134 VMSTATE_UNUSED(4), /* uint32_t xirr */
135 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
136 VMSTATE_UNUSED(1), /* uint8_t mfrr */
137 VMSTATE_END_OF_LIST()
141 static void pre_2_10_vmstate_register_dummy_icp(int i
)
143 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
144 (void *)(uintptr_t) i
);
147 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
149 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
150 (void *)(uintptr_t) i
);
153 int spapr_max_server_number(SpaprMachineState
*spapr
)
156 return DIV_ROUND_UP(max_cpus
* spapr
->vsmt
, smp_threads
);
159 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
163 uint32_t servers_prop
[smt_threads
];
164 uint32_t gservers_prop
[smt_threads
* 2];
165 int index
= spapr_get_vcpu_id(cpu
);
167 if (cpu
->compat_pvr
) {
168 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
174 /* Build interrupt servers and gservers properties */
175 for (i
= 0; i
< smt_threads
; i
++) {
176 servers_prop
[i
] = cpu_to_be32(index
+ i
);
177 /* Hack, direct the group queues back to cpu 0 */
178 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
179 gservers_prop
[i
*2 + 1] = 0;
181 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
182 servers_prop
, sizeof(servers_prop
));
186 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
187 gservers_prop
, sizeof(gservers_prop
));
192 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
194 int index
= spapr_get_vcpu_id(cpu
);
195 uint32_t associativity
[] = {cpu_to_be32(0x5),
199 cpu_to_be32(cpu
->node_id
),
202 /* Advertise NUMA via ibm,associativity */
203 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
204 sizeof(associativity
));
207 /* Populate the "ibm,pa-features" property */
208 static void spapr_populate_pa_features(SpaprMachineState
*spapr
,
210 void *fdt
, int offset
,
213 uint8_t pa_features_206
[] = { 6, 0,
214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
215 uint8_t pa_features_207
[] = { 24, 0,
216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
220 uint8_t pa_features_300
[] = { 66, 0,
221 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
222 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
228 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
230 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
232 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
234 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
236 /* 42: PM, 44: PC RA, 46: SC vec'd */
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
238 /* 48: SIMD, 50: QP BFP, 52: String */
239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
240 /* 54: DecFP, 56: DecI, 58: SHA */
241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
242 /* 60: NM atomic, 62: RNG */
243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
245 uint8_t *pa_features
= NULL
;
248 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
249 pa_features
= pa_features_206
;
250 pa_size
= sizeof(pa_features_206
);
252 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
253 pa_features
= pa_features_207
;
254 pa_size
= sizeof(pa_features_207
);
256 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
257 pa_features
= pa_features_300
;
258 pa_size
= sizeof(pa_features_300
);
264 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
266 * Note: we keep CI large pages off by default because a 64K capable
267 * guest provisioned with large pages might otherwise try to map a qemu
268 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
269 * even if that qemu runs on a 4k host.
270 * We dd this bit back here if we are confident this is not an issue
272 pa_features
[3] |= 0x20;
274 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
275 pa_features
[24] |= 0x80; /* Transactional memory support */
277 if (legacy_guest
&& pa_size
> 40) {
278 /* Workaround for broken kernels that attempt (guest) radix
279 * mode when they can't handle it, if they see the radix bit set
280 * in pa-features. So hide it from them. */
281 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
284 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
287 static int spapr_fixup_cpu_dt(void *fdt
, SpaprMachineState
*spapr
)
289 int ret
= 0, offset
, cpus_offset
;
292 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
295 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
296 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
297 int index
= spapr_get_vcpu_id(cpu
);
298 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
300 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
304 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
306 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
307 if (cpus_offset
< 0) {
308 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
309 if (cpus_offset
< 0) {
313 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
315 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
321 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
322 pft_size_prop
, sizeof(pft_size_prop
));
327 if (nb_numa_nodes
> 1) {
328 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
);
334 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
339 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
,
340 spapr
->cas_legacy_guest_workaround
);
345 static hwaddr
spapr_node0_size(MachineState
*machine
)
349 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
350 if (numa_info
[i
].node_mem
) {
351 return MIN(pow2floor(numa_info
[i
].node_mem
),
356 return machine
->ram_size
;
359 static void add_str(GString
*s
, const gchar
*s1
)
361 g_string_append_len(s
, s1
, strlen(s1
) + 1);
364 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
367 uint32_t associativity
[] = {
368 cpu_to_be32(0x4), /* length */
369 cpu_to_be32(0x0), cpu_to_be32(0x0),
370 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
373 uint64_t mem_reg_property
[2];
376 mem_reg_property
[0] = cpu_to_be64(start
);
377 mem_reg_property
[1] = cpu_to_be64(size
);
379 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
380 off
= fdt_add_subnode(fdt
, 0, mem_name
);
382 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
383 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
384 sizeof(mem_reg_property
))));
385 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
386 sizeof(associativity
))));
390 static int spapr_populate_memory(SpaprMachineState
*spapr
, void *fdt
)
392 MachineState
*machine
= MACHINE(spapr
);
393 hwaddr mem_start
, node_size
;
394 int i
, nb_nodes
= nb_numa_nodes
;
395 NodeInfo
*nodes
= numa_info
;
398 /* No NUMA nodes, assume there is just one node with whole RAM */
399 if (!nb_numa_nodes
) {
401 ramnode
.node_mem
= machine
->ram_size
;
405 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
406 if (!nodes
[i
].node_mem
) {
409 if (mem_start
>= machine
->ram_size
) {
412 node_size
= nodes
[i
].node_mem
;
413 if (node_size
> machine
->ram_size
- mem_start
) {
414 node_size
= machine
->ram_size
- mem_start
;
418 /* spapr_machine_init() checks for rma_size <= node0_size
420 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
421 mem_start
+= spapr
->rma_size
;
422 node_size
-= spapr
->rma_size
;
424 for ( ; node_size
; ) {
425 hwaddr sizetmp
= pow2floor(node_size
);
427 /* mem_start != 0 here */
428 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
429 sizetmp
= 1ULL << ctzl(mem_start
);
432 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
433 node_size
-= sizetmp
;
434 mem_start
+= sizetmp
;
441 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
442 SpaprMachineState
*spapr
)
444 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
445 CPUPPCState
*env
= &cpu
->env
;
446 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
447 int index
= spapr_get_vcpu_id(cpu
);
448 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
449 0xffffffff, 0xffffffff};
450 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
451 : SPAPR_TIMEBASE_FREQ
;
452 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
453 uint32_t page_sizes_prop
[64];
454 size_t page_sizes_prop_size
;
455 uint32_t vcpus_per_socket
= smp_threads
* smp_cores
;
456 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
457 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
460 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
463 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
465 drc_index
= spapr_drc_index(drc
);
466 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
469 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
470 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
472 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
473 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
474 env
->dcache_line_size
)));
475 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
476 env
->dcache_line_size
)));
477 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
478 env
->icache_line_size
)));
479 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
480 env
->icache_line_size
)));
482 if (pcc
->l1_dcache_size
) {
483 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
484 pcc
->l1_dcache_size
)));
486 warn_report("Unknown L1 dcache size for cpu");
488 if (pcc
->l1_icache_size
) {
489 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
490 pcc
->l1_icache_size
)));
492 warn_report("Unknown L1 icache size for cpu");
495 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
496 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
497 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
498 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
499 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
500 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
502 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
503 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
505 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
506 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
509 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
510 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
511 segs
, sizeof(segs
))));
514 /* Advertise VSX (vector extensions) if available
515 * 1 == VMX / Altivec available
518 * Only CPUs for which we create core types in spapr_cpu_core.c
519 * are possible, and all of those have VMX */
520 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
521 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
523 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
526 /* Advertise DFP (Decimal Floating Point) if available
527 * 0 / no property == no DFP
528 * 1 == DFP available */
529 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
530 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
533 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
534 sizeof(page_sizes_prop
));
535 if (page_sizes_prop_size
) {
536 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
537 page_sizes_prop
, page_sizes_prop_size
)));
540 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
, false);
542 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
543 cs
->cpu_index
/ vcpus_per_socket
)));
545 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
546 pft_size_prop
, sizeof(pft_size_prop
))));
548 if (nb_numa_nodes
> 1) {
549 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
552 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
554 if (pcc
->radix_page_info
) {
555 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
556 radix_AP_encodings
[i
] =
557 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
559 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
561 pcc
->radix_page_info
->count
*
562 sizeof(radix_AP_encodings
[0]))));
566 * We set this property to let the guest know that it can use the large
567 * decrementer and its width in bits.
569 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
570 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
571 pcc
->lrg_decr_bits
)));
574 static void spapr_populate_cpus_dt_node(void *fdt
, SpaprMachineState
*spapr
)
583 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
585 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
586 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
589 * We walk the CPUs in reverse order to ensure that CPU DT nodes
590 * created by fdt_add_subnode() end up in the right order in FDT
591 * for the guest kernel the enumerate the CPUs correctly.
593 * The CPU list cannot be traversed in reverse order, so we need
599 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
603 for (i
= n_cpus
- 1; i
>= 0; i
--) {
604 CPUState
*cs
= rev
[i
];
605 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
606 int index
= spapr_get_vcpu_id(cpu
);
607 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
610 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
614 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
615 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
618 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
624 static int spapr_rng_populate_dt(void *fdt
)
629 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
633 ret
= fdt_setprop_string(fdt
, node
, "device_type",
634 "ibm,platform-facilities");
635 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
636 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
638 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
642 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
647 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
649 MemoryDeviceInfoList
*info
;
651 for (info
= list
; info
; info
= info
->next
) {
652 MemoryDeviceInfo
*value
= info
->value
;
654 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
655 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
657 if (addr
>= pcdimm_info
->addr
&&
658 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
659 return pcdimm_info
->node
;
667 struct sPAPRDrconfCellV2
{
675 typedef struct DrconfCellQueue
{
676 struct sPAPRDrconfCellV2 cell
;
677 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
680 static DrconfCellQueue
*
681 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
682 uint32_t drc_index
, uint32_t aa_index
,
685 DrconfCellQueue
*elem
;
687 elem
= g_malloc0(sizeof(*elem
));
688 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
689 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
690 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
691 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
692 elem
->cell
.flags
= cpu_to_be32(flags
);
697 /* ibm,dynamic-memory-v2 */
698 static int spapr_populate_drmem_v2(SpaprMachineState
*spapr
, void *fdt
,
699 int offset
, MemoryDeviceInfoList
*dimms
)
701 MachineState
*machine
= MACHINE(spapr
);
702 uint8_t *int_buf
, *cur_index
;
704 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
705 uint64_t addr
, cur_addr
, size
;
706 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
707 uint64_t mem_end
= machine
->device_memory
->base
+
708 memory_region_size(&machine
->device_memory
->mr
);
709 uint32_t node
, buf_len
, nr_entries
= 0;
711 DrconfCellQueue
*elem
, *next
;
712 MemoryDeviceInfoList
*info
;
713 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
714 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
716 /* Entry to cover RAM and the gap area */
717 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
718 SPAPR_LMB_FLAGS_RESERVED
|
719 SPAPR_LMB_FLAGS_DRC_INVALID
);
720 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
723 cur_addr
= machine
->device_memory
->base
;
724 for (info
= dimms
; info
; info
= info
->next
) {
725 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
731 /* Entry for hot-pluggable area */
732 if (cur_addr
< addr
) {
733 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
735 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
736 cur_addr
, spapr_drc_index(drc
), -1, 0);
737 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
742 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
744 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
745 spapr_drc_index(drc
), node
,
746 SPAPR_LMB_FLAGS_ASSIGNED
);
747 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
749 cur_addr
= addr
+ size
;
752 /* Entry for remaining hotpluggable area */
753 if (cur_addr
< mem_end
) {
754 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
756 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
757 cur_addr
, spapr_drc_index(drc
), -1, 0);
758 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
762 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
763 int_buf
= cur_index
= g_malloc0(buf_len
);
764 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
765 cur_index
+= sizeof(nr_entries
);
767 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
768 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
769 cur_index
+= sizeof(elem
->cell
);
770 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
774 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
782 /* ibm,dynamic-memory */
783 static int spapr_populate_drmem_v1(SpaprMachineState
*spapr
, void *fdt
,
784 int offset
, MemoryDeviceInfoList
*dimms
)
786 MachineState
*machine
= MACHINE(spapr
);
788 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
789 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
790 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
791 memory_region_size(&machine
->device_memory
->mr
)) /
793 uint32_t *int_buf
, *cur_index
, buf_len
;
796 * Allocate enough buffer size to fit in ibm,dynamic-memory
798 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
799 cur_index
= int_buf
= g_malloc0(buf_len
);
800 int_buf
[0] = cpu_to_be32(nr_lmbs
);
802 for (i
= 0; i
< nr_lmbs
; i
++) {
803 uint64_t addr
= i
* lmb_size
;
804 uint32_t *dynamic_memory
= cur_index
;
806 if (i
>= device_lmb_start
) {
809 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
812 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
813 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
814 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
815 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
816 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
817 if (memory_region_present(get_system_memory(), addr
)) {
818 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
820 dynamic_memory
[5] = cpu_to_be32(0);
824 * LMB information for RMA, boot time RAM and gap b/n RAM and
825 * device memory region -- all these are marked as reserved
826 * and as having no valid DRC.
828 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
829 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
830 dynamic_memory
[2] = cpu_to_be32(0);
831 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
832 dynamic_memory
[4] = cpu_to_be32(-1);
833 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
834 SPAPR_LMB_FLAGS_DRC_INVALID
);
837 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
839 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
848 * Adds ibm,dynamic-reconfiguration-memory node.
849 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
850 * of this device tree node.
852 static int spapr_populate_drconf_memory(SpaprMachineState
*spapr
, void *fdt
)
854 MachineState
*machine
= MACHINE(spapr
);
856 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
857 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
858 uint32_t *int_buf
, *cur_index
, buf_len
;
859 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
860 MemoryDeviceInfoList
*dimms
= NULL
;
863 * Don't create the node if there is no device memory
865 if (machine
->ram_size
== machine
->maxram_size
) {
869 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
871 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
872 sizeof(prop_lmb_size
));
877 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
882 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
887 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
888 dimms
= qmp_memory_device_list();
889 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
890 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
892 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
894 qapi_free_MemoryDeviceInfoList(dimms
);
900 /* ibm,associativity-lookup-arrays */
901 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
902 cur_index
= int_buf
= g_malloc0(buf_len
);
903 int_buf
[0] = cpu_to_be32(nr_nodes
);
904 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
906 for (i
= 0; i
< nr_nodes
; i
++) {
907 uint32_t associativity
[] = {
913 memcpy(cur_index
, associativity
, sizeof(associativity
));
916 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
917 (cur_index
- int_buf
) * sizeof(uint32_t));
923 static int spapr_dt_cas_updates(SpaprMachineState
*spapr
, void *fdt
,
924 SpaprOptionVector
*ov5_updates
)
926 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
929 /* Generate ibm,dynamic-reconfiguration-memory node if required */
930 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
931 g_assert(smc
->dr_lmb_enabled
);
932 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
938 offset
= fdt_path_offset(fdt
, "/chosen");
940 offset
= fdt_add_subnode(fdt
, 0, "chosen");
945 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
946 "ibm,architecture-vec-5");
952 static bool spapr_hotplugged_dev_before_cas(void)
954 Object
*drc_container
, *obj
;
955 ObjectProperty
*prop
;
956 ObjectPropertyIterator iter
;
958 drc_container
= container_get(object_get_root(), "/dr-connector");
959 object_property_iter_init(&iter
, drc_container
);
960 while ((prop
= object_property_iter_next(&iter
))) {
961 if (!strstart(prop
->type
, "link<", NULL
)) {
964 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
965 if (spapr_drc_needed(obj
)) {
972 int spapr_h_cas_compose_response(SpaprMachineState
*spapr
,
973 target_ulong addr
, target_ulong size
,
974 SpaprOptionVector
*ov5_updates
)
976 void *fdt
, *fdt_skel
;
977 SpaprDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
979 if (spapr_hotplugged_dev_before_cas()) {
983 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
984 error_report("SLOF provided an unexpected CAS buffer size "
985 TARGET_FMT_lu
" (min: %zu, max: %u)",
986 size
, sizeof(hdr
), FW_MAX_SIZE
);
992 /* Create skeleton */
993 fdt_skel
= g_malloc0(size
);
994 _FDT((fdt_create(fdt_skel
, size
)));
995 _FDT((fdt_finish_reservemap(fdt_skel
)));
996 _FDT((fdt_begin_node(fdt_skel
, "")));
997 _FDT((fdt_end_node(fdt_skel
)));
998 _FDT((fdt_finish(fdt_skel
)));
999 fdt
= g_malloc0(size
);
1000 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
1003 /* Fixup cpu nodes */
1004 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
1006 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
1010 /* Pack resulting tree */
1011 _FDT((fdt_pack(fdt
)));
1013 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
1014 trace_spapr_cas_failed(size
);
1018 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
1019 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
1020 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
1026 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
1029 GString
*hypertas
= g_string_sized_new(256);
1030 GString
*qemu_hypertas
= g_string_sized_new(256);
1031 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1032 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
1033 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
1034 uint32_t lrdr_capacity
[] = {
1035 cpu_to_be32(max_device_addr
>> 32),
1036 cpu_to_be32(max_device_addr
& 0xffffffff),
1037 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
1038 cpu_to_be32(max_cpus
/ smp_threads
),
1040 uint32_t maxdomain
= cpu_to_be32(spapr
->gpu_numa_id
> 1 ? 1 : 0);
1041 uint32_t maxdomains
[] = {
1046 cpu_to_be32(spapr
->gpu_numa_id
),
1049 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
1052 add_str(hypertas
, "hcall-pft");
1053 add_str(hypertas
, "hcall-term");
1054 add_str(hypertas
, "hcall-dabr");
1055 add_str(hypertas
, "hcall-interrupt");
1056 add_str(hypertas
, "hcall-tce");
1057 add_str(hypertas
, "hcall-vio");
1058 add_str(hypertas
, "hcall-splpar");
1059 add_str(hypertas
, "hcall-bulk");
1060 add_str(hypertas
, "hcall-set-mode");
1061 add_str(hypertas
, "hcall-sprg0");
1062 add_str(hypertas
, "hcall-copy");
1063 add_str(hypertas
, "hcall-debug");
1064 add_str(hypertas
, "hcall-vphn");
1065 add_str(qemu_hypertas
, "hcall-memop1");
1067 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1068 add_str(hypertas
, "hcall-multi-tce");
1071 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1072 add_str(hypertas
, "hcall-hpt-resize");
1075 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1076 hypertas
->str
, hypertas
->len
));
1077 g_string_free(hypertas
, TRUE
);
1078 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1079 qemu_hypertas
->str
, qemu_hypertas
->len
));
1080 g_string_free(qemu_hypertas
, TRUE
);
1082 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1083 refpoints
, sizeof(refpoints
)));
1085 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1086 maxdomains
, sizeof(maxdomains
)));
1088 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1089 RTAS_ERROR_LOG_MAX
));
1090 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1091 RTAS_EVENT_SCAN_RATE
));
1093 g_assert(msi_nonbroken
);
1094 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1097 * According to PAPR, rtas ibm,os-term does not guarantee a return
1098 * back to the guest cpu.
1100 * While an additional ibm,extended-os-term property indicates
1101 * that rtas call return will always occur. Set this property.
1103 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1105 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1106 lrdr_capacity
, sizeof(lrdr_capacity
)));
1108 spapr_dt_rtas_tokens(fdt
, rtas
);
1112 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1113 * and the XIVE features that the guest may request and thus the valid
1114 * values for bytes 23..26 of option vector 5:
1116 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
1119 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1122 23, spapr
->irq
->ov5
, /* Xive mode. */
1123 24, 0x00, /* Hash/Radix, filled in below. */
1124 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1125 26, 0x40, /* Radix options: GTSE == yes. */
1128 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1129 first_ppc_cpu
->compat_pvr
)) {
1131 * If we're in a pre POWER9 compat mode then the guest should
1132 * do hash and use the legacy interrupt mode
1134 val
[1] = 0x00; /* XICS */
1135 val
[3] = 0x00; /* Hash */
1136 } else if (kvm_enabled()) {
1137 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1138 val
[3] = 0x80; /* OV5_MMU_BOTH */
1139 } else if (kvmppc_has_cap_mmu_radix()) {
1140 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1142 val
[3] = 0x00; /* Hash */
1145 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1148 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1152 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
)
1154 MachineState
*machine
= MACHINE(spapr
);
1156 const char *boot_device
= machine
->boot_order
;
1157 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1159 char *bootlist
= get_boot_devices_list(&cb
);
1161 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1163 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs", machine
->kernel_cmdline
));
1164 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1165 spapr
->initrd_base
));
1166 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1167 spapr
->initrd_base
+ spapr
->initrd_size
));
1169 if (spapr
->kernel_size
) {
1170 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1171 cpu_to_be64(spapr
->kernel_size
) };
1173 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1174 &kprop
, sizeof(kprop
)));
1175 if (spapr
->kernel_le
) {
1176 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1180 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1182 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1183 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1184 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1186 if (cb
&& bootlist
) {
1189 for (i
= 0; i
< cb
; i
++) {
1190 if (bootlist
[i
] == '\n') {
1194 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1197 if (boot_device
&& strlen(boot_device
)) {
1198 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1201 if (!spapr
->has_graphics
&& stdout_path
) {
1203 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1204 * kernel. New platforms should only use the "stdout-path" property. Set
1205 * the new property and continue using older property to remain
1206 * compatible with the existing firmware.
1208 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1209 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1212 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1214 g_free(stdout_path
);
1218 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1220 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1221 * KVM to work under pHyp with some guest co-operation */
1223 uint8_t hypercall
[16];
1225 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1226 /* indicate KVM hypercall interface */
1227 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1228 if (kvmppc_has_cap_fixup_hcalls()) {
1230 * Older KVM versions with older guest kernels were broken
1231 * with the magic page, don't allow the guest to map it.
1233 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1234 sizeof(hypercall
))) {
1235 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1236 hypercall
, sizeof(hypercall
)));
1241 static void *spapr_build_fdt(SpaprMachineState
*spapr
)
1243 MachineState
*machine
= MACHINE(spapr
);
1244 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1245 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1251 fdt
= g_malloc0(FDT_MAX_SIZE
);
1252 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1255 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1256 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1257 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1259 /* Guest UUID & Name*/
1260 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1261 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1262 if (qemu_uuid_set
) {
1263 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1267 if (qemu_get_vm_name()) {
1268 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1269 qemu_get_vm_name()));
1272 /* Host Model & Serial Number */
1273 if (spapr
->host_model
) {
1274 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1275 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1276 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1280 if (spapr
->host_serial
) {
1281 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1282 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1283 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1287 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1288 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1290 /* /interrupt controller */
1291 spapr
->irq
->dt_populate(spapr
, spapr_max_server_number(spapr
), fdt
,
1294 ret
= spapr_populate_memory(spapr
, fdt
);
1296 error_report("couldn't setup memory nodes in fdt");
1301 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1303 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1304 ret
= spapr_rng_populate_dt(fdt
);
1306 error_report("could not set up rng device in the fdt");
1311 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1312 ret
= spapr_dt_phb(phb
, PHANDLE_INTC
, fdt
, spapr
->irq
->nr_msis
, NULL
);
1314 error_report("couldn't setup PCI devices in fdt");
1320 spapr_populate_cpus_dt_node(fdt
, spapr
);
1322 if (smc
->dr_lmb_enabled
) {
1323 _FDT(spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1326 if (mc
->has_hotpluggable_cpus
) {
1327 int offset
= fdt_path_offset(fdt
, "/cpus");
1328 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1330 error_report("Couldn't set up CPU DR device tree properties");
1335 /* /event-sources */
1336 spapr_dt_events(spapr
, fdt
);
1339 spapr_dt_rtas(spapr
, fdt
);
1342 spapr_dt_chosen(spapr
, fdt
);
1345 if (kvm_enabled()) {
1346 spapr_dt_hypervisor(spapr
, fdt
);
1349 /* Build memory reserve map */
1350 if (spapr
->kernel_size
) {
1351 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1353 if (spapr
->initrd_size
) {
1354 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1357 /* ibm,client-architecture-support updates */
1358 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1360 error_report("couldn't setup CAS properties fdt");
1364 if (smc
->dr_phb_enabled
) {
1365 ret
= spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_PHB
);
1367 error_report("Couldn't set up PHB DR device tree properties");
1375 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1377 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1380 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1383 CPUPPCState
*env
= &cpu
->env
;
1385 /* The TCG path should also be holding the BQL at this point */
1386 g_assert(qemu_mutex_iothread_locked());
1389 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1390 env
->gpr
[3] = H_PRIVILEGE
;
1392 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1396 struct LPCRSyncState
{
1401 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1403 struct LPCRSyncState
*s
= arg
.host_ptr
;
1404 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1405 CPUPPCState
*env
= &cpu
->env
;
1408 cpu_synchronize_state(cs
);
1409 lpcr
= env
->spr
[SPR_LPCR
];
1412 ppc_store_lpcr(cpu
, lpcr
);
1415 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1418 struct LPCRSyncState s
= {
1423 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1427 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1429 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1431 /* Copy PATE1:GR into PATE0:HR */
1432 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1433 entry
->dw1
= spapr
->patb_entry
;
1436 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1437 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1438 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1439 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1440 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1443 * Get the fd to access the kernel htab, re-opening it if necessary
1445 static int get_htab_fd(SpaprMachineState
*spapr
)
1447 Error
*local_err
= NULL
;
1449 if (spapr
->htab_fd
>= 0) {
1450 return spapr
->htab_fd
;
1453 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1454 if (spapr
->htab_fd
< 0) {
1455 error_report_err(local_err
);
1458 return spapr
->htab_fd
;
1461 void close_htab_fd(SpaprMachineState
*spapr
)
1463 if (spapr
->htab_fd
>= 0) {
1464 close(spapr
->htab_fd
);
1466 spapr
->htab_fd
= -1;
1469 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1471 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1473 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1476 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1478 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1480 assert(kvm_enabled());
1486 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1489 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1492 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1493 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1497 * HTAB is controlled by KVM. Fetch into temporary buffer
1499 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1500 kvmppc_read_hptes(hptes
, ptex
, n
);
1505 * HTAB is controlled by QEMU. Just point to the internally
1508 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1511 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1512 const ppc_hash_pte64_t
*hptes
,
1515 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1518 g_free((void *)hptes
);
1521 /* Nothing to do for qemu managed HPT */
1524 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1525 uint64_t pte0
, uint64_t pte1
)
1527 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1528 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1531 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1533 if (pte0
& HPTE64_V_VALID
) {
1534 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1536 * When setting valid, we write PTE1 first. This ensures
1537 * proper synchronization with the reading code in
1538 * ppc_hash64_pteg_search()
1541 stq_p(spapr
->htab
+ offset
, pte0
);
1543 stq_p(spapr
->htab
+ offset
, pte0
);
1545 * When clearing it we set PTE0 first. This ensures proper
1546 * synchronization with the reading code in
1547 * ppc_hash64_pteg_search()
1550 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1555 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1558 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1559 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1562 /* There should always be a hash table when this is called */
1563 error_report("spapr_hpte_set_c called with no hash table !");
1567 /* The HW performs a non-atomic byte update */
1568 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1571 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1574 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1575 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1578 /* There should always be a hash table when this is called */
1579 error_report("spapr_hpte_set_r called with no hash table !");
1583 /* The HW performs a non-atomic byte update */
1584 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1587 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1591 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1592 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1593 * that's much more than is needed for Linux guests */
1594 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1595 shift
= MAX(shift
, 18); /* Minimum architected size */
1596 shift
= MIN(shift
, 46); /* Maximum architected size */
1600 void spapr_free_hpt(SpaprMachineState
*spapr
)
1602 g_free(spapr
->htab
);
1604 spapr
->htab_shift
= 0;
1605 close_htab_fd(spapr
);
1608 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
1613 /* Clean up any HPT info from a previous boot */
1614 spapr_free_hpt(spapr
);
1616 rc
= kvmppc_reset_htab(shift
);
1618 /* kernel-side HPT needed, but couldn't allocate one */
1619 error_setg_errno(errp
, errno
,
1620 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1622 /* This is almost certainly fatal, but if the caller really
1623 * wants to carry on with shift == 0, it's welcome to try */
1624 } else if (rc
> 0) {
1625 /* kernel-side HPT allocated */
1628 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1632 spapr
->htab_shift
= shift
;
1635 /* kernel-side HPT not needed, allocate in userspace instead */
1636 size_t size
= 1ULL << shift
;
1639 spapr
->htab
= qemu_memalign(size
, size
);
1641 error_setg_errno(errp
, errno
,
1642 "Could not allocate HPT of order %d", shift
);
1646 memset(spapr
->htab
, 0, size
);
1647 spapr
->htab_shift
= shift
;
1649 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1650 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1653 /* We're setting up a hash table, so that means we're not radix */
1654 spapr
->patb_entry
= 0;
1655 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1658 void spapr_setup_hpt_and_vrma(SpaprMachineState
*spapr
)
1662 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1663 || (spapr
->cas_reboot
1664 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1665 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1667 uint64_t current_ram_size
;
1669 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1670 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1672 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1674 if (spapr
->vrma_adjust
) {
1675 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1680 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1683 (SpaprDrc
*) object_dynamic_cast(child
,
1684 TYPE_SPAPR_DR_CONNECTOR
);
1687 spapr_drc_reset(drc
);
1693 static void spapr_machine_reset(void)
1695 MachineState
*machine
= MACHINE(qdev_get_machine());
1696 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1697 PowerPCCPU
*first_ppc_cpu
;
1698 uint32_t rtas_limit
;
1699 hwaddr rtas_addr
, fdt_addr
;
1703 spapr_caps_apply(spapr
);
1705 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1706 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1707 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1708 spapr
->max_compat_pvr
)) {
1710 * If using KVM with radix mode available, VCPUs can be started
1711 * without a HPT because KVM will start them in radix mode.
1712 * Set the GR bit in PATE so that we know there is no HPT.
1714 spapr
->patb_entry
= PATE1_GR
;
1715 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1717 spapr_setup_hpt_and_vrma(spapr
);
1721 * If this reset wasn't generated by CAS, we should reset our
1722 * negotiated options and start from scratch
1724 if (!spapr
->cas_reboot
) {
1725 spapr_ovec_cleanup(spapr
->ov5_cas
);
1726 spapr
->ov5_cas
= spapr_ovec_new();
1728 ppc_set_compat(first_ppc_cpu
, spapr
->max_compat_pvr
, &error_fatal
);
1731 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
1732 spapr_irq_msi_reset(spapr
);
1736 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
1737 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
1738 * called from vPHB reset handler so we initialize the counter here.
1739 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
1740 * must be equally distant from any other node.
1741 * The final value of spapr->gpu_numa_id is going to be written to
1742 * max-associativity-domains in spapr_build_fdt().
1744 spapr
->gpu_numa_id
= MAX(1, nb_numa_nodes
);
1745 qemu_devices_reset();
1748 * This is fixing some of the default configuration of the XIVE
1749 * devices. To be called after the reset of the machine devices.
1751 spapr_irq_reset(spapr
, &error_fatal
);
1754 * There is no CAS under qtest. Simulate one to please the code that
1755 * depends on spapr->ov5_cas. This is especially needed to test device
1756 * unplug, so we do that before resetting the DRCs.
1758 if (qtest_enabled()) {
1759 spapr_ovec_cleanup(spapr
->ov5_cas
);
1760 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1763 /* DRC reset may cause a device to be unplugged. This will cause troubles
1764 * if this device is used by another device (eg, a running vhost backend
1765 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1766 * situations, we reset DRCs after all devices have been reset.
1768 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1770 spapr_clear_pending_events(spapr
);
1773 * We place the device tree and RTAS just below either the top of the RMA,
1774 * or just below 2GB, whichever is lower, so that it can be
1775 * processed with 32-bit real mode code if necessary
1777 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1778 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1779 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1781 fdt
= spapr_build_fdt(spapr
);
1783 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1787 /* Should only fail if we've built a corrupted tree */
1790 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1791 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1792 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1797 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1798 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1799 g_free(spapr
->fdt_blob
);
1800 spapr
->fdt_size
= fdt_totalsize(fdt
);
1801 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1802 spapr
->fdt_blob
= fdt
;
1804 /* Set up the entry state */
1805 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1806 first_ppc_cpu
->env
.gpr
[5] = 0;
1808 spapr
->cas_reboot
= false;
1811 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1813 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1814 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1817 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1821 qdev_init_nofail(dev
);
1823 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1826 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1828 object_initialize_child(OBJECT(spapr
), "rtc",
1829 &spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1830 &error_fatal
, NULL
);
1831 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1833 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1834 "date", &error_fatal
);
1837 /* Returns whether we want to use VGA or not */
1838 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1840 switch (vga_interface_type
) {
1848 return pci_vga_init(pci_bus
) != NULL
;
1851 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1856 static int spapr_pre_load(void *opaque
)
1860 rc
= spapr_caps_pre_load(opaque
);
1868 static int spapr_post_load(void *opaque
, int version_id
)
1870 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1873 err
= spapr_caps_post_migration(spapr
);
1879 * In earlier versions, there was no separate qdev for the PAPR
1880 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1881 * So when migrating from those versions, poke the incoming offset
1882 * value into the RTC device
1884 if (version_id
< 3) {
1885 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1891 if (kvm_enabled() && spapr
->patb_entry
) {
1892 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1893 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1894 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1897 * Update LPCR:HR and UPRT as they may not be set properly in
1900 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1901 LPCR_HR
| LPCR_UPRT
);
1903 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1905 error_report("Process table config unsupported by the host");
1910 err
= spapr_irq_post_load(spapr
, version_id
);
1918 static int spapr_pre_save(void *opaque
)
1922 rc
= spapr_caps_pre_save(opaque
);
1930 static bool version_before_3(void *opaque
, int version_id
)
1932 return version_id
< 3;
1935 static bool spapr_pending_events_needed(void *opaque
)
1937 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1938 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1941 static const VMStateDescription vmstate_spapr_event_entry
= {
1942 .name
= "spapr_event_log_entry",
1944 .minimum_version_id
= 1,
1945 .fields
= (VMStateField
[]) {
1946 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1947 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1948 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1949 NULL
, extended_length
),
1950 VMSTATE_END_OF_LIST()
1954 static const VMStateDescription vmstate_spapr_pending_events
= {
1955 .name
= "spapr_pending_events",
1957 .minimum_version_id
= 1,
1958 .needed
= spapr_pending_events_needed
,
1959 .fields
= (VMStateField
[]) {
1960 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1961 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1962 VMSTATE_END_OF_LIST()
1966 static bool spapr_ov5_cas_needed(void *opaque
)
1968 SpaprMachineState
*spapr
= opaque
;
1969 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1970 SpaprOptionVector
*ov5_legacy
= spapr_ovec_new();
1971 SpaprOptionVector
*ov5_removed
= spapr_ovec_new();
1974 /* Prior to the introduction of SpaprOptionVector, we had two option
1975 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1976 * Both of these options encode machine topology into the device-tree
1977 * in such a way that the now-booted OS should still be able to interact
1978 * appropriately with QEMU regardless of what options were actually
1979 * negotiatied on the source side.
1981 * As such, we can avoid migrating the CAS-negotiated options if these
1982 * are the only options available on the current machine/platform.
1983 * Since these are the only options available for pseries-2.7 and
1984 * earlier, this allows us to maintain old->new/new->old migration
1987 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1988 * via default pseries-2.8 machines and explicit command-line parameters.
1989 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1990 * of the actual CAS-negotiated values to continue working properly. For
1991 * example, availability of memory unplug depends on knowing whether
1992 * OV5_HP_EVT was negotiated via CAS.
1994 * Thus, for any cases where the set of available CAS-negotiatable
1995 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1996 * include the CAS-negotiated options in the migration stream, unless
1997 * if they affect boot time behaviour only.
1999 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
2000 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
2001 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
2003 /* spapr_ovec_diff returns true if bits were removed. we avoid using
2004 * the mask itself since in the future it's possible "legacy" bits may be
2005 * removed via machine options, which could generate a false positive
2006 * that breaks migration.
2008 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
2009 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
2011 spapr_ovec_cleanup(ov5_mask
);
2012 spapr_ovec_cleanup(ov5_legacy
);
2013 spapr_ovec_cleanup(ov5_removed
);
2018 static const VMStateDescription vmstate_spapr_ov5_cas
= {
2019 .name
= "spapr_option_vector_ov5_cas",
2021 .minimum_version_id
= 1,
2022 .needed
= spapr_ov5_cas_needed
,
2023 .fields
= (VMStateField
[]) {
2024 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
2025 vmstate_spapr_ovec
, SpaprOptionVector
),
2026 VMSTATE_END_OF_LIST()
2030 static bool spapr_patb_entry_needed(void *opaque
)
2032 SpaprMachineState
*spapr
= opaque
;
2034 return !!spapr
->patb_entry
;
2037 static const VMStateDescription vmstate_spapr_patb_entry
= {
2038 .name
= "spapr_patb_entry",
2040 .minimum_version_id
= 1,
2041 .needed
= spapr_patb_entry_needed
,
2042 .fields
= (VMStateField
[]) {
2043 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
2044 VMSTATE_END_OF_LIST()
2048 static bool spapr_irq_map_needed(void *opaque
)
2050 SpaprMachineState
*spapr
= opaque
;
2052 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
2055 static const VMStateDescription vmstate_spapr_irq_map
= {
2056 .name
= "spapr_irq_map",
2058 .minimum_version_id
= 1,
2059 .needed
= spapr_irq_map_needed
,
2060 .fields
= (VMStateField
[]) {
2061 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
2062 VMSTATE_END_OF_LIST()
2066 static bool spapr_dtb_needed(void *opaque
)
2068 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
2070 return smc
->update_dt_enabled
;
2073 static int spapr_dtb_pre_load(void *opaque
)
2075 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2077 g_free(spapr
->fdt_blob
);
2078 spapr
->fdt_blob
= NULL
;
2079 spapr
->fdt_size
= 0;
2084 static const VMStateDescription vmstate_spapr_dtb
= {
2085 .name
= "spapr_dtb",
2087 .minimum_version_id
= 1,
2088 .needed
= spapr_dtb_needed
,
2089 .pre_load
= spapr_dtb_pre_load
,
2090 .fields
= (VMStateField
[]) {
2091 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
2092 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
2093 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
2095 VMSTATE_END_OF_LIST()
2099 static const VMStateDescription vmstate_spapr
= {
2102 .minimum_version_id
= 1,
2103 .pre_load
= spapr_pre_load
,
2104 .post_load
= spapr_post_load
,
2105 .pre_save
= spapr_pre_save
,
2106 .fields
= (VMStateField
[]) {
2107 /* used to be @next_irq */
2108 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2111 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2113 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2114 VMSTATE_END_OF_LIST()
2116 .subsections
= (const VMStateDescription
*[]) {
2117 &vmstate_spapr_ov5_cas
,
2118 &vmstate_spapr_patb_entry
,
2119 &vmstate_spapr_pending_events
,
2120 &vmstate_spapr_cap_htm
,
2121 &vmstate_spapr_cap_vsx
,
2122 &vmstate_spapr_cap_dfp
,
2123 &vmstate_spapr_cap_cfpc
,
2124 &vmstate_spapr_cap_sbbc
,
2125 &vmstate_spapr_cap_ibs
,
2126 &vmstate_spapr_cap_hpt_maxpagesize
,
2127 &vmstate_spapr_irq_map
,
2128 &vmstate_spapr_cap_nested_kvm_hv
,
2130 &vmstate_spapr_cap_large_decr
,
2131 &vmstate_spapr_cap_ccf_assist
,
2136 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2138 SpaprMachineState
*spapr
= opaque
;
2140 /* "Iteration" header */
2141 if (!spapr
->htab_shift
) {
2142 qemu_put_be32(f
, -1);
2144 qemu_put_be32(f
, spapr
->htab_shift
);
2148 spapr
->htab_save_index
= 0;
2149 spapr
->htab_first_pass
= true;
2151 if (spapr
->htab_shift
) {
2152 assert(kvm_enabled());
2160 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2161 int chunkstart
, int n_valid
, int n_invalid
)
2163 qemu_put_be32(f
, chunkstart
);
2164 qemu_put_be16(f
, n_valid
);
2165 qemu_put_be16(f
, n_invalid
);
2166 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2167 HASH_PTE_SIZE_64
* n_valid
);
2170 static void htab_save_end_marker(QEMUFile
*f
)
2172 qemu_put_be32(f
, 0);
2173 qemu_put_be16(f
, 0);
2174 qemu_put_be16(f
, 0);
2177 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2180 bool has_timeout
= max_ns
!= -1;
2181 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2182 int index
= spapr
->htab_save_index
;
2183 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2185 assert(spapr
->htab_first_pass
);
2190 /* Consume invalid HPTEs */
2191 while ((index
< htabslots
)
2192 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2193 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2197 /* Consume valid HPTEs */
2199 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2200 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2201 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2205 if (index
> chunkstart
) {
2206 int n_valid
= index
- chunkstart
;
2208 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2211 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2215 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2217 if (index
>= htabslots
) {
2218 assert(index
== htabslots
);
2220 spapr
->htab_first_pass
= false;
2222 spapr
->htab_save_index
= index
;
2225 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2228 bool final
= max_ns
< 0;
2229 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2230 int examined
= 0, sent
= 0;
2231 int index
= spapr
->htab_save_index
;
2232 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2234 assert(!spapr
->htab_first_pass
);
2237 int chunkstart
, invalidstart
;
2239 /* Consume non-dirty HPTEs */
2240 while ((index
< htabslots
)
2241 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2247 /* Consume valid dirty HPTEs */
2248 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2249 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2250 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2251 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2256 invalidstart
= index
;
2257 /* Consume invalid dirty HPTEs */
2258 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2259 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2260 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2261 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2266 if (index
> chunkstart
) {
2267 int n_valid
= invalidstart
- chunkstart
;
2268 int n_invalid
= index
- invalidstart
;
2270 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2271 sent
+= index
- chunkstart
;
2273 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2278 if (examined
>= htabslots
) {
2282 if (index
>= htabslots
) {
2283 assert(index
== htabslots
);
2286 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2288 if (index
>= htabslots
) {
2289 assert(index
== htabslots
);
2293 spapr
->htab_save_index
= index
;
2295 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2298 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2299 #define MAX_KVM_BUF_SIZE 2048
2301 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2303 SpaprMachineState
*spapr
= opaque
;
2307 /* Iteration header */
2308 if (!spapr
->htab_shift
) {
2309 qemu_put_be32(f
, -1);
2312 qemu_put_be32(f
, 0);
2316 assert(kvm_enabled());
2318 fd
= get_htab_fd(spapr
);
2323 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2327 } else if (spapr
->htab_first_pass
) {
2328 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2330 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2333 htab_save_end_marker(f
);
2338 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2340 SpaprMachineState
*spapr
= opaque
;
2343 /* Iteration header */
2344 if (!spapr
->htab_shift
) {
2345 qemu_put_be32(f
, -1);
2348 qemu_put_be32(f
, 0);
2354 assert(kvm_enabled());
2356 fd
= get_htab_fd(spapr
);
2361 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2366 if (spapr
->htab_first_pass
) {
2367 htab_save_first_pass(f
, spapr
, -1);
2369 htab_save_later_pass(f
, spapr
, -1);
2373 htab_save_end_marker(f
);
2378 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2380 SpaprMachineState
*spapr
= opaque
;
2381 uint32_t section_hdr
;
2383 Error
*local_err
= NULL
;
2385 if (version_id
< 1 || version_id
> 1) {
2386 error_report("htab_load() bad version");
2390 section_hdr
= qemu_get_be32(f
);
2392 if (section_hdr
== -1) {
2393 spapr_free_hpt(spapr
);
2398 /* First section gives the htab size */
2399 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2401 error_report_err(local_err
);
2408 assert(kvm_enabled());
2410 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2412 error_report_err(local_err
);
2419 uint16_t n_valid
, n_invalid
;
2421 index
= qemu_get_be32(f
);
2422 n_valid
= qemu_get_be16(f
);
2423 n_invalid
= qemu_get_be16(f
);
2425 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2430 if ((index
+ n_valid
+ n_invalid
) >
2431 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2432 /* Bad index in stream */
2434 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2435 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2441 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2442 HASH_PTE_SIZE_64
* n_valid
);
2445 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2446 HASH_PTE_SIZE_64
* n_invalid
);
2453 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2468 static void htab_save_cleanup(void *opaque
)
2470 SpaprMachineState
*spapr
= opaque
;
2472 close_htab_fd(spapr
);
2475 static SaveVMHandlers savevm_htab_handlers
= {
2476 .save_setup
= htab_save_setup
,
2477 .save_live_iterate
= htab_save_iterate
,
2478 .save_live_complete_precopy
= htab_save_complete
,
2479 .save_cleanup
= htab_save_cleanup
,
2480 .load_state
= htab_load
,
2483 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2486 MachineState
*machine
= MACHINE(opaque
);
2487 machine
->boot_order
= g_strdup(boot_device
);
2490 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2492 MachineState
*machine
= MACHINE(spapr
);
2493 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2494 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2497 for (i
= 0; i
< nr_lmbs
; i
++) {
2500 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2501 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2507 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2508 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2509 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2511 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2515 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2516 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2517 " is not aligned to %" PRIu64
" MiB",
2519 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2523 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2524 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2525 " is not aligned to %" PRIu64
" MiB",
2527 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2531 for (i
= 0; i
< nb_numa_nodes
; i
++) {
2532 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2534 "Node %d memory size 0x%" PRIx64
2535 " is not aligned to %" PRIu64
" MiB",
2536 i
, numa_info
[i
].node_mem
,
2537 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2543 /* find cpu slot in machine->possible_cpus by core_id */
2544 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2546 int index
= id
/ smp_threads
;
2548 if (index
>= ms
->possible_cpus
->len
) {
2554 return &ms
->possible_cpus
->cpus
[index
];
2557 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2559 Error
*local_err
= NULL
;
2560 bool vsmt_user
= !!spapr
->vsmt
;
2561 int kvm_smt
= kvmppc_smt_threads();
2564 if (!kvm_enabled() && (smp_threads
> 1)) {
2565 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2566 "on a pseries machine");
2569 if (!is_power_of_2(smp_threads
)) {
2570 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2571 "machine because it must be a power of 2", smp_threads
);
2575 /* Detemine the VSMT mode to use: */
2577 if (spapr
->vsmt
< smp_threads
) {
2578 error_setg(&local_err
, "Cannot support VSMT mode %d"
2579 " because it must be >= threads/core (%d)",
2580 spapr
->vsmt
, smp_threads
);
2583 /* In this case, spapr->vsmt has been set by the command line */
2586 * Default VSMT value is tricky, because we need it to be as
2587 * consistent as possible (for migration), but this requires
2588 * changing it for at least some existing cases. We pick 8 as
2589 * the value that we'd get with KVM on POWER8, the
2590 * overwhelmingly common case in production systems.
2592 spapr
->vsmt
= MAX(8, smp_threads
);
2595 /* KVM: If necessary, set the SMT mode: */
2596 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2597 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2599 /* Looks like KVM isn't able to change VSMT mode */
2600 error_setg(&local_err
,
2601 "Failed to set KVM's VSMT mode to %d (errno %d)",
2603 /* We can live with that if the default one is big enough
2604 * for the number of threads, and a submultiple of the one
2605 * we want. In this case we'll waste some vcpu ids, but
2606 * behaviour will be correct */
2607 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2608 warn_report_err(local_err
);
2613 error_append_hint(&local_err
,
2614 "On PPC, a VM with %d threads/core"
2615 " on a host with %d threads/core"
2616 " requires the use of VSMT mode %d.\n",
2617 smp_threads
, kvm_smt
, spapr
->vsmt
);
2619 kvmppc_hint_smt_possible(&local_err
);
2624 /* else TCG: nothing to do currently */
2626 error_propagate(errp
, local_err
);
2629 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2631 MachineState
*machine
= MACHINE(spapr
);
2632 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2633 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2634 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2635 const CPUArchIdList
*possible_cpus
;
2636 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2639 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2640 if (mc
->has_hotpluggable_cpus
) {
2641 if (smp_cpus
% smp_threads
) {
2642 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2643 smp_cpus
, smp_threads
);
2646 if (max_cpus
% smp_threads
) {
2647 error_report("max_cpus (%u) must be multiple of threads (%u)",
2648 max_cpus
, smp_threads
);
2652 if (max_cpus
!= smp_cpus
) {
2653 error_report("This machine version does not support CPU hotplug");
2656 boot_cores_nr
= possible_cpus
->len
;
2659 if (smc
->pre_2_10_has_unused_icps
) {
2662 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2663 /* Dummy entries get deregistered when real ICPState objects
2664 * are registered during CPU core hotplug.
2666 pre_2_10_vmstate_register_dummy_icp(i
);
2670 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2671 int core_id
= i
* smp_threads
;
2673 if (mc
->has_hotpluggable_cpus
) {
2674 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2675 spapr_vcpu_id(spapr
, core_id
));
2678 if (i
< boot_cores_nr
) {
2679 Object
*core
= object_new(type
);
2680 int nr_threads
= smp_threads
;
2682 /* Handle the partially filled core for older machine types */
2683 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2684 nr_threads
= smp_cpus
- i
* smp_threads
;
2687 object_property_set_int(core
, nr_threads
, "nr-threads",
2689 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2691 object_property_set_bool(core
, true, "realized", &error_fatal
);
2698 static PCIHostState
*spapr_create_default_phb(void)
2702 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2703 qdev_prop_set_uint32(dev
, "index", 0);
2704 qdev_init_nofail(dev
);
2706 return PCI_HOST_BRIDGE(dev
);
2709 /* pSeries LPAR / sPAPR hardware init */
2710 static void spapr_machine_init(MachineState
*machine
)
2712 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2713 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2714 const char *kernel_filename
= machine
->kernel_filename
;
2715 const char *initrd_filename
= machine
->initrd_filename
;
2718 MemoryRegion
*sysmem
= get_system_memory();
2719 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2720 hwaddr node0_size
= spapr_node0_size(machine
);
2721 long load_limit
, fw_size
;
2723 Error
*resize_hpt_err
= NULL
;
2725 msi_nonbroken
= true;
2727 QLIST_INIT(&spapr
->phbs
);
2728 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2730 /* Determine capabilities to run with */
2731 spapr_caps_init(spapr
);
2733 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2734 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2736 * If the user explicitly requested a mode we should either
2737 * supply it, or fail completely (which we do below). But if
2738 * it's not set explicitly, we reset our mode to something
2741 if (resize_hpt_err
) {
2742 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2743 error_free(resize_hpt_err
);
2744 resize_hpt_err
= NULL
;
2746 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2750 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2752 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2754 * User requested HPT resize, but this host can't supply it. Bail out
2756 error_report_err(resize_hpt_err
);
2760 spapr
->rma_size
= node0_size
;
2762 /* With KVM, we don't actually know whether KVM supports an
2763 * unbounded RMA (PR KVM) or is limited by the hash table size
2764 * (HV KVM using VRMA), so we always assume the latter
2766 * In that case, we also limit the initial allocations for RTAS
2767 * etc... to 256M since we have no way to know what the VRMA size
2768 * is going to be as it depends on the size of the hash table
2769 * which isn't determined yet.
2771 if (kvm_enabled()) {
2772 spapr
->vrma_adjust
= 1;
2773 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2776 /* Actually we don't support unbounded RMA anymore since we added
2777 * proper emulation of HV mode. The max we can get is 16G which
2778 * also happens to be what we configure for PAPR mode so make sure
2779 * we don't do anything bigger than that
2781 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2783 if (spapr
->rma_size
> node0_size
) {
2784 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2789 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2790 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2793 * VSMT must be set in order to be able to compute VCPU ids, ie to
2794 * call spapr_max_server_number() or spapr_vcpu_id().
2796 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2798 /* Set up Interrupt Controller before we create the VCPUs */
2799 spapr_irq_init(spapr
, &error_fatal
);
2801 /* Set up containers for ibm,client-architecture-support negotiated options
2803 spapr
->ov5
= spapr_ovec_new();
2804 spapr
->ov5_cas
= spapr_ovec_new();
2806 if (smc
->dr_lmb_enabled
) {
2807 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2808 spapr_validate_node_memory(machine
, &error_fatal
);
2811 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2813 /* advertise support for dedicated HP event source to guests */
2814 if (spapr
->use_hotplug_event_source
) {
2815 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2818 /* advertise support for HPT resizing */
2819 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2820 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2823 /* advertise support for ibm,dyamic-memory-v2 */
2824 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2826 /* advertise XIVE on POWER9 machines */
2827 if (spapr
->irq
->ov5
& (SPAPR_OV5_XIVE_EXPLOIT
| SPAPR_OV5_XIVE_BOTH
)) {
2828 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2832 spapr_init_cpus(spapr
);
2834 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2835 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2836 spapr
->max_compat_pvr
)) {
2837 /* KVM and TCG always allow GTSE with radix... */
2838 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2840 /* ... but not with hash (currently). */
2842 if (kvm_enabled()) {
2843 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2844 kvmppc_enable_logical_ci_hcalls();
2845 kvmppc_enable_set_mode_hcall();
2847 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2848 kvmppc_enable_clear_ref_mod_hcalls();
2850 /* Enable H_PAGE_INIT */
2851 kvmppc_enable_h_page_init();
2855 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2857 memory_region_add_subregion(sysmem
, 0, ram
);
2859 /* always allocate the device memory information */
2860 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2862 /* initialize hotplug memory address space */
2863 if (machine
->ram_size
< machine
->maxram_size
) {
2864 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2866 * Limit the number of hotpluggable memory slots to half the number
2867 * slots that KVM supports, leaving the other half for PCI and other
2868 * devices. However ensure that number of slots doesn't drop below 32.
2870 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2871 SPAPR_MAX_RAM_SLOTS
;
2873 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2874 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2876 if (machine
->ram_slots
> max_memslots
) {
2877 error_report("Specified number of memory slots %"
2878 PRIu64
" exceeds max supported %d",
2879 machine
->ram_slots
, max_memslots
);
2883 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2884 SPAPR_DEVICE_MEM_ALIGN
);
2885 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2886 "device-memory", device_mem_size
);
2887 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2888 &machine
->device_memory
->mr
);
2891 if (smc
->dr_lmb_enabled
) {
2892 spapr_create_lmb_dr_connectors(spapr
);
2895 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2897 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2900 spapr
->rtas_size
= get_image_size(filename
);
2901 if (spapr
->rtas_size
< 0) {
2902 error_report("Could not get size of LPAR rtas '%s'", filename
);
2905 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2906 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2907 error_report("Could not load LPAR rtas '%s'", filename
);
2910 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2911 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2912 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2917 /* Set up RTAS event infrastructure */
2918 spapr_events_init(spapr
);
2920 /* Set up the RTC RTAS interfaces */
2921 spapr_rtc_create(spapr
);
2923 /* Set up VIO bus */
2924 spapr
->vio_bus
= spapr_vio_bus_init();
2926 for (i
= 0; i
< serial_max_hds(); i
++) {
2928 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2932 /* We always have at least the nvram device on VIO */
2933 spapr_create_nvram(spapr
);
2936 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2937 * connectors (described in root DT node's "ibm,drc-types" property)
2938 * are pre-initialized here. additional child connectors (such as
2939 * connectors for a PHBs PCI slots) are added as needed during their
2940 * parent's realization.
2942 if (smc
->dr_phb_enabled
) {
2943 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2944 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2949 spapr_pci_rtas_init();
2951 phb
= spapr_create_default_phb();
2953 for (i
= 0; i
< nb_nics
; i
++) {
2954 NICInfo
*nd
= &nd_table
[i
];
2957 nd
->model
= g_strdup("spapr-vlan");
2960 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2961 g_str_equal(nd
->model
, "ibmveth")) {
2962 spapr_vlan_create(spapr
->vio_bus
, nd
);
2964 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2968 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2969 spapr_vscsi_create(spapr
->vio_bus
);
2973 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2974 spapr
->has_graphics
= true;
2975 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2979 if (smc
->use_ohci_by_default
) {
2980 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2982 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2985 if (spapr
->has_graphics
) {
2986 USBBus
*usb_bus
= usb_bus_find(-1);
2988 usb_create_simple(usb_bus
, "usb-kbd");
2989 usb_create_simple(usb_bus
, "usb-mouse");
2993 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
2995 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
3000 if (kernel_filename
) {
3001 uint64_t lowaddr
= 0;
3003 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3004 translate_kernel_address
, NULL
,
3005 NULL
, &lowaddr
, NULL
, 1,
3006 PPC_ELF_MACHINE
, 0, 0);
3007 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
3008 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3009 translate_kernel_address
, NULL
, NULL
,
3010 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
3012 spapr
->kernel_le
= spapr
->kernel_size
> 0;
3014 if (spapr
->kernel_size
< 0) {
3015 error_report("error loading %s: %s", kernel_filename
,
3016 load_elf_strerror(spapr
->kernel_size
));
3021 if (initrd_filename
) {
3022 /* Try to locate the initrd in the gap between the kernel
3023 * and the firmware. Add a bit of space just in case
3025 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
3026 + 0x1ffff) & ~0xffff;
3027 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
3030 - spapr
->initrd_base
);
3031 if (spapr
->initrd_size
< 0) {
3032 error_report("could not load initial ram disk '%s'",
3039 if (bios_name
== NULL
) {
3040 bios_name
= FW_FILE_NAME
;
3042 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
3044 error_report("Could not find LPAR firmware '%s'", bios_name
);
3047 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
3049 error_report("Could not load LPAR firmware '%s'", filename
);
3054 /* FIXME: Should register things through the MachineState's qdev
3055 * interface, this is a legacy from the sPAPREnvironment structure
3056 * which predated MachineState but had a similar function */
3057 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3058 register_savevm_live(NULL
, "spapr/htab", -1, 1,
3059 &savevm_htab_handlers
, spapr
);
3061 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
),
3064 qemu_register_boot_set(spapr_boot_set
, spapr
);
3066 if (kvm_enabled()) {
3067 /* to stop and start vmclock */
3068 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3071 kvmppc_spapr_enable_inkernel_multitce();
3075 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3081 if (!strcmp(vm_type
, "HV")) {
3085 if (!strcmp(vm_type
, "PR")) {
3089 error_report("Unknown kvm-type specified '%s'", vm_type
);
3094 * Implementation of an interface to adjust firmware path
3095 * for the bootindex property handling.
3097 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3100 #define CAST(type, obj, name) \
3101 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3102 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3103 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3104 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3107 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3108 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3109 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3113 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3114 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3115 * 0x8000 | (target << 8) | (bus << 5) | lun
3116 * (see the "Logical unit addressing format" table in SAM5)
3118 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3119 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3120 (uint64_t)id
<< 48);
3121 } else if (virtio
) {
3123 * We use SRP luns of the form 01000000 | (target << 8) | lun
3124 * in the top 32 bits of the 64-bit LUN
3125 * Note: the quote above is from SLOF and it is wrong,
3126 * the actual binding is:
3127 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3129 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3130 if (d
->lun
>= 256) {
3131 /* Use the LUN "flat space addressing method" */
3134 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3135 (uint64_t)id
<< 32);
3138 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3139 * in the top 32 bits of the 64-bit LUN
3141 unsigned usb_port
= atoi(usb
->port
->path
);
3142 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3143 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3144 (uint64_t)id
<< 32);
3149 * SLOF probes the USB devices, and if it recognizes that the device is a
3150 * storage device, it changes its name to "storage" instead of "usb-host",
3151 * and additionally adds a child node for the SCSI LUN, so the correct
3152 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3154 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3155 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3156 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3157 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3162 /* Replace "pci" with "pci@800000020000000" */
3163 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3167 /* Same logic as virtio above */
3168 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3169 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3172 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3173 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3174 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3175 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3181 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3183 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3185 return g_strdup(spapr
->kvm_type
);
3188 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3190 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3192 g_free(spapr
->kvm_type
);
3193 spapr
->kvm_type
= g_strdup(value
);
3196 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3198 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3200 return spapr
->use_hotplug_event_source
;
3203 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3206 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3208 spapr
->use_hotplug_event_source
= value
;
3211 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3216 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3218 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3220 switch (spapr
->resize_hpt
) {
3221 case SPAPR_RESIZE_HPT_DEFAULT
:
3222 return g_strdup("default");
3223 case SPAPR_RESIZE_HPT_DISABLED
:
3224 return g_strdup("disabled");
3225 case SPAPR_RESIZE_HPT_ENABLED
:
3226 return g_strdup("enabled");
3227 case SPAPR_RESIZE_HPT_REQUIRED
:
3228 return g_strdup("required");
3230 g_assert_not_reached();
3233 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3235 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3237 if (strcmp(value
, "default") == 0) {
3238 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3239 } else if (strcmp(value
, "disabled") == 0) {
3240 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3241 } else if (strcmp(value
, "enabled") == 0) {
3242 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3243 } else if (strcmp(value
, "required") == 0) {
3244 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3246 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3250 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3251 void *opaque
, Error
**errp
)
3253 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3256 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3257 void *opaque
, Error
**errp
)
3259 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3262 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3264 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3266 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3267 return g_strdup("legacy");
3268 } else if (spapr
->irq
== &spapr_irq_xics
) {
3269 return g_strdup("xics");
3270 } else if (spapr
->irq
== &spapr_irq_xive
) {
3271 return g_strdup("xive");
3272 } else if (spapr
->irq
== &spapr_irq_dual
) {
3273 return g_strdup("dual");
3275 g_assert_not_reached();
3278 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3280 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3282 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3283 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3287 /* The legacy IRQ backend can not be set */
3288 if (strcmp(value
, "xics") == 0) {
3289 spapr
->irq
= &spapr_irq_xics
;
3290 } else if (strcmp(value
, "xive") == 0) {
3291 spapr
->irq
= &spapr_irq_xive
;
3292 } else if (strcmp(value
, "dual") == 0) {
3293 spapr
->irq
= &spapr_irq_dual
;
3295 error_setg(errp
, "Bad value for \"ic-mode\" property");
3299 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3301 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3303 return g_strdup(spapr
->host_model
);
3306 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3308 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3310 g_free(spapr
->host_model
);
3311 spapr
->host_model
= g_strdup(value
);
3314 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3316 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3318 return g_strdup(spapr
->host_serial
);
3321 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3323 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3325 g_free(spapr
->host_serial
);
3326 spapr
->host_serial
= g_strdup(value
);
3329 static void spapr_instance_init(Object
*obj
)
3331 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3332 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3334 spapr
->htab_fd
= -1;
3335 spapr
->use_hotplug_event_source
= true;
3336 object_property_add_str(obj
, "kvm-type",
3337 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3338 object_property_set_description(obj
, "kvm-type",
3339 "Specifies the KVM virtualization mode (HV, PR)",
3341 object_property_add_bool(obj
, "modern-hotplug-events",
3342 spapr_get_modern_hotplug_events
,
3343 spapr_set_modern_hotplug_events
,
3345 object_property_set_description(obj
, "modern-hotplug-events",
3346 "Use dedicated hotplug event mechanism in"
3347 " place of standard EPOW events when possible"
3348 " (required for memory hot-unplug support)",
3350 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3351 "Maximum permitted CPU compatibility mode",
3354 object_property_add_str(obj
, "resize-hpt",
3355 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3356 object_property_set_description(obj
, "resize-hpt",
3357 "Resizing of the Hash Page Table (enabled, disabled, required)",
3359 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3360 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3361 object_property_set_description(obj
, "vsmt",
3362 "Virtual SMT: KVM behaves as if this were"
3363 " the host's SMT mode", &error_abort
);
3364 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3365 spapr_get_msix_emulation
, NULL
, NULL
);
3367 /* The machine class defines the default interrupt controller mode */
3368 spapr
->irq
= smc
->irq
;
3369 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3370 spapr_set_ic_mode
, NULL
);
3371 object_property_set_description(obj
, "ic-mode",
3372 "Specifies the interrupt controller mode (xics, xive, dual)",
3375 object_property_add_str(obj
, "host-model",
3376 spapr_get_host_model
, spapr_set_host_model
,
3378 object_property_set_description(obj
, "host-model",
3379 "Host model to advertise in guest device tree", &error_abort
);
3380 object_property_add_str(obj
, "host-serial",
3381 spapr_get_host_serial
, spapr_set_host_serial
,
3383 object_property_set_description(obj
, "host-serial",
3384 "Host serial number to advertise in guest device tree", &error_abort
);
3387 static void spapr_machine_finalizefn(Object
*obj
)
3389 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3391 g_free(spapr
->kvm_type
);
3394 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3396 cpu_synchronize_state(cs
);
3397 ppc_cpu_do_system_reset(cs
);
3400 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3405 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3409 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3410 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3415 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3416 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3418 *fdt_start_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3419 SPAPR_MEMORY_BLOCK_SIZE
);
3423 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3424 bool dedicated_hp_event_source
, Error
**errp
)
3427 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3429 uint64_t addr
= addr_start
;
3430 bool hotplugged
= spapr_drc_hotplugged(dev
);
3431 Error
*local_err
= NULL
;
3433 for (i
= 0; i
< nr_lmbs
; i
++) {
3434 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3435 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3438 spapr_drc_attach(drc
, dev
, &local_err
);
3440 while (addr
> addr_start
) {
3441 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3442 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3443 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3444 spapr_drc_detach(drc
);
3446 error_propagate(errp
, local_err
);
3450 spapr_drc_reset(drc
);
3452 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3454 /* send hotplug notification to the
3455 * guest only in case of hotplugged memory
3458 if (dedicated_hp_event_source
) {
3459 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3460 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3461 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3463 spapr_drc_index(drc
));
3465 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3471 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3474 Error
*local_err
= NULL
;
3475 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3476 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3477 uint64_t size
, addr
;
3479 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3481 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3486 addr
= object_property_get_uint(OBJECT(dimm
),
3487 PC_DIMM_ADDR_PROP
, &local_err
);
3492 spapr_add_lmbs(dev
, addr
, size
, spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3501 pc_dimm_unplug(dimm
, MACHINE(ms
));
3503 error_propagate(errp
, local_err
);
3506 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3509 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3510 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3511 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3512 Error
*local_err
= NULL
;
3517 if (!smc
->dr_lmb_enabled
) {
3518 error_setg(errp
, "Memory hotplug not supported for this machine");
3522 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3524 error_propagate(errp
, local_err
);
3528 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3529 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3530 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3534 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3536 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3537 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3539 error_propagate(errp
, local_err
);
3543 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3546 struct SpaprDimmState
{
3549 QTAILQ_ENTRY(SpaprDimmState
) next
;
3552 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3555 SpaprDimmState
*dimm_state
= NULL
;
3557 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3558 if (dimm_state
->dimm
== dimm
) {
3565 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3569 SpaprDimmState
*ds
= NULL
;
3572 * If this request is for a DIMM whose removal had failed earlier
3573 * (due to guest's refusal to remove the LMBs), we would have this
3574 * dimm already in the pending_dimm_unplugs list. In that
3575 * case don't add again.
3577 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3579 ds
= g_malloc0(sizeof(SpaprDimmState
));
3580 ds
->nr_lmbs
= nr_lmbs
;
3582 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3587 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3588 SpaprDimmState
*dimm_state
)
3590 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3594 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3598 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3600 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3601 uint32_t avail_lmbs
= 0;
3602 uint64_t addr_start
, addr
;
3605 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3609 for (i
= 0; i
< nr_lmbs
; i
++) {
3610 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3611 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3616 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3619 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3622 /* Callback to be called during DRC release. */
3623 void spapr_lmb_release(DeviceState
*dev
)
3625 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3626 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3627 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3629 /* This information will get lost if a migration occurs
3630 * during the unplug process. In this case recover it. */
3632 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3634 /* The DRC being examined by the caller at least must be counted */
3635 g_assert(ds
->nr_lmbs
);
3638 if (--ds
->nr_lmbs
) {
3643 * Now that all the LMBs have been removed by the guest, call the
3644 * unplug handler chain. This can never fail.
3646 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3647 object_unparent(OBJECT(dev
));
3650 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3652 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3653 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3655 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3656 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3657 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3660 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3661 DeviceState
*dev
, Error
**errp
)
3663 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3664 Error
*local_err
= NULL
;
3665 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3667 uint64_t size
, addr_start
, addr
;
3671 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3672 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3674 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3681 * An existing pending dimm state for this DIMM means that there is an
3682 * unplug operation in progress, waiting for the spapr_lmb_release
3683 * callback to complete the job (BQL can't cover that far). In this case,
3684 * bail out to avoid detaching DRCs that were already released.
3686 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3687 error_setg(&local_err
,
3688 "Memory unplug already in progress for device %s",
3693 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3696 for (i
= 0; i
< nr_lmbs
; i
++) {
3697 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3698 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3701 spapr_drc_detach(drc
);
3702 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3705 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3706 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3707 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3708 nr_lmbs
, spapr_drc_index(drc
));
3710 error_propagate(errp
, local_err
);
3713 /* Callback to be called during DRC release. */
3714 void spapr_core_release(DeviceState
*dev
)
3716 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3718 /* Call the unplug handler chain. This can never fail. */
3719 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3720 object_unparent(OBJECT(dev
));
3723 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3725 MachineState
*ms
= MACHINE(hotplug_dev
);
3726 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3727 CPUCore
*cc
= CPU_CORE(dev
);
3728 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3730 if (smc
->pre_2_10_has_unused_icps
) {
3731 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3734 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3735 CPUState
*cs
= CPU(sc
->threads
[i
]);
3737 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3742 core_slot
->cpu
= NULL
;
3743 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3747 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3750 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3753 CPUCore
*cc
= CPU_CORE(dev
);
3755 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3756 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3761 error_setg(errp
, "Boot CPU core may not be unplugged");
3765 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3766 spapr_vcpu_id(spapr
, cc
->core_id
));
3769 spapr_drc_detach(drc
);
3771 spapr_hotplug_req_remove_by_index(drc
);
3774 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3775 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3777 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3778 CPUState
*cs
= CPU(core
->threads
[0]);
3779 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3780 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3781 int id
= spapr_get_vcpu_id(cpu
);
3785 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3786 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3789 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3791 *fdt_start_offset
= offset
;
3795 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3798 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3799 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3800 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3801 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3802 CPUCore
*cc
= CPU_CORE(dev
);
3805 Error
*local_err
= NULL
;
3806 CPUArchId
*core_slot
;
3808 bool hotplugged
= spapr_drc_hotplugged(dev
);
3810 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3812 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3816 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3817 spapr_vcpu_id(spapr
, cc
->core_id
));
3819 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3822 spapr_drc_attach(drc
, dev
, &local_err
);
3824 error_propagate(errp
, local_err
);
3830 * Send hotplug notification interrupt to the guest only
3831 * in case of hotplugged CPUs.
3833 spapr_hotplug_req_add_by_index(drc
);
3835 spapr_drc_reset(drc
);
3839 core_slot
->cpu
= OBJECT(dev
);
3841 if (smc
->pre_2_10_has_unused_icps
) {
3844 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3845 cs
= CPU(core
->threads
[i
]);
3846 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3851 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3854 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3855 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3856 Error
*local_err
= NULL
;
3857 CPUCore
*cc
= CPU_CORE(dev
);
3858 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3859 const char *type
= object_get_typename(OBJECT(dev
));
3860 CPUArchId
*core_slot
;
3863 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3864 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3868 if (strcmp(base_core_type
, type
)) {
3869 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3873 if (cc
->core_id
% smp_threads
) {
3874 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3879 * In general we should have homogeneous threads-per-core, but old
3880 * (pre hotplug support) machine types allow the last core to have
3881 * reduced threads as a compatibility hack for when we allowed
3882 * total vcpus not a multiple of threads-per-core.
3884 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3885 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3886 cc
->nr_threads
, smp_threads
);
3890 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3892 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3896 if (core_slot
->cpu
) {
3897 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3901 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3904 error_propagate(errp
, local_err
);
3907 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3908 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3910 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3913 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3914 if (intc_phandle
<= 0) {
3918 if (spapr_dt_phb(sphb
, intc_phandle
, fdt
, spapr
->irq
->nr_msis
,
3919 fdt_start_offset
)) {
3920 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
3924 /* generally SLOF creates these, for hotplug it's up to QEMU */
3925 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
3930 static void spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3933 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3934 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3935 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3936 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
3938 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
3939 error_setg(errp
, "PHB hotplug not supported for this machine");
3943 if (sphb
->index
== (uint32_t)-1) {
3944 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
3949 * This will check that sphb->index doesn't exceed the maximum number of
3950 * PHBs for the current machine type.
3952 smc
->phb_placement(spapr
, sphb
->index
,
3953 &sphb
->buid
, &sphb
->io_win_addr
,
3954 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
3955 windows_supported
, sphb
->dma_liobn
,
3956 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
3960 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3963 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3964 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3965 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3967 bool hotplugged
= spapr_drc_hotplugged(dev
);
3968 Error
*local_err
= NULL
;
3970 if (!smc
->dr_phb_enabled
) {
3974 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3975 /* hotplug hooks should check it's enabled before getting this far */
3978 spapr_drc_attach(drc
, DEVICE(dev
), &local_err
);
3980 error_propagate(errp
, local_err
);
3985 spapr_hotplug_req_add_by_index(drc
);
3987 spapr_drc_reset(drc
);
3991 void spapr_phb_release(DeviceState
*dev
)
3993 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3995 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3996 object_unparent(OBJECT(dev
));
3999 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4001 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4004 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4005 DeviceState
*dev
, Error
**errp
)
4007 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4010 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4013 if (!spapr_drc_unplug_requested(drc
)) {
4014 spapr_drc_detach(drc
);
4015 spapr_hotplug_req_remove_by_index(drc
);
4019 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4020 DeviceState
*dev
, Error
**errp
)
4022 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4023 spapr_memory_plug(hotplug_dev
, dev
, errp
);
4024 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4025 spapr_core_plug(hotplug_dev
, dev
, errp
);
4026 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4027 spapr_phb_plug(hotplug_dev
, dev
, errp
);
4031 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4032 DeviceState
*dev
, Error
**errp
)
4034 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4035 spapr_memory_unplug(hotplug_dev
, dev
);
4036 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4037 spapr_core_unplug(hotplug_dev
, dev
);
4038 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4039 spapr_phb_unplug(hotplug_dev
, dev
);
4043 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4044 DeviceState
*dev
, Error
**errp
)
4046 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4047 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4048 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4050 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4051 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
4052 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4054 /* NOTE: this means there is a window after guest reset, prior to
4055 * CAS negotiation, where unplug requests will fail due to the
4056 * capability not being detected yet. This is a bit different than
4057 * the case with PCI unplug, where the events will be queued and
4058 * eventually handled by the guest after boot
4060 error_setg(errp
, "Memory hot unplug not supported for this guest");
4062 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4063 if (!mc
->has_hotpluggable_cpus
) {
4064 error_setg(errp
, "CPU hot unplug not supported on this machine");
4067 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4068 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4069 if (!smc
->dr_phb_enabled
) {
4070 error_setg(errp
, "PHB hot unplug not supported on this machine");
4073 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4077 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4078 DeviceState
*dev
, Error
**errp
)
4080 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4081 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4082 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4083 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4084 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4085 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4089 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4092 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4093 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4094 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4095 return HOTPLUG_HANDLER(machine
);
4100 static CpuInstanceProperties
4101 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4103 CPUArchId
*core_slot
;
4104 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4106 /* make sure possible_cpu are intialized */
4107 mc
->possible_cpu_arch_ids(machine
);
4108 /* get CPU core slot containing thread that matches cpu_index */
4109 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4111 return core_slot
->props
;
4114 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4116 return idx
/ smp_cores
% nb_numa_nodes
;
4119 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4122 const char *core_type
;
4123 int spapr_max_cores
= max_cpus
/ smp_threads
;
4124 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4126 if (!mc
->has_hotpluggable_cpus
) {
4127 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4129 if (machine
->possible_cpus
) {
4130 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4131 return machine
->possible_cpus
;
4134 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4136 error_report("Unable to find sPAPR CPU Core definition");
4140 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4141 sizeof(CPUArchId
) * spapr_max_cores
);
4142 machine
->possible_cpus
->len
= spapr_max_cores
;
4143 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4144 int core_id
= i
* smp_threads
;
4146 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4147 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4148 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4149 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4150 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4152 return machine
->possible_cpus
;
4155 static void spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4156 uint64_t *buid
, hwaddr
*pio
,
4157 hwaddr
*mmio32
, hwaddr
*mmio64
,
4158 unsigned n_dma
, uint32_t *liobns
,
4159 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4162 * New-style PHB window placement.
4164 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4165 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4168 * Some guest kernels can't work with MMIO windows above 1<<46
4169 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4171 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4172 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4173 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4174 * 1TiB 64-bit MMIO windows for each PHB.
4176 const uint64_t base_buid
= 0x800000020000000ULL
;
4179 /* Sanity check natural alignments */
4180 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4181 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4182 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4183 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4184 /* Sanity check bounds */
4185 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4186 SPAPR_PCI_MEM32_WIN_SIZE
);
4187 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4188 SPAPR_PCI_MEM64_WIN_SIZE
);
4190 if (index
>= SPAPR_MAX_PHBS
) {
4191 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4192 SPAPR_MAX_PHBS
- 1);
4196 *buid
= base_buid
+ index
;
4197 for (i
= 0; i
< n_dma
; ++i
) {
4198 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4201 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4202 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4203 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4205 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4206 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4209 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4211 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4213 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4216 static void spapr_ics_resend(XICSFabric
*dev
)
4218 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4220 ics_resend(spapr
->ics
);
4223 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4225 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4227 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4230 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4233 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4235 spapr
->irq
->print_info(spapr
, mon
);
4238 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4240 return cpu
->vcpu_id
;
4243 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4245 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4248 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4250 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4251 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4252 error_append_hint(errp
, "Adjust the number of cpus to %d "
4253 "or try to raise the number of threads per core\n",
4254 vcpu_id
* smp_threads
/ spapr
->vsmt
);
4258 cpu
->vcpu_id
= vcpu_id
;
4261 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4266 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4268 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4276 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4278 MachineClass
*mc
= MACHINE_CLASS(oc
);
4279 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4280 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4281 NMIClass
*nc
= NMI_CLASS(oc
);
4282 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4283 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4284 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4285 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4287 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4288 mc
->ignore_boot_device_suffixes
= true;
4291 * We set up the default / latest behaviour here. The class_init
4292 * functions for the specific versioned machine types can override
4293 * these details for backwards compatibility
4295 mc
->init
= spapr_machine_init
;
4296 mc
->reset
= spapr_machine_reset
;
4297 mc
->block_default_type
= IF_SCSI
;
4298 mc
->max_cpus
= 1024;
4299 mc
->no_parallel
= 1;
4300 mc
->default_boot_order
= "";
4301 mc
->default_ram_size
= 512 * MiB
;
4302 mc
->default_display
= "std";
4303 mc
->kvm_type
= spapr_kvm_type
;
4304 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4305 mc
->pci_allow_0_address
= true;
4306 assert(!mc
->get_hotplug_handler
);
4307 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4308 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4309 hc
->plug
= spapr_machine_device_plug
;
4310 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4311 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4312 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4313 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4314 hc
->unplug
= spapr_machine_device_unplug
;
4316 smc
->dr_lmb_enabled
= true;
4317 smc
->update_dt_enabled
= true;
4318 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4319 mc
->has_hotpluggable_cpus
= true;
4320 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4321 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4322 nc
->nmi_monitor_handler
= spapr_nmi
;
4323 smc
->phb_placement
= spapr_phb_placement
;
4324 vhc
->hypercall
= emulate_spapr_hypercall
;
4325 vhc
->hpt_mask
= spapr_hpt_mask
;
4326 vhc
->map_hptes
= spapr_map_hptes
;
4327 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4328 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4329 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4330 vhc
->get_pate
= spapr_get_pate
;
4331 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4332 xic
->ics_get
= spapr_ics_get
;
4333 xic
->ics_resend
= spapr_ics_resend
;
4334 xic
->icp_get
= spapr_icp_get
;
4335 ispc
->print_info
= spapr_pic_print_info
;
4336 /* Force NUMA node memory size to be a multiple of
4337 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4338 * in which LMBs are represented and hot-added
4340 mc
->numa_mem_align_shift
= 28;
4342 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4343 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4344 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4345 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4346 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4347 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4348 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4349 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4350 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4351 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4352 spapr_caps_add_properties(smc
, &error_abort
);
4353 smc
->irq
= &spapr_irq_dual
;
4354 smc
->dr_phb_enabled
= true;
4357 static const TypeInfo spapr_machine_info
= {
4358 .name
= TYPE_SPAPR_MACHINE
,
4359 .parent
= TYPE_MACHINE
,
4361 .instance_size
= sizeof(SpaprMachineState
),
4362 .instance_init
= spapr_instance_init
,
4363 .instance_finalize
= spapr_machine_finalizefn
,
4364 .class_size
= sizeof(SpaprMachineClass
),
4365 .class_init
= spapr_machine_class_init
,
4366 .interfaces
= (InterfaceInfo
[]) {
4367 { TYPE_FW_PATH_PROVIDER
},
4369 { TYPE_HOTPLUG_HANDLER
},
4370 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4371 { TYPE_XICS_FABRIC
},
4372 { TYPE_INTERRUPT_STATS_PROVIDER
},
4377 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4378 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4381 MachineClass *mc = MACHINE_CLASS(oc); \
4382 spapr_machine_##suffix##_class_options(mc); \
4384 mc->alias = "pseries"; \
4385 mc->is_default = 1; \
4388 static const TypeInfo spapr_machine_##suffix##_info = { \
4389 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4390 .parent = TYPE_SPAPR_MACHINE, \
4391 .class_init = spapr_machine_##suffix##_class_init, \
4393 static void spapr_machine_register_##suffix(void) \
4395 type_register(&spapr_machine_##suffix##_info); \
4397 type_init(spapr_machine_register_##suffix)
4402 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4404 /* Defaults for the latest behaviour inherited from the base class */
4407 DEFINE_SPAPR_MACHINE(4_1
, "4.1", true);
4412 static void phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4413 uint64_t *buid
, hwaddr
*pio
,
4414 hwaddr
*mmio32
, hwaddr
*mmio64
,
4415 unsigned n_dma
, uint32_t *liobns
,
4416 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4418 spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
, liobns
,
4419 nv2gpa
, nv2atsd
, errp
);
4424 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4426 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4428 spapr_machine_4_1_class_options(mc
);
4429 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4430 smc
->phb_placement
= phb_placement_4_0
;
4431 smc
->irq
= &spapr_irq_xics
;
4432 smc
->pre_4_1_migration
= true;
4435 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4440 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4442 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4444 spapr_machine_4_0_class_options(mc
);
4445 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4447 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4448 smc
->update_dt_enabled
= false;
4449 smc
->dr_phb_enabled
= false;
4450 smc
->broken_host_serial_model
= true;
4451 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4452 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4453 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4454 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4457 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4463 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4465 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4467 spapr_machine_3_1_class_options(mc
);
4468 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4470 smc
->legacy_irq_allocation
= true;
4471 smc
->irq
= &spapr_irq_xics_legacy
;
4474 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4479 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4481 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4482 static GlobalProperty compat
[] = {
4483 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4484 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4487 spapr_machine_3_0_class_options(mc
);
4488 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4489 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4491 /* We depend on kvm_enabled() to choose a default value for the
4492 * hpt-max-page-size capability. Of course we can't do it here
4493 * because this is too early and the HW accelerator isn't initialzed
4494 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4496 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4499 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4501 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4503 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4505 spapr_machine_2_12_class_options(mc
);
4506 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4507 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4508 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4511 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4517 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4519 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4521 spapr_machine_2_12_class_options(mc
);
4522 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4523 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4526 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4532 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4534 spapr_machine_2_11_class_options(mc
);
4535 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4538 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4544 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4546 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4547 static GlobalProperty compat
[] = {
4548 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4551 spapr_machine_2_10_class_options(mc
);
4552 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4553 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4554 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4555 smc
->pre_2_10_has_unused_icps
= true;
4556 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4559 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4565 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4567 static GlobalProperty compat
[] = {
4568 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4571 spapr_machine_2_9_class_options(mc
);
4572 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4573 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4574 mc
->numa_mem_align_shift
= 23;
4577 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4583 static void phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4584 uint64_t *buid
, hwaddr
*pio
,
4585 hwaddr
*mmio32
, hwaddr
*mmio64
,
4586 unsigned n_dma
, uint32_t *liobns
,
4587 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4589 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4590 const uint64_t base_buid
= 0x800000020000000ULL
;
4591 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4592 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4593 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4594 const uint32_t max_index
= 255;
4595 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4597 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4598 hwaddr phb0_base
, phb_base
;
4601 /* Do we have device memory? */
4602 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4603 /* Can't just use maxram_size, because there may be an
4604 * alignment gap between normal and device memory regions
4606 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4607 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4610 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4612 if (index
> max_index
) {
4613 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4618 *buid
= base_buid
+ index
;
4619 for (i
= 0; i
< n_dma
; ++i
) {
4620 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4623 phb_base
= phb0_base
+ index
* phb_spacing
;
4624 *pio
= phb_base
+ pio_offset
;
4625 *mmio32
= phb_base
+ mmio_offset
;
4627 * We don't set the 64-bit MMIO window, relying on the PHB's
4628 * fallback behaviour of automatically splitting a large "32-bit"
4629 * window into contiguous 32-bit and 64-bit windows
4636 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4638 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4639 static GlobalProperty compat
[] = {
4640 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4641 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4642 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4643 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4646 spapr_machine_2_8_class_options(mc
);
4647 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4648 mc
->default_machine_opts
= "modern-hotplug-events=off";
4649 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4650 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4651 smc
->phb_placement
= phb_placement_2_7
;
4654 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4660 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4662 static GlobalProperty compat
[] = {
4663 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4666 spapr_machine_2_7_class_options(mc
);
4667 mc
->has_hotpluggable_cpus
= false;
4668 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4669 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4672 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4678 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4680 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4681 static GlobalProperty compat
[] = {
4682 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4685 spapr_machine_2_6_class_options(mc
);
4686 smc
->use_ohci_by_default
= true;
4687 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4688 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4691 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4697 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4699 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4701 spapr_machine_2_5_class_options(mc
);
4702 smc
->dr_lmb_enabled
= false;
4703 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4706 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4712 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4714 static GlobalProperty compat
[] = {
4715 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4717 spapr_machine_2_4_class_options(mc
);
4718 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4719 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4721 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4727 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4729 static GlobalProperty compat
[] = {
4730 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4733 spapr_machine_2_3_class_options(mc
);
4734 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4735 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4736 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4738 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4744 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4746 spapr_machine_2_2_class_options(mc
);
4747 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4749 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4751 static void spapr_machine_register_types(void)
4753 type_register_static(&spapr_machine_info
);
4756 type_init(spapr_machine_register_types
)