2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
33 #include "hw/fw-path-provider.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
41 #include "migration/migration.h"
42 #include "mmu-hash64.h"
43 #include "mmu-book3s-v3.h"
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
61 #include "exec/address-spaces.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
67 #include "hw/intc/intc.h"
69 #include "hw/compat.h"
70 #include "qemu/cutils.h"
71 #include "hw/ppc/spapr_cpu_core.h"
72 #include "qmp-commands.h"
76 /* SLOF memory layout:
78 * SLOF raw image loaded at 0, copies its romfs right below the flat
79 * device-tree, then position SLOF itself 31M below that
81 * So we set FW_OVERHEAD to 40MB which should account for all of that
84 * We load our kernel at 4M, leaving space for SLOF initial image
86 #define FDT_MAX_SIZE 0x100000
87 #define RTAS_MAX_SIZE 0x10000
88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
89 #define FW_MAX_SIZE 0x400000
90 #define FW_FILE_NAME "slof.bin"
91 #define FW_OVERHEAD 0x2800000
92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
94 #define MIN_RMA_SLOF 128UL
96 #define PHANDLE_XICP 0x00001111
98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
100 static ICSState
*spapr_ics_create(sPAPRMachineState
*spapr
,
101 const char *type_ics
,
102 int nr_irqs
, Error
**errp
)
104 Error
*local_err
= NULL
;
107 obj
= object_new(type_ics
);
108 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
109 object_property_add_const_link(obj
, "xics", OBJECT(spapr
), &error_abort
);
110 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &local_err
);
114 object_property_set_bool(obj
, true, "realized", &local_err
);
119 return ICS_SIMPLE(obj
);
122 error_propagate(errp
, local_err
);
126 static void xics_system_init(MachineState
*machine
, int nr_irqs
, Error
**errp
)
128 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
131 if (machine_kernel_irqchip_allowed(machine
) &&
132 !xics_kvm_init(spapr
, errp
)) {
133 spapr
->icp_type
= TYPE_KVM_ICP
;
134 spapr
->ics
= spapr_ics_create(spapr
, TYPE_ICS_KVM
, nr_irqs
, errp
);
136 if (machine_kernel_irqchip_required(machine
) && !spapr
->ics
) {
137 error_prepend(errp
, "kernel_irqchip requested but unavailable: ");
143 xics_spapr_init(spapr
);
144 spapr
->icp_type
= TYPE_ICP
;
145 spapr
->ics
= spapr_ics_create(spapr
, TYPE_ICS_SIMPLE
, nr_irqs
, errp
);
152 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
156 uint32_t servers_prop
[smt_threads
];
157 uint32_t gservers_prop
[smt_threads
* 2];
158 int index
= ppc_get_vcpu_dt_id(cpu
);
160 if (cpu
->compat_pvr
) {
161 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
167 /* Build interrupt servers and gservers properties */
168 for (i
= 0; i
< smt_threads
; i
++) {
169 servers_prop
[i
] = cpu_to_be32(index
+ i
);
170 /* Hack, direct the group queues back to cpu 0 */
171 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
172 gservers_prop
[i
*2 + 1] = 0;
174 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
175 servers_prop
, sizeof(servers_prop
));
179 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
180 gservers_prop
, sizeof(gservers_prop
));
185 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, CPUState
*cs
)
188 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
189 int index
= ppc_get_vcpu_dt_id(cpu
);
190 uint32_t associativity
[] = {cpu_to_be32(0x5),
194 cpu_to_be32(cs
->numa_node
),
197 /* Advertise NUMA via ibm,associativity */
198 if (nb_numa_nodes
> 1) {
199 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
200 sizeof(associativity
));
206 /* Populate the "ibm,pa-features" property */
207 static void spapr_populate_pa_features(CPUPPCState
*env
, void *fdt
, int offset
,
210 uint8_t pa_features_206
[] = { 6, 0,
211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
212 uint8_t pa_features_207
[] = { 24, 0,
213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
217 uint8_t pa_features_300
[] = { 66, 0,
218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
233 /* 42: PM, 44: PC RA, 46: SC vec'd */
234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
235 /* 48: SIMD, 50: QP BFP, 52: String */
236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
237 /* 54: DecFP, 56: DecI, 58: SHA */
238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
239 /* 60: NM atomic, 62: RNG */
240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
242 uint8_t *pa_features
;
245 switch (POWERPC_MMU_VER(env
->mmu_model
)) {
246 case POWERPC_MMU_VER_2_06
:
247 pa_features
= pa_features_206
;
248 pa_size
= sizeof(pa_features_206
);
250 case POWERPC_MMU_VER_2_07
:
251 pa_features
= pa_features_207
;
252 pa_size
= sizeof(pa_features_207
);
254 case POWERPC_MMU_VER_3_00
:
255 pa_features
= pa_features_300
;
256 pa_size
= sizeof(pa_features_300
);
262 if (env
->ci_large_pages
) {
264 * Note: we keep CI large pages off by default because a 64K capable
265 * guest provisioned with large pages might otherwise try to map a qemu
266 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
267 * even if that qemu runs on a 4k host.
268 * We dd this bit back here if we are confident this is not an issue
270 pa_features
[3] |= 0x20;
272 if (kvmppc_has_cap_htm() && pa_size
> 24) {
273 pa_features
[24] |= 0x80; /* Transactional memory support */
275 if (legacy_guest
&& pa_size
> 40) {
276 /* Workaround for broken kernels that attempt (guest) radix
277 * mode when they can't handle it, if they see the radix bit set
278 * in pa-features. So hide it from them. */
279 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
282 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
285 static int spapr_fixup_cpu_dt(void *fdt
, sPAPRMachineState
*spapr
)
287 int ret
= 0, offset
, cpus_offset
;
290 int smt
= kvmppc_smt_threads();
291 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
294 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
295 CPUPPCState
*env
= &cpu
->env
;
296 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
297 int index
= ppc_get_vcpu_dt_id(cpu
);
298 int compat_smt
= MIN(smp_threads
, ppc_compat_max_threads(cpu
));
300 if ((index
% smt
) != 0) {
304 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
306 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
307 if (cpus_offset
< 0) {
308 cpus_offset
= fdt_add_subnode(fdt
, fdt_path_offset(fdt
, "/"),
310 if (cpus_offset
< 0) {
314 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
316 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
322 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
323 pft_size_prop
, sizeof(pft_size_prop
));
328 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cs
);
333 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
338 spapr_populate_pa_features(env
, fdt
, offset
,
339 spapr
->cas_legacy_guest_workaround
);
344 static hwaddr
spapr_node0_size(void)
346 MachineState
*machine
= MACHINE(qdev_get_machine());
350 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
351 if (numa_info
[i
].node_mem
) {
352 return MIN(pow2floor(numa_info
[i
].node_mem
),
357 return machine
->ram_size
;
360 static void add_str(GString
*s
, const gchar
*s1
)
362 g_string_append_len(s
, s1
, strlen(s1
) + 1);
365 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
368 uint32_t associativity
[] = {
369 cpu_to_be32(0x4), /* length */
370 cpu_to_be32(0x0), cpu_to_be32(0x0),
371 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
374 uint64_t mem_reg_property
[2];
377 mem_reg_property
[0] = cpu_to_be64(start
);
378 mem_reg_property
[1] = cpu_to_be64(size
);
380 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
381 off
= fdt_add_subnode(fdt
, 0, mem_name
);
383 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
384 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
385 sizeof(mem_reg_property
))));
386 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
387 sizeof(associativity
))));
391 static int spapr_populate_memory(sPAPRMachineState
*spapr
, void *fdt
)
393 MachineState
*machine
= MACHINE(spapr
);
394 hwaddr mem_start
, node_size
;
395 int i
, nb_nodes
= nb_numa_nodes
;
396 NodeInfo
*nodes
= numa_info
;
399 /* No NUMA nodes, assume there is just one node with whole RAM */
400 if (!nb_numa_nodes
) {
402 ramnode
.node_mem
= machine
->ram_size
;
406 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
407 if (!nodes
[i
].node_mem
) {
410 if (mem_start
>= machine
->ram_size
) {
413 node_size
= nodes
[i
].node_mem
;
414 if (node_size
> machine
->ram_size
- mem_start
) {
415 node_size
= machine
->ram_size
- mem_start
;
419 /* ppc_spapr_init() checks for rma_size <= node0_size already */
420 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
421 mem_start
+= spapr
->rma_size
;
422 node_size
-= spapr
->rma_size
;
424 for ( ; node_size
; ) {
425 hwaddr sizetmp
= pow2floor(node_size
);
427 /* mem_start != 0 here */
428 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
429 sizetmp
= 1ULL << ctzl(mem_start
);
432 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
433 node_size
-= sizetmp
;
434 mem_start
+= sizetmp
;
441 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
442 sPAPRMachineState
*spapr
)
444 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
445 CPUPPCState
*env
= &cpu
->env
;
446 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
447 int index
= ppc_get_vcpu_dt_id(cpu
);
448 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
449 0xffffffff, 0xffffffff};
450 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
451 : SPAPR_TIMEBASE_FREQ
;
452 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
453 uint32_t page_sizes_prop
[64];
454 size_t page_sizes_prop_size
;
455 uint32_t vcpus_per_socket
= smp_threads
* smp_cores
;
456 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
457 int compat_smt
= MIN(smp_threads
, ppc_compat_max_threads(cpu
));
458 sPAPRDRConnector
*drc
;
459 sPAPRDRConnectorClass
*drck
;
461 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
464 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU
, index
);
466 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
467 drc_index
= drck
->get_index(drc
);
468 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
471 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
472 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
474 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
475 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
476 env
->dcache_line_size
)));
477 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
478 env
->dcache_line_size
)));
479 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
480 env
->icache_line_size
)));
481 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
482 env
->icache_line_size
)));
484 if (pcc
->l1_dcache_size
) {
485 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
486 pcc
->l1_dcache_size
)));
488 error_report("Warning: Unknown L1 dcache size for cpu");
490 if (pcc
->l1_icache_size
) {
491 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
492 pcc
->l1_icache_size
)));
494 error_report("Warning: Unknown L1 icache size for cpu");
497 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
498 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
499 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", env
->slb_nr
)));
500 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", env
->slb_nr
)));
501 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
502 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
504 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
505 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
508 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
509 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
510 segs
, sizeof(segs
))));
513 /* Advertise VMX/VSX (vector extensions) if available
514 * 0 / no property == no vector extensions
515 * 1 == VMX / Altivec available
516 * 2 == VSX available */
517 if (env
->insns_flags
& PPC_ALTIVEC
) {
518 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
520 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
523 /* Advertise DFP (Decimal Floating Point) if available
524 * 0 / no property == no DFP
525 * 1 == DFP available */
526 if (env
->insns_flags2
& PPC2_DFP
) {
527 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
530 page_sizes_prop_size
= ppc_create_page_sizes_prop(env
, page_sizes_prop
,
531 sizeof(page_sizes_prop
));
532 if (page_sizes_prop_size
) {
533 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
534 page_sizes_prop
, page_sizes_prop_size
)));
537 spapr_populate_pa_features(env
, fdt
, offset
, false);
539 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
540 cs
->cpu_index
/ vcpus_per_socket
)));
542 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
543 pft_size_prop
, sizeof(pft_size_prop
))));
545 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cs
));
547 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
549 if (pcc
->radix_page_info
) {
550 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
551 radix_AP_encodings
[i
] =
552 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
554 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
556 pcc
->radix_page_info
->count
*
557 sizeof(radix_AP_encodings
[0]))));
561 static void spapr_populate_cpus_dt_node(void *fdt
, sPAPRMachineState
*spapr
)
566 int smt
= kvmppc_smt_threads();
568 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
570 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
571 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
574 * We walk the CPUs in reverse order to ensure that CPU DT nodes
575 * created by fdt_add_subnode() end up in the right order in FDT
576 * for the guest kernel the enumerate the CPUs correctly.
578 CPU_FOREACH_REVERSE(cs
) {
579 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
580 int index
= ppc_get_vcpu_dt_id(cpu
);
581 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
584 if ((index
% smt
) != 0) {
588 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
589 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
592 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
598 * Adds ibm,dynamic-reconfiguration-memory node.
599 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
600 * of this device tree node.
602 static int spapr_populate_drconf_memory(sPAPRMachineState
*spapr
, void *fdt
)
604 MachineState
*machine
= MACHINE(spapr
);
606 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
607 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
608 uint32_t hotplug_lmb_start
= spapr
->hotplug_memory
.base
/ lmb_size
;
609 uint32_t nr_lmbs
= (spapr
->hotplug_memory
.base
+
610 memory_region_size(&spapr
->hotplug_memory
.mr
)) /
612 uint32_t *int_buf
, *cur_index
, buf_len
;
613 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
616 * Don't create the node if there is no hotpluggable memory
618 if (machine
->ram_size
== machine
->maxram_size
) {
623 * Allocate enough buffer size to fit in ibm,dynamic-memory
624 * or ibm,associativity-lookup-arrays
626 buf_len
= MAX(nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1, nr_nodes
* 4 + 2)
628 cur_index
= int_buf
= g_malloc0(buf_len
);
630 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
632 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
633 sizeof(prop_lmb_size
));
638 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
643 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
648 /* ibm,dynamic-memory */
649 int_buf
[0] = cpu_to_be32(nr_lmbs
);
651 for (i
= 0; i
< nr_lmbs
; i
++) {
652 uint64_t addr
= i
* lmb_size
;
653 uint32_t *dynamic_memory
= cur_index
;
655 if (i
>= hotplug_lmb_start
) {
656 sPAPRDRConnector
*drc
;
657 sPAPRDRConnectorClass
*drck
;
659 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
, i
);
661 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
663 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
664 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
665 dynamic_memory
[2] = cpu_to_be32(drck
->get_index(drc
));
666 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
667 dynamic_memory
[4] = cpu_to_be32(numa_get_node(addr
, NULL
));
668 if (memory_region_present(get_system_memory(), addr
)) {
669 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
671 dynamic_memory
[5] = cpu_to_be32(0);
675 * LMB information for RMA, boot time RAM and gap b/n RAM and
676 * hotplug memory region -- all these are marked as reserved
677 * and as having no valid DRC.
679 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
680 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
681 dynamic_memory
[2] = cpu_to_be32(0);
682 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
683 dynamic_memory
[4] = cpu_to_be32(-1);
684 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
685 SPAPR_LMB_FLAGS_DRC_INVALID
);
688 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
690 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
695 /* ibm,associativity-lookup-arrays */
697 int_buf
[0] = cpu_to_be32(nr_nodes
);
698 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
700 for (i
= 0; i
< nr_nodes
; i
++) {
701 uint32_t associativity
[] = {
707 memcpy(cur_index
, associativity
, sizeof(associativity
));
710 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
711 (cur_index
- int_buf
) * sizeof(uint32_t));
717 static int spapr_dt_cas_updates(sPAPRMachineState
*spapr
, void *fdt
,
718 sPAPROptionVector
*ov5_updates
)
720 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
723 /* Generate ibm,dynamic-reconfiguration-memory node if required */
724 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
725 g_assert(smc
->dr_lmb_enabled
);
726 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
732 offset
= fdt_path_offset(fdt
, "/chosen");
734 offset
= fdt_add_subnode(fdt
, 0, "chosen");
739 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
740 "ibm,architecture-vec-5");
746 int spapr_h_cas_compose_response(sPAPRMachineState
*spapr
,
747 target_ulong addr
, target_ulong size
,
748 sPAPROptionVector
*ov5_updates
)
750 void *fdt
, *fdt_skel
;
751 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
755 /* Create sceleton */
756 fdt_skel
= g_malloc0(size
);
757 _FDT((fdt_create(fdt_skel
, size
)));
758 _FDT((fdt_begin_node(fdt_skel
, "")));
759 _FDT((fdt_end_node(fdt_skel
)));
760 _FDT((fdt_finish(fdt_skel
)));
761 fdt
= g_malloc0(size
);
762 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
765 /* Fixup cpu nodes */
766 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
768 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
772 /* Pack resulting tree */
773 _FDT((fdt_pack(fdt
)));
775 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
776 trace_spapr_cas_failed(size
);
780 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
781 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
782 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
788 static void spapr_dt_rtas(sPAPRMachineState
*spapr
, void *fdt
)
791 GString
*hypertas
= g_string_sized_new(256);
792 GString
*qemu_hypertas
= g_string_sized_new(256);
793 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
794 uint64_t max_hotplug_addr
= spapr
->hotplug_memory
.base
+
795 memory_region_size(&spapr
->hotplug_memory
.mr
);
796 uint32_t lrdr_capacity
[] = {
797 cpu_to_be32(max_hotplug_addr
>> 32),
798 cpu_to_be32(max_hotplug_addr
& 0xffffffff),
799 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
800 cpu_to_be32(max_cpus
/ smp_threads
),
803 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
806 add_str(hypertas
, "hcall-pft");
807 add_str(hypertas
, "hcall-term");
808 add_str(hypertas
, "hcall-dabr");
809 add_str(hypertas
, "hcall-interrupt");
810 add_str(hypertas
, "hcall-tce");
811 add_str(hypertas
, "hcall-vio");
812 add_str(hypertas
, "hcall-splpar");
813 add_str(hypertas
, "hcall-bulk");
814 add_str(hypertas
, "hcall-set-mode");
815 add_str(hypertas
, "hcall-sprg0");
816 add_str(hypertas
, "hcall-copy");
817 add_str(hypertas
, "hcall-debug");
818 add_str(qemu_hypertas
, "hcall-memop1");
820 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
821 add_str(hypertas
, "hcall-multi-tce");
823 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
824 hypertas
->str
, hypertas
->len
));
825 g_string_free(hypertas
, TRUE
);
826 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
827 qemu_hypertas
->str
, qemu_hypertas
->len
));
828 g_string_free(qemu_hypertas
, TRUE
);
830 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
831 refpoints
, sizeof(refpoints
)));
833 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
834 RTAS_ERROR_LOG_MAX
));
835 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
836 RTAS_EVENT_SCAN_RATE
));
839 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
843 * According to PAPR, rtas ibm,os-term does not guarantee a return
844 * back to the guest cpu.
846 * While an additional ibm,extended-os-term property indicates
847 * that rtas call return will always occur. Set this property.
849 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
851 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
852 lrdr_capacity
, sizeof(lrdr_capacity
)));
854 spapr_dt_rtas_tokens(fdt
, rtas
);
857 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
858 * that the guest may request and thus the valid values for bytes 24..26 of
859 * option vector 5: */
860 static void spapr_dt_ov5_platform_support(void *fdt
, int chosen
)
862 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
865 24, 0x00, /* Hash/Radix, filled in below. */
866 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
867 26, 0x40, /* Radix options: GTSE == yes. */
871 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
872 val
[1] = 0x80; /* OV5_MMU_BOTH */
873 } else if (kvmppc_has_cap_mmu_radix()) {
874 val
[1] = 0x40; /* OV5_MMU_RADIX_300 */
876 val
[1] = 0x00; /* Hash */
879 if (first_ppc_cpu
->env
.mmu_model
& POWERPC_MMU_V3
) {
880 /* V3 MMU supports both hash and radix (with dynamic switching) */
883 /* Otherwise we can only do hash */
887 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
891 static void spapr_dt_chosen(sPAPRMachineState
*spapr
, void *fdt
)
893 MachineState
*machine
= MACHINE(spapr
);
895 const char *boot_device
= machine
->boot_order
;
896 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
898 char *bootlist
= get_boot_devices_list(&cb
, true);
900 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
902 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs", machine
->kernel_cmdline
));
903 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
904 spapr
->initrd_base
));
905 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
906 spapr
->initrd_base
+ spapr
->initrd_size
));
908 if (spapr
->kernel_size
) {
909 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
910 cpu_to_be64(spapr
->kernel_size
) };
912 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
913 &kprop
, sizeof(kprop
)));
914 if (spapr
->kernel_le
) {
915 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
919 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
921 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
922 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
923 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
925 if (cb
&& bootlist
) {
928 for (i
= 0; i
< cb
; i
++) {
929 if (bootlist
[i
] == '\n') {
933 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
936 if (boot_device
&& strlen(boot_device
)) {
937 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
940 if (!spapr
->has_graphics
&& stdout_path
) {
941 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
944 spapr_dt_ov5_platform_support(fdt
, chosen
);
950 static void spapr_dt_hypervisor(sPAPRMachineState
*spapr
, void *fdt
)
952 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
953 * KVM to work under pHyp with some guest co-operation */
955 uint8_t hypercall
[16];
957 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
958 /* indicate KVM hypercall interface */
959 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
960 if (kvmppc_has_cap_fixup_hcalls()) {
962 * Older KVM versions with older guest kernels were broken
963 * with the magic page, don't allow the guest to map it.
965 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
966 sizeof(hypercall
))) {
967 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
968 hypercall
, sizeof(hypercall
)));
973 static void *spapr_build_fdt(sPAPRMachineState
*spapr
,
977 MachineState
*machine
= MACHINE(qdev_get_machine());
978 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
979 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
984 int smt
= kvmppc_smt_threads();
986 fdt
= g_malloc0(FDT_MAX_SIZE
);
987 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
990 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
991 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
992 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
995 * Add info to guest to indentify which host is it being run on
996 * and what is the uuid of the guest
998 if (kvmppc_get_host_model(&buf
)) {
999 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1002 if (kvmppc_get_host_serial(&buf
)) {
1003 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1007 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1009 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1010 if (qemu_uuid_set
) {
1011 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1015 if (qemu_get_vm_name()) {
1016 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1017 qemu_get_vm_name()));
1020 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1021 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1023 /* /interrupt controller */
1024 spapr_dt_xics(DIV_ROUND_UP(max_cpus
* smt
, smp_threads
), fdt
, PHANDLE_XICP
);
1026 ret
= spapr_populate_memory(spapr
, fdt
);
1028 error_report("couldn't setup memory nodes in fdt");
1033 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1035 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1036 ret
= spapr_rng_populate_dt(fdt
);
1038 error_report("could not set up rng device in the fdt");
1043 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1044 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
1046 error_report("couldn't setup PCI devices in fdt");
1052 spapr_populate_cpus_dt_node(fdt
, spapr
);
1054 if (smc
->dr_lmb_enabled
) {
1055 _FDT(spapr_drc_populate_dt(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1058 if (mc
->has_hotpluggable_cpus
) {
1059 int offset
= fdt_path_offset(fdt
, "/cpus");
1060 ret
= spapr_drc_populate_dt(fdt
, offset
, NULL
,
1061 SPAPR_DR_CONNECTOR_TYPE_CPU
);
1063 error_report("Couldn't set up CPU DR device tree properties");
1068 /* /event-sources */
1069 spapr_dt_events(spapr
, fdt
);
1072 spapr_dt_rtas(spapr
, fdt
);
1075 spapr_dt_chosen(spapr
, fdt
);
1078 if (kvm_enabled()) {
1079 spapr_dt_hypervisor(spapr
, fdt
);
1082 /* Build memory reserve map */
1083 if (spapr
->kernel_size
) {
1084 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1086 if (spapr
->initrd_size
) {
1087 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1090 /* ibm,client-architecture-support updates */
1091 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1093 error_report("couldn't setup CAS properties fdt");
1100 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1102 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1105 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1108 CPUPPCState
*env
= &cpu
->env
;
1110 /* The TCG path should also be holding the BQL at this point */
1111 g_assert(qemu_mutex_iothread_locked());
1114 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1115 env
->gpr
[3] = H_PRIVILEGE
;
1117 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1121 static uint64_t spapr_get_patbe(PPCVirtualHypervisor
*vhyp
)
1123 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1125 return spapr
->patb_entry
;
1128 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1129 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1130 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1131 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1132 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1135 * Get the fd to access the kernel htab, re-opening it if necessary
1137 static int get_htab_fd(sPAPRMachineState
*spapr
)
1139 if (spapr
->htab_fd
>= 0) {
1140 return spapr
->htab_fd
;
1143 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
1144 if (spapr
->htab_fd
< 0) {
1145 error_report("Unable to open fd for reading hash table from KVM: %s",
1149 return spapr
->htab_fd
;
1152 void close_htab_fd(sPAPRMachineState
*spapr
)
1154 if (spapr
->htab_fd
>= 0) {
1155 close(spapr
->htab_fd
);
1157 spapr
->htab_fd
= -1;
1160 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1162 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1164 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1167 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1170 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1171 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1175 * HTAB is controlled by KVM. Fetch into temporary buffer
1177 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1178 kvmppc_read_hptes(hptes
, ptex
, n
);
1183 * HTAB is controlled by QEMU. Just point to the internally
1186 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1189 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1190 const ppc_hash_pte64_t
*hptes
,
1193 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1196 g_free((void *)hptes
);
1199 /* Nothing to do for qemu managed HPT */
1202 static void spapr_store_hpte(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1203 uint64_t pte0
, uint64_t pte1
)
1205 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1206 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1209 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1211 stq_p(spapr
->htab
+ offset
, pte0
);
1212 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1216 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1220 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1221 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1222 * that's much more than is needed for Linux guests */
1223 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1224 shift
= MAX(shift
, 18); /* Minimum architected size */
1225 shift
= MIN(shift
, 46); /* Maximum architected size */
1229 void spapr_free_hpt(sPAPRMachineState
*spapr
)
1231 g_free(spapr
->htab
);
1233 spapr
->htab_shift
= 0;
1234 close_htab_fd(spapr
);
1237 static void spapr_reallocate_hpt(sPAPRMachineState
*spapr
, int shift
,
1242 /* Clean up any HPT info from a previous boot */
1243 spapr_free_hpt(spapr
);
1245 rc
= kvmppc_reset_htab(shift
);
1247 /* kernel-side HPT needed, but couldn't allocate one */
1248 error_setg_errno(errp
, errno
,
1249 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1251 /* This is almost certainly fatal, but if the caller really
1252 * wants to carry on with shift == 0, it's welcome to try */
1253 } else if (rc
> 0) {
1254 /* kernel-side HPT allocated */
1257 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1261 spapr
->htab_shift
= shift
;
1264 /* kernel-side HPT not needed, allocate in userspace instead */
1265 size_t size
= 1ULL << shift
;
1268 spapr
->htab
= qemu_memalign(size
, size
);
1270 error_setg_errno(errp
, errno
,
1271 "Could not allocate HPT of order %d", shift
);
1275 memset(spapr
->htab
, 0, size
);
1276 spapr
->htab_shift
= shift
;
1278 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1279 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1284 void spapr_setup_hpt_and_vrma(sPAPRMachineState
*spapr
)
1286 spapr_reallocate_hpt(spapr
,
1287 spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
),
1289 if (spapr
->vrma_adjust
) {
1290 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(),
1293 /* We're setting up a hash table, so that means we're not radix */
1294 spapr
->patb_entry
= 0;
1297 static void find_unknown_sysbus_device(SysBusDevice
*sbdev
, void *opaque
)
1299 bool matched
= false;
1301 if (object_dynamic_cast(OBJECT(sbdev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
1306 error_report("Device %s is not supported by this machine yet.",
1307 qdev_fw_name(DEVICE(sbdev
)));
1312 static void ppc_spapr_reset(void)
1314 MachineState
*machine
= MACHINE(qdev_get_machine());
1315 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
1316 PowerPCCPU
*first_ppc_cpu
;
1317 uint32_t rtas_limit
;
1318 hwaddr rtas_addr
, fdt_addr
;
1322 /* Check for unknown sysbus devices */
1323 foreach_dynamic_sysbus_device(find_unknown_sysbus_device
, NULL
);
1325 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) {
1326 /* If using KVM with radix mode available, VCPUs can be started
1327 * without a HPT because KVM will start them in radix mode.
1328 * Set the GR bit in PATB so that we know there is no HPT. */
1329 spapr
->patb_entry
= PATBE1_GR
;
1331 spapr
->patb_entry
= 0;
1332 spapr_setup_hpt_and_vrma(spapr
);
1335 qemu_devices_reset();
1338 * We place the device tree and RTAS just below either the top of the RMA,
1339 * or just below 2GB, whichever is lowere, so that it can be
1340 * processed with 32-bit real mode code if necessary
1342 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1343 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1344 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1346 /* if this reset wasn't generated by CAS, we should reset our
1347 * negotiated options and start from scratch */
1348 if (!spapr
->cas_reboot
) {
1349 spapr_ovec_cleanup(spapr
->ov5_cas
);
1350 spapr
->ov5_cas
= spapr_ovec_new();
1353 fdt
= spapr_build_fdt(spapr
, rtas_addr
, spapr
->rtas_size
);
1355 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1359 /* Should only fail if we've built a corrupted tree */
1362 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1363 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1364 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1369 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1370 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1373 /* Set up the entry state */
1374 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1375 first_ppc_cpu
->env
.gpr
[3] = fdt_addr
;
1376 first_ppc_cpu
->env
.gpr
[5] = 0;
1377 first_cpu
->halted
= 0;
1378 first_ppc_cpu
->env
.nip
= SPAPR_ENTRY_POINT
;
1380 spapr
->cas_reboot
= false;
1383 static void spapr_create_nvram(sPAPRMachineState
*spapr
)
1385 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1386 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1389 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1393 qdev_init_nofail(dev
);
1395 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
1398 static void spapr_rtc_create(sPAPRMachineState
*spapr
)
1400 object_initialize(&spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
);
1401 object_property_add_child(OBJECT(spapr
), "rtc", OBJECT(&spapr
->rtc
),
1403 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1405 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1406 "date", &error_fatal
);
1409 /* Returns whether we want to use VGA or not */
1410 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1412 switch (vga_interface_type
) {
1419 return pci_vga_init(pci_bus
) != NULL
;
1422 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1427 static int spapr_post_load(void *opaque
, int version_id
)
1429 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1432 if (!object_dynamic_cast(OBJECT(spapr
->ics
), TYPE_ICS_KVM
)) {
1435 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1436 icp_resend(ICP(cpu
->intc
));
1440 /* In earlier versions, there was no separate qdev for the PAPR
1441 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1442 * So when migrating from those versions, poke the incoming offset
1443 * value into the RTC device */
1444 if (version_id
< 3) {
1445 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1451 static bool version_before_3(void *opaque
, int version_id
)
1453 return version_id
< 3;
1456 static bool spapr_ov5_cas_needed(void *opaque
)
1458 sPAPRMachineState
*spapr
= opaque
;
1459 sPAPROptionVector
*ov5_mask
= spapr_ovec_new();
1460 sPAPROptionVector
*ov5_legacy
= spapr_ovec_new();
1461 sPAPROptionVector
*ov5_removed
= spapr_ovec_new();
1464 /* Prior to the introduction of sPAPROptionVector, we had two option
1465 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1466 * Both of these options encode machine topology into the device-tree
1467 * in such a way that the now-booted OS should still be able to interact
1468 * appropriately with QEMU regardless of what options were actually
1469 * negotiatied on the source side.
1471 * As such, we can avoid migrating the CAS-negotiated options if these
1472 * are the only options available on the current machine/platform.
1473 * Since these are the only options available for pseries-2.7 and
1474 * earlier, this allows us to maintain old->new/new->old migration
1477 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1478 * via default pseries-2.8 machines and explicit command-line parameters.
1479 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1480 * of the actual CAS-negotiated values to continue working properly. For
1481 * example, availability of memory unplug depends on knowing whether
1482 * OV5_HP_EVT was negotiated via CAS.
1484 * Thus, for any cases where the set of available CAS-negotiatable
1485 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1486 * include the CAS-negotiated options in the migration stream.
1488 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1489 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1491 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1492 * the mask itself since in the future it's possible "legacy" bits may be
1493 * removed via machine options, which could generate a false positive
1494 * that breaks migration.
1496 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
1497 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
1499 spapr_ovec_cleanup(ov5_mask
);
1500 spapr_ovec_cleanup(ov5_legacy
);
1501 spapr_ovec_cleanup(ov5_removed
);
1506 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1507 .name
= "spapr_option_vector_ov5_cas",
1509 .minimum_version_id
= 1,
1510 .needed
= spapr_ov5_cas_needed
,
1511 .fields
= (VMStateField
[]) {
1512 VMSTATE_STRUCT_POINTER_V(ov5_cas
, sPAPRMachineState
, 1,
1513 vmstate_spapr_ovec
, sPAPROptionVector
),
1514 VMSTATE_END_OF_LIST()
1518 static bool spapr_patb_entry_needed(void *opaque
)
1520 sPAPRMachineState
*spapr
= opaque
;
1522 return !!spapr
->patb_entry
;
1525 static const VMStateDescription vmstate_spapr_patb_entry
= {
1526 .name
= "spapr_patb_entry",
1528 .minimum_version_id
= 1,
1529 .needed
= spapr_patb_entry_needed
,
1530 .fields
= (VMStateField
[]) {
1531 VMSTATE_UINT64(patb_entry
, sPAPRMachineState
),
1532 VMSTATE_END_OF_LIST()
1536 static const VMStateDescription vmstate_spapr
= {
1539 .minimum_version_id
= 1,
1540 .post_load
= spapr_post_load
,
1541 .fields
= (VMStateField
[]) {
1542 /* used to be @next_irq */
1543 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
1546 VMSTATE_UINT64_TEST(rtc_offset
, sPAPRMachineState
, version_before_3
),
1548 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPRMachineState
, 2),
1549 VMSTATE_END_OF_LIST()
1551 .subsections
= (const VMStateDescription
*[]) {
1552 &vmstate_spapr_ov5_cas
,
1553 &vmstate_spapr_patb_entry
,
1558 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
1560 sPAPRMachineState
*spapr
= opaque
;
1562 /* "Iteration" header */
1563 qemu_put_be32(f
, spapr
->htab_shift
);
1566 spapr
->htab_save_index
= 0;
1567 spapr
->htab_first_pass
= true;
1569 assert(kvm_enabled());
1576 static void htab_save_first_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1579 bool has_timeout
= max_ns
!= -1;
1580 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1581 int index
= spapr
->htab_save_index
;
1582 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1584 assert(spapr
->htab_first_pass
);
1589 /* Consume invalid HPTEs */
1590 while ((index
< htabslots
)
1591 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1592 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1596 /* Consume valid HPTEs */
1598 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
1599 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1600 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1604 if (index
> chunkstart
) {
1605 int n_valid
= index
- chunkstart
;
1607 qemu_put_be32(f
, chunkstart
);
1608 qemu_put_be16(f
, n_valid
);
1609 qemu_put_be16(f
, 0);
1610 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1611 HASH_PTE_SIZE_64
* n_valid
);
1614 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1618 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
1620 if (index
>= htabslots
) {
1621 assert(index
== htabslots
);
1623 spapr
->htab_first_pass
= false;
1625 spapr
->htab_save_index
= index
;
1628 static int htab_save_later_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1631 bool final
= max_ns
< 0;
1632 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1633 int examined
= 0, sent
= 0;
1634 int index
= spapr
->htab_save_index
;
1635 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1637 assert(!spapr
->htab_first_pass
);
1640 int chunkstart
, invalidstart
;
1642 /* Consume non-dirty HPTEs */
1643 while ((index
< htabslots
)
1644 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
1650 /* Consume valid dirty HPTEs */
1651 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
1652 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1653 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1654 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1659 invalidstart
= index
;
1660 /* Consume invalid dirty HPTEs */
1661 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
1662 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1663 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1664 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1669 if (index
> chunkstart
) {
1670 int n_valid
= invalidstart
- chunkstart
;
1671 int n_invalid
= index
- invalidstart
;
1673 qemu_put_be32(f
, chunkstart
);
1674 qemu_put_be16(f
, n_valid
);
1675 qemu_put_be16(f
, n_invalid
);
1676 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1677 HASH_PTE_SIZE_64
* n_valid
);
1678 sent
+= index
- chunkstart
;
1680 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1685 if (examined
>= htabslots
) {
1689 if (index
>= htabslots
) {
1690 assert(index
== htabslots
);
1693 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
1695 if (index
>= htabslots
) {
1696 assert(index
== htabslots
);
1700 spapr
->htab_save_index
= index
;
1702 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
1705 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1706 #define MAX_KVM_BUF_SIZE 2048
1708 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
1710 sPAPRMachineState
*spapr
= opaque
;
1714 /* Iteration header */
1715 qemu_put_be32(f
, 0);
1718 assert(kvm_enabled());
1720 fd
= get_htab_fd(spapr
);
1725 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
1729 } else if (spapr
->htab_first_pass
) {
1730 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
1732 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
1736 qemu_put_be32(f
, 0);
1737 qemu_put_be16(f
, 0);
1738 qemu_put_be16(f
, 0);
1743 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
1745 sPAPRMachineState
*spapr
= opaque
;
1748 /* Iteration header */
1749 qemu_put_be32(f
, 0);
1754 assert(kvm_enabled());
1756 fd
= get_htab_fd(spapr
);
1761 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
1766 if (spapr
->htab_first_pass
) {
1767 htab_save_first_pass(f
, spapr
, -1);
1769 htab_save_later_pass(f
, spapr
, -1);
1773 qemu_put_be32(f
, 0);
1774 qemu_put_be16(f
, 0);
1775 qemu_put_be16(f
, 0);
1780 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
1782 sPAPRMachineState
*spapr
= opaque
;
1783 uint32_t section_hdr
;
1786 if (version_id
< 1 || version_id
> 1) {
1787 error_report("htab_load() bad version");
1791 section_hdr
= qemu_get_be32(f
);
1794 Error
*local_err
= NULL
;
1796 /* First section gives the htab size */
1797 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
1799 error_report_err(local_err
);
1806 assert(kvm_enabled());
1808 fd
= kvmppc_get_htab_fd(true);
1810 error_report("Unable to open fd to restore KVM hash table: %s",
1817 uint16_t n_valid
, n_invalid
;
1819 index
= qemu_get_be32(f
);
1820 n_valid
= qemu_get_be16(f
);
1821 n_invalid
= qemu_get_be16(f
);
1823 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1828 if ((index
+ n_valid
+ n_invalid
) >
1829 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1830 /* Bad index in stream */
1832 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1833 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
1839 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1840 HASH_PTE_SIZE_64
* n_valid
);
1843 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1844 HASH_PTE_SIZE_64
* n_invalid
);
1851 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1866 static void htab_cleanup(void *opaque
)
1868 sPAPRMachineState
*spapr
= opaque
;
1870 close_htab_fd(spapr
);
1873 static SaveVMHandlers savevm_htab_handlers
= {
1874 .save_live_setup
= htab_save_setup
,
1875 .save_live_iterate
= htab_save_iterate
,
1876 .save_live_complete_precopy
= htab_save_complete
,
1877 .cleanup
= htab_cleanup
,
1878 .load_state
= htab_load
,
1881 static void spapr_boot_set(void *opaque
, const char *boot_device
,
1884 MachineState
*machine
= MACHINE(qdev_get_machine());
1885 machine
->boot_order
= g_strdup(boot_device
);
1889 * Reset routine for LMB DR devices.
1891 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1892 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1893 * when it walks all its children devices. LMB devices reset occurs
1894 * as part of spapr_ppc_reset().
1896 static void spapr_drc_reset(void *opaque
)
1898 sPAPRDRConnector
*drc
= opaque
;
1899 DeviceState
*d
= DEVICE(drc
);
1906 static void spapr_create_lmb_dr_connectors(sPAPRMachineState
*spapr
)
1908 MachineState
*machine
= MACHINE(spapr
);
1909 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
1910 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
1913 for (i
= 0; i
< nr_lmbs
; i
++) {
1914 sPAPRDRConnector
*drc
;
1917 addr
= i
* lmb_size
+ spapr
->hotplug_memory
.base
;
1918 drc
= spapr_dr_connector_new(OBJECT(spapr
), SPAPR_DR_CONNECTOR_TYPE_LMB
,
1920 qemu_register_reset(spapr_drc_reset
, drc
);
1925 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1926 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1927 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1929 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
1933 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
1934 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
1935 " is not aligned to %llu MiB",
1937 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
1941 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
1942 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
1943 " is not aligned to %llu MiB",
1945 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
1949 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1950 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
1952 "Node %d memory size 0x%" PRIx64
1953 " is not aligned to %llu MiB",
1954 i
, numa_info
[i
].node_mem
,
1955 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
1961 /* find cpu slot in machine->possible_cpus by core_id */
1962 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
1964 int index
= id
/ smp_threads
;
1966 if (index
>= ms
->possible_cpus
->len
) {
1972 return &ms
->possible_cpus
->cpus
[index
];
1975 static void spapr_init_cpus(sPAPRMachineState
*spapr
)
1977 MachineState
*machine
= MACHINE(spapr
);
1978 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1979 char *type
= spapr_get_cpu_core_type(machine
->cpu_model
);
1980 int smt
= kvmppc_smt_threads();
1981 const CPUArchIdList
*possible_cpus
;
1982 int boot_cores_nr
= smp_cpus
/ smp_threads
;
1986 error_report("Unable to find sPAPR CPU Core definition");
1990 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1991 if (mc
->has_hotpluggable_cpus
) {
1992 if (smp_cpus
% smp_threads
) {
1993 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1994 smp_cpus
, smp_threads
);
1997 if (max_cpus
% smp_threads
) {
1998 error_report("max_cpus (%u) must be multiple of threads (%u)",
1999 max_cpus
, smp_threads
);
2003 if (max_cpus
!= smp_cpus
) {
2004 error_report("This machine version does not support CPU hotplug");
2007 boot_cores_nr
= possible_cpus
->len
;
2010 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2011 int core_id
= i
* smp_threads
;
2013 if (mc
->has_hotpluggable_cpus
) {
2014 sPAPRDRConnector
*drc
=
2015 spapr_dr_connector_new(OBJECT(spapr
),
2016 SPAPR_DR_CONNECTOR_TYPE_CPU
,
2017 (core_id
/ smp_threads
) * smt
);
2019 qemu_register_reset(spapr_drc_reset
, drc
);
2022 if (i
< boot_cores_nr
) {
2023 Object
*core
= object_new(type
);
2024 int nr_threads
= smp_threads
;
2026 /* Handle the partially filled core for older machine types */
2027 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2028 nr_threads
= smp_cpus
- i
* smp_threads
;
2031 object_property_set_int(core
, nr_threads
, "nr-threads",
2033 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2035 object_property_set_bool(core
, true, "realized", &error_fatal
);
2041 /* pSeries LPAR / sPAPR hardware init */
2042 static void ppc_spapr_init(MachineState
*machine
)
2044 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
2045 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2046 const char *kernel_filename
= machine
->kernel_filename
;
2047 const char *initrd_filename
= machine
->initrd_filename
;
2050 MemoryRegion
*sysmem
= get_system_memory();
2051 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2052 MemoryRegion
*rma_region
;
2054 hwaddr rma_alloc_size
;
2055 hwaddr node0_size
= spapr_node0_size();
2056 long load_limit
, fw_size
;
2059 msi_nonbroken
= true;
2061 QLIST_INIT(&spapr
->phbs
);
2063 /* Allocate RMA if necessary */
2064 rma_alloc_size
= kvmppc_alloc_rma(&rma
);
2066 if (rma_alloc_size
== -1) {
2067 error_report("Unable to create RMA");
2071 if (rma_alloc_size
&& (rma_alloc_size
< node0_size
)) {
2072 spapr
->rma_size
= rma_alloc_size
;
2074 spapr
->rma_size
= node0_size
;
2076 /* With KVM, we don't actually know whether KVM supports an
2077 * unbounded RMA (PR KVM) or is limited by the hash table size
2078 * (HV KVM using VRMA), so we always assume the latter
2080 * In that case, we also limit the initial allocations for RTAS
2081 * etc... to 256M since we have no way to know what the VRMA size
2082 * is going to be as it depends on the size of the hash table
2083 * isn't determined yet.
2085 if (kvm_enabled()) {
2086 spapr
->vrma_adjust
= 1;
2087 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2090 /* Actually we don't support unbounded RMA anymore since we
2091 * added proper emulation of HV mode. The max we can get is
2092 * 16G which also happens to be what we configure for PAPR
2093 * mode so make sure we don't do anything bigger than that
2095 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2098 if (spapr
->rma_size
> node0_size
) {
2099 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2104 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2105 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2107 /* Set up Interrupt Controller before we create the VCPUs */
2108 xics_system_init(machine
, XICS_IRQS_SPAPR
, &error_fatal
);
2110 /* Set up containers for ibm,client-set-architecture negotiated options */
2111 spapr
->ov5
= spapr_ovec_new();
2112 spapr
->ov5_cas
= spapr_ovec_new();
2114 if (smc
->dr_lmb_enabled
) {
2115 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2116 spapr_validate_node_memory(machine
, &error_fatal
);
2119 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2120 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2121 /* KVM and TCG always allow GTSE with radix... */
2122 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2124 /* ... but not with hash (currently). */
2126 /* advertise support for dedicated HP event source to guests */
2127 if (spapr
->use_hotplug_event_source
) {
2128 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2132 if (machine
->cpu_model
== NULL
) {
2133 machine
->cpu_model
= kvm_enabled() ? "host" : smc
->tcg_default_cpu
;
2136 ppc_cpu_parse_features(machine
->cpu_model
);
2138 spapr_init_cpus(spapr
);
2140 if (kvm_enabled()) {
2141 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2142 kvmppc_enable_logical_ci_hcalls();
2143 kvmppc_enable_set_mode_hcall();
2145 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2146 kvmppc_enable_clear_ref_mod_hcalls();
2150 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2152 memory_region_add_subregion(sysmem
, 0, ram
);
2154 if (rma_alloc_size
&& rma
) {
2155 rma_region
= g_new(MemoryRegion
, 1);
2156 memory_region_init_ram_ptr(rma_region
, NULL
, "ppc_spapr.rma",
2157 rma_alloc_size
, rma
);
2158 vmstate_register_ram_global(rma_region
);
2159 memory_region_add_subregion(sysmem
, 0, rma_region
);
2162 /* initialize hotplug memory address space */
2163 if (machine
->ram_size
< machine
->maxram_size
) {
2164 ram_addr_t hotplug_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2166 * Limit the number of hotpluggable memory slots to half the number
2167 * slots that KVM supports, leaving the other half for PCI and other
2168 * devices. However ensure that number of slots doesn't drop below 32.
2170 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2171 SPAPR_MAX_RAM_SLOTS
;
2173 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2174 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2176 if (machine
->ram_slots
> max_memslots
) {
2177 error_report("Specified number of memory slots %"
2178 PRIu64
" exceeds max supported %d",
2179 machine
->ram_slots
, max_memslots
);
2183 spapr
->hotplug_memory
.base
= ROUND_UP(machine
->ram_size
,
2184 SPAPR_HOTPLUG_MEM_ALIGN
);
2185 memory_region_init(&spapr
->hotplug_memory
.mr
, OBJECT(spapr
),
2186 "hotplug-memory", hotplug_mem_size
);
2187 memory_region_add_subregion(sysmem
, spapr
->hotplug_memory
.base
,
2188 &spapr
->hotplug_memory
.mr
);
2191 if (smc
->dr_lmb_enabled
) {
2192 spapr_create_lmb_dr_connectors(spapr
);
2195 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2197 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2200 spapr
->rtas_size
= get_image_size(filename
);
2201 if (spapr
->rtas_size
< 0) {
2202 error_report("Could not get size of LPAR rtas '%s'", filename
);
2205 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2206 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2207 error_report("Could not load LPAR rtas '%s'", filename
);
2210 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2211 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2212 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2217 /* Set up RTAS event infrastructure */
2218 spapr_events_init(spapr
);
2220 /* Set up the RTC RTAS interfaces */
2221 spapr_rtc_create(spapr
);
2223 /* Set up VIO bus */
2224 spapr
->vio_bus
= spapr_vio_bus_init();
2226 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
2227 if (serial_hds
[i
]) {
2228 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
2232 /* We always have at least the nvram device on VIO */
2233 spapr_create_nvram(spapr
);
2236 spapr_pci_rtas_init();
2238 phb
= spapr_create_phb(spapr
, 0);
2240 for (i
= 0; i
< nb_nics
; i
++) {
2241 NICInfo
*nd
= &nd_table
[i
];
2244 nd
->model
= g_strdup("ibmveth");
2247 if (strcmp(nd
->model
, "ibmveth") == 0) {
2248 spapr_vlan_create(spapr
->vio_bus
, nd
);
2250 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2254 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2255 spapr_vscsi_create(spapr
->vio_bus
);
2259 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2260 spapr
->has_graphics
= true;
2261 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2265 if (smc
->use_ohci_by_default
) {
2266 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2268 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2271 if (spapr
->has_graphics
) {
2272 USBBus
*usb_bus
= usb_bus_find(-1);
2274 usb_create_simple(usb_bus
, "usb-kbd");
2275 usb_create_simple(usb_bus
, "usb-mouse");
2279 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
2281 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2286 if (kernel_filename
) {
2287 uint64_t lowaddr
= 0;
2289 spapr
->kernel_size
= load_elf(kernel_filename
, translate_kernel_address
,
2290 NULL
, NULL
, &lowaddr
, NULL
, 1,
2291 PPC_ELF_MACHINE
, 0, 0);
2292 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2293 spapr
->kernel_size
= load_elf(kernel_filename
,
2294 translate_kernel_address
, NULL
, NULL
,
2295 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
2297 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2299 if (spapr
->kernel_size
< 0) {
2300 error_report("error loading %s: %s", kernel_filename
,
2301 load_elf_strerror(spapr
->kernel_size
));
2306 if (initrd_filename
) {
2307 /* Try to locate the initrd in the gap between the kernel
2308 * and the firmware. Add a bit of space just in case
2310 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
2311 + 0x1ffff) & ~0xffff;
2312 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2315 - spapr
->initrd_base
);
2316 if (spapr
->initrd_size
< 0) {
2317 error_report("could not load initial ram disk '%s'",
2324 if (bios_name
== NULL
) {
2325 bios_name
= FW_FILE_NAME
;
2327 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2329 error_report("Could not find LPAR firmware '%s'", bios_name
);
2332 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2334 error_report("Could not load LPAR firmware '%s'", filename
);
2339 /* FIXME: Should register things through the MachineState's qdev
2340 * interface, this is a legacy from the sPAPREnvironment structure
2341 * which predated MachineState but had a similar function */
2342 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
2343 register_savevm_live(NULL
, "spapr/htab", -1, 1,
2344 &savevm_htab_handlers
, spapr
);
2347 QTAILQ_INIT(&spapr
->ccs_list
);
2348 qemu_register_reset(spapr_ccs_reset_hook
, spapr
);
2350 qemu_register_boot_set(spapr_boot_set
, spapr
);
2352 if (kvm_enabled()) {
2353 /* to stop and start vmclock */
2354 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
2357 kvmppc_spapr_enable_inkernel_multitce();
2361 static int spapr_kvm_type(const char *vm_type
)
2367 if (!strcmp(vm_type
, "HV")) {
2371 if (!strcmp(vm_type
, "PR")) {
2375 error_report("Unknown kvm-type specified '%s'", vm_type
);
2380 * Implementation of an interface to adjust firmware path
2381 * for the bootindex property handling.
2383 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
2386 #define CAST(type, obj, name) \
2387 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2388 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
2389 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2392 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
2393 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
2394 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
2398 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2399 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2400 * in the top 16 bits of the 64-bit LUN
2402 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
2403 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2404 (uint64_t)id
<< 48);
2405 } else if (virtio
) {
2407 * We use SRP luns of the form 01000000 | (target << 8) | lun
2408 * in the top 32 bits of the 64-bit LUN
2409 * Note: the quote above is from SLOF and it is wrong,
2410 * the actual binding is:
2411 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2413 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
2414 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2415 (uint64_t)id
<< 32);
2418 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2419 * in the top 32 bits of the 64-bit LUN
2421 unsigned usb_port
= atoi(usb
->port
->path
);
2422 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
2423 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2424 (uint64_t)id
<< 32);
2429 * SLOF probes the USB devices, and if it recognizes that the device is a
2430 * storage device, it changes its name to "storage" instead of "usb-host",
2431 * and additionally adds a child node for the SCSI LUN, so the correct
2432 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2434 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
2435 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
2436 if (usb_host_dev_is_scsi_storage(usbdev
)) {
2437 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
2442 /* Replace "pci" with "pci@800000020000000" */
2443 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
2449 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
2451 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2453 return g_strdup(spapr
->kvm_type
);
2456 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
2458 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2460 g_free(spapr
->kvm_type
);
2461 spapr
->kvm_type
= g_strdup(value
);
2464 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
2466 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2468 return spapr
->use_hotplug_event_source
;
2471 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
2474 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2476 spapr
->use_hotplug_event_source
= value
;
2479 static void spapr_machine_initfn(Object
*obj
)
2481 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2483 spapr
->htab_fd
= -1;
2484 spapr
->use_hotplug_event_source
= true;
2485 object_property_add_str(obj
, "kvm-type",
2486 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
2487 object_property_set_description(obj
, "kvm-type",
2488 "Specifies the KVM virtualization mode (HV, PR)",
2490 object_property_add_bool(obj
, "modern-hotplug-events",
2491 spapr_get_modern_hotplug_events
,
2492 spapr_set_modern_hotplug_events
,
2494 object_property_set_description(obj
, "modern-hotplug-events",
2495 "Use dedicated hotplug event mechanism in"
2496 " place of standard EPOW events when possible"
2497 " (required for memory hot-unplug support)",
2501 static void spapr_machine_finalizefn(Object
*obj
)
2503 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2505 g_free(spapr
->kvm_type
);
2508 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
2510 cpu_synchronize_state(cs
);
2511 ppc_cpu_do_system_reset(cs
);
2514 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2519 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
2523 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
2524 uint32_t node
, bool dedicated_hp_event_source
,
2527 sPAPRDRConnector
*drc
;
2528 sPAPRDRConnectorClass
*drck
;
2529 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
2530 int i
, fdt_offset
, fdt_size
;
2532 uint64_t addr
= addr_start
;
2534 for (i
= 0; i
< nr_lmbs
; i
++) {
2535 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2536 addr
/SPAPR_MEMORY_BLOCK_SIZE
);
2539 fdt
= create_device_tree(&fdt_size
);
2540 fdt_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
2541 SPAPR_MEMORY_BLOCK_SIZE
);
2543 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2544 drck
->attach(drc
, dev
, fdt
, fdt_offset
, !dev
->hotplugged
, errp
);
2545 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
2546 if (!dev
->hotplugged
) {
2547 /* guests expect coldplugged LMBs to be pre-allocated */
2548 drck
->set_allocation_state(drc
, SPAPR_DR_ALLOCATION_STATE_USABLE
);
2549 drck
->set_isolation_state(drc
, SPAPR_DR_ISOLATION_STATE_UNISOLATED
);
2552 /* send hotplug notification to the
2553 * guest only in case of hotplugged memory
2555 if (dev
->hotplugged
) {
2556 if (dedicated_hp_event_source
) {
2557 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2558 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
2559 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2560 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2562 drck
->get_index(drc
));
2564 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2570 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2571 uint32_t node
, Error
**errp
)
2573 Error
*local_err
= NULL
;
2574 sPAPRMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
2575 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
2576 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
2577 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
);
2578 uint64_t align
= memory_region_get_alignment(mr
);
2579 uint64_t size
= memory_region_size(mr
);
2583 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2584 error_setg(&local_err
, "Hotplugged memory size must be a multiple of "
2585 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE
/M_BYTE
);
2589 mem_dev
= object_property_get_str(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
, NULL
);
2590 if (mem_dev
&& !kvmppc_is_mem_backend_page_size_ok(mem_dev
)) {
2591 error_setg(&local_err
, "Memory backend has bad page size. "
2592 "Use 'memory-backend-file' with correct mem-path.");
2596 pc_dimm_memory_plug(dev
, &ms
->hotplug_memory
, mr
, align
, &local_err
);
2601 addr
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
, &local_err
);
2603 pc_dimm_memory_unplug(dev
, &ms
->hotplug_memory
, mr
);
2607 spapr_add_lmbs(dev
, addr
, size
, node
,
2608 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
2612 error_propagate(errp
, local_err
);
2615 typedef struct sPAPRDIMMState
{
2619 static void spapr_lmb_release(DeviceState
*dev
, void *opaque
)
2621 sPAPRDIMMState
*ds
= (sPAPRDIMMState
*)opaque
;
2622 HotplugHandler
*hotplug_ctrl
;
2624 if (--ds
->nr_lmbs
) {
2631 * Now that all the LMBs have been removed by the guest, call the
2632 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2634 hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
2635 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
2638 static void spapr_del_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
2641 sPAPRDRConnector
*drc
;
2642 sPAPRDRConnectorClass
*drck
;
2643 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
2645 sPAPRDIMMState
*ds
= g_malloc0(sizeof(sPAPRDIMMState
));
2646 uint64_t addr
= addr_start
;
2648 ds
->nr_lmbs
= nr_lmbs
;
2649 for (i
= 0; i
< nr_lmbs
; i
++) {
2650 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2651 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
2654 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2655 drck
->detach(drc
, dev
, spapr_lmb_release
, ds
, errp
);
2656 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
2659 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2660 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
2661 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2662 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2664 drck
->get_index(drc
));
2667 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2670 sPAPRMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
2671 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
2672 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
2673 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
);
2675 pc_dimm_memory_unplug(dev
, &ms
->hotplug_memory
, mr
);
2676 object_unparent(OBJECT(dev
));
2679 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
2680 DeviceState
*dev
, Error
**errp
)
2682 Error
*local_err
= NULL
;
2683 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
2684 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
2685 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
);
2686 uint64_t size
= memory_region_size(mr
);
2689 addr
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
, &local_err
);
2694 spapr_del_lmbs(dev
, addr
, size
, &error_abort
);
2696 error_propagate(errp
, local_err
);
2699 void *spapr_populate_hotplug_cpu_dt(CPUState
*cs
, int *fdt_offset
,
2700 sPAPRMachineState
*spapr
)
2702 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2703 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
2704 int id
= ppc_get_vcpu_dt_id(cpu
);
2706 int offset
, fdt_size
;
2709 fdt
= create_device_tree(&fdt_size
);
2710 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
2711 offset
= fdt_add_subnode(fdt
, 0, nodename
);
2713 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
2716 *fdt_offset
= offset
;
2720 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2723 MachineState
*ms
= MACHINE(qdev_get_machine());
2724 CPUCore
*cc
= CPU_CORE(dev
);
2725 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
2728 core_slot
->cpu
= NULL
;
2729 object_unparent(OBJECT(dev
));
2732 static void spapr_core_release(DeviceState
*dev
, void *opaque
)
2734 HotplugHandler
*hotplug_ctrl
;
2736 hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
2737 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
2741 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2745 sPAPRDRConnector
*drc
;
2746 sPAPRDRConnectorClass
*drck
;
2747 Error
*local_err
= NULL
;
2748 CPUCore
*cc
= CPU_CORE(dev
);
2749 int smt
= kvmppc_smt_threads();
2751 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
2752 error_setg(errp
, "Unable to find CPU core with core-id: %d",
2757 error_setg(errp
, "Boot CPU core may not be unplugged");
2761 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU
, index
* smt
);
2764 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2765 drck
->detach(drc
, dev
, spapr_core_release
, NULL
, &local_err
);
2767 error_propagate(errp
, local_err
);
2771 spapr_hotplug_req_remove_by_index(drc
);
2774 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2777 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
2778 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
2779 sPAPRCPUCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
2780 CPUCore
*cc
= CPU_CORE(dev
);
2781 CPUState
*cs
= CPU(core
->threads
);
2782 sPAPRDRConnector
*drc
;
2783 Error
*local_err
= NULL
;
2786 int smt
= kvmppc_smt_threads();
2787 CPUArchId
*core_slot
;
2790 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
2792 error_setg(errp
, "Unable to find CPU core with core-id: %d",
2796 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU
, index
* smt
);
2798 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
2801 * Setup CPU DT entries only for hotplugged CPUs. For boot time or
2802 * coldplugged CPUs DT entries are setup in spapr_build_fdt().
2804 if (dev
->hotplugged
) {
2805 fdt
= spapr_populate_hotplug_cpu_dt(cs
, &fdt_offset
, spapr
);
2809 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2810 drck
->attach(drc
, dev
, fdt
, fdt_offset
, !dev
->hotplugged
, &local_err
);
2813 error_propagate(errp
, local_err
);
2818 if (dev
->hotplugged
) {
2820 * Send hotplug notification interrupt to the guest only in case
2821 * of hotplugged CPUs.
2823 spapr_hotplug_req_add_by_index(drc
);
2826 * Set the right DRC states for cold plugged CPU.
2829 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2830 drck
->set_allocation_state(drc
, SPAPR_DR_ALLOCATION_STATE_USABLE
);
2831 drck
->set_isolation_state(drc
, SPAPR_DR_ISOLATION_STATE_UNISOLATED
);
2834 core_slot
->cpu
= OBJECT(dev
);
2837 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2840 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
2841 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
2842 Error
*local_err
= NULL
;
2843 CPUCore
*cc
= CPU_CORE(dev
);
2844 sPAPRCPUCore
*sc
= SPAPR_CPU_CORE(dev
);
2845 char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_model
);
2846 const char *type
= object_get_typename(OBJECT(dev
));
2847 CPUArchId
*core_slot
;
2851 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
2852 error_setg(&local_err
, "CPU hotplug not supported for this machine");
2856 if (strcmp(base_core_type
, type
)) {
2857 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
2861 if (cc
->core_id
% smp_threads
) {
2862 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
2867 * In general we should have homogeneous threads-per-core, but old
2868 * (pre hotplug support) machine types allow the last core to have
2869 * reduced threads as a compatibility hack for when we allowed
2870 * total vcpus not a multiple of threads-per-core.
2872 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
2873 error_setg(errp
, "invalid nr-threads %d, must be %d",
2874 cc
->nr_threads
, smp_threads
);
2878 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
2880 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
2884 if (core_slot
->cpu
) {
2885 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
2889 node_id
= core_slot
->props
.node_id
;
2890 if (!core_slot
->props
.has_node_id
) {
2891 /* by default CPUState::numa_node was 0 if it's not set via CLI
2892 * keep it this way for now but in future we probably should
2893 * refuse to start up with incomplete numa mapping */
2896 if (sc
->node_id
== CPU_UNSET_NUMA_NODE_ID
) {
2897 sc
->node_id
= node_id
;
2898 } else if (sc
->node_id
!= node_id
) {
2899 error_setg(&local_err
, "node-id %d must match numa node specified"
2900 "with -numa option for cpu-index %d", sc
->node_id
, cc
->core_id
);
2905 g_free(base_core_type
);
2906 error_propagate(errp
, local_err
);
2909 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
2910 DeviceState
*dev
, Error
**errp
)
2912 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2914 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2917 if (!smc
->dr_lmb_enabled
) {
2918 error_setg(errp
, "Memory hotplug not supported for this machine");
2921 node
= object_property_get_int(OBJECT(dev
), PC_DIMM_NODE_PROP
, errp
);
2925 if (node
< 0 || node
>= MAX_NODES
) {
2926 error_setg(errp
, "Invaild node %d", node
);
2931 * Currently PowerPC kernel doesn't allow hot-adding memory to
2932 * memory-less node, but instead will silently add the memory
2933 * to the first node that has some memory. This causes two
2934 * unexpected behaviours for the user.
2936 * - Memory gets hotplugged to a different node than what the user
2938 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2939 * to memory-less node, a reboot will set things accordingly
2940 * and the previously hotplugged memory now ends in the right node.
2941 * This appears as if some memory moved from one node to another.
2943 * So until kernel starts supporting memory hotplug to memory-less
2944 * nodes, just prevent such attempts upfront in QEMU.
2946 if (nb_numa_nodes
&& !numa_info
[node
].node_mem
) {
2947 error_setg(errp
, "Can't hotplug memory to memory-less node %d",
2952 spapr_memory_plug(hotplug_dev
, dev
, node
, errp
);
2953 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
2954 spapr_core_plug(hotplug_dev
, dev
, errp
);
2958 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
2959 DeviceState
*dev
, Error
**errp
)
2961 sPAPRMachineState
*sms
= SPAPR_MACHINE(qdev_get_machine());
2962 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
2964 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2965 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
2966 spapr_memory_unplug(hotplug_dev
, dev
, errp
);
2968 error_setg(errp
, "Memory hot unplug not supported for this guest");
2970 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
2971 if (!mc
->has_hotpluggable_cpus
) {
2972 error_setg(errp
, "CPU hot unplug not supported on this machine");
2975 spapr_core_unplug(hotplug_dev
, dev
, errp
);
2979 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
2980 DeviceState
*dev
, Error
**errp
)
2982 sPAPRMachineState
*sms
= SPAPR_MACHINE(qdev_get_machine());
2983 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
2985 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2986 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
2987 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
2989 /* NOTE: this means there is a window after guest reset, prior to
2990 * CAS negotiation, where unplug requests will fail due to the
2991 * capability not being detected yet. This is a bit different than
2992 * the case with PCI unplug, where the events will be queued and
2993 * eventually handled by the guest after boot
2995 error_setg(errp
, "Memory hot unplug not supported for this guest");
2997 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
2998 if (!mc
->has_hotpluggable_cpus
) {
2999 error_setg(errp
, "CPU hot unplug not supported on this machine");
3002 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
3006 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
3007 DeviceState
*dev
, Error
**errp
)
3009 if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3010 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
3014 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
3017 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
3018 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3019 return HOTPLUG_HANDLER(machine
);
3024 static CpuInstanceProperties
3025 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
3027 CPUArchId
*core_slot
;
3028 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3030 /* make sure possible_cpu are intialized */
3031 mc
->possible_cpu_arch_ids(machine
);
3032 /* get CPU core slot containing thread that matches cpu_index */
3033 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
3035 return core_slot
->props
;
3038 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
3041 int spapr_max_cores
= max_cpus
/ smp_threads
;
3042 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3044 if (!mc
->has_hotpluggable_cpus
) {
3045 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
3047 if (machine
->possible_cpus
) {
3048 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
3049 return machine
->possible_cpus
;
3052 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
3053 sizeof(CPUArchId
) * spapr_max_cores
);
3054 machine
->possible_cpus
->len
= spapr_max_cores
;
3055 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
3056 int core_id
= i
* smp_threads
;
3058 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
3059 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
3060 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
3061 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
3063 /* default distribution of CPUs over NUMA nodes */
3064 if (nb_numa_nodes
) {
3065 /* preset values but do not enable them i.e. 'has_node_id = false',
3066 * numa init code will enable them later if manual mapping wasn't
3068 machine
->possible_cpus
->cpus
[i
].props
.node_id
=
3069 core_id
/ smp_threads
/ smp_cores
% nb_numa_nodes
;
3072 return machine
->possible_cpus
;
3075 static void spapr_phb_placement(sPAPRMachineState
*spapr
, uint32_t index
,
3076 uint64_t *buid
, hwaddr
*pio
,
3077 hwaddr
*mmio32
, hwaddr
*mmio64
,
3078 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
3081 * New-style PHB window placement.
3083 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3084 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3087 * Some guest kernels can't work with MMIO windows above 1<<46
3088 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3090 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3091 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3092 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3093 * 1TiB 64-bit MMIO windows for each PHB.
3095 const uint64_t base_buid
= 0x800000020000000ULL
;
3096 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3097 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3100 /* Sanity check natural alignments */
3101 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3102 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3103 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
3104 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
3105 /* Sanity check bounds */
3106 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
3107 SPAPR_PCI_MEM32_WIN_SIZE
);
3108 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
3109 SPAPR_PCI_MEM64_WIN_SIZE
);
3111 if (index
>= SPAPR_MAX_PHBS
) {
3112 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
3113 SPAPR_MAX_PHBS
- 1);
3117 *buid
= base_buid
+ index
;
3118 for (i
= 0; i
< n_dma
; ++i
) {
3119 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
3122 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
3123 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
3124 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
3127 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
3129 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3131 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
3134 static void spapr_ics_resend(XICSFabric
*dev
)
3136 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3138 ics_resend(spapr
->ics
);
3141 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int cpu_dt_id
)
3143 PowerPCCPU
*cpu
= ppc_get_vcpu_by_dt_id(cpu_dt_id
);
3145 return cpu
? ICP(cpu
->intc
) : NULL
;
3148 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
3151 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3155 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3157 icp_pic_print_info(ICP(cpu
->intc
), mon
);
3160 ics_pic_print_info(spapr
->ics
, mon
);
3163 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
3165 MachineClass
*mc
= MACHINE_CLASS(oc
);
3166 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
3167 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
3168 NMIClass
*nc
= NMI_CLASS(oc
);
3169 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
3170 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
3171 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
3172 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
3174 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
3177 * We set up the default / latest behaviour here. The class_init
3178 * functions for the specific versioned machine types can override
3179 * these details for backwards compatibility
3181 mc
->init
= ppc_spapr_init
;
3182 mc
->reset
= ppc_spapr_reset
;
3183 mc
->block_default_type
= IF_SCSI
;
3184 mc
->max_cpus
= 1024;
3185 mc
->no_parallel
= 1;
3186 mc
->default_boot_order
= "";
3187 mc
->default_ram_size
= 512 * M_BYTE
;
3188 mc
->kvm_type
= spapr_kvm_type
;
3189 mc
->has_dynamic_sysbus
= true;
3190 mc
->pci_allow_0_address
= true;
3191 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
3192 hc
->pre_plug
= spapr_machine_device_pre_plug
;
3193 hc
->plug
= spapr_machine_device_plug
;
3194 hc
->unplug
= spapr_machine_device_unplug
;
3195 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
3196 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
3197 hc
->unplug_request
= spapr_machine_device_unplug_request
;
3199 smc
->dr_lmb_enabled
= true;
3200 smc
->tcg_default_cpu
= "POWER8";
3201 mc
->has_hotpluggable_cpus
= true;
3202 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
3203 nc
->nmi_monitor_handler
= spapr_nmi
;
3204 smc
->phb_placement
= spapr_phb_placement
;
3205 vhc
->hypercall
= emulate_spapr_hypercall
;
3206 vhc
->hpt_mask
= spapr_hpt_mask
;
3207 vhc
->map_hptes
= spapr_map_hptes
;
3208 vhc
->unmap_hptes
= spapr_unmap_hptes
;
3209 vhc
->store_hpte
= spapr_store_hpte
;
3210 vhc
->get_patbe
= spapr_get_patbe
;
3211 xic
->ics_get
= spapr_ics_get
;
3212 xic
->ics_resend
= spapr_ics_resend
;
3213 xic
->icp_get
= spapr_icp_get
;
3214 ispc
->print_info
= spapr_pic_print_info
;
3215 /* Force NUMA node memory size to be a multiple of
3216 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3217 * in which LMBs are represented and hot-added
3219 mc
->numa_mem_align_shift
= 28;
3222 static const TypeInfo spapr_machine_info
= {
3223 .name
= TYPE_SPAPR_MACHINE
,
3224 .parent
= TYPE_MACHINE
,
3226 .instance_size
= sizeof(sPAPRMachineState
),
3227 .instance_init
= spapr_machine_initfn
,
3228 .instance_finalize
= spapr_machine_finalizefn
,
3229 .class_size
= sizeof(sPAPRMachineClass
),
3230 .class_init
= spapr_machine_class_init
,
3231 .interfaces
= (InterfaceInfo
[]) {
3232 { TYPE_FW_PATH_PROVIDER
},
3234 { TYPE_HOTPLUG_HANDLER
},
3235 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
3236 { TYPE_XICS_FABRIC
},
3237 { TYPE_INTERRUPT_STATS_PROVIDER
},
3242 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3243 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3246 MachineClass *mc = MACHINE_CLASS(oc); \
3247 spapr_machine_##suffix##_class_options(mc); \
3249 mc->alias = "pseries"; \
3250 mc->is_default = 1; \
3253 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3255 MachineState *machine = MACHINE(obj); \
3256 spapr_machine_##suffix##_instance_options(machine); \
3258 static const TypeInfo spapr_machine_##suffix##_info = { \
3259 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3260 .parent = TYPE_SPAPR_MACHINE, \
3261 .class_init = spapr_machine_##suffix##_class_init, \
3262 .instance_init = spapr_machine_##suffix##_instance_init, \
3264 static void spapr_machine_register_##suffix(void) \
3266 type_register(&spapr_machine_##suffix##_info); \
3268 type_init(spapr_machine_register_##suffix)
3273 static void spapr_machine_2_10_instance_options(MachineState
*machine
)
3277 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
3279 /* Defaults for the latest behaviour inherited from the base class */
3282 DEFINE_SPAPR_MACHINE(2_10
, "2.10", true);
3287 #define SPAPR_COMPAT_2_9 \
3290 static void spapr_machine_2_9_instance_options(MachineState
*machine
)
3292 spapr_machine_2_10_instance_options(machine
);
3295 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
3297 spapr_machine_2_10_class_options(mc
);
3298 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_9
);
3299 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
3302 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
3307 #define SPAPR_COMPAT_2_8 \
3310 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3311 .property = "pcie-extended-configuration-space", \
3315 static void spapr_machine_2_8_instance_options(MachineState
*machine
)
3317 spapr_machine_2_9_instance_options(machine
);
3320 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
3322 spapr_machine_2_9_class_options(mc
);
3323 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_8
);
3324 mc
->numa_mem_align_shift
= 23;
3327 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
3332 #define SPAPR_COMPAT_2_7 \
3335 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3336 .property = "mem_win_size", \
3337 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3340 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3341 .property = "mem64_win_size", \
3345 .driver = TYPE_POWERPC_CPU, \
3346 .property = "pre-2.8-migration", \
3350 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3351 .property = "pre-2.8-migration", \
3355 static void phb_placement_2_7(sPAPRMachineState
*spapr
, uint32_t index
,
3356 uint64_t *buid
, hwaddr
*pio
,
3357 hwaddr
*mmio32
, hwaddr
*mmio64
,
3358 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
3360 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3361 const uint64_t base_buid
= 0x800000020000000ULL
;
3362 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
3363 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
3364 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
3365 const uint32_t max_index
= 255;
3366 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
3368 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
3369 hwaddr phb0_base
, phb_base
;
3372 /* Do we have hotpluggable memory? */
3373 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
3374 /* Can't just use maxram_size, because there may be an
3375 * alignment gap between normal and hotpluggable memory
3377 ram_top
= spapr
->hotplug_memory
.base
+
3378 memory_region_size(&spapr
->hotplug_memory
.mr
);
3381 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
3383 if (index
> max_index
) {
3384 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
3389 *buid
= base_buid
+ index
;
3390 for (i
= 0; i
< n_dma
; ++i
) {
3391 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
3394 phb_base
= phb0_base
+ index
* phb_spacing
;
3395 *pio
= phb_base
+ pio_offset
;
3396 *mmio32
= phb_base
+ mmio_offset
;
3398 * We don't set the 64-bit MMIO window, relying on the PHB's
3399 * fallback behaviour of automatically splitting a large "32-bit"
3400 * window into contiguous 32-bit and 64-bit windows
3404 static void spapr_machine_2_7_instance_options(MachineState
*machine
)
3406 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
3408 spapr_machine_2_8_instance_options(machine
);
3409 spapr
->use_hotplug_event_source
= false;
3412 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
3414 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3416 spapr_machine_2_8_class_options(mc
);
3417 smc
->tcg_default_cpu
= "POWER7";
3418 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_7
);
3419 smc
->phb_placement
= phb_placement_2_7
;
3422 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
3427 #define SPAPR_COMPAT_2_6 \
3430 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3432 .value = stringify(off),\
3435 static void spapr_machine_2_6_instance_options(MachineState
*machine
)
3437 spapr_machine_2_7_instance_options(machine
);
3440 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
3442 spapr_machine_2_7_class_options(mc
);
3443 mc
->has_hotpluggable_cpus
= false;
3444 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_6
);
3447 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
3452 #define SPAPR_COMPAT_2_5 \
3455 .driver = "spapr-vlan", \
3456 .property = "use-rx-buffer-pools", \
3460 static void spapr_machine_2_5_instance_options(MachineState
*machine
)
3462 spapr_machine_2_6_instance_options(machine
);
3465 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
3467 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3469 spapr_machine_2_6_class_options(mc
);
3470 smc
->use_ohci_by_default
= true;
3471 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_5
);
3474 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
3479 #define SPAPR_COMPAT_2_4 \
3482 static void spapr_machine_2_4_instance_options(MachineState
*machine
)
3484 spapr_machine_2_5_instance_options(machine
);
3487 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
3489 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3491 spapr_machine_2_5_class_options(mc
);
3492 smc
->dr_lmb_enabled
= false;
3493 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_4
);
3496 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
3501 #define SPAPR_COMPAT_2_3 \
3504 .driver = "spapr-pci-host-bridge",\
3505 .property = "dynamic-reconfiguration",\
3509 static void spapr_machine_2_3_instance_options(MachineState
*machine
)
3511 spapr_machine_2_4_instance_options(machine
);
3512 savevm_skip_section_footers();
3513 global_state_set_optional();
3514 savevm_skip_configuration();
3517 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
3519 spapr_machine_2_4_class_options(mc
);
3520 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_3
);
3522 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
3528 #define SPAPR_COMPAT_2_2 \
3531 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3532 .property = "mem_win_size",\
3533 .value = "0x20000000",\
3536 static void spapr_machine_2_2_instance_options(MachineState
*machine
)
3538 spapr_machine_2_3_instance_options(machine
);
3539 machine
->suppress_vmdesc
= true;
3542 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
3544 spapr_machine_2_3_class_options(mc
);
3545 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_2
);
3547 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
3552 #define SPAPR_COMPAT_2_1 \
3555 static void spapr_machine_2_1_instance_options(MachineState
*machine
)
3557 spapr_machine_2_2_instance_options(machine
);
3560 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
3562 spapr_machine_2_2_class_options(mc
);
3563 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_1
);
3565 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
3567 static void spapr_machine_register_types(void)
3569 type_register_static(&spapr_machine_info
);
3572 type_init(spapr_machine_register_types
)