2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qemu/datadir.h"
30 #include "qapi/error.h"
31 #include "qapi/qapi-events-machine.h"
32 #include "qapi/visitor.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/hostmem.h"
35 #include "sysemu/numa.h"
36 #include "sysemu/qtest.h"
37 #include "sysemu/reset.h"
38 #include "sysemu/runstate.h"
40 #include "hw/fw-path-provider.h"
43 #include "sysemu/device_tree.h"
44 #include "sysemu/cpus.h"
45 #include "sysemu/hw_accel.h"
47 #include "migration/misc.h"
48 #include "migration/qemu-file-types.h"
49 #include "migration/global_state.h"
50 #include "migration/register.h"
51 #include "migration/blocker.h"
52 #include "mmu-hash64.h"
53 #include "mmu-book3s-v3.h"
54 #include "cpu-models.h"
55 #include "hw/core/cpu.h"
57 #include "hw/ppc/ppc.h"
58 #include "hw/loader.h"
60 #include "hw/ppc/fdt.h"
61 #include "hw/ppc/spapr.h"
62 #include "hw/ppc/spapr_vio.h"
63 #include "hw/qdev-properties.h"
64 #include "hw/pci-host/spapr.h"
65 #include "hw/pci/msi.h"
67 #include "hw/pci/pci.h"
68 #include "hw/scsi/scsi.h"
69 #include "hw/virtio/virtio-scsi.h"
70 #include "hw/virtio/vhost-scsi-common.h"
72 #include "exec/ram_addr.h"
74 #include "qemu/config-file.h"
75 #include "qemu/error-report.h"
78 #include "hw/intc/intc.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83 #include "hw/ppc/spapr_nvdimm.h"
84 #include "hw/ppc/spapr_numa.h"
85 #include "hw/ppc/pef.h"
87 #include "monitor/monitor.h"
91 /* SLOF memory layout:
93 * SLOF raw image loaded at 0, copies its romfs right below the flat
94 * device-tree, then position SLOF itself 31M below that
96 * So we set FW_OVERHEAD to 40MB which should account for all of that
99 * We load our kernel at 4M, leaving space for SLOF initial image
101 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */
102 #define FW_MAX_SIZE 0x400000
103 #define FW_FILE_NAME "slof.bin"
104 #define FW_FILE_NAME_VOF "vof.bin"
105 #define FW_OVERHEAD 0x2800000
106 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
108 #define MIN_RMA_SLOF (128 * MiB)
110 #define PHANDLE_INTC 0x00001111
112 /* These two functions implement the VCPU id numbering: one to compute them
113 * all and one to identify thread 0 of a VCORE. Any change to the first one
114 * is likely to have an impact on the second one, so let's keep them close.
116 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
118 MachineState
*ms
= MACHINE(spapr
);
119 unsigned int smp_threads
= ms
->smp
.threads
;
123 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
125 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
129 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
132 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
134 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
135 * and newer QEMUs don't even have them. In both cases, we don't want
136 * to send anything on the wire.
141 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
142 .name
= "icp/server",
144 .minimum_version_id
= 1,
145 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
146 .fields
= (VMStateField
[]) {
147 VMSTATE_UNUSED(4), /* uint32_t xirr */
148 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
149 VMSTATE_UNUSED(1), /* uint8_t mfrr */
150 VMSTATE_END_OF_LIST()
154 static void pre_2_10_vmstate_register_dummy_icp(int i
)
156 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
157 (void *)(uintptr_t) i
);
160 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
162 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
163 (void *)(uintptr_t) i
);
166 int spapr_max_server_number(SpaprMachineState
*spapr
)
168 MachineState
*ms
= MACHINE(spapr
);
171 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
174 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
178 uint32_t servers_prop
[smt_threads
];
179 uint32_t gservers_prop
[smt_threads
* 2];
180 int index
= spapr_get_vcpu_id(cpu
);
182 if (cpu
->compat_pvr
) {
183 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
189 /* Build interrupt servers and gservers properties */
190 for (i
= 0; i
< smt_threads
; i
++) {
191 servers_prop
[i
] = cpu_to_be32(index
+ i
);
192 /* Hack, direct the group queues back to cpu 0 */
193 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
194 gservers_prop
[i
*2 + 1] = 0;
196 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
197 servers_prop
, sizeof(servers_prop
));
201 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
202 gservers_prop
, sizeof(gservers_prop
));
207 static void spapr_dt_pa_features(SpaprMachineState
*spapr
,
209 void *fdt
, int offset
)
211 uint8_t pa_features_206
[] = { 6, 0,
212 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
213 uint8_t pa_features_207
[] = { 24, 0,
214 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
215 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
216 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
217 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
218 uint8_t pa_features_300
[] = { 66, 0,
219 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
220 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
221 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
223 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
225 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
226 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
227 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
228 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
229 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
230 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
231 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
232 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
234 /* 42: PM, 44: PC RA, 46: SC vec'd */
235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
236 /* 48: SIMD, 50: QP BFP, 52: String */
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
238 /* 54: DecFP, 56: DecI, 58: SHA */
239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
240 /* 60: NM atomic, 62: RNG */
241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
243 uint8_t *pa_features
= NULL
;
246 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
247 pa_features
= pa_features_206
;
248 pa_size
= sizeof(pa_features_206
);
250 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
251 pa_features
= pa_features_207
;
252 pa_size
= sizeof(pa_features_207
);
254 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
255 pa_features
= pa_features_300
;
256 pa_size
= sizeof(pa_features_300
);
262 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
264 * Note: we keep CI large pages off by default because a 64K capable
265 * guest provisioned with large pages might otherwise try to map a qemu
266 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
267 * even if that qemu runs on a 4k host.
268 * We dd this bit back here if we are confident this is not an issue
270 pa_features
[3] |= 0x20;
272 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
273 pa_features
[24] |= 0x80; /* Transactional memory support */
275 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
276 /* Workaround for broken kernels that attempt (guest) radix
277 * mode when they can't handle it, if they see the radix bit set
278 * in pa-features. So hide it from them. */
279 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
282 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
285 static hwaddr
spapr_node0_size(MachineState
*machine
)
287 if (machine
->numa_state
->num_nodes
) {
289 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
290 if (machine
->numa_state
->nodes
[i
].node_mem
) {
291 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
296 return machine
->ram_size
;
299 static void add_str(GString
*s
, const gchar
*s1
)
301 g_string_append_len(s
, s1
, strlen(s1
) + 1);
304 static int spapr_dt_memory_node(SpaprMachineState
*spapr
, void *fdt
, int nodeid
,
305 hwaddr start
, hwaddr size
)
308 uint64_t mem_reg_property
[2];
311 mem_reg_property
[0] = cpu_to_be64(start
);
312 mem_reg_property
[1] = cpu_to_be64(size
);
314 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
315 off
= fdt_add_subnode(fdt
, 0, mem_name
);
317 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
318 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
319 sizeof(mem_reg_property
))));
320 spapr_numa_write_associativity_dt(spapr
, fdt
, off
, nodeid
);
324 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
326 MemoryDeviceInfoList
*info
;
328 for (info
= list
; info
; info
= info
->next
) {
329 MemoryDeviceInfo
*value
= info
->value
;
331 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
332 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
334 if (addr
>= pcdimm_info
->addr
&&
335 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
336 return pcdimm_info
->node
;
344 struct sPAPRDrconfCellV2
{
352 typedef struct DrconfCellQueue
{
353 struct sPAPRDrconfCellV2 cell
;
354 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
357 static DrconfCellQueue
*
358 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
359 uint32_t drc_index
, uint32_t aa_index
,
362 DrconfCellQueue
*elem
;
364 elem
= g_malloc0(sizeof(*elem
));
365 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
366 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
367 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
368 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
369 elem
->cell
.flags
= cpu_to_be32(flags
);
374 static int spapr_dt_dynamic_memory_v2(SpaprMachineState
*spapr
, void *fdt
,
375 int offset
, MemoryDeviceInfoList
*dimms
)
377 MachineState
*machine
= MACHINE(spapr
);
378 uint8_t *int_buf
, *cur_index
;
380 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
381 uint64_t addr
, cur_addr
, size
;
382 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
383 uint64_t mem_end
= machine
->device_memory
->base
+
384 memory_region_size(&machine
->device_memory
->mr
);
385 uint32_t node
, buf_len
, nr_entries
= 0;
387 DrconfCellQueue
*elem
, *next
;
388 MemoryDeviceInfoList
*info
;
389 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
390 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
392 /* Entry to cover RAM and the gap area */
393 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
394 SPAPR_LMB_FLAGS_RESERVED
|
395 SPAPR_LMB_FLAGS_DRC_INVALID
);
396 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
399 cur_addr
= machine
->device_memory
->base
;
400 for (info
= dimms
; info
; info
= info
->next
) {
401 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
408 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
409 * area is marked hotpluggable in the next iteration for the bigger
410 * chunk including the NVDIMM occupied area.
412 if (info
->value
->type
== MEMORY_DEVICE_INFO_KIND_NVDIMM
)
415 /* Entry for hot-pluggable area */
416 if (cur_addr
< addr
) {
417 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
419 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
420 cur_addr
, spapr_drc_index(drc
), -1, 0);
421 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
426 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
428 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
429 spapr_drc_index(drc
), node
,
430 (SPAPR_LMB_FLAGS_ASSIGNED
|
431 SPAPR_LMB_FLAGS_HOTREMOVABLE
));
432 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
434 cur_addr
= addr
+ size
;
437 /* Entry for remaining hotpluggable area */
438 if (cur_addr
< mem_end
) {
439 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
441 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
442 cur_addr
, spapr_drc_index(drc
), -1, 0);
443 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
447 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
448 int_buf
= cur_index
= g_malloc0(buf_len
);
449 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
450 cur_index
+= sizeof(nr_entries
);
452 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
453 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
454 cur_index
+= sizeof(elem
->cell
);
455 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
459 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
467 static int spapr_dt_dynamic_memory(SpaprMachineState
*spapr
, void *fdt
,
468 int offset
, MemoryDeviceInfoList
*dimms
)
470 MachineState
*machine
= MACHINE(spapr
);
472 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
473 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
474 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
475 memory_region_size(&machine
->device_memory
->mr
)) /
477 uint32_t *int_buf
, *cur_index
, buf_len
;
480 * Allocate enough buffer size to fit in ibm,dynamic-memory
482 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
483 cur_index
= int_buf
= g_malloc0(buf_len
);
484 int_buf
[0] = cpu_to_be32(nr_lmbs
);
486 for (i
= 0; i
< nr_lmbs
; i
++) {
487 uint64_t addr
= i
* lmb_size
;
488 uint32_t *dynamic_memory
= cur_index
;
490 if (i
>= device_lmb_start
) {
493 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
496 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
497 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
498 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
499 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
500 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
501 if (memory_region_present(get_system_memory(), addr
)) {
502 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
504 dynamic_memory
[5] = cpu_to_be32(0);
508 * LMB information for RMA, boot time RAM and gap b/n RAM and
509 * device memory region -- all these are marked as reserved
510 * and as having no valid DRC.
512 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
513 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
514 dynamic_memory
[2] = cpu_to_be32(0);
515 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
516 dynamic_memory
[4] = cpu_to_be32(-1);
517 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
518 SPAPR_LMB_FLAGS_DRC_INVALID
);
521 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
523 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
532 * Adds ibm,dynamic-reconfiguration-memory node.
533 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
534 * of this device tree node.
536 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState
*spapr
,
539 MachineState
*machine
= MACHINE(spapr
);
541 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
542 uint32_t prop_lmb_size
[] = {cpu_to_be32(lmb_size
>> 32),
543 cpu_to_be32(lmb_size
& 0xffffffff)};
544 MemoryDeviceInfoList
*dimms
= NULL
;
547 * Don't create the node if there is no device memory
549 if (machine
->ram_size
== machine
->maxram_size
) {
553 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
555 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
556 sizeof(prop_lmb_size
));
561 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
566 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
571 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
572 dimms
= qmp_memory_device_list();
573 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
574 ret
= spapr_dt_dynamic_memory_v2(spapr
, fdt
, offset
, dimms
);
576 ret
= spapr_dt_dynamic_memory(spapr
, fdt
, offset
, dimms
);
578 qapi_free_MemoryDeviceInfoList(dimms
);
584 ret
= spapr_numa_write_assoc_lookup_arrays(spapr
, fdt
, offset
);
589 static int spapr_dt_memory(SpaprMachineState
*spapr
, void *fdt
)
591 MachineState
*machine
= MACHINE(spapr
);
592 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
593 hwaddr mem_start
, node_size
;
594 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
595 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
597 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
598 if (!nodes
[i
].node_mem
) {
601 if (mem_start
>= machine
->ram_size
) {
604 node_size
= nodes
[i
].node_mem
;
605 if (node_size
> machine
->ram_size
- mem_start
) {
606 node_size
= machine
->ram_size
- mem_start
;
610 /* spapr_machine_init() checks for rma_size <= node0_size
612 spapr_dt_memory_node(spapr
, fdt
, i
, 0, spapr
->rma_size
);
613 mem_start
+= spapr
->rma_size
;
614 node_size
-= spapr
->rma_size
;
616 for ( ; node_size
; ) {
617 hwaddr sizetmp
= pow2floor(node_size
);
619 /* mem_start != 0 here */
620 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
621 sizetmp
= 1ULL << ctzl(mem_start
);
624 spapr_dt_memory_node(spapr
, fdt
, i
, mem_start
, sizetmp
);
625 node_size
-= sizetmp
;
626 mem_start
+= sizetmp
;
630 /* Generate ibm,dynamic-reconfiguration-memory node if required */
631 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRCONF_MEMORY
)) {
634 g_assert(smc
->dr_lmb_enabled
);
635 ret
= spapr_dt_dynamic_reconfiguration_memory(spapr
, fdt
);
644 static void spapr_dt_cpu(CPUState
*cs
, void *fdt
, int offset
,
645 SpaprMachineState
*spapr
)
647 MachineState
*ms
= MACHINE(spapr
);
648 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
649 CPUPPCState
*env
= &cpu
->env
;
650 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
651 int index
= spapr_get_vcpu_id(cpu
);
652 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
653 0xffffffff, 0xffffffff};
654 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
655 : SPAPR_TIMEBASE_FREQ
;
656 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
657 uint32_t page_sizes_prop
[64];
658 size_t page_sizes_prop_size
;
659 unsigned int smp_threads
= ms
->smp
.threads
;
660 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
661 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
662 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
665 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
668 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
670 drc_index
= spapr_drc_index(drc
);
671 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
674 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
675 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
677 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
678 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
679 env
->dcache_line_size
)));
680 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
681 env
->dcache_line_size
)));
682 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
683 env
->icache_line_size
)));
684 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
685 env
->icache_line_size
)));
687 if (pcc
->l1_dcache_size
) {
688 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
689 pcc
->l1_dcache_size
)));
691 warn_report("Unknown L1 dcache size for cpu");
693 if (pcc
->l1_icache_size
) {
694 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
695 pcc
->l1_icache_size
)));
697 warn_report("Unknown L1 icache size for cpu");
700 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
701 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
702 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
703 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
704 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
705 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
707 if (ppc_has_spr(cpu
, SPR_PURR
)) {
708 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
710 if (ppc_has_spr(cpu
, SPR_PURR
)) {
711 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
714 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
715 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
716 segs
, sizeof(segs
))));
719 /* Advertise VSX (vector extensions) if available
720 * 1 == VMX / Altivec available
723 * Only CPUs for which we create core types in spapr_cpu_core.c
724 * are possible, and all of those have VMX */
725 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
726 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
728 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
731 /* Advertise DFP (Decimal Floating Point) if available
732 * 0 / no property == no DFP
733 * 1 == DFP available */
734 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
735 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
738 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
739 sizeof(page_sizes_prop
));
740 if (page_sizes_prop_size
) {
741 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
742 page_sizes_prop
, page_sizes_prop_size
)));
745 spapr_dt_pa_features(spapr
, cpu
, fdt
, offset
);
747 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
748 cs
->cpu_index
/ vcpus_per_socket
)));
750 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
751 pft_size_prop
, sizeof(pft_size_prop
))));
753 if (ms
->numa_state
->num_nodes
> 1) {
754 _FDT(spapr_numa_fixup_cpu_dt(spapr
, fdt
, offset
, cpu
));
757 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
759 if (pcc
->radix_page_info
) {
760 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
761 radix_AP_encodings
[i
] =
762 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
764 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
766 pcc
->radix_page_info
->count
*
767 sizeof(radix_AP_encodings
[0]))));
771 * We set this property to let the guest know that it can use the large
772 * decrementer and its width in bits.
774 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
775 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
776 pcc
->lrg_decr_bits
)));
779 static void spapr_dt_cpus(void *fdt
, SpaprMachineState
*spapr
)
787 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
789 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
790 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
793 * We walk the CPUs in reverse order to ensure that CPU DT nodes
794 * created by fdt_add_subnode() end up in the right order in FDT
795 * for the guest kernel the enumerate the CPUs correctly.
797 * The CPU list cannot be traversed in reverse order, so we need
803 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
807 for (i
= n_cpus
- 1; i
>= 0; i
--) {
808 CPUState
*cs
= rev
[i
];
809 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
810 int index
= spapr_get_vcpu_id(cpu
);
811 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
812 g_autofree
char *nodename
= NULL
;
815 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
819 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
820 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
822 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
828 static int spapr_dt_rng(void *fdt
)
833 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
837 ret
= fdt_setprop_string(fdt
, node
, "device_type",
838 "ibm,platform-facilities");
839 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
840 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
842 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
846 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
851 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
853 MachineState
*ms
= MACHINE(spapr
);
855 GString
*hypertas
= g_string_sized_new(256);
856 GString
*qemu_hypertas
= g_string_sized_new(256);
857 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
858 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
859 uint32_t lrdr_capacity
[] = {
860 cpu_to_be32(max_device_addr
>> 32),
861 cpu_to_be32(max_device_addr
& 0xffffffff),
862 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
>> 32),
863 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
& 0xffffffff),
864 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
867 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
870 add_str(hypertas
, "hcall-pft");
871 add_str(hypertas
, "hcall-term");
872 add_str(hypertas
, "hcall-dabr");
873 add_str(hypertas
, "hcall-interrupt");
874 add_str(hypertas
, "hcall-tce");
875 add_str(hypertas
, "hcall-vio");
876 add_str(hypertas
, "hcall-splpar");
877 add_str(hypertas
, "hcall-join");
878 add_str(hypertas
, "hcall-bulk");
879 add_str(hypertas
, "hcall-set-mode");
880 add_str(hypertas
, "hcall-sprg0");
881 add_str(hypertas
, "hcall-copy");
882 add_str(hypertas
, "hcall-debug");
883 add_str(hypertas
, "hcall-vphn");
884 add_str(qemu_hypertas
, "hcall-memop1");
886 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
887 add_str(hypertas
, "hcall-multi-tce");
890 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
891 add_str(hypertas
, "hcall-hpt-resize");
894 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
895 hypertas
->str
, hypertas
->len
));
896 g_string_free(hypertas
, TRUE
);
897 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
898 qemu_hypertas
->str
, qemu_hypertas
->len
));
899 g_string_free(qemu_hypertas
, TRUE
);
901 spapr_numa_write_rtas_dt(spapr
, fdt
, rtas
);
904 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
905 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
907 * The system reset requirements are driven by existing Linux and PowerVM
908 * implementation which (contrary to PAPR) saves r3 in the error log
909 * structure like machine check, so Linux expects to find the saved r3
910 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
911 * does not look at the error value).
913 * System reset interrupts are not subject to interlock like machine
914 * check, so this memory area could be corrupted if the sreset is
915 * interrupted by a machine check (or vice versa) if it was shared. To
916 * prevent this, system reset uses per-CPU areas for the sreset save
917 * area. A system reset that interrupts a system reset handler could
918 * still overwrite this area, but Linux doesn't try to recover in that
921 * The extra 8 bytes is required because Linux's FWNMI error log check
924 * RTAS_MIN_SIZE is required for the RTAS blob itself.
926 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-size", RTAS_MIN_SIZE
+
928 ms
->smp
.max_cpus
* sizeof(uint64_t) * 2 +
930 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
931 RTAS_ERROR_LOG_MAX
));
932 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
933 RTAS_EVENT_SCAN_RATE
));
935 g_assert(msi_nonbroken
);
936 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
939 * According to PAPR, rtas ibm,os-term does not guarantee a return
940 * back to the guest cpu.
942 * While an additional ibm,extended-os-term property indicates
943 * that rtas call return will always occur. Set this property.
945 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
947 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
948 lrdr_capacity
, sizeof(lrdr_capacity
)));
950 spapr_dt_rtas_tokens(fdt
, rtas
);
954 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
955 * and the XIVE features that the guest may request and thus the valid
956 * values for bytes 23..26 of option vector 5:
958 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
961 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
964 23, 0x00, /* XICS / XIVE mode */
965 24, 0x00, /* Hash/Radix, filled in below. */
966 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
967 26, 0x40, /* Radix options: GTSE == yes. */
970 if (spapr
->irq
->xics
&& spapr
->irq
->xive
) {
971 val
[1] = SPAPR_OV5_XIVE_BOTH
;
972 } else if (spapr
->irq
->xive
) {
973 val
[1] = SPAPR_OV5_XIVE_EXPLOIT
;
975 assert(spapr
->irq
->xics
);
976 val
[1] = SPAPR_OV5_XIVE_LEGACY
;
979 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
980 first_ppc_cpu
->compat_pvr
)) {
982 * If we're in a pre POWER9 compat mode then the guest should
983 * do hash and use the legacy interrupt mode
985 val
[1] = SPAPR_OV5_XIVE_LEGACY
; /* XICS */
986 val
[3] = 0x00; /* Hash */
987 spapr_check_mmu_mode(false);
988 } else if (kvm_enabled()) {
989 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
990 val
[3] = 0x80; /* OV5_MMU_BOTH */
991 } else if (kvmppc_has_cap_mmu_radix()) {
992 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
994 val
[3] = 0x00; /* Hash */
997 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1000 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1004 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
, bool reset
)
1006 MachineState
*machine
= MACHINE(spapr
);
1007 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1010 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1013 const char *boot_device
= spapr
->boot_device
;
1014 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1016 char *bootlist
= get_boot_devices_list(&cb
);
1018 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1019 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1020 machine
->kernel_cmdline
));
1023 if (spapr
->initrd_size
) {
1024 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1025 spapr
->initrd_base
));
1026 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1027 spapr
->initrd_base
+ spapr
->initrd_size
));
1030 if (spapr
->kernel_size
) {
1031 uint64_t kprop
[2] = { cpu_to_be64(spapr
->kernel_addr
),
1032 cpu_to_be64(spapr
->kernel_size
) };
1034 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1035 &kprop
, sizeof(kprop
)));
1036 if (spapr
->kernel_le
) {
1037 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1041 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1043 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1044 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1045 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1047 if (cb
&& bootlist
) {
1050 for (i
= 0; i
< cb
; i
++) {
1051 if (bootlist
[i
] == '\n') {
1055 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1058 if (boot_device
&& strlen(boot_device
)) {
1059 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1062 if (!spapr
->has_graphics
&& stdout_path
) {
1064 * "linux,stdout-path" and "stdout" properties are
1065 * deprecated by linux kernel. New platforms should only
1066 * use the "stdout-path" property. Set the new property
1067 * and continue using older property to remain compatible
1068 * with the existing firmware.
1070 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1071 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1075 * We can deal with BAR reallocation just fine, advertise it
1078 if (smc
->linux_pci_probe
) {
1079 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1082 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1084 g_free(stdout_path
);
1088 _FDT(spapr_dt_ovec(fdt
, chosen
, spapr
->ov5_cas
, "ibm,architecture-vec-5"));
1091 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1093 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1094 * KVM to work under pHyp with some guest co-operation */
1096 uint8_t hypercall
[16];
1098 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1099 /* indicate KVM hypercall interface */
1100 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1101 if (kvmppc_has_cap_fixup_hcalls()) {
1103 * Older KVM versions with older guest kernels were broken
1104 * with the magic page, don't allow the guest to map it.
1106 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1107 sizeof(hypercall
))) {
1108 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1109 hypercall
, sizeof(hypercall
)));
1114 void *spapr_build_fdt(SpaprMachineState
*spapr
, bool reset
, size_t space
)
1116 MachineState
*machine
= MACHINE(spapr
);
1117 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1118 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1119 uint32_t root_drc_type_mask
= 0;
1125 fdt
= g_malloc0(space
);
1126 _FDT((fdt_create_empty_tree(fdt
, space
)));
1129 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1130 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1131 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1133 /* Guest UUID & Name*/
1134 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1135 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1136 if (qemu_uuid_set
) {
1137 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1141 if (qemu_get_vm_name()) {
1142 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1143 qemu_get_vm_name()));
1146 /* Host Model & Serial Number */
1147 if (spapr
->host_model
) {
1148 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1149 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1150 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1154 if (spapr
->host_serial
) {
1155 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1156 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1157 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1161 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1162 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1164 /* /interrupt controller */
1165 spapr_irq_dt(spapr
, spapr_max_server_number(spapr
), fdt
, PHANDLE_INTC
);
1167 ret
= spapr_dt_memory(spapr
, fdt
);
1169 error_report("couldn't setup memory nodes in fdt");
1174 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1176 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1177 ret
= spapr_dt_rng(fdt
);
1179 error_report("could not set up rng device in the fdt");
1184 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1185 ret
= spapr_dt_phb(spapr
, phb
, PHANDLE_INTC
, fdt
, NULL
);
1187 error_report("couldn't setup PCI devices in fdt");
1192 spapr_dt_cpus(fdt
, spapr
);
1194 /* ibm,drc-indexes and friends */
1195 if (smc
->dr_lmb_enabled
) {
1196 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_LMB
;
1198 if (smc
->dr_phb_enabled
) {
1199 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_PHB
;
1201 if (mc
->nvdimm_supported
) {
1202 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_PMEM
;
1204 if (root_drc_type_mask
) {
1205 _FDT(spapr_dt_drc(fdt
, 0, NULL
, root_drc_type_mask
));
1208 if (mc
->has_hotpluggable_cpus
) {
1209 int offset
= fdt_path_offset(fdt
, "/cpus");
1210 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1212 error_report("Couldn't set up CPU DR device tree properties");
1217 /* /event-sources */
1218 spapr_dt_events(spapr
, fdt
);
1221 spapr_dt_rtas(spapr
, fdt
);
1224 spapr_dt_chosen(spapr
, fdt
, reset
);
1227 if (kvm_enabled()) {
1228 spapr_dt_hypervisor(spapr
, fdt
);
1231 /* Build memory reserve map */
1233 if (spapr
->kernel_size
) {
1234 _FDT((fdt_add_mem_rsv(fdt
, spapr
->kernel_addr
,
1235 spapr
->kernel_size
)));
1237 if (spapr
->initrd_size
) {
1238 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
,
1239 spapr
->initrd_size
)));
1243 /* NVDIMM devices */
1244 if (mc
->nvdimm_supported
) {
1245 spapr_dt_persistent_memory(spapr
, fdt
);
1251 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1253 SpaprMachineState
*spapr
= opaque
;
1255 return (addr
& 0x0fffffff) + spapr
->kernel_addr
;
1258 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1261 CPUPPCState
*env
= &cpu
->env
;
1263 /* The TCG path should also be holding the BQL at this point */
1264 g_assert(qemu_mutex_iothread_locked());
1267 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1268 env
->gpr
[3] = H_PRIVILEGE
;
1270 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1274 struct LPCRSyncState
{
1279 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1281 struct LPCRSyncState
*s
= arg
.host_ptr
;
1282 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1283 CPUPPCState
*env
= &cpu
->env
;
1286 cpu_synchronize_state(cs
);
1287 lpcr
= env
->spr
[SPR_LPCR
];
1290 ppc_store_lpcr(cpu
, lpcr
);
1293 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1296 struct LPCRSyncState s
= {
1301 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1305 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1307 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1309 /* Copy PATE1:GR into PATE0:HR */
1310 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1311 entry
->dw1
= spapr
->patb_entry
;
1314 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1315 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1316 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1317 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1318 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1321 * Get the fd to access the kernel htab, re-opening it if necessary
1323 static int get_htab_fd(SpaprMachineState
*spapr
)
1325 Error
*local_err
= NULL
;
1327 if (spapr
->htab_fd
>= 0) {
1328 return spapr
->htab_fd
;
1331 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1332 if (spapr
->htab_fd
< 0) {
1333 error_report_err(local_err
);
1336 return spapr
->htab_fd
;
1339 void close_htab_fd(SpaprMachineState
*spapr
)
1341 if (spapr
->htab_fd
>= 0) {
1342 close(spapr
->htab_fd
);
1344 spapr
->htab_fd
= -1;
1347 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1349 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1351 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1354 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1356 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1358 assert(kvm_enabled());
1364 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1367 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1370 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1371 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1375 * HTAB is controlled by KVM. Fetch into temporary buffer
1377 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1378 kvmppc_read_hptes(hptes
, ptex
, n
);
1383 * HTAB is controlled by QEMU. Just point to the internally
1386 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1389 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1390 const ppc_hash_pte64_t
*hptes
,
1393 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1396 g_free((void *)hptes
);
1399 /* Nothing to do for qemu managed HPT */
1402 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1403 uint64_t pte0
, uint64_t pte1
)
1405 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1406 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1409 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1411 if (pte0
& HPTE64_V_VALID
) {
1412 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1414 * When setting valid, we write PTE1 first. This ensures
1415 * proper synchronization with the reading code in
1416 * ppc_hash64_pteg_search()
1419 stq_p(spapr
->htab
+ offset
, pte0
);
1421 stq_p(spapr
->htab
+ offset
, pte0
);
1423 * When clearing it we set PTE0 first. This ensures proper
1424 * synchronization with the reading code in
1425 * ppc_hash64_pteg_search()
1428 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1433 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1436 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1437 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1440 /* There should always be a hash table when this is called */
1441 error_report("spapr_hpte_set_c called with no hash table !");
1445 /* The HW performs a non-atomic byte update */
1446 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1449 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1452 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1453 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1456 /* There should always be a hash table when this is called */
1457 error_report("spapr_hpte_set_r called with no hash table !");
1461 /* The HW performs a non-atomic byte update */
1462 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1465 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1469 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1470 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1471 * that's much more than is needed for Linux guests */
1472 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1473 shift
= MAX(shift
, 18); /* Minimum architected size */
1474 shift
= MIN(shift
, 46); /* Maximum architected size */
1478 void spapr_free_hpt(SpaprMachineState
*spapr
)
1480 g_free(spapr
->htab
);
1482 spapr
->htab_shift
= 0;
1483 close_htab_fd(spapr
);
1486 int spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
, Error
**errp
)
1491 /* Clean up any HPT info from a previous boot */
1492 spapr_free_hpt(spapr
);
1494 rc
= kvmppc_reset_htab(shift
);
1496 if (rc
== -EOPNOTSUPP
) {
1497 error_setg(errp
, "HPT not supported in nested guests");
1502 /* kernel-side HPT needed, but couldn't allocate one */
1503 error_setg_errno(errp
, errno
, "Failed to allocate KVM HPT of order %d",
1505 error_append_hint(errp
, "Try smaller maxmem?\n");
1507 } else if (rc
> 0) {
1508 /* kernel-side HPT allocated */
1511 "Requested order %d HPT, but kernel allocated order %ld",
1513 error_append_hint(errp
, "Try smaller maxmem?\n");
1517 spapr
->htab_shift
= shift
;
1520 /* kernel-side HPT not needed, allocate in userspace instead */
1521 size_t size
= 1ULL << shift
;
1524 spapr
->htab
= qemu_memalign(size
, size
);
1525 memset(spapr
->htab
, 0, size
);
1526 spapr
->htab_shift
= shift
;
1528 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1529 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1532 /* We're setting up a hash table, so that means we're not radix */
1533 spapr
->patb_entry
= 0;
1534 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1538 void spapr_setup_hpt(SpaprMachineState
*spapr
)
1542 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
) {
1543 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1545 uint64_t current_ram_size
;
1547 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1548 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1550 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1552 if (kvm_enabled()) {
1553 hwaddr vrma_limit
= kvmppc_vrma_limit(spapr
->htab_shift
);
1555 /* Check our RMA fits in the possible VRMA */
1556 if (vrma_limit
< spapr
->rma_size
) {
1557 error_report("Unable to create %" HWADDR_PRIu
1558 "MiB RMA (VRMA only allows %" HWADDR_PRIu
"MiB",
1559 spapr
->rma_size
/ MiB
, vrma_limit
/ MiB
);
1565 void spapr_check_mmu_mode(bool guest_radix
)
1568 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) {
1569 error_report("Guest requested unavailable MMU mode (radix).");
1573 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()
1574 && !kvmppc_has_cap_mmu_hash_v3()) {
1575 error_report("Guest requested unavailable MMU mode (hash).");
1581 static void spapr_machine_reset(MachineState
*machine
)
1583 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1584 PowerPCCPU
*first_ppc_cpu
;
1589 pef_kvm_reset(machine
->cgs
, &error_fatal
);
1590 spapr_caps_apply(spapr
);
1592 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1593 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1594 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1595 spapr
->max_compat_pvr
)) {
1597 * If using KVM with radix mode available, VCPUs can be started
1598 * without a HPT because KVM will start them in radix mode.
1599 * Set the GR bit in PATE so that we know there is no HPT.
1601 spapr
->patb_entry
= PATE1_GR
;
1602 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1604 spapr_setup_hpt(spapr
);
1607 qemu_devices_reset();
1609 spapr_ovec_cleanup(spapr
->ov5_cas
);
1610 spapr
->ov5_cas
= spapr_ovec_new();
1612 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1615 * This is fixing some of the default configuration of the XIVE
1616 * devices. To be called after the reset of the machine devices.
1618 spapr_irq_reset(spapr
, &error_fatal
);
1621 * There is no CAS under qtest. Simulate one to please the code that
1622 * depends on spapr->ov5_cas. This is especially needed to test device
1623 * unplug, so we do that before resetting the DRCs.
1625 if (qtest_enabled()) {
1626 spapr_ovec_cleanup(spapr
->ov5_cas
);
1627 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1630 /* DRC reset may cause a device to be unplugged. This will cause troubles
1631 * if this device is used by another device (eg, a running vhost backend
1632 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1633 * situations, we reset DRCs after all devices have been reset.
1635 spapr_drc_reset_all(spapr
);
1637 spapr_clear_pending_events(spapr
);
1640 * We place the device tree just below either the top of the RMA,
1641 * or just below 2GB, whichever is lower, so that it can be
1642 * processed with 32-bit real mode code if necessary
1644 fdt_addr
= MIN(spapr
->rma_size
, FDT_MAX_ADDR
) - FDT_MAX_SIZE
;
1646 fdt
= spapr_build_fdt(spapr
, true, FDT_MAX_SIZE
);
1648 spapr_vof_reset(spapr
, fdt
, &error_fatal
);
1650 * Do not pack the FDT as the client may change properties.
1651 * VOF client does not expect the FDT so we do not load it to the VM.
1655 /* Should only fail if we've built a corrupted tree */
1658 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
,
1660 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1662 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1664 g_free(spapr
->fdt_blob
);
1665 spapr
->fdt_size
= fdt_totalsize(fdt
);
1666 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1667 spapr
->fdt_blob
= fdt
;
1669 /* Set up the entry state */
1670 first_ppc_cpu
->env
.gpr
[5] = 0;
1672 spapr
->fwnmi_system_reset_addr
= -1;
1673 spapr
->fwnmi_machine_check_addr
= -1;
1674 spapr
->fwnmi_machine_check_interlock
= -1;
1676 /* Signal all vCPUs waiting on this condition */
1677 qemu_cond_broadcast(&spapr
->fwnmi_machine_check_interlock_cond
);
1679 migrate_del_blocker(spapr
->fwnmi_migration_blocker
);
1682 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1684 DeviceState
*dev
= qdev_new("spapr-nvram");
1685 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1688 qdev_prop_set_drive_err(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1692 qdev_realize_and_unref(dev
, &spapr
->vio_bus
->bus
, &error_fatal
);
1694 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1697 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1699 object_initialize_child_with_props(OBJECT(spapr
), "rtc", &spapr
->rtc
,
1700 sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1701 &error_fatal
, NULL
);
1702 qdev_realize(DEVICE(&spapr
->rtc
), NULL
, &error_fatal
);
1703 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1707 /* Returns whether we want to use VGA or not */
1708 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1710 switch (vga_interface_type
) {
1718 return pci_vga_init(pci_bus
) != NULL
;
1721 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1726 static int spapr_pre_load(void *opaque
)
1730 rc
= spapr_caps_pre_load(opaque
);
1738 static int spapr_post_load(void *opaque
, int version_id
)
1740 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1743 err
= spapr_caps_post_migration(spapr
);
1749 * In earlier versions, there was no separate qdev for the PAPR
1750 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1751 * So when migrating from those versions, poke the incoming offset
1752 * value into the RTC device
1754 if (version_id
< 3) {
1755 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1761 if (kvm_enabled() && spapr
->patb_entry
) {
1762 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1763 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1764 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1767 * Update LPCR:HR and UPRT as they may not be set properly in
1770 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1771 LPCR_HR
| LPCR_UPRT
);
1773 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1775 error_report("Process table config unsupported by the host");
1780 err
= spapr_irq_post_load(spapr
, version_id
);
1788 static int spapr_pre_save(void *opaque
)
1792 rc
= spapr_caps_pre_save(opaque
);
1800 static bool version_before_3(void *opaque
, int version_id
)
1802 return version_id
< 3;
1805 static bool spapr_pending_events_needed(void *opaque
)
1807 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1808 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1811 static const VMStateDescription vmstate_spapr_event_entry
= {
1812 .name
= "spapr_event_log_entry",
1814 .minimum_version_id
= 1,
1815 .fields
= (VMStateField
[]) {
1816 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1817 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1818 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1819 NULL
, extended_length
),
1820 VMSTATE_END_OF_LIST()
1824 static const VMStateDescription vmstate_spapr_pending_events
= {
1825 .name
= "spapr_pending_events",
1827 .minimum_version_id
= 1,
1828 .needed
= spapr_pending_events_needed
,
1829 .fields
= (VMStateField
[]) {
1830 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1831 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1832 VMSTATE_END_OF_LIST()
1836 static bool spapr_ov5_cas_needed(void *opaque
)
1838 SpaprMachineState
*spapr
= opaque
;
1839 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1842 /* Prior to the introduction of SpaprOptionVector, we had two option
1843 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1844 * Both of these options encode machine topology into the device-tree
1845 * in such a way that the now-booted OS should still be able to interact
1846 * appropriately with QEMU regardless of what options were actually
1847 * negotiatied on the source side.
1849 * As such, we can avoid migrating the CAS-negotiated options if these
1850 * are the only options available on the current machine/platform.
1851 * Since these are the only options available for pseries-2.7 and
1852 * earlier, this allows us to maintain old->new/new->old migration
1855 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1856 * via default pseries-2.8 machines and explicit command-line parameters.
1857 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1858 * of the actual CAS-negotiated values to continue working properly. For
1859 * example, availability of memory unplug depends on knowing whether
1860 * OV5_HP_EVT was negotiated via CAS.
1862 * Thus, for any cases where the set of available CAS-negotiatable
1863 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1864 * include the CAS-negotiated options in the migration stream, unless
1865 * if they affect boot time behaviour only.
1867 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1868 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1869 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1871 /* We need extra information if we have any bits outside the mask
1873 cas_needed
= !spapr_ovec_subset(spapr
->ov5
, ov5_mask
);
1875 spapr_ovec_cleanup(ov5_mask
);
1880 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1881 .name
= "spapr_option_vector_ov5_cas",
1883 .minimum_version_id
= 1,
1884 .needed
= spapr_ov5_cas_needed
,
1885 .fields
= (VMStateField
[]) {
1886 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1887 vmstate_spapr_ovec
, SpaprOptionVector
),
1888 VMSTATE_END_OF_LIST()
1892 static bool spapr_patb_entry_needed(void *opaque
)
1894 SpaprMachineState
*spapr
= opaque
;
1896 return !!spapr
->patb_entry
;
1899 static const VMStateDescription vmstate_spapr_patb_entry
= {
1900 .name
= "spapr_patb_entry",
1902 .minimum_version_id
= 1,
1903 .needed
= spapr_patb_entry_needed
,
1904 .fields
= (VMStateField
[]) {
1905 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1906 VMSTATE_END_OF_LIST()
1910 static bool spapr_irq_map_needed(void *opaque
)
1912 SpaprMachineState
*spapr
= opaque
;
1914 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1917 static const VMStateDescription vmstate_spapr_irq_map
= {
1918 .name
= "spapr_irq_map",
1920 .minimum_version_id
= 1,
1921 .needed
= spapr_irq_map_needed
,
1922 .fields
= (VMStateField
[]) {
1923 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
1924 VMSTATE_END_OF_LIST()
1928 static bool spapr_dtb_needed(void *opaque
)
1930 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
1932 return smc
->update_dt_enabled
;
1935 static int spapr_dtb_pre_load(void *opaque
)
1937 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1939 g_free(spapr
->fdt_blob
);
1940 spapr
->fdt_blob
= NULL
;
1941 spapr
->fdt_size
= 0;
1946 static const VMStateDescription vmstate_spapr_dtb
= {
1947 .name
= "spapr_dtb",
1949 .minimum_version_id
= 1,
1950 .needed
= spapr_dtb_needed
,
1951 .pre_load
= spapr_dtb_pre_load
,
1952 .fields
= (VMStateField
[]) {
1953 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
1954 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
1955 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
1957 VMSTATE_END_OF_LIST()
1961 static bool spapr_fwnmi_needed(void *opaque
)
1963 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1965 return spapr
->fwnmi_machine_check_addr
!= -1;
1968 static int spapr_fwnmi_pre_save(void *opaque
)
1970 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1973 * Check if machine check handling is in progress and print a
1976 if (spapr
->fwnmi_machine_check_interlock
!= -1) {
1977 warn_report("A machine check is being handled during migration. The"
1978 "handler may run and log hardware error on the destination");
1984 static const VMStateDescription vmstate_spapr_fwnmi
= {
1985 .name
= "spapr_fwnmi",
1987 .minimum_version_id
= 1,
1988 .needed
= spapr_fwnmi_needed
,
1989 .pre_save
= spapr_fwnmi_pre_save
,
1990 .fields
= (VMStateField
[]) {
1991 VMSTATE_UINT64(fwnmi_system_reset_addr
, SpaprMachineState
),
1992 VMSTATE_UINT64(fwnmi_machine_check_addr
, SpaprMachineState
),
1993 VMSTATE_INT32(fwnmi_machine_check_interlock
, SpaprMachineState
),
1994 VMSTATE_END_OF_LIST()
1998 static const VMStateDescription vmstate_spapr
= {
2001 .minimum_version_id
= 1,
2002 .pre_load
= spapr_pre_load
,
2003 .post_load
= spapr_post_load
,
2004 .pre_save
= spapr_pre_save
,
2005 .fields
= (VMStateField
[]) {
2006 /* used to be @next_irq */
2007 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2010 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2012 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2013 VMSTATE_END_OF_LIST()
2015 .subsections
= (const VMStateDescription
*[]) {
2016 &vmstate_spapr_ov5_cas
,
2017 &vmstate_spapr_patb_entry
,
2018 &vmstate_spapr_pending_events
,
2019 &vmstate_spapr_cap_htm
,
2020 &vmstate_spapr_cap_vsx
,
2021 &vmstate_spapr_cap_dfp
,
2022 &vmstate_spapr_cap_cfpc
,
2023 &vmstate_spapr_cap_sbbc
,
2024 &vmstate_spapr_cap_ibs
,
2025 &vmstate_spapr_cap_hpt_maxpagesize
,
2026 &vmstate_spapr_irq_map
,
2027 &vmstate_spapr_cap_nested_kvm_hv
,
2029 &vmstate_spapr_cap_large_decr
,
2030 &vmstate_spapr_cap_ccf_assist
,
2031 &vmstate_spapr_cap_fwnmi
,
2032 &vmstate_spapr_fwnmi
,
2037 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2039 SpaprMachineState
*spapr
= opaque
;
2041 /* "Iteration" header */
2042 if (!spapr
->htab_shift
) {
2043 qemu_put_be32(f
, -1);
2045 qemu_put_be32(f
, spapr
->htab_shift
);
2049 spapr
->htab_save_index
= 0;
2050 spapr
->htab_first_pass
= true;
2052 if (spapr
->htab_shift
) {
2053 assert(kvm_enabled());
2061 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2062 int chunkstart
, int n_valid
, int n_invalid
)
2064 qemu_put_be32(f
, chunkstart
);
2065 qemu_put_be16(f
, n_valid
);
2066 qemu_put_be16(f
, n_invalid
);
2067 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2068 HASH_PTE_SIZE_64
* n_valid
);
2071 static void htab_save_end_marker(QEMUFile
*f
)
2073 qemu_put_be32(f
, 0);
2074 qemu_put_be16(f
, 0);
2075 qemu_put_be16(f
, 0);
2078 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2081 bool has_timeout
= max_ns
!= -1;
2082 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2083 int index
= spapr
->htab_save_index
;
2084 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2086 assert(spapr
->htab_first_pass
);
2091 /* Consume invalid HPTEs */
2092 while ((index
< htabslots
)
2093 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2094 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2098 /* Consume valid HPTEs */
2100 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2101 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2102 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2106 if (index
> chunkstart
) {
2107 int n_valid
= index
- chunkstart
;
2109 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2112 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2116 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2118 if (index
>= htabslots
) {
2119 assert(index
== htabslots
);
2121 spapr
->htab_first_pass
= false;
2123 spapr
->htab_save_index
= index
;
2126 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2129 bool final
= max_ns
< 0;
2130 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2131 int examined
= 0, sent
= 0;
2132 int index
= spapr
->htab_save_index
;
2133 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2135 assert(!spapr
->htab_first_pass
);
2138 int chunkstart
, invalidstart
;
2140 /* Consume non-dirty HPTEs */
2141 while ((index
< htabslots
)
2142 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2148 /* Consume valid dirty HPTEs */
2149 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2150 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2151 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2152 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2157 invalidstart
= index
;
2158 /* Consume invalid dirty HPTEs */
2159 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2160 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2161 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2162 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2167 if (index
> chunkstart
) {
2168 int n_valid
= invalidstart
- chunkstart
;
2169 int n_invalid
= index
- invalidstart
;
2171 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2172 sent
+= index
- chunkstart
;
2174 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2179 if (examined
>= htabslots
) {
2183 if (index
>= htabslots
) {
2184 assert(index
== htabslots
);
2187 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2189 if (index
>= htabslots
) {
2190 assert(index
== htabslots
);
2194 spapr
->htab_save_index
= index
;
2196 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2199 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2200 #define MAX_KVM_BUF_SIZE 2048
2202 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2204 SpaprMachineState
*spapr
= opaque
;
2208 /* Iteration header */
2209 if (!spapr
->htab_shift
) {
2210 qemu_put_be32(f
, -1);
2213 qemu_put_be32(f
, 0);
2217 assert(kvm_enabled());
2219 fd
= get_htab_fd(spapr
);
2224 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2228 } else if (spapr
->htab_first_pass
) {
2229 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2231 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2234 htab_save_end_marker(f
);
2239 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2241 SpaprMachineState
*spapr
= opaque
;
2244 /* Iteration header */
2245 if (!spapr
->htab_shift
) {
2246 qemu_put_be32(f
, -1);
2249 qemu_put_be32(f
, 0);
2255 assert(kvm_enabled());
2257 fd
= get_htab_fd(spapr
);
2262 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2267 if (spapr
->htab_first_pass
) {
2268 htab_save_first_pass(f
, spapr
, -1);
2270 htab_save_later_pass(f
, spapr
, -1);
2274 htab_save_end_marker(f
);
2279 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2281 SpaprMachineState
*spapr
= opaque
;
2282 uint32_t section_hdr
;
2284 Error
*local_err
= NULL
;
2286 if (version_id
< 1 || version_id
> 1) {
2287 error_report("htab_load() bad version");
2291 section_hdr
= qemu_get_be32(f
);
2293 if (section_hdr
== -1) {
2294 spapr_free_hpt(spapr
);
2301 /* First section gives the htab size */
2302 ret
= spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2304 error_report_err(local_err
);
2311 assert(kvm_enabled());
2313 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2315 error_report_err(local_err
);
2322 uint16_t n_valid
, n_invalid
;
2324 index
= qemu_get_be32(f
);
2325 n_valid
= qemu_get_be16(f
);
2326 n_invalid
= qemu_get_be16(f
);
2328 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2333 if ((index
+ n_valid
+ n_invalid
) >
2334 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2335 /* Bad index in stream */
2337 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2338 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2344 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2345 HASH_PTE_SIZE_64
* n_valid
);
2348 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2349 HASH_PTE_SIZE_64
* n_invalid
);
2356 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
,
2359 error_report_err(local_err
);
2373 static void htab_save_cleanup(void *opaque
)
2375 SpaprMachineState
*spapr
= opaque
;
2377 close_htab_fd(spapr
);
2380 static SaveVMHandlers savevm_htab_handlers
= {
2381 .save_setup
= htab_save_setup
,
2382 .save_live_iterate
= htab_save_iterate
,
2383 .save_live_complete_precopy
= htab_save_complete
,
2384 .save_cleanup
= htab_save_cleanup
,
2385 .load_state
= htab_load
,
2388 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2391 SpaprMachineState
*spapr
= SPAPR_MACHINE(opaque
);
2393 g_free(spapr
->boot_device
);
2394 spapr
->boot_device
= g_strdup(boot_device
);
2397 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2399 MachineState
*machine
= MACHINE(spapr
);
2400 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2401 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2404 for (i
= 0; i
< nr_lmbs
; i
++) {
2407 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2408 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2414 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2415 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2416 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2418 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2422 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2423 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2424 " is not aligned to %" PRIu64
" MiB",
2426 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2430 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2431 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2432 " is not aligned to %" PRIu64
" MiB",
2434 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2438 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2439 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2441 "Node %d memory size 0x%" PRIx64
2442 " is not aligned to %" PRIu64
" MiB",
2443 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2444 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2450 /* find cpu slot in machine->possible_cpus by core_id */
2451 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2453 int index
= id
/ ms
->smp
.threads
;
2455 if (index
>= ms
->possible_cpus
->len
) {
2461 return &ms
->possible_cpus
->cpus
[index
];
2464 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2466 MachineState
*ms
= MACHINE(spapr
);
2467 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2468 Error
*local_err
= NULL
;
2469 bool vsmt_user
= !!spapr
->vsmt
;
2470 int kvm_smt
= kvmppc_smt_threads();
2472 unsigned int smp_threads
= ms
->smp
.threads
;
2474 if (!kvm_enabled() && (smp_threads
> 1)) {
2475 error_setg(errp
, "TCG cannot support more than 1 thread/core "
2476 "on a pseries machine");
2479 if (!is_power_of_2(smp_threads
)) {
2480 error_setg(errp
, "Cannot support %d threads/core on a pseries "
2481 "machine because it must be a power of 2", smp_threads
);
2485 /* Detemine the VSMT mode to use: */
2487 if (spapr
->vsmt
< smp_threads
) {
2488 error_setg(errp
, "Cannot support VSMT mode %d"
2489 " because it must be >= threads/core (%d)",
2490 spapr
->vsmt
, smp_threads
);
2493 /* In this case, spapr->vsmt has been set by the command line */
2494 } else if (!smc
->smp_threads_vsmt
) {
2496 * Default VSMT value is tricky, because we need it to be as
2497 * consistent as possible (for migration), but this requires
2498 * changing it for at least some existing cases. We pick 8 as
2499 * the value that we'd get with KVM on POWER8, the
2500 * overwhelmingly common case in production systems.
2502 spapr
->vsmt
= MAX(8, smp_threads
);
2504 spapr
->vsmt
= smp_threads
;
2507 /* KVM: If necessary, set the SMT mode: */
2508 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2509 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2511 /* Looks like KVM isn't able to change VSMT mode */
2512 error_setg(&local_err
,
2513 "Failed to set KVM's VSMT mode to %d (errno %d)",
2515 /* We can live with that if the default one is big enough
2516 * for the number of threads, and a submultiple of the one
2517 * we want. In this case we'll waste some vcpu ids, but
2518 * behaviour will be correct */
2519 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2520 warn_report_err(local_err
);
2523 error_append_hint(&local_err
,
2524 "On PPC, a VM with %d threads/core"
2525 " on a host with %d threads/core"
2526 " requires the use of VSMT mode %d.\n",
2527 smp_threads
, kvm_smt
, spapr
->vsmt
);
2529 kvmppc_error_append_smt_possible_hint(&local_err
);
2530 error_propagate(errp
, local_err
);
2534 /* else TCG: nothing to do currently */
2537 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2539 MachineState
*machine
= MACHINE(spapr
);
2540 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2541 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2542 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2543 const CPUArchIdList
*possible_cpus
;
2544 unsigned int smp_cpus
= machine
->smp
.cpus
;
2545 unsigned int smp_threads
= machine
->smp
.threads
;
2546 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2547 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2550 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2551 if (mc
->has_hotpluggable_cpus
) {
2552 if (smp_cpus
% smp_threads
) {
2553 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2554 smp_cpus
, smp_threads
);
2557 if (max_cpus
% smp_threads
) {
2558 error_report("max_cpus (%u) must be multiple of threads (%u)",
2559 max_cpus
, smp_threads
);
2563 if (max_cpus
!= smp_cpus
) {
2564 error_report("This machine version does not support CPU hotplug");
2567 boot_cores_nr
= possible_cpus
->len
;
2570 if (smc
->pre_2_10_has_unused_icps
) {
2573 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2574 /* Dummy entries get deregistered when real ICPState objects
2575 * are registered during CPU core hotplug.
2577 pre_2_10_vmstate_register_dummy_icp(i
);
2581 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2582 int core_id
= i
* smp_threads
;
2584 if (mc
->has_hotpluggable_cpus
) {
2585 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2586 spapr_vcpu_id(spapr
, core_id
));
2589 if (i
< boot_cores_nr
) {
2590 Object
*core
= object_new(type
);
2591 int nr_threads
= smp_threads
;
2593 /* Handle the partially filled core for older machine types */
2594 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2595 nr_threads
= smp_cpus
- i
* smp_threads
;
2598 object_property_set_int(core
, "nr-threads", nr_threads
,
2600 object_property_set_int(core
, CPU_CORE_PROP_CORE_ID
, core_id
,
2602 qdev_realize(DEVICE(core
), NULL
, &error_fatal
);
2609 static PCIHostState
*spapr_create_default_phb(void)
2613 dev
= qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE
);
2614 qdev_prop_set_uint32(dev
, "index", 0);
2615 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
2617 return PCI_HOST_BRIDGE(dev
);
2620 static hwaddr
spapr_rma_size(SpaprMachineState
*spapr
, Error
**errp
)
2622 MachineState
*machine
= MACHINE(spapr
);
2623 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2624 hwaddr rma_size
= machine
->ram_size
;
2625 hwaddr node0_size
= spapr_node0_size(machine
);
2627 /* RMA has to fit in the first NUMA node */
2628 rma_size
= MIN(rma_size
, node0_size
);
2631 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2634 rma_size
= MIN(rma_size
, 1 * TiB
);
2637 * Clamp the RMA size based on machine type. This is for
2638 * migration compatibility with older qemu versions, which limited
2639 * the RMA size for complicated and mostly bad reasons.
2641 if (smc
->rma_limit
) {
2642 rma_size
= MIN(rma_size
, smc
->rma_limit
);
2645 if (rma_size
< MIN_RMA_SLOF
) {
2647 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2648 "ldMiB guest RMA (Real Mode Area memory)",
2649 MIN_RMA_SLOF
/ MiB
);
2656 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState
*spapr
)
2658 MachineState
*machine
= MACHINE(spapr
);
2661 for (i
= 0; i
< machine
->ram_slots
; i
++) {
2662 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_PMEM
, i
);
2666 /* pSeries LPAR / sPAPR hardware init */
2667 static void spapr_machine_init(MachineState
*machine
)
2669 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2670 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2671 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2672 const char *bios_default
= spapr
->vof
? FW_FILE_NAME_VOF
: FW_FILE_NAME
;
2673 const char *bios_name
= machine
->firmware
?: bios_default
;
2674 const char *kernel_filename
= machine
->kernel_filename
;
2675 const char *initrd_filename
= machine
->initrd_filename
;
2678 MemoryRegion
*sysmem
= get_system_memory();
2679 long load_limit
, fw_size
;
2681 Error
*resize_hpt_err
= NULL
;
2684 * if Secure VM (PEF) support is configured, then initialize it
2686 pef_kvm_init(machine
->cgs
, &error_fatal
);
2688 msi_nonbroken
= true;
2690 QLIST_INIT(&spapr
->phbs
);
2691 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2693 /* Determine capabilities to run with */
2694 spapr_caps_init(spapr
);
2696 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2697 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2699 * If the user explicitly requested a mode we should either
2700 * supply it, or fail completely (which we do below). But if
2701 * it's not set explicitly, we reset our mode to something
2704 if (resize_hpt_err
) {
2705 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2706 error_free(resize_hpt_err
);
2707 resize_hpt_err
= NULL
;
2709 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2713 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2715 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2717 * User requested HPT resize, but this host can't supply it. Bail out
2719 error_report_err(resize_hpt_err
);
2722 error_free(resize_hpt_err
);
2724 spapr
->rma_size
= spapr_rma_size(spapr
, &error_fatal
);
2726 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2727 load_limit
= MIN(spapr
->rma_size
, FDT_MAX_ADDR
) - FW_OVERHEAD
;
2730 * VSMT must be set in order to be able to compute VCPU ids, ie to
2731 * call spapr_max_server_number() or spapr_vcpu_id().
2733 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2735 /* Set up Interrupt Controller before we create the VCPUs */
2736 spapr_irq_init(spapr
, &error_fatal
);
2738 /* Set up containers for ibm,client-architecture-support negotiated options
2740 spapr
->ov5
= spapr_ovec_new();
2741 spapr
->ov5_cas
= spapr_ovec_new();
2743 if (smc
->dr_lmb_enabled
) {
2744 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2745 spapr_validate_node_memory(machine
, &error_fatal
);
2748 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2750 /* advertise support for dedicated HP event source to guests */
2751 if (spapr
->use_hotplug_event_source
) {
2752 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2755 /* advertise support for HPT resizing */
2756 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2757 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2760 /* advertise support for ibm,dyamic-memory-v2 */
2761 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2763 /* advertise XIVE on POWER9 machines */
2764 if (spapr
->irq
->xive
) {
2765 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2769 spapr_init_cpus(spapr
);
2772 * check we don't have a memory-less/cpu-less NUMA node
2773 * Firmware relies on the existing memory/cpu topology to provide the
2774 * NUMA topology to the kernel.
2775 * And the linux kernel needs to know the NUMA topology at start
2776 * to be able to hotplug CPUs later.
2778 if (machine
->numa_state
->num_nodes
) {
2779 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
2780 /* check for memory-less node */
2781 if (machine
->numa_state
->nodes
[i
].node_mem
== 0) {
2784 /* check for cpu-less node */
2786 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2787 if (cpu
->node_id
== i
) {
2792 /* memory-less and cpu-less node */
2795 "Memory-less/cpu-less nodes are not supported (node %d)",
2804 spapr
->gpu_numa_id
= spapr_numa_initial_nvgpu_numa_id(machine
);
2806 /* Init numa_assoc_array */
2807 spapr_numa_associativity_init(spapr
, machine
);
2809 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2810 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2811 spapr
->max_compat_pvr
)) {
2812 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_300
);
2813 /* KVM and TCG always allow GTSE with radix... */
2814 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2816 /* ... but not with hash (currently). */
2818 if (kvm_enabled()) {
2819 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2820 kvmppc_enable_logical_ci_hcalls();
2821 kvmppc_enable_set_mode_hcall();
2823 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2824 kvmppc_enable_clear_ref_mod_hcalls();
2826 /* Enable H_PAGE_INIT */
2827 kvmppc_enable_h_page_init();
2831 memory_region_add_subregion(sysmem
, 0, machine
->ram
);
2833 /* always allocate the device memory information */
2834 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2836 /* initialize hotplug memory address space */
2837 if (machine
->ram_size
< machine
->maxram_size
) {
2838 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2840 * Limit the number of hotpluggable memory slots to half the number
2841 * slots that KVM supports, leaving the other half for PCI and other
2842 * devices. However ensure that number of slots doesn't drop below 32.
2844 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2845 SPAPR_MAX_RAM_SLOTS
;
2847 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2848 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2850 if (machine
->ram_slots
> max_memslots
) {
2851 error_report("Specified number of memory slots %"
2852 PRIu64
" exceeds max supported %d",
2853 machine
->ram_slots
, max_memslots
);
2857 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2858 SPAPR_DEVICE_MEM_ALIGN
);
2859 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2860 "device-memory", device_mem_size
);
2861 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2862 &machine
->device_memory
->mr
);
2865 if (smc
->dr_lmb_enabled
) {
2866 spapr_create_lmb_dr_connectors(spapr
);
2869 if (spapr_get_cap(spapr
, SPAPR_CAP_FWNMI
) == SPAPR_CAP_ON
) {
2870 /* Create the error string for live migration blocker */
2871 error_setg(&spapr
->fwnmi_migration_blocker
,
2872 "A machine check is being handled during migration. The handler"
2873 "may run and log hardware error on the destination");
2876 if (mc
->nvdimm_supported
) {
2877 spapr_create_nvdimm_dr_connectors(spapr
);
2880 /* Set up RTAS event infrastructure */
2881 spapr_events_init(spapr
);
2883 /* Set up the RTC RTAS interfaces */
2884 spapr_rtc_create(spapr
);
2886 /* Set up VIO bus */
2887 spapr
->vio_bus
= spapr_vio_bus_init();
2889 for (i
= 0; serial_hd(i
); i
++) {
2890 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2893 /* We always have at least the nvram device on VIO */
2894 spapr_create_nvram(spapr
);
2897 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2898 * connectors (described in root DT node's "ibm,drc-types" property)
2899 * are pre-initialized here. additional child connectors (such as
2900 * connectors for a PHBs PCI slots) are added as needed during their
2901 * parent's realization.
2903 if (smc
->dr_phb_enabled
) {
2904 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2905 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2910 spapr_pci_rtas_init();
2912 phb
= spapr_create_default_phb();
2914 for (i
= 0; i
< nb_nics
; i
++) {
2915 NICInfo
*nd
= &nd_table
[i
];
2918 nd
->model
= g_strdup("spapr-vlan");
2921 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2922 g_str_equal(nd
->model
, "ibmveth")) {
2923 spapr_vlan_create(spapr
->vio_bus
, nd
);
2925 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2929 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2930 spapr_vscsi_create(spapr
->vio_bus
);
2934 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2935 spapr
->has_graphics
= true;
2936 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2940 if (smc
->use_ohci_by_default
) {
2941 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2943 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2946 if (spapr
->has_graphics
) {
2947 USBBus
*usb_bus
= usb_bus_find(-1);
2949 usb_create_simple(usb_bus
, "usb-kbd");
2950 usb_create_simple(usb_bus
, "usb-mouse");
2954 if (kernel_filename
) {
2955 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2956 translate_kernel_address
, spapr
,
2957 NULL
, NULL
, NULL
, NULL
, 1,
2958 PPC_ELF_MACHINE
, 0, 0);
2959 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2960 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2961 translate_kernel_address
, spapr
,
2962 NULL
, NULL
, NULL
, NULL
, 0,
2963 PPC_ELF_MACHINE
, 0, 0);
2964 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2966 if (spapr
->kernel_size
< 0) {
2967 error_report("error loading %s: %s", kernel_filename
,
2968 load_elf_strerror(spapr
->kernel_size
));
2973 if (initrd_filename
) {
2974 /* Try to locate the initrd in the gap between the kernel
2975 * and the firmware. Add a bit of space just in case
2977 spapr
->initrd_base
= (spapr
->kernel_addr
+ spapr
->kernel_size
2978 + 0x1ffff) & ~0xffff;
2979 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2982 - spapr
->initrd_base
);
2983 if (spapr
->initrd_size
< 0) {
2984 error_report("could not load initial ram disk '%s'",
2991 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2993 error_report("Could not find LPAR firmware '%s'", bios_name
);
2996 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2998 error_report("Could not load LPAR firmware '%s'", filename
);
3003 /* FIXME: Should register things through the MachineState's qdev
3004 * interface, this is a legacy from the sPAPREnvironment structure
3005 * which predated MachineState but had a similar function */
3006 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3007 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY
, 1,
3008 &savevm_htab_handlers
, spapr
);
3010 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
));
3012 qemu_register_boot_set(spapr_boot_set
, spapr
);
3015 * Nothing needs to be done to resume a suspended guest because
3016 * suspending does not change the machine state, so no need for
3017 * a ->wakeup method.
3019 qemu_register_wakeup_support();
3021 if (kvm_enabled()) {
3022 /* to stop and start vmclock */
3023 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3026 kvmppc_spapr_enable_inkernel_multitce();
3029 qemu_cond_init(&spapr
->fwnmi_machine_check_interlock_cond
);
3031 spapr
->vof
->fw_size
= fw_size
; /* for claim() on itself */
3032 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT
, spapr_h_vof_client
);
3036 #define DEFAULT_KVM_TYPE "auto"
3037 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3040 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to
3041 * accomodate the 'HV' and 'PV' formats that exists in the
3042 * wild. The 'auto' mode is being introduced already as
3043 * lower-case, thus we don't need to bother checking for
3046 if (!vm_type
|| !strcmp(vm_type
, DEFAULT_KVM_TYPE
)) {
3050 if (!g_ascii_strcasecmp(vm_type
, "hv")) {
3054 if (!g_ascii_strcasecmp(vm_type
, "pr")) {
3058 error_report("Unknown kvm-type specified '%s'", vm_type
);
3063 * Implementation of an interface to adjust firmware path
3064 * for the bootindex property handling.
3066 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3069 #define CAST(type, obj, name) \
3070 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3071 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3072 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3073 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3074 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3077 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3078 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3079 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3083 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3084 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3085 * 0x8000 | (target << 8) | (bus << 5) | lun
3086 * (see the "Logical unit addressing format" table in SAM5)
3088 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3089 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3090 (uint64_t)id
<< 48);
3091 } else if (virtio
) {
3093 * We use SRP luns of the form 01000000 | (target << 8) | lun
3094 * in the top 32 bits of the 64-bit LUN
3095 * Note: the quote above is from SLOF and it is wrong,
3096 * the actual binding is:
3097 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3099 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3100 if (d
->lun
>= 256) {
3101 /* Use the LUN "flat space addressing method" */
3104 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3105 (uint64_t)id
<< 32);
3108 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3109 * in the top 32 bits of the 64-bit LUN
3111 unsigned usb_port
= atoi(usb
->port
->path
);
3112 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3113 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3114 (uint64_t)id
<< 32);
3119 * SLOF probes the USB devices, and if it recognizes that the device is a
3120 * storage device, it changes its name to "storage" instead of "usb-host",
3121 * and additionally adds a child node for the SCSI LUN, so the correct
3122 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3124 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3125 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3126 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3127 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3132 /* Replace "pci" with "pci@800000020000000" */
3133 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3137 /* Same logic as virtio above */
3138 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3139 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3142 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3143 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3144 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3145 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3149 return spapr_pci_fw_dev_name(pcidev
);
3155 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3157 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3159 return g_strdup(spapr
->kvm_type
);
3162 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3164 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3166 g_free(spapr
->kvm_type
);
3167 spapr
->kvm_type
= g_strdup(value
);
3170 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3172 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3174 return spapr
->use_hotplug_event_source
;
3177 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3180 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3182 spapr
->use_hotplug_event_source
= value
;
3185 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3190 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3192 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3194 switch (spapr
->resize_hpt
) {
3195 case SPAPR_RESIZE_HPT_DEFAULT
:
3196 return g_strdup("default");
3197 case SPAPR_RESIZE_HPT_DISABLED
:
3198 return g_strdup("disabled");
3199 case SPAPR_RESIZE_HPT_ENABLED
:
3200 return g_strdup("enabled");
3201 case SPAPR_RESIZE_HPT_REQUIRED
:
3202 return g_strdup("required");
3204 g_assert_not_reached();
3207 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3209 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3211 if (strcmp(value
, "default") == 0) {
3212 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3213 } else if (strcmp(value
, "disabled") == 0) {
3214 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3215 } else if (strcmp(value
, "enabled") == 0) {
3216 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3217 } else if (strcmp(value
, "required") == 0) {
3218 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3220 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3224 static bool spapr_get_vof(Object
*obj
, Error
**errp
)
3226 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3228 return spapr
->vof
!= NULL
;
3231 static void spapr_set_vof(Object
*obj
, bool value
, Error
**errp
)
3233 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3236 vof_cleanup(spapr
->vof
);
3243 spapr
->vof
= g_malloc0(sizeof(*spapr
->vof
));
3246 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3248 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3250 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3251 return g_strdup("legacy");
3252 } else if (spapr
->irq
== &spapr_irq_xics
) {
3253 return g_strdup("xics");
3254 } else if (spapr
->irq
== &spapr_irq_xive
) {
3255 return g_strdup("xive");
3256 } else if (spapr
->irq
== &spapr_irq_dual
) {
3257 return g_strdup("dual");
3259 g_assert_not_reached();
3262 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3264 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3266 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3267 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3271 /* The legacy IRQ backend can not be set */
3272 if (strcmp(value
, "xics") == 0) {
3273 spapr
->irq
= &spapr_irq_xics
;
3274 } else if (strcmp(value
, "xive") == 0) {
3275 spapr
->irq
= &spapr_irq_xive
;
3276 } else if (strcmp(value
, "dual") == 0) {
3277 spapr
->irq
= &spapr_irq_dual
;
3279 error_setg(errp
, "Bad value for \"ic-mode\" property");
3283 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3285 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3287 return g_strdup(spapr
->host_model
);
3290 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3292 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3294 g_free(spapr
->host_model
);
3295 spapr
->host_model
= g_strdup(value
);
3298 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3300 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3302 return g_strdup(spapr
->host_serial
);
3305 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3307 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3309 g_free(spapr
->host_serial
);
3310 spapr
->host_serial
= g_strdup(value
);
3313 static void spapr_instance_init(Object
*obj
)
3315 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3316 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3317 MachineState
*ms
= MACHINE(spapr
);
3318 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
3321 * NVDIMM support went live in 5.1 without considering that, in
3322 * other archs, the user needs to enable NVDIMM support with the
3323 * 'nvdimm' machine option and the default behavior is NVDIMM
3324 * support disabled. It is too late to roll back to the standard
3325 * behavior without breaking 5.1 guests.
3327 if (mc
->nvdimm_supported
) {
3328 ms
->nvdimms_state
->is_enabled
= true;
3331 spapr
->htab_fd
= -1;
3332 spapr
->use_hotplug_event_source
= true;
3333 spapr
->kvm_type
= g_strdup(DEFAULT_KVM_TYPE
);
3334 object_property_add_str(obj
, "kvm-type",
3335 spapr_get_kvm_type
, spapr_set_kvm_type
);
3336 object_property_set_description(obj
, "kvm-type",
3337 "Specifies the KVM virtualization mode (auto,"
3338 " hv, pr). Defaults to 'auto'. This mode will use"
3339 " any available KVM module loaded in the host,"
3340 " where kvm_hv takes precedence if both kvm_hv and"
3341 " kvm_pr are loaded.");
3342 object_property_add_bool(obj
, "modern-hotplug-events",
3343 spapr_get_modern_hotplug_events
,
3344 spapr_set_modern_hotplug_events
);
3345 object_property_set_description(obj
, "modern-hotplug-events",
3346 "Use dedicated hotplug event mechanism in"
3347 " place of standard EPOW events when possible"
3348 " (required for memory hot-unplug support)");
3349 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3350 "Maximum permitted CPU compatibility mode");
3352 object_property_add_str(obj
, "resize-hpt",
3353 spapr_get_resize_hpt
, spapr_set_resize_hpt
);
3354 object_property_set_description(obj
, "resize-hpt",
3355 "Resizing of the Hash Page Table (enabled, disabled, required)");
3356 object_property_add_uint32_ptr(obj
, "vsmt",
3357 &spapr
->vsmt
, OBJ_PROP_FLAG_READWRITE
);
3358 object_property_set_description(obj
, "vsmt",
3359 "Virtual SMT: KVM behaves as if this were"
3360 " the host's SMT mode");
3362 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3363 spapr_get_msix_emulation
, NULL
);
3365 object_property_add_uint64_ptr(obj
, "kernel-addr",
3366 &spapr
->kernel_addr
, OBJ_PROP_FLAG_READWRITE
);
3367 object_property_set_description(obj
, "kernel-addr",
3368 stringify(KERNEL_LOAD_ADDR
)
3369 " for -kernel is the default");
3370 spapr
->kernel_addr
= KERNEL_LOAD_ADDR
;
3372 object_property_add_bool(obj
, "x-vof", spapr_get_vof
, spapr_set_vof
);
3373 object_property_set_description(obj
, "x-vof",
3374 "Enable Virtual Open Firmware (experimental)");
3376 /* The machine class defines the default interrupt controller mode */
3377 spapr
->irq
= smc
->irq
;
3378 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3380 object_property_set_description(obj
, "ic-mode",
3381 "Specifies the interrupt controller mode (xics, xive, dual)");
3383 object_property_add_str(obj
, "host-model",
3384 spapr_get_host_model
, spapr_set_host_model
);
3385 object_property_set_description(obj
, "host-model",
3386 "Host model to advertise in guest device tree");
3387 object_property_add_str(obj
, "host-serial",
3388 spapr_get_host_serial
, spapr_set_host_serial
);
3389 object_property_set_description(obj
, "host-serial",
3390 "Host serial number to advertise in guest device tree");
3393 static void spapr_machine_finalizefn(Object
*obj
)
3395 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3397 g_free(spapr
->kvm_type
);
3400 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3402 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3403 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3404 CPUPPCState
*env
= &cpu
->env
;
3406 cpu_synchronize_state(cs
);
3407 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
3408 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3409 uint64_t rtas_addr
, addr
;
3411 /* get rtas addr from fdt */
3412 rtas_addr
= spapr_get_rtas_addr();
3414 qemu_system_guest_panicked(NULL
);
3418 addr
= rtas_addr
+ RTAS_ERROR_LOG_MAX
+ cs
->cpu_index
* sizeof(uint64_t)*2;
3419 stq_be_phys(&address_space_memory
, addr
, env
->gpr
[3]);
3420 stq_be_phys(&address_space_memory
, addr
+ sizeof(uint64_t), 0);
3423 ppc_cpu_do_system_reset(cs
);
3424 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3425 env
->nip
= spapr
->fwnmi_system_reset_addr
;
3429 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3434 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3438 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3439 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3444 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3445 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3447 *fdt_start_offset
= spapr_dt_memory_node(spapr
, fdt
, node
, addr
,
3448 SPAPR_MEMORY_BLOCK_SIZE
);
3452 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3453 bool dedicated_hp_event_source
)
3456 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3458 uint64_t addr
= addr_start
;
3459 bool hotplugged
= spapr_drc_hotplugged(dev
);
3461 for (i
= 0; i
< nr_lmbs
; i
++) {
3462 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3463 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3467 * memory_device_get_free_addr() provided a range of free addresses
3468 * that doesn't overlap with any existing mapping at pre-plug. The
3469 * corresponding LMB DRCs are thus assumed to be all attachable.
3471 spapr_drc_attach(drc
, dev
);
3473 spapr_drc_reset(drc
);
3475 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3477 /* send hotplug notification to the
3478 * guest only in case of hotplugged memory
3481 if (dedicated_hp_event_source
) {
3482 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3483 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3485 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3487 spapr_drc_index(drc
));
3489 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3495 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3497 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3498 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3499 uint64_t size
, addr
;
3501 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3503 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3505 pc_dimm_plug(dimm
, MACHINE(ms
));
3508 addr
= object_property_get_uint(OBJECT(dimm
),
3509 PC_DIMM_ADDR_PROP
, &error_abort
);
3510 spapr_add_lmbs(dev
, addr
, size
,
3511 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
));
3513 slot
= object_property_get_int(OBJECT(dimm
),
3514 PC_DIMM_SLOT_PROP
, &error_abort
);
3515 /* We should have valid slot number at this point */
3516 g_assert(slot
>= 0);
3517 spapr_add_nvdimm(dev
, slot
);
3521 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3524 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3525 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3526 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3527 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3528 Error
*local_err
= NULL
;
3533 if (!smc
->dr_lmb_enabled
) {
3534 error_setg(errp
, "Memory hotplug not supported for this machine");
3538 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3540 error_propagate(errp
, local_err
);
3545 if (!spapr_nvdimm_validate(hotplug_dev
, NVDIMM(dev
), size
, errp
)) {
3548 } else if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3549 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3550 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3554 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3556 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3557 if (!spapr_check_pagesize(spapr
, pagesize
, errp
)) {
3561 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3564 struct SpaprDimmState
{
3567 QTAILQ_ENTRY(SpaprDimmState
) next
;
3570 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3573 SpaprDimmState
*dimm_state
= NULL
;
3575 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3576 if (dimm_state
->dimm
== dimm
) {
3583 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3587 SpaprDimmState
*ds
= NULL
;
3590 * If this request is for a DIMM whose removal had failed earlier
3591 * (due to guest's refusal to remove the LMBs), we would have this
3592 * dimm already in the pending_dimm_unplugs list. In that
3593 * case don't add again.
3595 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3597 ds
= g_malloc0(sizeof(SpaprDimmState
));
3598 ds
->nr_lmbs
= nr_lmbs
;
3600 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3605 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3606 SpaprDimmState
*dimm_state
)
3608 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3612 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3616 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3618 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3619 uint32_t avail_lmbs
= 0;
3620 uint64_t addr_start
, addr
;
3623 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3627 for (i
= 0; i
< nr_lmbs
; i
++) {
3628 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3629 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3634 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3637 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3640 void spapr_memory_unplug_rollback(SpaprMachineState
*spapr
, DeviceState
*dev
)
3646 uint64_t size
, addr_start
, addr
;
3647 g_autofree
char *qapi_error
= NULL
;
3654 dimm
= PC_DIMM(dev
);
3655 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3658 * 'ds == NULL' would mean that the DIMM doesn't have a pending
3659 * unplug state, but one of its DRC is marked as unplug_requested.
3660 * This is bad and weird enough to g_assert() out.
3664 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3666 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3667 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3669 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3673 for (i
= 0; i
< nr_lmbs
; i
++) {
3674 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3675 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3678 drc
->unplug_requested
= false;
3679 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3683 * Tell QAPI that something happened and the memory
3684 * hotunplug wasn't successful.
3686 qapi_error
= g_strdup_printf("Memory hotunplug rejected by the guest "
3687 "for device %s", dev
->id
);
3688 qapi_event_send_mem_unplug_error(dev
->id
, qapi_error
);
3691 /* Callback to be called during DRC release. */
3692 void spapr_lmb_release(DeviceState
*dev
)
3694 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3695 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3696 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3698 /* This information will get lost if a migration occurs
3699 * during the unplug process. In this case recover it. */
3701 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3703 /* The DRC being examined by the caller at least must be counted */
3704 g_assert(ds
->nr_lmbs
);
3707 if (--ds
->nr_lmbs
) {
3712 * Now that all the LMBs have been removed by the guest, call the
3713 * unplug handler chain. This can never fail.
3715 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3716 object_unparent(OBJECT(dev
));
3719 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3721 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3722 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3724 /* We really shouldn't get this far without anything to unplug */
3727 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3728 qdev_unrealize(dev
);
3729 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3732 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3733 DeviceState
*dev
, Error
**errp
)
3735 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3736 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3738 uint64_t size
, addr_start
, addr
;
3742 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
3743 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
3747 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3748 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3750 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3754 * An existing pending dimm state for this DIMM means that there is an
3755 * unplug operation in progress, waiting for the spapr_lmb_release
3756 * callback to complete the job (BQL can't cover that far). In this case,
3757 * bail out to avoid detaching DRCs that were already released.
3759 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3760 error_setg(errp
, "Memory unplug already in progress for device %s",
3765 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3768 for (i
= 0; i
< nr_lmbs
; i
++) {
3769 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3770 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3773 spapr_drc_unplug_request(drc
);
3774 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3777 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3778 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3779 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3780 nr_lmbs
, spapr_drc_index(drc
));
3783 /* Callback to be called during DRC release. */
3784 void spapr_core_release(DeviceState
*dev
)
3786 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3788 /* Call the unplug handler chain. This can never fail. */
3789 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3790 object_unparent(OBJECT(dev
));
3793 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3795 MachineState
*ms
= MACHINE(hotplug_dev
);
3796 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3797 CPUCore
*cc
= CPU_CORE(dev
);
3798 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3800 if (smc
->pre_2_10_has_unused_icps
) {
3801 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3804 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3805 CPUState
*cs
= CPU(sc
->threads
[i
]);
3807 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3812 core_slot
->cpu
= NULL
;
3813 qdev_unrealize(dev
);
3817 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3820 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3823 CPUCore
*cc
= CPU_CORE(dev
);
3825 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3826 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3831 error_setg(errp
, "Boot CPU core may not be unplugged");
3835 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3836 spapr_vcpu_id(spapr
, cc
->core_id
));
3839 if (!spapr_drc_unplug_requested(drc
)) {
3840 spapr_drc_unplug_request(drc
);
3844 * spapr_hotplug_req_remove_by_index is left unguarded, out of the
3845 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ
3846 * pulses removing the same CPU. Otherwise, in an failed hotunplug
3847 * attempt (e.g. the kernel will refuse to remove the last online
3848 * CPU), we will never attempt it again because unplug_requested
3849 * will still be 'true' in that case.
3851 spapr_hotplug_req_remove_by_index(drc
);
3854 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3855 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3857 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3858 CPUState
*cs
= CPU(core
->threads
[0]);
3859 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3860 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3861 int id
= spapr_get_vcpu_id(cpu
);
3862 g_autofree
char *nodename
= NULL
;
3865 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3866 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3868 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
3871 * spapr_dt_cpu() does not fill the 'name' property in the
3872 * CPU node. The function is called during boot process, before
3873 * and after CAS, and overwriting the 'name' property written
3874 * by SLOF is not allowed.
3876 * Write it manually after spapr_dt_cpu(). This makes the hotplug
3877 * CPUs more compatible with the coldplugged ones, which have
3878 * the 'name' property. Linux Kernel also relies on this
3879 * property to identify CPU nodes.
3881 _FDT((fdt_setprop_string(fdt
, offset
, "name", nodename
)));
3883 *fdt_start_offset
= offset
;
3887 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3889 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3890 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3891 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3892 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3893 CPUCore
*cc
= CPU_CORE(dev
);
3896 CPUArchId
*core_slot
;
3898 bool hotplugged
= spapr_drc_hotplugged(dev
);
3901 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3902 g_assert(core_slot
); /* Already checked in spapr_core_pre_plug() */
3904 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3905 spapr_vcpu_id(spapr
, cc
->core_id
));
3907 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3911 * spapr_core_pre_plug() already buys us this is a brand new
3912 * core being plugged into a free slot. Nothing should already
3913 * be attached to the corresponding DRC.
3915 spapr_drc_attach(drc
, dev
);
3919 * Send hotplug notification interrupt to the guest only
3920 * in case of hotplugged CPUs.
3922 spapr_hotplug_req_add_by_index(drc
);
3924 spapr_drc_reset(drc
);
3928 core_slot
->cpu
= OBJECT(dev
);
3931 * Set compatibility mode to match the boot CPU, which was either set
3932 * by the machine reset code or by CAS. This really shouldn't fail at
3936 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3937 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3942 if (smc
->pre_2_10_has_unused_icps
) {
3943 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3944 cs
= CPU(core
->threads
[i
]);
3945 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3950 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3953 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3954 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3955 CPUCore
*cc
= CPU_CORE(dev
);
3956 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3957 const char *type
= object_get_typename(OBJECT(dev
));
3958 CPUArchId
*core_slot
;
3960 unsigned int smp_threads
= machine
->smp
.threads
;
3962 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3963 error_setg(errp
, "CPU hotplug not supported for this machine");
3967 if (strcmp(base_core_type
, type
)) {
3968 error_setg(errp
, "CPU core type should be %s", base_core_type
);
3972 if (cc
->core_id
% smp_threads
) {
3973 error_setg(errp
, "invalid core id %d", cc
->core_id
);
3978 * In general we should have homogeneous threads-per-core, but old
3979 * (pre hotplug support) machine types allow the last core to have
3980 * reduced threads as a compatibility hack for when we allowed
3981 * total vcpus not a multiple of threads-per-core.
3983 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3984 error_setg(errp
, "invalid nr-threads %d, must be %d", cc
->nr_threads
,
3989 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3991 error_setg(errp
, "core id %d out of range", cc
->core_id
);
3995 if (core_slot
->cpu
) {
3996 error_setg(errp
, "core %d already populated", cc
->core_id
);
4000 numa_cpu_pre_plug(core_slot
, dev
, errp
);
4003 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
4004 void *fdt
, int *fdt_start_offset
, Error
**errp
)
4006 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
4009 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
4010 if (intc_phandle
<= 0) {
4014 if (spapr_dt_phb(spapr
, sphb
, intc_phandle
, fdt
, fdt_start_offset
)) {
4015 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
4019 /* generally SLOF creates these, for hotplug it's up to QEMU */
4020 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
4025 static bool spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4028 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4029 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4030 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4031 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
4034 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
4035 error_setg(errp
, "PHB hotplug not supported for this machine");
4039 if (sphb
->index
== (uint32_t)-1) {
4040 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
4044 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4045 if (drc
&& drc
->dev
) {
4046 error_setg(errp
, "PHB %d already attached", sphb
->index
);
4051 * This will check that sphb->index doesn't exceed the maximum number of
4052 * PHBs for the current machine type.
4055 smc
->phb_placement(spapr
, sphb
->index
,
4056 &sphb
->buid
, &sphb
->io_win_addr
,
4057 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
4058 windows_supported
, sphb
->dma_liobn
,
4059 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
4063 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4065 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4066 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4067 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4069 bool hotplugged
= spapr_drc_hotplugged(dev
);
4071 if (!smc
->dr_phb_enabled
) {
4075 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4076 /* hotplug hooks should check it's enabled before getting this far */
4079 /* spapr_phb_pre_plug() already checked the DRC is attachable */
4080 spapr_drc_attach(drc
, dev
);
4083 spapr_hotplug_req_add_by_index(drc
);
4085 spapr_drc_reset(drc
);
4089 void spapr_phb_release(DeviceState
*dev
)
4091 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
4093 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
4094 object_unparent(OBJECT(dev
));
4097 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4099 qdev_unrealize(dev
);
4102 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4103 DeviceState
*dev
, Error
**errp
)
4105 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4108 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4111 if (!spapr_drc_unplug_requested(drc
)) {
4112 spapr_drc_unplug_request(drc
);
4113 spapr_hotplug_req_remove_by_index(drc
);
4116 "PCI Host Bridge unplug already in progress for device %s",
4122 bool spapr_tpm_proxy_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4125 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4127 if (spapr
->tpm_proxy
!= NULL
) {
4128 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4135 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4137 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4138 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4140 /* Already checked in spapr_tpm_proxy_pre_plug() */
4141 g_assert(spapr
->tpm_proxy
== NULL
);
4143 spapr
->tpm_proxy
= tpm_proxy
;
4146 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4148 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4150 qdev_unrealize(dev
);
4151 object_unparent(OBJECT(dev
));
4152 spapr
->tpm_proxy
= NULL
;
4155 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4156 DeviceState
*dev
, Error
**errp
)
4158 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4159 spapr_memory_plug(hotplug_dev
, dev
);
4160 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4161 spapr_core_plug(hotplug_dev
, dev
);
4162 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4163 spapr_phb_plug(hotplug_dev
, dev
);
4164 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4165 spapr_tpm_proxy_plug(hotplug_dev
, dev
);
4169 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4170 DeviceState
*dev
, Error
**errp
)
4172 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4173 spapr_memory_unplug(hotplug_dev
, dev
);
4174 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4175 spapr_core_unplug(hotplug_dev
, dev
);
4176 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4177 spapr_phb_unplug(hotplug_dev
, dev
);
4178 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4179 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4183 bool spapr_memory_hot_unplug_supported(SpaprMachineState
*spapr
)
4185 return spapr_ovec_test(spapr
->ov5_cas
, OV5_HP_EVT
) ||
4187 * CAS will process all pending unplug requests.
4189 * HACK: a guest could theoretically have cleared all bits in OV5,
4190 * but none of the guests we care for do.
4192 spapr_ovec_empty(spapr
->ov5_cas
);
4195 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4196 DeviceState
*dev
, Error
**errp
)
4198 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4199 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4200 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4202 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4203 if (spapr_memory_hot_unplug_supported(sms
)) {
4204 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4206 error_setg(errp
, "Memory hot unplug not supported for this guest");
4208 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4209 if (!mc
->has_hotpluggable_cpus
) {
4210 error_setg(errp
, "CPU hot unplug not supported on this machine");
4213 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4214 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4215 if (!smc
->dr_phb_enabled
) {
4216 error_setg(errp
, "PHB hot unplug not supported on this machine");
4219 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4220 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4221 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4225 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4226 DeviceState
*dev
, Error
**errp
)
4228 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4229 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4230 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4231 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4232 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4233 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4234 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4235 spapr_tpm_proxy_pre_plug(hotplug_dev
, dev
, errp
);
4239 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4242 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4243 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4244 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4245 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4246 return HOTPLUG_HANDLER(machine
);
4248 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4249 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4250 PCIBus
*root
= pci_device_root_bus(pcidev
);
4251 SpaprPhbState
*phb
=
4252 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4253 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4256 return HOTPLUG_HANDLER(phb
);
4262 static CpuInstanceProperties
4263 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4265 CPUArchId
*core_slot
;
4266 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4268 /* make sure possible_cpu are intialized */
4269 mc
->possible_cpu_arch_ids(machine
);
4270 /* get CPU core slot containing thread that matches cpu_index */
4271 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4273 return core_slot
->props
;
4276 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4278 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4281 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4284 unsigned int smp_threads
= machine
->smp
.threads
;
4285 unsigned int smp_cpus
= machine
->smp
.cpus
;
4286 const char *core_type
;
4287 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4288 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4290 if (!mc
->has_hotpluggable_cpus
) {
4291 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4293 if (machine
->possible_cpus
) {
4294 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4295 return machine
->possible_cpus
;
4298 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4300 error_report("Unable to find sPAPR CPU Core definition");
4304 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4305 sizeof(CPUArchId
) * spapr_max_cores
);
4306 machine
->possible_cpus
->len
= spapr_max_cores
;
4307 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4308 int core_id
= i
* smp_threads
;
4310 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4311 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4312 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4313 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4314 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4316 return machine
->possible_cpus
;
4319 static bool spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4320 uint64_t *buid
, hwaddr
*pio
,
4321 hwaddr
*mmio32
, hwaddr
*mmio64
,
4322 unsigned n_dma
, uint32_t *liobns
,
4323 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4326 * New-style PHB window placement.
4328 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4329 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4332 * Some guest kernels can't work with MMIO windows above 1<<46
4333 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4335 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4336 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4337 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4338 * 1TiB 64-bit MMIO windows for each PHB.
4340 const uint64_t base_buid
= 0x800000020000000ULL
;
4343 /* Sanity check natural alignments */
4344 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4345 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4346 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4347 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4348 /* Sanity check bounds */
4349 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4350 SPAPR_PCI_MEM32_WIN_SIZE
);
4351 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4352 SPAPR_PCI_MEM64_WIN_SIZE
);
4354 if (index
>= SPAPR_MAX_PHBS
) {
4355 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4356 SPAPR_MAX_PHBS
- 1);
4360 *buid
= base_buid
+ index
;
4361 for (i
= 0; i
< n_dma
; ++i
) {
4362 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4365 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4366 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4367 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4369 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4370 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4374 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4376 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4378 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4381 static void spapr_ics_resend(XICSFabric
*dev
)
4383 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4385 ics_resend(spapr
->ics
);
4388 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4390 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4392 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4395 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4398 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4400 spapr_irq_print_info(spapr
, mon
);
4401 monitor_printf(mon
, "irqchip: %s\n",
4402 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4406 * This is a XIVE only operation
4408 static int spapr_match_nvt(XiveFabric
*xfb
, uint8_t format
,
4409 uint8_t nvt_blk
, uint32_t nvt_idx
,
4410 bool cam_ignore
, uint8_t priority
,
4411 uint32_t logic_serv
, XiveTCTXMatch
*match
)
4413 SpaprMachineState
*spapr
= SPAPR_MACHINE(xfb
);
4414 XivePresenter
*xptr
= XIVE_PRESENTER(spapr
->active_intc
);
4415 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
4418 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
4419 priority
, logic_serv
, match
);
4425 * When we implement the save and restore of the thread interrupt
4426 * contexts in the enter/exit CPU handlers of the machine and the
4427 * escalations in QEMU, we should be able to handle non dispatched
4430 * Until this is done, the sPAPR machine should find at least one
4431 * matching context always.
4434 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is not dispatched\n",
4441 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4443 return cpu
->vcpu_id
;
4446 bool spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4448 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4449 MachineState
*ms
= MACHINE(spapr
);
4452 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4454 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4455 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4456 error_append_hint(errp
, "Adjust the number of cpus to %d "
4457 "or try to raise the number of threads per core\n",
4458 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4462 cpu
->vcpu_id
= vcpu_id
;
4466 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4471 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4473 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4481 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4483 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4485 /* These are only called by TCG, KVM maintains dispatch state */
4487 spapr_cpu
->prod
= false;
4488 if (spapr_cpu
->vpa_addr
) {
4489 CPUState
*cs
= CPU(cpu
);
4492 dispatch
= ldl_be_phys(cs
->as
,
4493 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4495 if ((dispatch
& 1) != 0) {
4496 qemu_log_mask(LOG_GUEST_ERROR
,
4497 "VPA: incorrect dispatch counter value for "
4498 "dispatched partition %u, correcting.\n", dispatch
);
4502 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4506 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4508 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4510 if (spapr_cpu
->vpa_addr
) {
4511 CPUState
*cs
= CPU(cpu
);
4514 dispatch
= ldl_be_phys(cs
->as
,
4515 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4517 if ((dispatch
& 1) != 1) {
4518 qemu_log_mask(LOG_GUEST_ERROR
,
4519 "VPA: incorrect dispatch counter value for "
4520 "preempted partition %u, correcting.\n", dispatch
);
4524 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4528 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4530 MachineClass
*mc
= MACHINE_CLASS(oc
);
4531 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4532 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4533 NMIClass
*nc
= NMI_CLASS(oc
);
4534 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4535 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4536 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4537 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4538 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
4539 VofMachineIfClass
*vmc
= VOF_MACHINE_CLASS(oc
);
4541 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4542 mc
->ignore_boot_device_suffixes
= true;
4545 * We set up the default / latest behaviour here. The class_init
4546 * functions for the specific versioned machine types can override
4547 * these details for backwards compatibility
4549 mc
->init
= spapr_machine_init
;
4550 mc
->reset
= spapr_machine_reset
;
4551 mc
->block_default_type
= IF_SCSI
;
4554 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values
4555 * should be limited by the host capability instead of hardcoded.
4556 * max_cpus for KVM guests will be checked in kvm_init(), and TCG
4557 * guests are welcome to have as many CPUs as the host are capable
4560 mc
->max_cpus
= INT32_MAX
;
4562 mc
->no_parallel
= 1;
4563 mc
->default_boot_order
= "";
4564 mc
->default_ram_size
= 512 * MiB
;
4565 mc
->default_ram_id
= "ppc_spapr.ram";
4566 mc
->default_display
= "std";
4567 mc
->kvm_type
= spapr_kvm_type
;
4568 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4569 mc
->pci_allow_0_address
= true;
4570 assert(!mc
->get_hotplug_handler
);
4571 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4572 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4573 hc
->plug
= spapr_machine_device_plug
;
4574 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4575 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4576 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4577 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4578 hc
->unplug
= spapr_machine_device_unplug
;
4580 smc
->dr_lmb_enabled
= true;
4581 smc
->update_dt_enabled
= true;
4582 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4583 mc
->has_hotpluggable_cpus
= true;
4584 mc
->nvdimm_supported
= true;
4585 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4586 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4587 nc
->nmi_monitor_handler
= spapr_nmi
;
4588 smc
->phb_placement
= spapr_phb_placement
;
4589 vhc
->hypercall
= emulate_spapr_hypercall
;
4590 vhc
->hpt_mask
= spapr_hpt_mask
;
4591 vhc
->map_hptes
= spapr_map_hptes
;
4592 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4593 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4594 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4595 vhc
->get_pate
= spapr_get_pate
;
4596 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4597 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4598 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4599 xic
->ics_get
= spapr_ics_get
;
4600 xic
->ics_resend
= spapr_ics_resend
;
4601 xic
->icp_get
= spapr_icp_get
;
4602 ispc
->print_info
= spapr_pic_print_info
;
4603 /* Force NUMA node memory size to be a multiple of
4604 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4605 * in which LMBs are represented and hot-added
4607 mc
->numa_mem_align_shift
= 28;
4608 mc
->auto_enable_numa
= true;
4610 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4611 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4612 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4613 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4614 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4615 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4616 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4617 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4618 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4619 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_ON
;
4620 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_ON
;
4621 spapr_caps_add_properties(smc
);
4622 smc
->irq
= &spapr_irq_dual
;
4623 smc
->dr_phb_enabled
= true;
4624 smc
->linux_pci_probe
= true;
4625 smc
->smp_threads_vsmt
= true;
4626 smc
->nr_xirqs
= SPAPR_NR_XIRQS
;
4627 xfc
->match_nvt
= spapr_match_nvt
;
4628 vmc
->client_architecture_support
= spapr_vof_client_architecture_support
;
4629 vmc
->quiesce
= spapr_vof_quiesce
;
4630 vmc
->setprop
= spapr_vof_setprop
;
4633 static const TypeInfo spapr_machine_info
= {
4634 .name
= TYPE_SPAPR_MACHINE
,
4635 .parent
= TYPE_MACHINE
,
4637 .instance_size
= sizeof(SpaprMachineState
),
4638 .instance_init
= spapr_instance_init
,
4639 .instance_finalize
= spapr_machine_finalizefn
,
4640 .class_size
= sizeof(SpaprMachineClass
),
4641 .class_init
= spapr_machine_class_init
,
4642 .interfaces
= (InterfaceInfo
[]) {
4643 { TYPE_FW_PATH_PROVIDER
},
4645 { TYPE_HOTPLUG_HANDLER
},
4646 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4647 { TYPE_XICS_FABRIC
},
4648 { TYPE_INTERRUPT_STATS_PROVIDER
},
4649 { TYPE_XIVE_FABRIC
},
4650 { TYPE_VOF_MACHINE_IF
},
4655 static void spapr_machine_latest_class_options(MachineClass
*mc
)
4657 mc
->alias
= "pseries";
4658 mc
->is_default
= true;
4661 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4662 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4665 MachineClass *mc = MACHINE_CLASS(oc); \
4666 spapr_machine_##suffix##_class_options(mc); \
4668 spapr_machine_latest_class_options(mc); \
4671 static const TypeInfo spapr_machine_##suffix##_info = { \
4672 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4673 .parent = TYPE_SPAPR_MACHINE, \
4674 .class_init = spapr_machine_##suffix##_class_init, \
4676 static void spapr_machine_register_##suffix(void) \
4678 type_register(&spapr_machine_##suffix##_info); \
4680 type_init(spapr_machine_register_##suffix)
4685 static void spapr_machine_6_1_class_options(MachineClass
*mc
)
4687 /* Defaults for the latest behaviour inherited from the base class */
4690 DEFINE_SPAPR_MACHINE(6_1
, "6.1", true);
4695 static void spapr_machine_6_0_class_options(MachineClass
*mc
)
4697 spapr_machine_6_1_class_options(mc
);
4698 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
4701 DEFINE_SPAPR_MACHINE(6_0
, "6.0", false);
4706 static void spapr_machine_5_2_class_options(MachineClass
*mc
)
4708 spapr_machine_6_0_class_options(mc
);
4709 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
4712 DEFINE_SPAPR_MACHINE(5_2
, "5.2", false);
4717 static void spapr_machine_5_1_class_options(MachineClass
*mc
)
4719 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4721 spapr_machine_5_2_class_options(mc
);
4722 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
4723 smc
->pre_5_2_numa_associativity
= true;
4726 DEFINE_SPAPR_MACHINE(5_1
, "5.1", false);
4731 static void spapr_machine_5_0_class_options(MachineClass
*mc
)
4733 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4734 static GlobalProperty compat
[] = {
4735 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-5.1-associativity", "on" },
4738 spapr_machine_5_1_class_options(mc
);
4739 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
4740 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4741 mc
->numa_mem_supported
= true;
4742 smc
->pre_5_1_assoc_refpoints
= true;
4745 DEFINE_SPAPR_MACHINE(5_0
, "5.0", false);
4750 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4752 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4754 spapr_machine_5_0_class_options(mc
);
4755 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
4756 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4757 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_OFF
;
4758 smc
->rma_limit
= 16 * GiB
;
4759 mc
->nvdimm_supported
= false;
4762 DEFINE_SPAPR_MACHINE(4_2
, "4.2", false);
4767 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4769 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4770 static GlobalProperty compat
[] = {
4771 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4772 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4775 spapr_machine_4_2_class_options(mc
);
4776 smc
->linux_pci_probe
= false;
4777 smc
->smp_threads_vsmt
= false;
4778 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4779 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4782 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4787 static bool phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4788 uint64_t *buid
, hwaddr
*pio
,
4789 hwaddr
*mmio32
, hwaddr
*mmio64
,
4790 unsigned n_dma
, uint32_t *liobns
,
4791 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4793 if (!spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
,
4794 liobns
, nv2gpa
, nv2atsd
, errp
)) {
4802 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4804 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4806 spapr_machine_4_1_class_options(mc
);
4807 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4808 smc
->phb_placement
= phb_placement_4_0
;
4809 smc
->irq
= &spapr_irq_xics
;
4810 smc
->pre_4_1_migration
= true;
4813 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4818 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4820 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4822 spapr_machine_4_0_class_options(mc
);
4823 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4825 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4826 smc
->update_dt_enabled
= false;
4827 smc
->dr_phb_enabled
= false;
4828 smc
->broken_host_serial_model
= true;
4829 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4830 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4831 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4832 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4835 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4841 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4843 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4845 spapr_machine_3_1_class_options(mc
);
4846 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4848 smc
->legacy_irq_allocation
= true;
4849 smc
->nr_xirqs
= 0x400;
4850 smc
->irq
= &spapr_irq_xics_legacy
;
4853 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4858 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4860 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4861 static GlobalProperty compat
[] = {
4862 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4863 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4866 spapr_machine_3_0_class_options(mc
);
4867 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4868 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4870 /* We depend on kvm_enabled() to choose a default value for the
4871 * hpt-max-page-size capability. Of course we can't do it here
4872 * because this is too early and the HW accelerator isn't initialzed
4873 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4875 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4878 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4880 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4882 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4884 spapr_machine_2_12_class_options(mc
);
4885 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4886 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4887 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4890 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4896 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4898 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4900 spapr_machine_2_12_class_options(mc
);
4901 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4902 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4905 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4911 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4913 spapr_machine_2_11_class_options(mc
);
4914 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4917 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4923 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4925 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4926 static GlobalProperty compat
[] = {
4927 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4930 spapr_machine_2_10_class_options(mc
);
4931 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4932 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4933 smc
->pre_2_10_has_unused_icps
= true;
4934 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4937 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4943 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4945 static GlobalProperty compat
[] = {
4946 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4949 spapr_machine_2_9_class_options(mc
);
4950 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4951 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4952 mc
->numa_mem_align_shift
= 23;
4955 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4961 static bool phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4962 uint64_t *buid
, hwaddr
*pio
,
4963 hwaddr
*mmio32
, hwaddr
*mmio64
,
4964 unsigned n_dma
, uint32_t *liobns
,
4965 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4967 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4968 const uint64_t base_buid
= 0x800000020000000ULL
;
4969 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4970 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4971 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4972 const uint32_t max_index
= 255;
4973 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4975 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4976 hwaddr phb0_base
, phb_base
;
4979 /* Do we have device memory? */
4980 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4981 /* Can't just use maxram_size, because there may be an
4982 * alignment gap between normal and device memory regions
4984 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4985 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4988 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4990 if (index
> max_index
) {
4991 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4996 *buid
= base_buid
+ index
;
4997 for (i
= 0; i
< n_dma
; ++i
) {
4998 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
5001 phb_base
= phb0_base
+ index
* phb_spacing
;
5002 *pio
= phb_base
+ pio_offset
;
5003 *mmio32
= phb_base
+ mmio_offset
;
5005 * We don't set the 64-bit MMIO window, relying on the PHB's
5006 * fallback behaviour of automatically splitting a large "32-bit"
5007 * window into contiguous 32-bit and 64-bit windows
5015 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
5017 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5018 static GlobalProperty compat
[] = {
5019 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
5020 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
5021 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
5022 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
5025 spapr_machine_2_8_class_options(mc
);
5026 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
5027 mc
->default_machine_opts
= "modern-hotplug-events=off";
5028 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
5029 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5030 smc
->phb_placement
= phb_placement_2_7
;
5033 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
5039 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
5041 static GlobalProperty compat
[] = {
5042 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
5045 spapr_machine_2_7_class_options(mc
);
5046 mc
->has_hotpluggable_cpus
= false;
5047 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
5048 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5051 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
5057 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
5059 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5060 static GlobalProperty compat
[] = {
5061 { "spapr-vlan", "use-rx-buffer-pools", "off" },
5064 spapr_machine_2_6_class_options(mc
);
5065 smc
->use_ohci_by_default
= true;
5066 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
5067 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5070 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
5076 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
5078 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5080 spapr_machine_2_5_class_options(mc
);
5081 smc
->dr_lmb_enabled
= false;
5082 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
5085 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
5091 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
5093 static GlobalProperty compat
[] = {
5094 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
5096 spapr_machine_2_4_class_options(mc
);
5097 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
5098 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5100 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
5106 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
5108 static GlobalProperty compat
[] = {
5109 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
5112 spapr_machine_2_3_class_options(mc
);
5113 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
5114 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5115 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
5117 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
5123 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
5125 spapr_machine_2_2_class_options(mc
);
5126 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
5128 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
5130 static void spapr_machine_register_types(void)
5132 type_register_static(&spapr_machine_info
);
5135 type_init(spapr_machine_register_types
)