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hw/ppc/spapr: Move code related to "ibm,pa-features" to a separate function
[mirror_qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/device_tree.h"
41 #include "kvm_ppc.h"
42 #include "migration/migration.h"
43 #include "mmu-hash64.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
56
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
60
61 #include "exec/address-spaces.h"
62 #include "hw/usb.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
65 #include "trace.h"
66 #include "hw/nmi.h"
67
68 #include "hw/compat.h"
69 #include "qemu/cutils.h"
70 #include "hw/ppc/spapr_cpu_core.h"
71 #include "qmp-commands.h"
72
73 #include <libfdt.h>
74
75 /* SLOF memory layout:
76 *
77 * SLOF raw image loaded at 0, copies its romfs right below the flat
78 * device-tree, then position SLOF itself 31M below that
79 *
80 * So we set FW_OVERHEAD to 40MB which should account for all of that
81 * and more
82 *
83 * We load our kernel at 4M, leaving space for SLOF initial image
84 */
85 #define FDT_MAX_SIZE 0x100000
86 #define RTAS_MAX_SIZE 0x10000
87 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
88 #define FW_MAX_SIZE 0x400000
89 #define FW_FILE_NAME "slof.bin"
90 #define FW_OVERHEAD 0x2800000
91 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
92
93 #define MIN_RMA_SLOF 128UL
94
95 #define PHANDLE_XICP 0x00001111
96
97 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
98
99 static XICSState *try_create_xics(const char *type, int nr_servers,
100 int nr_irqs, Error **errp)
101 {
102 Error *err = NULL;
103 DeviceState *dev;
104
105 dev = qdev_create(NULL, type);
106 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
107 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
108 object_property_set_bool(OBJECT(dev), true, "realized", &err);
109 if (err) {
110 error_propagate(errp, err);
111 object_unparent(OBJECT(dev));
112 return NULL;
113 }
114 return XICS_COMMON(dev);
115 }
116
117 static XICSState *xics_system_init(MachineState *machine,
118 int nr_servers, int nr_irqs, Error **errp)
119 {
120 XICSState *xics = NULL;
121
122 if (kvm_enabled()) {
123 Error *err = NULL;
124
125 if (machine_kernel_irqchip_allowed(machine)) {
126 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
127 &err);
128 }
129 if (machine_kernel_irqchip_required(machine) && !xics) {
130 error_reportf_err(err,
131 "kernel_irqchip requested but unavailable: ");
132 } else {
133 error_free(err);
134 }
135 }
136
137 if (!xics) {
138 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
139 }
140
141 return xics;
142 }
143
144 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
145 int smt_threads)
146 {
147 int i, ret = 0;
148 uint32_t servers_prop[smt_threads];
149 uint32_t gservers_prop[smt_threads * 2];
150 int index = ppc_get_vcpu_dt_id(cpu);
151
152 if (cpu->cpu_version) {
153 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
154 if (ret < 0) {
155 return ret;
156 }
157 }
158
159 /* Build interrupt servers and gservers properties */
160 for (i = 0; i < smt_threads; i++) {
161 servers_prop[i] = cpu_to_be32(index + i);
162 /* Hack, direct the group queues back to cpu 0 */
163 gservers_prop[i*2] = cpu_to_be32(index + i);
164 gservers_prop[i*2 + 1] = 0;
165 }
166 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
167 servers_prop, sizeof(servers_prop));
168 if (ret < 0) {
169 return ret;
170 }
171 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
172 gservers_prop, sizeof(gservers_prop));
173
174 return ret;
175 }
176
177 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
178 {
179 int ret = 0;
180 PowerPCCPU *cpu = POWERPC_CPU(cs);
181 int index = ppc_get_vcpu_dt_id(cpu);
182 uint32_t associativity[] = {cpu_to_be32(0x5),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(0x0),
186 cpu_to_be32(cs->numa_node),
187 cpu_to_be32(index)};
188
189 /* Advertise NUMA via ibm,associativity */
190 if (nb_numa_nodes > 1) {
191 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
192 sizeof(associativity));
193 }
194
195 return ret;
196 }
197
198 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
199 {
200 int ret = 0, offset, cpus_offset;
201 CPUState *cs;
202 char cpu_model[32];
203 int smt = kvmppc_smt_threads();
204 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
205
206 CPU_FOREACH(cs) {
207 PowerPCCPU *cpu = POWERPC_CPU(cs);
208 DeviceClass *dc = DEVICE_GET_CLASS(cs);
209 int index = ppc_get_vcpu_dt_id(cpu);
210
211 if ((index % smt) != 0) {
212 continue;
213 }
214
215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
216
217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
231 }
232
233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
235 if (ret < 0) {
236 return ret;
237 }
238
239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
245 ppc_get_compat_smt_threads(cpu));
246 if (ret < 0) {
247 return ret;
248 }
249 }
250 return ret;
251 }
252
253 static hwaddr spapr_node0_size(void)
254 {
255 MachineState *machine = MACHINE(qdev_get_machine());
256
257 if (nb_numa_nodes) {
258 int i;
259 for (i = 0; i < nb_numa_nodes; ++i) {
260 if (numa_info[i].node_mem) {
261 return MIN(pow2floor(numa_info[i].node_mem),
262 machine->ram_size);
263 }
264 }
265 }
266 return machine->ram_size;
267 }
268
269 static void add_str(GString *s, const gchar *s1)
270 {
271 g_string_append_len(s, s1, strlen(s1) + 1);
272 }
273
274 static void *spapr_create_fdt_skel(hwaddr initrd_base,
275 hwaddr initrd_size,
276 hwaddr kernel_size,
277 bool little_endian,
278 const char *kernel_cmdline,
279 uint32_t epow_irq)
280 {
281 void *fdt;
282 uint32_t start_prop = cpu_to_be32(initrd_base);
283 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
284 GString *hypertas = g_string_sized_new(256);
285 GString *qemu_hypertas = g_string_sized_new(256);
286 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
287 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
288 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
289 char *buf;
290
291 add_str(hypertas, "hcall-pft");
292 add_str(hypertas, "hcall-term");
293 add_str(hypertas, "hcall-dabr");
294 add_str(hypertas, "hcall-interrupt");
295 add_str(hypertas, "hcall-tce");
296 add_str(hypertas, "hcall-vio");
297 add_str(hypertas, "hcall-splpar");
298 add_str(hypertas, "hcall-bulk");
299 add_str(hypertas, "hcall-set-mode");
300 add_str(hypertas, "hcall-sprg0");
301 add_str(hypertas, "hcall-copy");
302 add_str(hypertas, "hcall-debug");
303 add_str(qemu_hypertas, "hcall-memop1");
304
305 fdt = g_malloc0(FDT_MAX_SIZE);
306 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
307
308 if (kernel_size) {
309 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
310 }
311 if (initrd_size) {
312 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
313 }
314 _FDT((fdt_finish_reservemap(fdt)));
315
316 /* Root node */
317 _FDT((fdt_begin_node(fdt, "")));
318 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
319 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
320 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
321
322 /*
323 * Add info to guest to indentify which host is it being run on
324 * and what is the uuid of the guest
325 */
326 if (kvmppc_get_host_model(&buf)) {
327 _FDT((fdt_property_string(fdt, "host-model", buf)));
328 g_free(buf);
329 }
330 if (kvmppc_get_host_serial(&buf)) {
331 _FDT((fdt_property_string(fdt, "host-serial", buf)));
332 g_free(buf);
333 }
334
335 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
336
337 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
338 if (qemu_uuid_set) {
339 _FDT((fdt_property_string(fdt, "system-id", buf)));
340 }
341 g_free(buf);
342
343 if (qemu_get_vm_name()) {
344 _FDT((fdt_property_string(fdt, "ibm,partition-name",
345 qemu_get_vm_name())));
346 }
347
348 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
349 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
350
351 /* /chosen */
352 _FDT((fdt_begin_node(fdt, "chosen")));
353
354 /* Set Form1_affinity */
355 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
356
357 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
358 _FDT((fdt_property(fdt, "linux,initrd-start",
359 &start_prop, sizeof(start_prop))));
360 _FDT((fdt_property(fdt, "linux,initrd-end",
361 &end_prop, sizeof(end_prop))));
362 if (kernel_size) {
363 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
364 cpu_to_be64(kernel_size) };
365
366 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
367 if (little_endian) {
368 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
369 }
370 }
371 if (boot_menu) {
372 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
373 }
374 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
375 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
376 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
377
378 _FDT((fdt_end_node(fdt)));
379
380 /* RTAS */
381 _FDT((fdt_begin_node(fdt, "rtas")));
382
383 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
384 add_str(hypertas, "hcall-multi-tce");
385 }
386 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
387 hypertas->len)));
388 g_string_free(hypertas, TRUE);
389 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
390 qemu_hypertas->len)));
391 g_string_free(qemu_hypertas, TRUE);
392
393 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
394 refpoints, sizeof(refpoints))));
395
396 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
397 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
398 RTAS_EVENT_SCAN_RATE)));
399
400 if (msi_nonbroken) {
401 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
402 }
403
404 /*
405 * According to PAPR, rtas ibm,os-term does not guarantee a return
406 * back to the guest cpu.
407 *
408 * While an additional ibm,extended-os-term property indicates that
409 * rtas call return will always occur. Set this property.
410 */
411 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
412
413 _FDT((fdt_end_node(fdt)));
414
415 /* interrupt controller */
416 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
417
418 _FDT((fdt_property_string(fdt, "device_type",
419 "PowerPC-External-Interrupt-Presentation")));
420 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
421 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
422 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
423 interrupt_server_ranges_prop,
424 sizeof(interrupt_server_ranges_prop))));
425 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
426 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
427 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
428
429 _FDT((fdt_end_node(fdt)));
430
431 /* vdevice */
432 _FDT((fdt_begin_node(fdt, "vdevice")));
433
434 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
435 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
436 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
437 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
438 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
439 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
440
441 _FDT((fdt_end_node(fdt)));
442
443 /* event-sources */
444 spapr_events_fdt_skel(fdt, epow_irq);
445
446 /* /hypervisor node */
447 if (kvm_enabled()) {
448 uint8_t hypercall[16];
449
450 /* indicate KVM hypercall interface */
451 _FDT((fdt_begin_node(fdt, "hypervisor")));
452 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
453 if (kvmppc_has_cap_fixup_hcalls()) {
454 /*
455 * Older KVM versions with older guest kernels were broken with the
456 * magic page, don't allow the guest to map it.
457 */
458 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
459 sizeof(hypercall))) {
460 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
461 sizeof(hypercall))));
462 }
463 }
464 _FDT((fdt_end_node(fdt)));
465 }
466
467 _FDT((fdt_end_node(fdt))); /* close root node */
468 _FDT((fdt_finish(fdt)));
469
470 return fdt;
471 }
472
473 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
474 hwaddr size)
475 {
476 uint32_t associativity[] = {
477 cpu_to_be32(0x4), /* length */
478 cpu_to_be32(0x0), cpu_to_be32(0x0),
479 cpu_to_be32(0x0), cpu_to_be32(nodeid)
480 };
481 char mem_name[32];
482 uint64_t mem_reg_property[2];
483 int off;
484
485 mem_reg_property[0] = cpu_to_be64(start);
486 mem_reg_property[1] = cpu_to_be64(size);
487
488 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
489 off = fdt_add_subnode(fdt, 0, mem_name);
490 _FDT(off);
491 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
492 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
493 sizeof(mem_reg_property))));
494 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
495 sizeof(associativity))));
496 return off;
497 }
498
499 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
500 {
501 MachineState *machine = MACHINE(spapr);
502 hwaddr mem_start, node_size;
503 int i, nb_nodes = nb_numa_nodes;
504 NodeInfo *nodes = numa_info;
505 NodeInfo ramnode;
506
507 /* No NUMA nodes, assume there is just one node with whole RAM */
508 if (!nb_numa_nodes) {
509 nb_nodes = 1;
510 ramnode.node_mem = machine->ram_size;
511 nodes = &ramnode;
512 }
513
514 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
515 if (!nodes[i].node_mem) {
516 continue;
517 }
518 if (mem_start >= machine->ram_size) {
519 node_size = 0;
520 } else {
521 node_size = nodes[i].node_mem;
522 if (node_size > machine->ram_size - mem_start) {
523 node_size = machine->ram_size - mem_start;
524 }
525 }
526 if (!mem_start) {
527 /* ppc_spapr_init() checks for rma_size <= node0_size already */
528 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
529 mem_start += spapr->rma_size;
530 node_size -= spapr->rma_size;
531 }
532 for ( ; node_size; ) {
533 hwaddr sizetmp = pow2floor(node_size);
534
535 /* mem_start != 0 here */
536 if (ctzl(mem_start) < ctzl(sizetmp)) {
537 sizetmp = 1ULL << ctzl(mem_start);
538 }
539
540 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
541 node_size -= sizetmp;
542 mem_start += sizetmp;
543 }
544 }
545
546 return 0;
547 }
548
549 /* Populate the "ibm,pa-features" property */
550 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
551 {
552 uint8_t pa_features_206[] = { 6, 0,
553 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
554 uint8_t pa_features_207[] = { 24, 0,
555 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
556 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
557 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
558 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
559 uint8_t *pa_features;
560 size_t pa_size;
561
562 if (env->mmu_model == POWERPC_MMU_2_06) {
563 pa_features = pa_features_206;
564 pa_size = sizeof(pa_features_206);
565 } else { /* env->mmu_model == POWERPC_MMU_2_07 */
566 pa_features = pa_features_207;
567 pa_size = sizeof(pa_features_207);
568 }
569
570 if (env->ci_large_pages) {
571 /*
572 * Note: we keep CI large pages off by default because a 64K capable
573 * guest provisioned with large pages might otherwise try to map a qemu
574 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
575 * even if that qemu runs on a 4k host.
576 * We dd this bit back here if we are confident this is not an issue
577 */
578 pa_features[3] |= 0x20;
579 }
580
581 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
582 }
583
584 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
585 sPAPRMachineState *spapr)
586 {
587 PowerPCCPU *cpu = POWERPC_CPU(cs);
588 CPUPPCState *env = &cpu->env;
589 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
590 int index = ppc_get_vcpu_dt_id(cpu);
591 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
592 0xffffffff, 0xffffffff};
593 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
594 : SPAPR_TIMEBASE_FREQ;
595 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
596 uint32_t page_sizes_prop[64];
597 size_t page_sizes_prop_size;
598 uint32_t vcpus_per_socket = smp_threads * smp_cores;
599 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
600 sPAPRDRConnector *drc;
601 sPAPRDRConnectorClass *drck;
602 int drc_index;
603
604 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
605 if (drc) {
606 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
607 drc_index = drck->get_index(drc);
608 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
609 }
610
611 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
612 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
613
614 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
615 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
616 env->dcache_line_size)));
617 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
618 env->dcache_line_size)));
619 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
620 env->icache_line_size)));
621 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
622 env->icache_line_size)));
623
624 if (pcc->l1_dcache_size) {
625 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
626 pcc->l1_dcache_size)));
627 } else {
628 error_report("Warning: Unknown L1 dcache size for cpu");
629 }
630 if (pcc->l1_icache_size) {
631 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
632 pcc->l1_icache_size)));
633 } else {
634 error_report("Warning: Unknown L1 icache size for cpu");
635 }
636
637 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
638 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
639 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
640 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
641 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
642 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
643
644 if (env->spr_cb[SPR_PURR].oea_read) {
645 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
646 }
647
648 if (env->mmu_model & POWERPC_MMU_1TSEG) {
649 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
650 segs, sizeof(segs))));
651 }
652
653 /* Advertise VMX/VSX (vector extensions) if available
654 * 0 / no property == no vector extensions
655 * 1 == VMX / Altivec available
656 * 2 == VSX available */
657 if (env->insns_flags & PPC_ALTIVEC) {
658 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
659
660 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
661 }
662
663 /* Advertise DFP (Decimal Floating Point) if available
664 * 0 / no property == no DFP
665 * 1 == DFP available */
666 if (env->insns_flags2 & PPC2_DFP) {
667 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
668 }
669
670 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
671 sizeof(page_sizes_prop));
672 if (page_sizes_prop_size) {
673 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
674 page_sizes_prop, page_sizes_prop_size)));
675 }
676
677 spapr_populate_pa_features(env, fdt, offset);
678
679 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
680 cs->cpu_index / vcpus_per_socket)));
681
682 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
683 pft_size_prop, sizeof(pft_size_prop))));
684
685 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
686
687 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
688 ppc_get_compat_smt_threads(cpu)));
689 }
690
691 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
692 {
693 CPUState *cs;
694 int cpus_offset;
695 char *nodename;
696 int smt = kvmppc_smt_threads();
697
698 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
699 _FDT(cpus_offset);
700 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
701 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
702
703 /*
704 * We walk the CPUs in reverse order to ensure that CPU DT nodes
705 * created by fdt_add_subnode() end up in the right order in FDT
706 * for the guest kernel the enumerate the CPUs correctly.
707 */
708 CPU_FOREACH_REVERSE(cs) {
709 PowerPCCPU *cpu = POWERPC_CPU(cs);
710 int index = ppc_get_vcpu_dt_id(cpu);
711 DeviceClass *dc = DEVICE_GET_CLASS(cs);
712 int offset;
713
714 if ((index % smt) != 0) {
715 continue;
716 }
717
718 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
719 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
720 g_free(nodename);
721 _FDT(offset);
722 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
723 }
724
725 }
726
727 /*
728 * Adds ibm,dynamic-reconfiguration-memory node.
729 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
730 * of this device tree node.
731 */
732 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
733 {
734 MachineState *machine = MACHINE(spapr);
735 int ret, i, offset;
736 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
737 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
738 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
739 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
740 memory_region_size(&spapr->hotplug_memory.mr)) /
741 lmb_size;
742 uint32_t *int_buf, *cur_index, buf_len;
743 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
744
745 /*
746 * Don't create the node if there is no hotpluggable memory
747 */
748 if (machine->ram_size == machine->maxram_size) {
749 return 0;
750 }
751
752 /*
753 * Allocate enough buffer size to fit in ibm,dynamic-memory
754 * or ibm,associativity-lookup-arrays
755 */
756 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
757 * sizeof(uint32_t);
758 cur_index = int_buf = g_malloc0(buf_len);
759
760 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
761
762 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
763 sizeof(prop_lmb_size));
764 if (ret < 0) {
765 goto out;
766 }
767
768 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
769 if (ret < 0) {
770 goto out;
771 }
772
773 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
774 if (ret < 0) {
775 goto out;
776 }
777
778 /* ibm,dynamic-memory */
779 int_buf[0] = cpu_to_be32(nr_lmbs);
780 cur_index++;
781 for (i = 0; i < nr_lmbs; i++) {
782 uint64_t addr = i * lmb_size;
783 uint32_t *dynamic_memory = cur_index;
784
785 if (i >= hotplug_lmb_start) {
786 sPAPRDRConnector *drc;
787 sPAPRDRConnectorClass *drck;
788
789 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
790 g_assert(drc);
791 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
792
793 dynamic_memory[0] = cpu_to_be32(addr >> 32);
794 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
795 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
796 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
797 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
798 if (memory_region_present(get_system_memory(), addr)) {
799 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
800 } else {
801 dynamic_memory[5] = cpu_to_be32(0);
802 }
803 } else {
804 /*
805 * LMB information for RMA, boot time RAM and gap b/n RAM and
806 * hotplug memory region -- all these are marked as reserved
807 * and as having no valid DRC.
808 */
809 dynamic_memory[0] = cpu_to_be32(addr >> 32);
810 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
811 dynamic_memory[2] = cpu_to_be32(0);
812 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
813 dynamic_memory[4] = cpu_to_be32(-1);
814 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
815 SPAPR_LMB_FLAGS_DRC_INVALID);
816 }
817
818 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
819 }
820 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
821 if (ret < 0) {
822 goto out;
823 }
824
825 /* ibm,associativity-lookup-arrays */
826 cur_index = int_buf;
827 int_buf[0] = cpu_to_be32(nr_nodes);
828 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
829 cur_index += 2;
830 for (i = 0; i < nr_nodes; i++) {
831 uint32_t associativity[] = {
832 cpu_to_be32(0x0),
833 cpu_to_be32(0x0),
834 cpu_to_be32(0x0),
835 cpu_to_be32(i)
836 };
837 memcpy(cur_index, associativity, sizeof(associativity));
838 cur_index += 4;
839 }
840 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
841 (cur_index - int_buf) * sizeof(uint32_t));
842 out:
843 g_free(int_buf);
844 return ret;
845 }
846
847 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
848 target_ulong addr, target_ulong size,
849 bool cpu_update, bool memory_update)
850 {
851 void *fdt, *fdt_skel;
852 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
853 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
854
855 size -= sizeof(hdr);
856
857 /* Create sceleton */
858 fdt_skel = g_malloc0(size);
859 _FDT((fdt_create(fdt_skel, size)));
860 _FDT((fdt_begin_node(fdt_skel, "")));
861 _FDT((fdt_end_node(fdt_skel)));
862 _FDT((fdt_finish(fdt_skel)));
863 fdt = g_malloc0(size);
864 _FDT((fdt_open_into(fdt_skel, fdt, size)));
865 g_free(fdt_skel);
866
867 /* Fixup cpu nodes */
868 if (cpu_update) {
869 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
870 }
871
872 /* Generate ibm,dynamic-reconfiguration-memory node if required */
873 if (memory_update && smc->dr_lmb_enabled) {
874 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
875 }
876
877 /* Pack resulting tree */
878 _FDT((fdt_pack(fdt)));
879
880 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
881 trace_spapr_cas_failed(size);
882 return -1;
883 }
884
885 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
886 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
887 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
888 g_free(fdt);
889
890 return 0;
891 }
892
893 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
894 hwaddr fdt_addr,
895 hwaddr rtas_addr,
896 hwaddr rtas_size)
897 {
898 MachineState *machine = MACHINE(qdev_get_machine());
899 MachineClass *mc = MACHINE_GET_CLASS(machine);
900 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
901 const char *boot_device = machine->boot_order;
902 int ret, i;
903 size_t cb = 0;
904 char *bootlist;
905 void *fdt;
906 sPAPRPHBState *phb;
907
908 fdt = g_malloc(FDT_MAX_SIZE);
909
910 /* open out the base tree into a temp buffer for the final tweaks */
911 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
912
913 ret = spapr_populate_memory(spapr, fdt);
914 if (ret < 0) {
915 error_report("couldn't setup memory nodes in fdt");
916 exit(1);
917 }
918
919 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
920 if (ret < 0) {
921 error_report("couldn't setup vio devices in fdt");
922 exit(1);
923 }
924
925 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
926 ret = spapr_rng_populate_dt(fdt);
927 if (ret < 0) {
928 error_report("could not set up rng device in the fdt");
929 exit(1);
930 }
931 }
932
933 QLIST_FOREACH(phb, &spapr->phbs, list) {
934 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
935 if (ret < 0) {
936 error_report("couldn't setup PCI devices in fdt");
937 exit(1);
938 }
939 }
940
941 /* RTAS */
942 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
943 if (ret < 0) {
944 error_report("Couldn't set up RTAS device tree properties");
945 }
946
947 /* cpus */
948 spapr_populate_cpus_dt_node(fdt, spapr);
949
950 bootlist = get_boot_devices_list(&cb, true);
951 if (cb && bootlist) {
952 int offset = fdt_path_offset(fdt, "/chosen");
953 if (offset < 0) {
954 exit(1);
955 }
956 for (i = 0; i < cb; i++) {
957 if (bootlist[i] == '\n') {
958 bootlist[i] = ' ';
959 }
960
961 }
962 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
963 }
964
965 if (boot_device && strlen(boot_device)) {
966 int offset = fdt_path_offset(fdt, "/chosen");
967
968 if (offset < 0) {
969 exit(1);
970 }
971 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
972 }
973
974 if (!spapr->has_graphics) {
975 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
976 }
977
978 if (smc->dr_lmb_enabled) {
979 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
980 }
981
982 if (mc->query_hotpluggable_cpus) {
983 int offset = fdt_path_offset(fdt, "/cpus");
984 ret = spapr_drc_populate_dt(fdt, offset, NULL,
985 SPAPR_DR_CONNECTOR_TYPE_CPU);
986 if (ret < 0) {
987 error_report("Couldn't set up CPU DR device tree properties");
988 exit(1);
989 }
990 }
991
992 _FDT((fdt_pack(fdt)));
993
994 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
995 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
996 fdt_totalsize(fdt), FDT_MAX_SIZE);
997 exit(1);
998 }
999
1000 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1001 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1002
1003 g_free(bootlist);
1004 g_free(fdt);
1005 }
1006
1007 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1008 {
1009 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1010 }
1011
1012 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1013 {
1014 CPUPPCState *env = &cpu->env;
1015
1016 if (msr_pr) {
1017 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1018 env->gpr[3] = H_PRIVILEGE;
1019 } else {
1020 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1021 }
1022 }
1023
1024 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1025 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1026 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1027 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1028 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1029
1030 /*
1031 * Get the fd to access the kernel htab, re-opening it if necessary
1032 */
1033 static int get_htab_fd(sPAPRMachineState *spapr)
1034 {
1035 if (spapr->htab_fd >= 0) {
1036 return spapr->htab_fd;
1037 }
1038
1039 spapr->htab_fd = kvmppc_get_htab_fd(false);
1040 if (spapr->htab_fd < 0) {
1041 error_report("Unable to open fd for reading hash table from KVM: %s",
1042 strerror(errno));
1043 }
1044
1045 return spapr->htab_fd;
1046 }
1047
1048 static void close_htab_fd(sPAPRMachineState *spapr)
1049 {
1050 if (spapr->htab_fd >= 0) {
1051 close(spapr->htab_fd);
1052 }
1053 spapr->htab_fd = -1;
1054 }
1055
1056 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1057 {
1058 int shift;
1059
1060 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1061 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1062 * that's much more than is needed for Linux guests */
1063 shift = ctz64(pow2ceil(ramsize)) - 7;
1064 shift = MAX(shift, 18); /* Minimum architected size */
1065 shift = MIN(shift, 46); /* Maximum architected size */
1066 return shift;
1067 }
1068
1069 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1070 Error **errp)
1071 {
1072 long rc;
1073
1074 /* Clean up any HPT info from a previous boot */
1075 g_free(spapr->htab);
1076 spapr->htab = NULL;
1077 spapr->htab_shift = 0;
1078 close_htab_fd(spapr);
1079
1080 rc = kvmppc_reset_htab(shift);
1081 if (rc < 0) {
1082 /* kernel-side HPT needed, but couldn't allocate one */
1083 error_setg_errno(errp, errno,
1084 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1085 shift);
1086 /* This is almost certainly fatal, but if the caller really
1087 * wants to carry on with shift == 0, it's welcome to try */
1088 } else if (rc > 0) {
1089 /* kernel-side HPT allocated */
1090 if (rc != shift) {
1091 error_setg(errp,
1092 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1093 shift, rc);
1094 }
1095
1096 spapr->htab_shift = shift;
1097 spapr->htab = NULL;
1098 } else {
1099 /* kernel-side HPT not needed, allocate in userspace instead */
1100 size_t size = 1ULL << shift;
1101 int i;
1102
1103 spapr->htab = qemu_memalign(size, size);
1104 if (!spapr->htab) {
1105 error_setg_errno(errp, errno,
1106 "Could not allocate HPT of order %d", shift);
1107 return;
1108 }
1109
1110 memset(spapr->htab, 0, size);
1111 spapr->htab_shift = shift;
1112
1113 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1114 DIRTY_HPTE(HPTE(spapr->htab, i));
1115 }
1116 }
1117 }
1118
1119 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1120 {
1121 bool matched = false;
1122
1123 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1124 matched = true;
1125 }
1126
1127 if (!matched) {
1128 error_report("Device %s is not supported by this machine yet.",
1129 qdev_fw_name(DEVICE(sbdev)));
1130 exit(1);
1131 }
1132 }
1133
1134 static void ppc_spapr_reset(void)
1135 {
1136 MachineState *machine = MACHINE(qdev_get_machine());
1137 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1138 PowerPCCPU *first_ppc_cpu;
1139 uint32_t rtas_limit;
1140
1141 /* Check for unknown sysbus devices */
1142 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1143
1144 /* Allocate and/or reset the hash page table */
1145 spapr_reallocate_hpt(spapr,
1146 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1147 &error_fatal);
1148
1149 /* Update the RMA size if necessary */
1150 if (spapr->vrma_adjust) {
1151 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1152 spapr->htab_shift);
1153 }
1154
1155 qemu_devices_reset();
1156
1157 /*
1158 * We place the device tree and RTAS just below either the top of the RMA,
1159 * or just below 2GB, whichever is lowere, so that it can be
1160 * processed with 32-bit real mode code if necessary
1161 */
1162 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1163 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1164 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1165
1166 /* Load the fdt */
1167 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1168 spapr->rtas_size);
1169
1170 /* Copy RTAS over */
1171 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1172 spapr->rtas_size);
1173
1174 /* Set up the entry state */
1175 first_ppc_cpu = POWERPC_CPU(first_cpu);
1176 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1177 first_ppc_cpu->env.gpr[5] = 0;
1178 first_cpu->halted = 0;
1179 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1180
1181 }
1182
1183 static void spapr_create_nvram(sPAPRMachineState *spapr)
1184 {
1185 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1186 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1187
1188 if (dinfo) {
1189 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1190 &error_fatal);
1191 }
1192
1193 qdev_init_nofail(dev);
1194
1195 spapr->nvram = (struct sPAPRNVRAM *)dev;
1196 }
1197
1198 static void spapr_rtc_create(sPAPRMachineState *spapr)
1199 {
1200 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1201
1202 qdev_init_nofail(dev);
1203 spapr->rtc = dev;
1204
1205 object_property_add_alias(qdev_get_machine(), "rtc-time",
1206 OBJECT(spapr->rtc), "date", NULL);
1207 }
1208
1209 /* Returns whether we want to use VGA or not */
1210 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1211 {
1212 switch (vga_interface_type) {
1213 case VGA_NONE:
1214 return false;
1215 case VGA_DEVICE:
1216 return true;
1217 case VGA_STD:
1218 case VGA_VIRTIO:
1219 return pci_vga_init(pci_bus) != NULL;
1220 default:
1221 error_setg(errp,
1222 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1223 return false;
1224 }
1225 }
1226
1227 static int spapr_post_load(void *opaque, int version_id)
1228 {
1229 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1230 int err = 0;
1231
1232 /* In earlier versions, there was no separate qdev for the PAPR
1233 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1234 * So when migrating from those versions, poke the incoming offset
1235 * value into the RTC device */
1236 if (version_id < 3) {
1237 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1238 }
1239
1240 return err;
1241 }
1242
1243 static bool version_before_3(void *opaque, int version_id)
1244 {
1245 return version_id < 3;
1246 }
1247
1248 static const VMStateDescription vmstate_spapr = {
1249 .name = "spapr",
1250 .version_id = 3,
1251 .minimum_version_id = 1,
1252 .post_load = spapr_post_load,
1253 .fields = (VMStateField[]) {
1254 /* used to be @next_irq */
1255 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1256
1257 /* RTC offset */
1258 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1259
1260 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1261 VMSTATE_END_OF_LIST()
1262 },
1263 };
1264
1265 static int htab_save_setup(QEMUFile *f, void *opaque)
1266 {
1267 sPAPRMachineState *spapr = opaque;
1268
1269 /* "Iteration" header */
1270 qemu_put_be32(f, spapr->htab_shift);
1271
1272 if (spapr->htab) {
1273 spapr->htab_save_index = 0;
1274 spapr->htab_first_pass = true;
1275 } else {
1276 assert(kvm_enabled());
1277 }
1278
1279
1280 return 0;
1281 }
1282
1283 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1284 int64_t max_ns)
1285 {
1286 bool has_timeout = max_ns != -1;
1287 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1288 int index = spapr->htab_save_index;
1289 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1290
1291 assert(spapr->htab_first_pass);
1292
1293 do {
1294 int chunkstart;
1295
1296 /* Consume invalid HPTEs */
1297 while ((index < htabslots)
1298 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1299 index++;
1300 CLEAN_HPTE(HPTE(spapr->htab, index));
1301 }
1302
1303 /* Consume valid HPTEs */
1304 chunkstart = index;
1305 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1306 && HPTE_VALID(HPTE(spapr->htab, index))) {
1307 index++;
1308 CLEAN_HPTE(HPTE(spapr->htab, index));
1309 }
1310
1311 if (index > chunkstart) {
1312 int n_valid = index - chunkstart;
1313
1314 qemu_put_be32(f, chunkstart);
1315 qemu_put_be16(f, n_valid);
1316 qemu_put_be16(f, 0);
1317 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1318 HASH_PTE_SIZE_64 * n_valid);
1319
1320 if (has_timeout &&
1321 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1322 break;
1323 }
1324 }
1325 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1326
1327 if (index >= htabslots) {
1328 assert(index == htabslots);
1329 index = 0;
1330 spapr->htab_first_pass = false;
1331 }
1332 spapr->htab_save_index = index;
1333 }
1334
1335 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1336 int64_t max_ns)
1337 {
1338 bool final = max_ns < 0;
1339 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1340 int examined = 0, sent = 0;
1341 int index = spapr->htab_save_index;
1342 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1343
1344 assert(!spapr->htab_first_pass);
1345
1346 do {
1347 int chunkstart, invalidstart;
1348
1349 /* Consume non-dirty HPTEs */
1350 while ((index < htabslots)
1351 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1352 index++;
1353 examined++;
1354 }
1355
1356 chunkstart = index;
1357 /* Consume valid dirty HPTEs */
1358 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1359 && HPTE_DIRTY(HPTE(spapr->htab, index))
1360 && HPTE_VALID(HPTE(spapr->htab, index))) {
1361 CLEAN_HPTE(HPTE(spapr->htab, index));
1362 index++;
1363 examined++;
1364 }
1365
1366 invalidstart = index;
1367 /* Consume invalid dirty HPTEs */
1368 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1369 && HPTE_DIRTY(HPTE(spapr->htab, index))
1370 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1371 CLEAN_HPTE(HPTE(spapr->htab, index));
1372 index++;
1373 examined++;
1374 }
1375
1376 if (index > chunkstart) {
1377 int n_valid = invalidstart - chunkstart;
1378 int n_invalid = index - invalidstart;
1379
1380 qemu_put_be32(f, chunkstart);
1381 qemu_put_be16(f, n_valid);
1382 qemu_put_be16(f, n_invalid);
1383 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1384 HASH_PTE_SIZE_64 * n_valid);
1385 sent += index - chunkstart;
1386
1387 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1388 break;
1389 }
1390 }
1391
1392 if (examined >= htabslots) {
1393 break;
1394 }
1395
1396 if (index >= htabslots) {
1397 assert(index == htabslots);
1398 index = 0;
1399 }
1400 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1401
1402 if (index >= htabslots) {
1403 assert(index == htabslots);
1404 index = 0;
1405 }
1406
1407 spapr->htab_save_index = index;
1408
1409 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1410 }
1411
1412 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1413 #define MAX_KVM_BUF_SIZE 2048
1414
1415 static int htab_save_iterate(QEMUFile *f, void *opaque)
1416 {
1417 sPAPRMachineState *spapr = opaque;
1418 int fd;
1419 int rc = 0;
1420
1421 /* Iteration header */
1422 qemu_put_be32(f, 0);
1423
1424 if (!spapr->htab) {
1425 assert(kvm_enabled());
1426
1427 fd = get_htab_fd(spapr);
1428 if (fd < 0) {
1429 return fd;
1430 }
1431
1432 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1433 if (rc < 0) {
1434 return rc;
1435 }
1436 } else if (spapr->htab_first_pass) {
1437 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1438 } else {
1439 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1440 }
1441
1442 /* End marker */
1443 qemu_put_be32(f, 0);
1444 qemu_put_be16(f, 0);
1445 qemu_put_be16(f, 0);
1446
1447 return rc;
1448 }
1449
1450 static int htab_save_complete(QEMUFile *f, void *opaque)
1451 {
1452 sPAPRMachineState *spapr = opaque;
1453 int fd;
1454
1455 /* Iteration header */
1456 qemu_put_be32(f, 0);
1457
1458 if (!spapr->htab) {
1459 int rc;
1460
1461 assert(kvm_enabled());
1462
1463 fd = get_htab_fd(spapr);
1464 if (fd < 0) {
1465 return fd;
1466 }
1467
1468 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1469 if (rc < 0) {
1470 return rc;
1471 }
1472 } else {
1473 if (spapr->htab_first_pass) {
1474 htab_save_first_pass(f, spapr, -1);
1475 }
1476 htab_save_later_pass(f, spapr, -1);
1477 }
1478
1479 /* End marker */
1480 qemu_put_be32(f, 0);
1481 qemu_put_be16(f, 0);
1482 qemu_put_be16(f, 0);
1483
1484 return 0;
1485 }
1486
1487 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1488 {
1489 sPAPRMachineState *spapr = opaque;
1490 uint32_t section_hdr;
1491 int fd = -1;
1492
1493 if (version_id < 1 || version_id > 1) {
1494 error_report("htab_load() bad version");
1495 return -EINVAL;
1496 }
1497
1498 section_hdr = qemu_get_be32(f);
1499
1500 if (section_hdr) {
1501 Error *local_err = NULL;
1502
1503 /* First section gives the htab size */
1504 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1505 if (local_err) {
1506 error_report_err(local_err);
1507 return -EINVAL;
1508 }
1509 return 0;
1510 }
1511
1512 if (!spapr->htab) {
1513 assert(kvm_enabled());
1514
1515 fd = kvmppc_get_htab_fd(true);
1516 if (fd < 0) {
1517 error_report("Unable to open fd to restore KVM hash table: %s",
1518 strerror(errno));
1519 }
1520 }
1521
1522 while (true) {
1523 uint32_t index;
1524 uint16_t n_valid, n_invalid;
1525
1526 index = qemu_get_be32(f);
1527 n_valid = qemu_get_be16(f);
1528 n_invalid = qemu_get_be16(f);
1529
1530 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1531 /* End of Stream */
1532 break;
1533 }
1534
1535 if ((index + n_valid + n_invalid) >
1536 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1537 /* Bad index in stream */
1538 error_report(
1539 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1540 index, n_valid, n_invalid, spapr->htab_shift);
1541 return -EINVAL;
1542 }
1543
1544 if (spapr->htab) {
1545 if (n_valid) {
1546 qemu_get_buffer(f, HPTE(spapr->htab, index),
1547 HASH_PTE_SIZE_64 * n_valid);
1548 }
1549 if (n_invalid) {
1550 memset(HPTE(spapr->htab, index + n_valid), 0,
1551 HASH_PTE_SIZE_64 * n_invalid);
1552 }
1553 } else {
1554 int rc;
1555
1556 assert(fd >= 0);
1557
1558 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1559 if (rc < 0) {
1560 return rc;
1561 }
1562 }
1563 }
1564
1565 if (!spapr->htab) {
1566 assert(fd >= 0);
1567 close(fd);
1568 }
1569
1570 return 0;
1571 }
1572
1573 static void htab_cleanup(void *opaque)
1574 {
1575 sPAPRMachineState *spapr = opaque;
1576
1577 close_htab_fd(spapr);
1578 }
1579
1580 static SaveVMHandlers savevm_htab_handlers = {
1581 .save_live_setup = htab_save_setup,
1582 .save_live_iterate = htab_save_iterate,
1583 .save_live_complete_precopy = htab_save_complete,
1584 .cleanup = htab_cleanup,
1585 .load_state = htab_load,
1586 };
1587
1588 static void spapr_boot_set(void *opaque, const char *boot_device,
1589 Error **errp)
1590 {
1591 MachineState *machine = MACHINE(qdev_get_machine());
1592 machine->boot_order = g_strdup(boot_device);
1593 }
1594
1595 /*
1596 * Reset routine for LMB DR devices.
1597 *
1598 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1599 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1600 * when it walks all its children devices. LMB devices reset occurs
1601 * as part of spapr_ppc_reset().
1602 */
1603 static void spapr_drc_reset(void *opaque)
1604 {
1605 sPAPRDRConnector *drc = opaque;
1606 DeviceState *d = DEVICE(drc);
1607
1608 if (d) {
1609 device_reset(d);
1610 }
1611 }
1612
1613 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1614 {
1615 MachineState *machine = MACHINE(spapr);
1616 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1617 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1618 int i;
1619
1620 for (i = 0; i < nr_lmbs; i++) {
1621 sPAPRDRConnector *drc;
1622 uint64_t addr;
1623
1624 addr = i * lmb_size + spapr->hotplug_memory.base;
1625 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1626 addr/lmb_size);
1627 qemu_register_reset(spapr_drc_reset, drc);
1628 }
1629 }
1630
1631 /*
1632 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1633 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1634 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1635 */
1636 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1637 {
1638 int i;
1639
1640 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1641 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1642 " is not aligned to %llu MiB",
1643 machine->ram_size,
1644 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1645 return;
1646 }
1647
1648 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1649 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1650 " is not aligned to %llu MiB",
1651 machine->ram_size,
1652 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1653 return;
1654 }
1655
1656 for (i = 0; i < nb_numa_nodes; i++) {
1657 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1658 error_setg(errp,
1659 "Node %d memory size 0x%" PRIx64
1660 " is not aligned to %llu MiB",
1661 i, numa_info[i].node_mem,
1662 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1663 return;
1664 }
1665 }
1666 }
1667
1668 /* pSeries LPAR / sPAPR hardware init */
1669 static void ppc_spapr_init(MachineState *machine)
1670 {
1671 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1672 MachineClass *mc = MACHINE_GET_CLASS(machine);
1673 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1674 const char *kernel_filename = machine->kernel_filename;
1675 const char *kernel_cmdline = machine->kernel_cmdline;
1676 const char *initrd_filename = machine->initrd_filename;
1677 PCIHostState *phb;
1678 int i;
1679 MemoryRegion *sysmem = get_system_memory();
1680 MemoryRegion *ram = g_new(MemoryRegion, 1);
1681 MemoryRegion *rma_region;
1682 void *rma = NULL;
1683 hwaddr rma_alloc_size;
1684 hwaddr node0_size = spapr_node0_size();
1685 uint32_t initrd_base = 0;
1686 long kernel_size = 0, initrd_size = 0;
1687 long load_limit, fw_size;
1688 bool kernel_le = false;
1689 char *filename;
1690 int smt = kvmppc_smt_threads();
1691 int spapr_cores = smp_cpus / smp_threads;
1692 int spapr_max_cores = max_cpus / smp_threads;
1693
1694 if (mc->query_hotpluggable_cpus) {
1695 if (smp_cpus % smp_threads) {
1696 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1697 smp_cpus, smp_threads);
1698 exit(1);
1699 }
1700 if (max_cpus % smp_threads) {
1701 error_report("max_cpus (%u) must be multiple of threads (%u)",
1702 max_cpus, smp_threads);
1703 exit(1);
1704 }
1705 }
1706
1707 msi_nonbroken = true;
1708
1709 QLIST_INIT(&spapr->phbs);
1710
1711 cpu_ppc_hypercall = emulate_spapr_hypercall;
1712
1713 /* Allocate RMA if necessary */
1714 rma_alloc_size = kvmppc_alloc_rma(&rma);
1715
1716 if (rma_alloc_size == -1) {
1717 error_report("Unable to create RMA");
1718 exit(1);
1719 }
1720
1721 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1722 spapr->rma_size = rma_alloc_size;
1723 } else {
1724 spapr->rma_size = node0_size;
1725
1726 /* With KVM, we don't actually know whether KVM supports an
1727 * unbounded RMA (PR KVM) or is limited by the hash table size
1728 * (HV KVM using VRMA), so we always assume the latter
1729 *
1730 * In that case, we also limit the initial allocations for RTAS
1731 * etc... to 256M since we have no way to know what the VRMA size
1732 * is going to be as it depends on the size of the hash table
1733 * isn't determined yet.
1734 */
1735 if (kvm_enabled()) {
1736 spapr->vrma_adjust = 1;
1737 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1738 }
1739
1740 /* Actually we don't support unbounded RMA anymore since we
1741 * added proper emulation of HV mode. The max we can get is
1742 * 16G which also happens to be what we configure for PAPR
1743 * mode so make sure we don't do anything bigger than that
1744 */
1745 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
1746 }
1747
1748 if (spapr->rma_size > node0_size) {
1749 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1750 spapr->rma_size);
1751 exit(1);
1752 }
1753
1754 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1755 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1756
1757 /* Set up Interrupt Controller before we create the VCPUs */
1758 spapr->xics = xics_system_init(machine,
1759 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1760 XICS_IRQS_SPAPR, &error_fatal);
1761
1762 if (smc->dr_lmb_enabled) {
1763 spapr_validate_node_memory(machine, &error_fatal);
1764 }
1765
1766 /* init CPUs */
1767 if (machine->cpu_model == NULL) {
1768 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1769 }
1770
1771 ppc_cpu_parse_features(machine->cpu_model);
1772
1773 if (mc->query_hotpluggable_cpus) {
1774 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1775
1776 if (type == NULL) {
1777 error_report("Unable to find sPAPR CPU Core definition");
1778 exit(1);
1779 }
1780
1781 spapr->cores = g_new0(Object *, spapr_max_cores);
1782 for (i = 0; i < spapr_max_cores; i++) {
1783 int core_id = i * smp_threads;
1784 sPAPRDRConnector *drc =
1785 spapr_dr_connector_new(OBJECT(spapr),
1786 SPAPR_DR_CONNECTOR_TYPE_CPU,
1787 (core_id / smp_threads) * smt);
1788
1789 qemu_register_reset(spapr_drc_reset, drc);
1790
1791 if (i < spapr_cores) {
1792 Object *core = object_new(type);
1793 object_property_set_int(core, smp_threads, "nr-threads",
1794 &error_fatal);
1795 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1796 &error_fatal);
1797 object_property_set_bool(core, true, "realized", &error_fatal);
1798 }
1799 }
1800 g_free(type);
1801 } else {
1802 for (i = 0; i < smp_cpus; i++) {
1803 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1804 if (cpu == NULL) {
1805 error_report("Unable to find PowerPC CPU definition");
1806 exit(1);
1807 }
1808 spapr_cpu_init(spapr, cpu, &error_fatal);
1809 }
1810 }
1811
1812 if (kvm_enabled()) {
1813 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1814 kvmppc_enable_logical_ci_hcalls();
1815 kvmppc_enable_set_mode_hcall();
1816
1817 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
1818 kvmppc_enable_clear_ref_mod_hcalls();
1819 }
1820
1821 /* allocate RAM */
1822 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1823 machine->ram_size);
1824 memory_region_add_subregion(sysmem, 0, ram);
1825
1826 if (rma_alloc_size && rma) {
1827 rma_region = g_new(MemoryRegion, 1);
1828 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1829 rma_alloc_size, rma);
1830 vmstate_register_ram_global(rma_region);
1831 memory_region_add_subregion(sysmem, 0, rma_region);
1832 }
1833
1834 /* initialize hotplug memory address space */
1835 if (machine->ram_size < machine->maxram_size) {
1836 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1837 /*
1838 * Limit the number of hotpluggable memory slots to half the number
1839 * slots that KVM supports, leaving the other half for PCI and other
1840 * devices. However ensure that number of slots doesn't drop below 32.
1841 */
1842 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1843 SPAPR_MAX_RAM_SLOTS;
1844
1845 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1846 max_memslots = SPAPR_MAX_RAM_SLOTS;
1847 }
1848 if (machine->ram_slots > max_memslots) {
1849 error_report("Specified number of memory slots %"
1850 PRIu64" exceeds max supported %d",
1851 machine->ram_slots, max_memslots);
1852 exit(1);
1853 }
1854
1855 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1856 SPAPR_HOTPLUG_MEM_ALIGN);
1857 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1858 "hotplug-memory", hotplug_mem_size);
1859 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1860 &spapr->hotplug_memory.mr);
1861 }
1862
1863 if (smc->dr_lmb_enabled) {
1864 spapr_create_lmb_dr_connectors(spapr);
1865 }
1866
1867 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1868 if (!filename) {
1869 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1870 exit(1);
1871 }
1872 spapr->rtas_size = get_image_size(filename);
1873 if (spapr->rtas_size < 0) {
1874 error_report("Could not get size of LPAR rtas '%s'", filename);
1875 exit(1);
1876 }
1877 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1878 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1879 error_report("Could not load LPAR rtas '%s'", filename);
1880 exit(1);
1881 }
1882 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1883 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1884 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1885 exit(1);
1886 }
1887 g_free(filename);
1888
1889 /* Set up EPOW events infrastructure */
1890 spapr_events_init(spapr);
1891
1892 /* Set up the RTC RTAS interfaces */
1893 spapr_rtc_create(spapr);
1894
1895 /* Set up VIO bus */
1896 spapr->vio_bus = spapr_vio_bus_init();
1897
1898 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1899 if (serial_hds[i]) {
1900 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1901 }
1902 }
1903
1904 /* We always have at least the nvram device on VIO */
1905 spapr_create_nvram(spapr);
1906
1907 /* Set up PCI */
1908 spapr_pci_rtas_init();
1909
1910 phb = spapr_create_phb(spapr, 0);
1911
1912 for (i = 0; i < nb_nics; i++) {
1913 NICInfo *nd = &nd_table[i];
1914
1915 if (!nd->model) {
1916 nd->model = g_strdup("ibmveth");
1917 }
1918
1919 if (strcmp(nd->model, "ibmveth") == 0) {
1920 spapr_vlan_create(spapr->vio_bus, nd);
1921 } else {
1922 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1923 }
1924 }
1925
1926 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1927 spapr_vscsi_create(spapr->vio_bus);
1928 }
1929
1930 /* Graphics */
1931 if (spapr_vga_init(phb->bus, &error_fatal)) {
1932 spapr->has_graphics = true;
1933 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1934 }
1935
1936 if (machine->usb) {
1937 if (smc->use_ohci_by_default) {
1938 pci_create_simple(phb->bus, -1, "pci-ohci");
1939 } else {
1940 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1941 }
1942
1943 if (spapr->has_graphics) {
1944 USBBus *usb_bus = usb_bus_find(-1);
1945
1946 usb_create_simple(usb_bus, "usb-kbd");
1947 usb_create_simple(usb_bus, "usb-mouse");
1948 }
1949 }
1950
1951 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1952 error_report(
1953 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1954 MIN_RMA_SLOF);
1955 exit(1);
1956 }
1957
1958 if (kernel_filename) {
1959 uint64_t lowaddr = 0;
1960
1961 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1962 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1963 0, 0);
1964 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1965 kernel_size = load_elf(kernel_filename,
1966 translate_kernel_address, NULL,
1967 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1968 0, 0);
1969 kernel_le = kernel_size > 0;
1970 }
1971 if (kernel_size < 0) {
1972 error_report("error loading %s: %s",
1973 kernel_filename, load_elf_strerror(kernel_size));
1974 exit(1);
1975 }
1976
1977 /* load initrd */
1978 if (initrd_filename) {
1979 /* Try to locate the initrd in the gap between the kernel
1980 * and the firmware. Add a bit of space just in case
1981 */
1982 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1983 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1984 load_limit - initrd_base);
1985 if (initrd_size < 0) {
1986 error_report("could not load initial ram disk '%s'",
1987 initrd_filename);
1988 exit(1);
1989 }
1990 } else {
1991 initrd_base = 0;
1992 initrd_size = 0;
1993 }
1994 }
1995
1996 if (bios_name == NULL) {
1997 bios_name = FW_FILE_NAME;
1998 }
1999 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2000 if (!filename) {
2001 error_report("Could not find LPAR firmware '%s'", bios_name);
2002 exit(1);
2003 }
2004 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2005 if (fw_size <= 0) {
2006 error_report("Could not load LPAR firmware '%s'", filename);
2007 exit(1);
2008 }
2009 g_free(filename);
2010
2011 /* FIXME: Should register things through the MachineState's qdev
2012 * interface, this is a legacy from the sPAPREnvironment structure
2013 * which predated MachineState but had a similar function */
2014 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2015 register_savevm_live(NULL, "spapr/htab", -1, 1,
2016 &savevm_htab_handlers, spapr);
2017
2018 /* Prepare the device tree */
2019 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
2020 kernel_size, kernel_le,
2021 kernel_cmdline,
2022 spapr->check_exception_irq);
2023 assert(spapr->fdt_skel != NULL);
2024
2025 /* used by RTAS */
2026 QTAILQ_INIT(&spapr->ccs_list);
2027 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2028
2029 qemu_register_boot_set(spapr_boot_set, spapr);
2030 }
2031
2032 static int spapr_kvm_type(const char *vm_type)
2033 {
2034 if (!vm_type) {
2035 return 0;
2036 }
2037
2038 if (!strcmp(vm_type, "HV")) {
2039 return 1;
2040 }
2041
2042 if (!strcmp(vm_type, "PR")) {
2043 return 2;
2044 }
2045
2046 error_report("Unknown kvm-type specified '%s'", vm_type);
2047 exit(1);
2048 }
2049
2050 /*
2051 * Implementation of an interface to adjust firmware path
2052 * for the bootindex property handling.
2053 */
2054 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2055 DeviceState *dev)
2056 {
2057 #define CAST(type, obj, name) \
2058 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2059 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2060 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2061
2062 if (d) {
2063 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2064 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2065 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2066
2067 if (spapr) {
2068 /*
2069 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2070 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2071 * in the top 16 bits of the 64-bit LUN
2072 */
2073 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2074 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2075 (uint64_t)id << 48);
2076 } else if (virtio) {
2077 /*
2078 * We use SRP luns of the form 01000000 | (target << 8) | lun
2079 * in the top 32 bits of the 64-bit LUN
2080 * Note: the quote above is from SLOF and it is wrong,
2081 * the actual binding is:
2082 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2083 */
2084 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2085 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2086 (uint64_t)id << 32);
2087 } else if (usb) {
2088 /*
2089 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2090 * in the top 32 bits of the 64-bit LUN
2091 */
2092 unsigned usb_port = atoi(usb->port->path);
2093 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2094 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2095 (uint64_t)id << 32);
2096 }
2097 }
2098
2099 if (phb) {
2100 /* Replace "pci" with "pci@800000020000000" */
2101 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2102 }
2103
2104 return NULL;
2105 }
2106
2107 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2108 {
2109 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2110
2111 return g_strdup(spapr->kvm_type);
2112 }
2113
2114 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2115 {
2116 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2117
2118 g_free(spapr->kvm_type);
2119 spapr->kvm_type = g_strdup(value);
2120 }
2121
2122 static void spapr_machine_initfn(Object *obj)
2123 {
2124 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2125
2126 spapr->htab_fd = -1;
2127 object_property_add_str(obj, "kvm-type",
2128 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2129 object_property_set_description(obj, "kvm-type",
2130 "Specifies the KVM virtualization mode (HV, PR)",
2131 NULL);
2132 }
2133
2134 static void spapr_machine_finalizefn(Object *obj)
2135 {
2136 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2137
2138 g_free(spapr->kvm_type);
2139 }
2140
2141 static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, void *arg)
2142 {
2143 cpu_synchronize_state(cs);
2144 ppc_cpu_do_system_reset(cs);
2145 }
2146
2147 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2148 {
2149 CPUState *cs;
2150
2151 CPU_FOREACH(cs) {
2152 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, NULL);
2153 }
2154 }
2155
2156 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2157 uint32_t node, Error **errp)
2158 {
2159 sPAPRDRConnector *drc;
2160 sPAPRDRConnectorClass *drck;
2161 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2162 int i, fdt_offset, fdt_size;
2163 void *fdt;
2164
2165 for (i = 0; i < nr_lmbs; i++) {
2166 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2167 addr/SPAPR_MEMORY_BLOCK_SIZE);
2168 g_assert(drc);
2169
2170 fdt = create_device_tree(&fdt_size);
2171 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2172 SPAPR_MEMORY_BLOCK_SIZE);
2173
2174 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2175 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2176 addr += SPAPR_MEMORY_BLOCK_SIZE;
2177 }
2178 /* send hotplug notification to the
2179 * guest only in case of hotplugged memory
2180 */
2181 if (dev->hotplugged) {
2182 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2183 }
2184 }
2185
2186 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2187 uint32_t node, Error **errp)
2188 {
2189 Error *local_err = NULL;
2190 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2191 PCDIMMDevice *dimm = PC_DIMM(dev);
2192 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2193 MemoryRegion *mr = ddc->get_memory_region(dimm);
2194 uint64_t align = memory_region_get_alignment(mr);
2195 uint64_t size = memory_region_size(mr);
2196 uint64_t addr;
2197
2198 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2199 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2200 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2201 goto out;
2202 }
2203
2204 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2205 if (local_err) {
2206 goto out;
2207 }
2208
2209 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2210 if (local_err) {
2211 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2212 goto out;
2213 }
2214
2215 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2216
2217 out:
2218 error_propagate(errp, local_err);
2219 }
2220
2221 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2222 sPAPRMachineState *spapr)
2223 {
2224 PowerPCCPU *cpu = POWERPC_CPU(cs);
2225 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2226 int id = ppc_get_vcpu_dt_id(cpu);
2227 void *fdt;
2228 int offset, fdt_size;
2229 char *nodename;
2230
2231 fdt = create_device_tree(&fdt_size);
2232 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2233 offset = fdt_add_subnode(fdt, 0, nodename);
2234
2235 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2236 g_free(nodename);
2237
2238 *fdt_offset = offset;
2239 return fdt;
2240 }
2241
2242 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2243 DeviceState *dev, Error **errp)
2244 {
2245 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2246
2247 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2248 int node;
2249
2250 if (!smc->dr_lmb_enabled) {
2251 error_setg(errp, "Memory hotplug not supported for this machine");
2252 return;
2253 }
2254 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2255 if (*errp) {
2256 return;
2257 }
2258 if (node < 0 || node >= MAX_NODES) {
2259 error_setg(errp, "Invaild node %d", node);
2260 return;
2261 }
2262
2263 /*
2264 * Currently PowerPC kernel doesn't allow hot-adding memory to
2265 * memory-less node, but instead will silently add the memory
2266 * to the first node that has some memory. This causes two
2267 * unexpected behaviours for the user.
2268 *
2269 * - Memory gets hotplugged to a different node than what the user
2270 * specified.
2271 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2272 * to memory-less node, a reboot will set things accordingly
2273 * and the previously hotplugged memory now ends in the right node.
2274 * This appears as if some memory moved from one node to another.
2275 *
2276 * So until kernel starts supporting memory hotplug to memory-less
2277 * nodes, just prevent such attempts upfront in QEMU.
2278 */
2279 if (nb_numa_nodes && !numa_info[node].node_mem) {
2280 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2281 node);
2282 return;
2283 }
2284
2285 spapr_memory_plug(hotplug_dev, dev, node, errp);
2286 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2287 spapr_core_plug(hotplug_dev, dev, errp);
2288 }
2289 }
2290
2291 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2292 DeviceState *dev, Error **errp)
2293 {
2294 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2295
2296 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2297 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2298 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2299 if (!mc->query_hotpluggable_cpus) {
2300 error_setg(errp, "CPU hot unplug not supported on this machine");
2301 return;
2302 }
2303 spapr_core_unplug(hotplug_dev, dev, errp);
2304 }
2305 }
2306
2307 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2308 DeviceState *dev, Error **errp)
2309 {
2310 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2311 spapr_core_pre_plug(hotplug_dev, dev, errp);
2312 }
2313 }
2314
2315 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2316 DeviceState *dev)
2317 {
2318 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2319 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2320 return HOTPLUG_HANDLER(machine);
2321 }
2322 return NULL;
2323 }
2324
2325 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2326 {
2327 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2328 * socket means much for the paravirtualized PAPR platform) */
2329 return cpu_index / smp_threads / smp_cores;
2330 }
2331
2332 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2333 {
2334 int i;
2335 HotpluggableCPUList *head = NULL;
2336 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2337 int spapr_max_cores = max_cpus / smp_threads;
2338
2339 for (i = 0; i < spapr_max_cores; i++) {
2340 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2341 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2342 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2343
2344 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2345 cpu_item->vcpus_count = smp_threads;
2346 cpu_props->has_core_id = true;
2347 cpu_props->core_id = i * smp_threads;
2348 /* TODO: add 'has_node/node' here to describe
2349 to which node core belongs */
2350
2351 cpu_item->props = cpu_props;
2352 if (spapr->cores[i]) {
2353 cpu_item->has_qom_path = true;
2354 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2355 }
2356 list_item->value = cpu_item;
2357 list_item->next = head;
2358 head = list_item;
2359 }
2360 return head;
2361 }
2362
2363 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2364 {
2365 MachineClass *mc = MACHINE_CLASS(oc);
2366 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2367 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2368 NMIClass *nc = NMI_CLASS(oc);
2369 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2370
2371 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2372
2373 /*
2374 * We set up the default / latest behaviour here. The class_init
2375 * functions for the specific versioned machine types can override
2376 * these details for backwards compatibility
2377 */
2378 mc->init = ppc_spapr_init;
2379 mc->reset = ppc_spapr_reset;
2380 mc->block_default_type = IF_SCSI;
2381 mc->max_cpus = MAX_CPUMASK_BITS;
2382 mc->no_parallel = 1;
2383 mc->default_boot_order = "";
2384 mc->default_ram_size = 512 * M_BYTE;
2385 mc->kvm_type = spapr_kvm_type;
2386 mc->has_dynamic_sysbus = true;
2387 mc->pci_allow_0_address = true;
2388 mc->get_hotplug_handler = spapr_get_hotplug_handler;
2389 hc->pre_plug = spapr_machine_device_pre_plug;
2390 hc->plug = spapr_machine_device_plug;
2391 hc->unplug = spapr_machine_device_unplug;
2392 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2393
2394 smc->dr_lmb_enabled = true;
2395 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
2396 fwc->get_dev_path = spapr_get_fw_dev_path;
2397 nc->nmi_monitor_handler = spapr_nmi;
2398 }
2399
2400 static const TypeInfo spapr_machine_info = {
2401 .name = TYPE_SPAPR_MACHINE,
2402 .parent = TYPE_MACHINE,
2403 .abstract = true,
2404 .instance_size = sizeof(sPAPRMachineState),
2405 .instance_init = spapr_machine_initfn,
2406 .instance_finalize = spapr_machine_finalizefn,
2407 .class_size = sizeof(sPAPRMachineClass),
2408 .class_init = spapr_machine_class_init,
2409 .interfaces = (InterfaceInfo[]) {
2410 { TYPE_FW_PATH_PROVIDER },
2411 { TYPE_NMI },
2412 { TYPE_HOTPLUG_HANDLER },
2413 { }
2414 },
2415 };
2416
2417 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2418 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2419 void *data) \
2420 { \
2421 MachineClass *mc = MACHINE_CLASS(oc); \
2422 spapr_machine_##suffix##_class_options(mc); \
2423 if (latest) { \
2424 mc->alias = "pseries"; \
2425 mc->is_default = 1; \
2426 } \
2427 } \
2428 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2429 { \
2430 MachineState *machine = MACHINE(obj); \
2431 spapr_machine_##suffix##_instance_options(machine); \
2432 } \
2433 static const TypeInfo spapr_machine_##suffix##_info = { \
2434 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2435 .parent = TYPE_SPAPR_MACHINE, \
2436 .class_init = spapr_machine_##suffix##_class_init, \
2437 .instance_init = spapr_machine_##suffix##_instance_init, \
2438 }; \
2439 static void spapr_machine_register_##suffix(void) \
2440 { \
2441 type_register(&spapr_machine_##suffix##_info); \
2442 } \
2443 type_init(spapr_machine_register_##suffix)
2444
2445 /*
2446 * pseries-2.8
2447 */
2448 static void spapr_machine_2_8_instance_options(MachineState *machine)
2449 {
2450 }
2451
2452 static void spapr_machine_2_8_class_options(MachineClass *mc)
2453 {
2454 /* Defaults for the latest behaviour inherited from the base class */
2455 }
2456
2457 DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
2458
2459 /*
2460 * pseries-2.7
2461 */
2462 #define SPAPR_COMPAT_2_7 \
2463 HW_COMPAT_2_7 \
2464
2465 static void spapr_machine_2_7_instance_options(MachineState *machine)
2466 {
2467 }
2468
2469 static void spapr_machine_2_7_class_options(MachineClass *mc)
2470 {
2471 spapr_machine_2_8_class_options(mc);
2472 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
2473 }
2474
2475 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
2476
2477 /*
2478 * pseries-2.6
2479 */
2480 #define SPAPR_COMPAT_2_6 \
2481 HW_COMPAT_2_6 \
2482 { \
2483 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2484 .property = "ddw",\
2485 .value = stringify(off),\
2486 },
2487
2488 static void spapr_machine_2_6_instance_options(MachineState *machine)
2489 {
2490 }
2491
2492 static void spapr_machine_2_6_class_options(MachineClass *mc)
2493 {
2494 spapr_machine_2_7_class_options(mc);
2495 mc->query_hotpluggable_cpus = NULL;
2496 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
2497 }
2498
2499 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
2500
2501 /*
2502 * pseries-2.5
2503 */
2504 #define SPAPR_COMPAT_2_5 \
2505 HW_COMPAT_2_5 \
2506 { \
2507 .driver = "spapr-vlan", \
2508 .property = "use-rx-buffer-pools", \
2509 .value = "off", \
2510 },
2511
2512 static void spapr_machine_2_5_instance_options(MachineState *machine)
2513 {
2514 }
2515
2516 static void spapr_machine_2_5_class_options(MachineClass *mc)
2517 {
2518 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2519
2520 spapr_machine_2_6_class_options(mc);
2521 smc->use_ohci_by_default = true;
2522 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2523 }
2524
2525 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2526
2527 /*
2528 * pseries-2.4
2529 */
2530 #define SPAPR_COMPAT_2_4 \
2531 HW_COMPAT_2_4
2532
2533 static void spapr_machine_2_4_instance_options(MachineState *machine)
2534 {
2535 spapr_machine_2_5_instance_options(machine);
2536 }
2537
2538 static void spapr_machine_2_4_class_options(MachineClass *mc)
2539 {
2540 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2541
2542 spapr_machine_2_5_class_options(mc);
2543 smc->dr_lmb_enabled = false;
2544 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2545 }
2546
2547 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2548
2549 /*
2550 * pseries-2.3
2551 */
2552 #define SPAPR_COMPAT_2_3 \
2553 HW_COMPAT_2_3 \
2554 {\
2555 .driver = "spapr-pci-host-bridge",\
2556 .property = "dynamic-reconfiguration",\
2557 .value = "off",\
2558 },
2559
2560 static void spapr_machine_2_3_instance_options(MachineState *machine)
2561 {
2562 spapr_machine_2_4_instance_options(machine);
2563 savevm_skip_section_footers();
2564 global_state_set_optional();
2565 savevm_skip_configuration();
2566 }
2567
2568 static void spapr_machine_2_3_class_options(MachineClass *mc)
2569 {
2570 spapr_machine_2_4_class_options(mc);
2571 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2572 }
2573 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2574
2575 /*
2576 * pseries-2.2
2577 */
2578
2579 #define SPAPR_COMPAT_2_2 \
2580 HW_COMPAT_2_2 \
2581 {\
2582 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2583 .property = "mem_win_size",\
2584 .value = "0x20000000",\
2585 },
2586
2587 static void spapr_machine_2_2_instance_options(MachineState *machine)
2588 {
2589 spapr_machine_2_3_instance_options(machine);
2590 machine->suppress_vmdesc = true;
2591 }
2592
2593 static void spapr_machine_2_2_class_options(MachineClass *mc)
2594 {
2595 spapr_machine_2_3_class_options(mc);
2596 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2597 }
2598 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2599
2600 /*
2601 * pseries-2.1
2602 */
2603 #define SPAPR_COMPAT_2_1 \
2604 HW_COMPAT_2_1
2605
2606 static void spapr_machine_2_1_instance_options(MachineState *machine)
2607 {
2608 spapr_machine_2_2_instance_options(machine);
2609 }
2610
2611 static void spapr_machine_2_1_class_options(MachineClass *mc)
2612 {
2613 spapr_machine_2_2_class_options(mc);
2614 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2615 }
2616 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2617
2618 static void spapr_machine_register_types(void)
2619 {
2620 type_register_static(&spapr_machine_info);
2621 }
2622
2623 type_init(spapr_machine_register_types)
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