2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu/datadir.h"
29 #include "qemu/memalign.h"
30 #include "qemu/guest-random.h"
31 #include "qapi/error.h"
32 #include "qapi/qapi-events-machine.h"
33 #include "qapi/qapi-events-qdev.h"
34 #include "qapi/visitor.h"
35 #include "sysemu/sysemu.h"
36 #include "sysemu/hostmem.h"
37 #include "sysemu/numa.h"
38 #include "sysemu/qtest.h"
39 #include "sysemu/reset.h"
40 #include "sysemu/runstate.h"
42 #include "hw/fw-path-provider.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/cpus.h"
47 #include "sysemu/hw_accel.h"
49 #include "migration/misc.h"
50 #include "migration/qemu-file-types.h"
51 #include "migration/global_state.h"
52 #include "migration/register.h"
53 #include "migration/blocker.h"
54 #include "mmu-hash64.h"
55 #include "mmu-book3s-v3.h"
56 #include "cpu-models.h"
57 #include "hw/core/cpu.h"
59 #include "hw/ppc/ppc.h"
60 #include "hw/loader.h"
62 #include "hw/ppc/fdt.h"
63 #include "hw/ppc/spapr.h"
64 #include "hw/ppc/spapr_vio.h"
65 #include "hw/ppc/vof.h"
66 #include "hw/qdev-properties.h"
67 #include "hw/pci-host/spapr.h"
68 #include "hw/pci/msi.h"
70 #include "hw/pci/pci.h"
71 #include "hw/scsi/scsi.h"
72 #include "hw/virtio/virtio-scsi.h"
73 #include "hw/virtio/vhost-scsi-common.h"
75 #include "exec/ram_addr.h"
77 #include "qemu/config-file.h"
78 #include "qemu/error-report.h"
81 #include "hw/intc/intc.h"
83 #include "hw/ppc/spapr_cpu_core.h"
84 #include "hw/mem/memory-device.h"
85 #include "hw/ppc/spapr_tpm_proxy.h"
86 #include "hw/ppc/spapr_nvdimm.h"
87 #include "hw/ppc/spapr_numa.h"
88 #include "hw/ppc/pef.h"
90 #include "monitor/monitor.h"
94 /* SLOF memory layout:
96 * SLOF raw image loaded at 0, copies its romfs right below the flat
97 * device-tree, then position SLOF itself 31M below that
99 * So we set FW_OVERHEAD to 40MB which should account for all of that
102 * We load our kernel at 4M, leaving space for SLOF initial image
104 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */
105 #define FW_MAX_SIZE 0x400000
106 #define FW_FILE_NAME "slof.bin"
107 #define FW_FILE_NAME_VOF "vof.bin"
108 #define FW_OVERHEAD 0x2800000
109 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
111 #define MIN_RMA_SLOF (128 * MiB)
113 #define PHANDLE_INTC 0x00001111
115 /* These two functions implement the VCPU id numbering: one to compute them
116 * all and one to identify thread 0 of a VCORE. Any change to the first one
117 * is likely to have an impact on the second one, so let's keep them close.
119 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
121 MachineState
*ms
= MACHINE(spapr
);
122 unsigned int smp_threads
= ms
->smp
.threads
;
126 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
128 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
132 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
135 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
137 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
138 * and newer QEMUs don't even have them. In both cases, we don't want
139 * to send anything on the wire.
144 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
145 .name
= "icp/server",
147 .minimum_version_id
= 1,
148 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
149 .fields
= (VMStateField
[]) {
150 VMSTATE_UNUSED(4), /* uint32_t xirr */
151 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
152 VMSTATE_UNUSED(1), /* uint8_t mfrr */
153 VMSTATE_END_OF_LIST()
157 static void pre_2_10_vmstate_register_dummy_icp(int i
)
159 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
160 (void *)(uintptr_t) i
);
163 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
165 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
166 (void *)(uintptr_t) i
);
169 int spapr_max_server_number(SpaprMachineState
*spapr
)
171 MachineState
*ms
= MACHINE(spapr
);
174 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
177 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
181 g_autofree
uint32_t *servers_prop
= g_new(uint32_t, smt_threads
);
182 g_autofree
uint32_t *gservers_prop
= g_new(uint32_t, smt_threads
* 2);
183 int index
= spapr_get_vcpu_id(cpu
);
185 if (cpu
->compat_pvr
) {
186 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
192 /* Build interrupt servers and gservers properties */
193 for (i
= 0; i
< smt_threads
; i
++) {
194 servers_prop
[i
] = cpu_to_be32(index
+ i
);
195 /* Hack, direct the group queues back to cpu 0 */
196 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
197 gservers_prop
[i
*2 + 1] = 0;
199 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
200 servers_prop
, sizeof(*servers_prop
) * smt_threads
);
204 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
205 gservers_prop
, sizeof(*gservers_prop
) * smt_threads
* 2);
210 static void spapr_dt_pa_features(SpaprMachineState
*spapr
,
212 void *fdt
, int offset
)
214 uint8_t pa_features_206
[] = { 6, 0,
215 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
216 uint8_t pa_features_207
[] = { 24, 0,
217 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
218 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
219 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
220 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
221 uint8_t pa_features_300
[] = { 66, 0,
222 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
223 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
224 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
226 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
228 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
229 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
231 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
233 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
234 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
235 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
237 /* 42: PM, 44: PC RA, 46: SC vec'd */
238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
239 /* 48: SIMD, 50: QP BFP, 52: String */
240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
241 /* 54: DecFP, 56: DecI, 58: SHA */
242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
243 /* 60: NM atomic, 62: RNG */
244 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
246 uint8_t *pa_features
= NULL
;
249 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
250 pa_features
= pa_features_206
;
251 pa_size
= sizeof(pa_features_206
);
253 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
254 pa_features
= pa_features_207
;
255 pa_size
= sizeof(pa_features_207
);
257 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
258 pa_features
= pa_features_300
;
259 pa_size
= sizeof(pa_features_300
);
265 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
267 * Note: we keep CI large pages off by default because a 64K capable
268 * guest provisioned with large pages might otherwise try to map a qemu
269 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
270 * even if that qemu runs on a 4k host.
271 * We dd this bit back here if we are confident this is not an issue
273 pa_features
[3] |= 0x20;
275 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
276 pa_features
[24] |= 0x80; /* Transactional memory support */
278 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
279 /* Workaround for broken kernels that attempt (guest) radix
280 * mode when they can't handle it, if they see the radix bit set
281 * in pa-features. So hide it from them. */
282 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
285 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
288 static hwaddr
spapr_node0_size(MachineState
*machine
)
290 if (machine
->numa_state
->num_nodes
) {
292 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
293 if (machine
->numa_state
->nodes
[i
].node_mem
) {
294 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
299 return machine
->ram_size
;
302 static void add_str(GString
*s
, const gchar
*s1
)
304 g_string_append_len(s
, s1
, strlen(s1
) + 1);
307 static int spapr_dt_memory_node(SpaprMachineState
*spapr
, void *fdt
, int nodeid
,
308 hwaddr start
, hwaddr size
)
311 uint64_t mem_reg_property
[2];
314 mem_reg_property
[0] = cpu_to_be64(start
);
315 mem_reg_property
[1] = cpu_to_be64(size
);
317 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
318 off
= fdt_add_subnode(fdt
, 0, mem_name
);
320 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
321 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
322 sizeof(mem_reg_property
))));
323 spapr_numa_write_associativity_dt(spapr
, fdt
, off
, nodeid
);
327 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
329 MemoryDeviceInfoList
*info
;
331 for (info
= list
; info
; info
= info
->next
) {
332 MemoryDeviceInfo
*value
= info
->value
;
334 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
335 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
337 if (addr
>= pcdimm_info
->addr
&&
338 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
339 return pcdimm_info
->node
;
347 struct sPAPRDrconfCellV2
{
355 typedef struct DrconfCellQueue
{
356 struct sPAPRDrconfCellV2 cell
;
357 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
360 static DrconfCellQueue
*
361 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
362 uint32_t drc_index
, uint32_t aa_index
,
365 DrconfCellQueue
*elem
;
367 elem
= g_malloc0(sizeof(*elem
));
368 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
369 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
370 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
371 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
372 elem
->cell
.flags
= cpu_to_be32(flags
);
377 static int spapr_dt_dynamic_memory_v2(SpaprMachineState
*spapr
, void *fdt
,
378 int offset
, MemoryDeviceInfoList
*dimms
)
380 MachineState
*machine
= MACHINE(spapr
);
381 uint8_t *int_buf
, *cur_index
;
383 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
384 uint64_t addr
, cur_addr
, size
;
385 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
386 uint64_t mem_end
= machine
->device_memory
->base
+
387 memory_region_size(&machine
->device_memory
->mr
);
388 uint32_t node
, buf_len
, nr_entries
= 0;
390 DrconfCellQueue
*elem
, *next
;
391 MemoryDeviceInfoList
*info
;
392 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
393 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
395 /* Entry to cover RAM and the gap area */
396 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
397 SPAPR_LMB_FLAGS_RESERVED
|
398 SPAPR_LMB_FLAGS_DRC_INVALID
);
399 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
402 cur_addr
= machine
->device_memory
->base
;
403 for (info
= dimms
; info
; info
= info
->next
) {
404 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
411 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
412 * area is marked hotpluggable in the next iteration for the bigger
413 * chunk including the NVDIMM occupied area.
415 if (info
->value
->type
== MEMORY_DEVICE_INFO_KIND_NVDIMM
)
418 /* Entry for hot-pluggable area */
419 if (cur_addr
< addr
) {
420 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
422 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
423 cur_addr
, spapr_drc_index(drc
), -1, 0);
424 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
429 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
431 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
432 spapr_drc_index(drc
), node
,
433 (SPAPR_LMB_FLAGS_ASSIGNED
|
434 SPAPR_LMB_FLAGS_HOTREMOVABLE
));
435 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
437 cur_addr
= addr
+ size
;
440 /* Entry for remaining hotpluggable area */
441 if (cur_addr
< mem_end
) {
442 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
444 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
445 cur_addr
, spapr_drc_index(drc
), -1, 0);
446 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
450 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
451 int_buf
= cur_index
= g_malloc0(buf_len
);
452 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
453 cur_index
+= sizeof(nr_entries
);
455 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
456 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
457 cur_index
+= sizeof(elem
->cell
);
458 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
462 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
470 static int spapr_dt_dynamic_memory(SpaprMachineState
*spapr
, void *fdt
,
471 int offset
, MemoryDeviceInfoList
*dimms
)
473 MachineState
*machine
= MACHINE(spapr
);
475 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
476 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
477 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
478 memory_region_size(&machine
->device_memory
->mr
)) /
480 uint32_t *int_buf
, *cur_index
, buf_len
;
483 * Allocate enough buffer size to fit in ibm,dynamic-memory
485 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
486 cur_index
= int_buf
= g_malloc0(buf_len
);
487 int_buf
[0] = cpu_to_be32(nr_lmbs
);
489 for (i
= 0; i
< nr_lmbs
; i
++) {
490 uint64_t addr
= i
* lmb_size
;
491 uint32_t *dynamic_memory
= cur_index
;
493 if (i
>= device_lmb_start
) {
496 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
499 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
500 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
501 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
502 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
503 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
504 if (memory_region_present(get_system_memory(), addr
)) {
505 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
507 dynamic_memory
[5] = cpu_to_be32(0);
511 * LMB information for RMA, boot time RAM and gap b/n RAM and
512 * device memory region -- all these are marked as reserved
513 * and as having no valid DRC.
515 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
516 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
517 dynamic_memory
[2] = cpu_to_be32(0);
518 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
519 dynamic_memory
[4] = cpu_to_be32(-1);
520 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
521 SPAPR_LMB_FLAGS_DRC_INVALID
);
524 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
526 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
535 * Adds ibm,dynamic-reconfiguration-memory node.
536 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
537 * of this device tree node.
539 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState
*spapr
,
542 MachineState
*machine
= MACHINE(spapr
);
544 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
545 uint32_t prop_lmb_size
[] = {cpu_to_be32(lmb_size
>> 32),
546 cpu_to_be32(lmb_size
& 0xffffffff)};
547 MemoryDeviceInfoList
*dimms
= NULL
;
550 * Don't create the node if there is no device memory
552 if (machine
->ram_size
== machine
->maxram_size
) {
556 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
558 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
559 sizeof(prop_lmb_size
));
564 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
569 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
574 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
575 dimms
= qmp_memory_device_list();
576 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
577 ret
= spapr_dt_dynamic_memory_v2(spapr
, fdt
, offset
, dimms
);
579 ret
= spapr_dt_dynamic_memory(spapr
, fdt
, offset
, dimms
);
581 qapi_free_MemoryDeviceInfoList(dimms
);
587 ret
= spapr_numa_write_assoc_lookup_arrays(spapr
, fdt
, offset
);
592 static int spapr_dt_memory(SpaprMachineState
*spapr
, void *fdt
)
594 MachineState
*machine
= MACHINE(spapr
);
595 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
596 hwaddr mem_start
, node_size
;
597 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
598 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
600 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
601 if (!nodes
[i
].node_mem
) {
604 if (mem_start
>= machine
->ram_size
) {
607 node_size
= nodes
[i
].node_mem
;
608 if (node_size
> machine
->ram_size
- mem_start
) {
609 node_size
= machine
->ram_size
- mem_start
;
613 /* spapr_machine_init() checks for rma_size <= node0_size
615 spapr_dt_memory_node(spapr
, fdt
, i
, 0, spapr
->rma_size
);
616 mem_start
+= spapr
->rma_size
;
617 node_size
-= spapr
->rma_size
;
619 for ( ; node_size
; ) {
620 hwaddr sizetmp
= pow2floor(node_size
);
622 /* mem_start != 0 here */
623 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
624 sizetmp
= 1ULL << ctzl(mem_start
);
627 spapr_dt_memory_node(spapr
, fdt
, i
, mem_start
, sizetmp
);
628 node_size
-= sizetmp
;
629 mem_start
+= sizetmp
;
633 /* Generate ibm,dynamic-reconfiguration-memory node if required */
634 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRCONF_MEMORY
)) {
637 g_assert(smc
->dr_lmb_enabled
);
638 ret
= spapr_dt_dynamic_reconfiguration_memory(spapr
, fdt
);
647 static void spapr_dt_cpu(CPUState
*cs
, void *fdt
, int offset
,
648 SpaprMachineState
*spapr
)
650 MachineState
*ms
= MACHINE(spapr
);
651 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
652 CPUPPCState
*env
= &cpu
->env
;
653 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
654 int index
= spapr_get_vcpu_id(cpu
);
655 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
656 0xffffffff, 0xffffffff};
657 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
658 : SPAPR_TIMEBASE_FREQ
;
659 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
660 uint32_t page_sizes_prop
[64];
661 size_t page_sizes_prop_size
;
662 unsigned int smp_threads
= ms
->smp
.threads
;
663 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
664 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
665 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
668 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
671 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
673 drc_index
= spapr_drc_index(drc
);
674 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
677 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
678 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
680 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
681 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
682 env
->dcache_line_size
)));
683 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
684 env
->dcache_line_size
)));
685 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
686 env
->icache_line_size
)));
687 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
688 env
->icache_line_size
)));
690 if (pcc
->l1_dcache_size
) {
691 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
692 pcc
->l1_dcache_size
)));
694 warn_report("Unknown L1 dcache size for cpu");
696 if (pcc
->l1_icache_size
) {
697 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
698 pcc
->l1_icache_size
)));
700 warn_report("Unknown L1 icache size for cpu");
703 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
704 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
705 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
706 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
707 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
708 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
710 if (ppc_has_spr(cpu
, SPR_PURR
)) {
711 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
713 if (ppc_has_spr(cpu
, SPR_PURR
)) {
714 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
717 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
718 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
719 segs
, sizeof(segs
))));
722 /* Advertise VSX (vector extensions) if available
723 * 1 == VMX / Altivec available
726 * Only CPUs for which we create core types in spapr_cpu_core.c
727 * are possible, and all of those have VMX */
728 if (env
->insns_flags
& PPC_ALTIVEC
) {
729 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
730 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
732 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
736 /* Advertise DFP (Decimal Floating Point) if available
737 * 0 / no property == no DFP
738 * 1 == DFP available */
739 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
740 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
743 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
744 sizeof(page_sizes_prop
));
745 if (page_sizes_prop_size
) {
746 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
747 page_sizes_prop
, page_sizes_prop_size
)));
750 spapr_dt_pa_features(spapr
, cpu
, fdt
, offset
);
752 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
753 cs
->cpu_index
/ vcpus_per_socket
)));
755 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
756 pft_size_prop
, sizeof(pft_size_prop
))));
758 if (ms
->numa_state
->num_nodes
> 1) {
759 _FDT(spapr_numa_fixup_cpu_dt(spapr
, fdt
, offset
, cpu
));
762 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
764 if (pcc
->radix_page_info
) {
765 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
766 radix_AP_encodings
[i
] =
767 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
769 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
771 pcc
->radix_page_info
->count
*
772 sizeof(radix_AP_encodings
[0]))));
776 * We set this property to let the guest know that it can use the large
777 * decrementer and its width in bits.
779 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
780 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
781 pcc
->lrg_decr_bits
)));
784 static void spapr_dt_cpus(void *fdt
, SpaprMachineState
*spapr
)
792 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
794 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
795 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
798 * We walk the CPUs in reverse order to ensure that CPU DT nodes
799 * created by fdt_add_subnode() end up in the right order in FDT
800 * for the guest kernel the enumerate the CPUs correctly.
802 * The CPU list cannot be traversed in reverse order, so we need
808 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
812 for (i
= n_cpus
- 1; i
>= 0; i
--) {
813 CPUState
*cs
= rev
[i
];
814 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
815 int index
= spapr_get_vcpu_id(cpu
);
816 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
817 g_autofree
char *nodename
= NULL
;
820 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
824 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
825 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
827 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
833 static int spapr_dt_rng(void *fdt
)
838 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
842 ret
= fdt_setprop_string(fdt
, node
, "device_type",
843 "ibm,platform-facilities");
844 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
845 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
847 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
851 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
856 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
858 MachineState
*ms
= MACHINE(spapr
);
860 GString
*hypertas
= g_string_sized_new(256);
861 GString
*qemu_hypertas
= g_string_sized_new(256);
862 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
863 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
864 uint32_t lrdr_capacity
[] = {
865 cpu_to_be32(max_device_addr
>> 32),
866 cpu_to_be32(max_device_addr
& 0xffffffff),
867 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
>> 32),
868 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
& 0xffffffff),
869 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
872 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
875 add_str(hypertas
, "hcall-pft");
876 add_str(hypertas
, "hcall-term");
877 add_str(hypertas
, "hcall-dabr");
878 add_str(hypertas
, "hcall-interrupt");
879 add_str(hypertas
, "hcall-tce");
880 add_str(hypertas
, "hcall-vio");
881 add_str(hypertas
, "hcall-splpar");
882 add_str(hypertas
, "hcall-join");
883 add_str(hypertas
, "hcall-bulk");
884 add_str(hypertas
, "hcall-set-mode");
885 add_str(hypertas
, "hcall-sprg0");
886 add_str(hypertas
, "hcall-copy");
887 add_str(hypertas
, "hcall-debug");
888 add_str(hypertas
, "hcall-vphn");
889 if (spapr_get_cap(spapr
, SPAPR_CAP_RPT_INVALIDATE
) == SPAPR_CAP_ON
) {
890 add_str(hypertas
, "hcall-rpt-invalidate");
893 add_str(qemu_hypertas
, "hcall-memop1");
895 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
896 add_str(hypertas
, "hcall-multi-tce");
899 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
900 add_str(hypertas
, "hcall-hpt-resize");
903 add_str(hypertas
, "hcall-watchdog");
905 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
906 hypertas
->str
, hypertas
->len
));
907 g_string_free(hypertas
, TRUE
);
908 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
909 qemu_hypertas
->str
, qemu_hypertas
->len
));
910 g_string_free(qemu_hypertas
, TRUE
);
912 spapr_numa_write_rtas_dt(spapr
, fdt
, rtas
);
915 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
916 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
918 * The system reset requirements are driven by existing Linux and PowerVM
919 * implementation which (contrary to PAPR) saves r3 in the error log
920 * structure like machine check, so Linux expects to find the saved r3
921 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
922 * does not look at the error value).
924 * System reset interrupts are not subject to interlock like machine
925 * check, so this memory area could be corrupted if the sreset is
926 * interrupted by a machine check (or vice versa) if it was shared. To
927 * prevent this, system reset uses per-CPU areas for the sreset save
928 * area. A system reset that interrupts a system reset handler could
929 * still overwrite this area, but Linux doesn't try to recover in that
932 * The extra 8 bytes is required because Linux's FWNMI error log check
935 * RTAS_MIN_SIZE is required for the RTAS blob itself.
937 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-size", RTAS_MIN_SIZE
+
939 ms
->smp
.max_cpus
* sizeof(uint64_t) * 2 +
941 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
942 RTAS_ERROR_LOG_MAX
));
943 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
944 RTAS_EVENT_SCAN_RATE
));
946 g_assert(msi_nonbroken
);
947 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
950 * According to PAPR, rtas ibm,os-term does not guarantee a return
951 * back to the guest cpu.
953 * While an additional ibm,extended-os-term property indicates
954 * that rtas call return will always occur. Set this property.
956 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
958 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
959 lrdr_capacity
, sizeof(lrdr_capacity
)));
961 spapr_dt_rtas_tokens(fdt
, rtas
);
965 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
966 * and the XIVE features that the guest may request and thus the valid
967 * values for bytes 23..26 of option vector 5:
969 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
972 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
975 23, 0x00, /* XICS / XIVE mode */
976 24, 0x00, /* Hash/Radix, filled in below. */
977 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
978 26, 0x40, /* Radix options: GTSE == yes. */
981 if (spapr
->irq
->xics
&& spapr
->irq
->xive
) {
982 val
[1] = SPAPR_OV5_XIVE_BOTH
;
983 } else if (spapr
->irq
->xive
) {
984 val
[1] = SPAPR_OV5_XIVE_EXPLOIT
;
986 assert(spapr
->irq
->xics
);
987 val
[1] = SPAPR_OV5_XIVE_LEGACY
;
990 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
991 first_ppc_cpu
->compat_pvr
)) {
993 * If we're in a pre POWER9 compat mode then the guest should
994 * do hash and use the legacy interrupt mode
996 val
[1] = SPAPR_OV5_XIVE_LEGACY
; /* XICS */
997 val
[3] = 0x00; /* Hash */
998 spapr_check_mmu_mode(false);
999 } else if (kvm_enabled()) {
1000 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1001 val
[3] = 0x80; /* OV5_MMU_BOTH */
1002 } else if (kvmppc_has_cap_mmu_radix()) {
1003 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1005 val
[3] = 0x00; /* Hash */
1008 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1011 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1015 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
, bool reset
)
1017 MachineState
*machine
= MACHINE(spapr
);
1018 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1019 uint8_t rng_seed
[32];
1022 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1025 const char *boot_device
= spapr
->boot_device
;
1026 g_autofree
char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1028 g_autofree
char *bootlist
= get_boot_devices_list(&cb
);
1030 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1031 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1032 machine
->kernel_cmdline
));
1035 if (spapr
->initrd_size
) {
1036 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1037 spapr
->initrd_base
));
1038 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1039 spapr
->initrd_base
+ spapr
->initrd_size
));
1042 if (spapr
->kernel_size
) {
1043 uint64_t kprop
[2] = { cpu_to_be64(spapr
->kernel_addr
),
1044 cpu_to_be64(spapr
->kernel_size
) };
1046 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1047 &kprop
, sizeof(kprop
)));
1048 if (spapr
->kernel_le
) {
1049 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1052 if (machine
->boot_config
.has_menu
&& machine
->boot_config
.menu
) {
1053 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", true)));
1055 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1056 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1057 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1059 if (cb
&& bootlist
) {
1062 for (i
= 0; i
< cb
; i
++) {
1063 if (bootlist
[i
] == '\n') {
1067 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1070 if (boot_device
&& strlen(boot_device
)) {
1071 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1074 if (spapr
->want_stdout_path
&& stdout_path
) {
1076 * "linux,stdout-path" and "stdout" properties are
1077 * deprecated by linux kernel. New platforms should only
1078 * use the "stdout-path" property. Set the new property
1079 * and continue using older property to remain compatible
1080 * with the existing firmware.
1082 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1083 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1087 * We can deal with BAR reallocation just fine, advertise it
1090 if (smc
->linux_pci_probe
) {
1091 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1094 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1097 qemu_guest_getrandom_nofail(rng_seed
, sizeof(rng_seed
));
1098 _FDT(fdt_setprop(fdt
, chosen
, "rng-seed", rng_seed
, sizeof(rng_seed
)));
1100 _FDT(spapr_dt_ovec(fdt
, chosen
, spapr
->ov5_cas
, "ibm,architecture-vec-5"));
1103 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1105 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1106 * KVM to work under pHyp with some guest co-operation */
1108 uint8_t hypercall
[16];
1110 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1111 /* indicate KVM hypercall interface */
1112 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1113 if (kvmppc_has_cap_fixup_hcalls()) {
1115 * Older KVM versions with older guest kernels were broken
1116 * with the magic page, don't allow the guest to map it.
1118 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1119 sizeof(hypercall
))) {
1120 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1121 hypercall
, sizeof(hypercall
)));
1126 void *spapr_build_fdt(SpaprMachineState
*spapr
, bool reset
, size_t space
)
1128 MachineState
*machine
= MACHINE(spapr
);
1129 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1130 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1131 uint32_t root_drc_type_mask
= 0;
1137 fdt
= g_malloc0(space
);
1138 _FDT((fdt_create_empty_tree(fdt
, space
)));
1141 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1142 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1143 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1145 /* Guest UUID & Name*/
1146 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1147 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1148 if (qemu_uuid_set
) {
1149 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1153 if (qemu_get_vm_name()) {
1154 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1155 qemu_get_vm_name()));
1158 /* Host Model & Serial Number */
1159 if (spapr
->host_model
) {
1160 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1161 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1162 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1166 if (spapr
->host_serial
) {
1167 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1168 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1169 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1173 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1174 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1176 /* /interrupt controller */
1177 spapr_irq_dt(spapr
, spapr_max_server_number(spapr
), fdt
, PHANDLE_INTC
);
1179 ret
= spapr_dt_memory(spapr
, fdt
);
1181 error_report("couldn't setup memory nodes in fdt");
1186 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1188 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1189 ret
= spapr_dt_rng(fdt
);
1191 error_report("could not set up rng device in the fdt");
1196 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1197 ret
= spapr_dt_phb(spapr
, phb
, PHANDLE_INTC
, fdt
, NULL
);
1199 error_report("couldn't setup PCI devices in fdt");
1204 spapr_dt_cpus(fdt
, spapr
);
1206 /* ibm,drc-indexes and friends */
1207 if (smc
->dr_lmb_enabled
) {
1208 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_LMB
;
1210 if (smc
->dr_phb_enabled
) {
1211 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_PHB
;
1213 if (mc
->nvdimm_supported
) {
1214 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_PMEM
;
1216 if (root_drc_type_mask
) {
1217 _FDT(spapr_dt_drc(fdt
, 0, NULL
, root_drc_type_mask
));
1220 if (mc
->has_hotpluggable_cpus
) {
1221 int offset
= fdt_path_offset(fdt
, "/cpus");
1222 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1224 error_report("Couldn't set up CPU DR device tree properties");
1229 /* /event-sources */
1230 spapr_dt_events(spapr
, fdt
);
1233 spapr_dt_rtas(spapr
, fdt
);
1236 spapr_dt_chosen(spapr
, fdt
, reset
);
1239 if (kvm_enabled()) {
1240 spapr_dt_hypervisor(spapr
, fdt
);
1243 /* Build memory reserve map */
1245 if (spapr
->kernel_size
) {
1246 _FDT((fdt_add_mem_rsv(fdt
, spapr
->kernel_addr
,
1247 spapr
->kernel_size
)));
1249 if (spapr
->initrd_size
) {
1250 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
,
1251 spapr
->initrd_size
)));
1255 /* NVDIMM devices */
1256 if (mc
->nvdimm_supported
) {
1257 spapr_dt_persistent_memory(spapr
, fdt
);
1263 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1265 SpaprMachineState
*spapr
= opaque
;
1267 return (addr
& 0x0fffffff) + spapr
->kernel_addr
;
1270 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1273 CPUPPCState
*env
= &cpu
->env
;
1275 /* The TCG path should also be holding the BQL at this point */
1276 g_assert(qemu_mutex_iothread_locked());
1278 g_assert(!vhyp_cpu_in_nested(cpu
));
1280 if (FIELD_EX64(env
->msr
, MSR
, PR
)) {
1281 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1282 env
->gpr
[3] = H_PRIVILEGE
;
1284 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1288 struct LPCRSyncState
{
1293 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1295 struct LPCRSyncState
*s
= arg
.host_ptr
;
1296 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1297 CPUPPCState
*env
= &cpu
->env
;
1300 cpu_synchronize_state(cs
);
1301 lpcr
= env
->spr
[SPR_LPCR
];
1304 ppc_store_lpcr(cpu
, lpcr
);
1307 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1310 struct LPCRSyncState s
= {
1315 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1319 static bool spapr_get_pate(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
,
1320 target_ulong lpid
, ppc_v3_pate_t
*entry
)
1322 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1323 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
1325 if (!spapr_cpu
->in_nested
) {
1328 /* Copy PATE1:GR into PATE0:HR */
1329 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1330 entry
->dw1
= spapr
->patb_entry
;
1333 uint64_t patb
, pats
;
1337 patb
= spapr
->nested_ptcr
& PTCR_PATB
;
1338 pats
= spapr
->nested_ptcr
& PTCR_PATS
;
1340 /* Check if partition table is properly aligned */
1341 if (patb
& MAKE_64BIT_MASK(0, pats
+ 12)) {
1345 /* Calculate number of entries */
1346 pats
= 1ull << (pats
+ 12 - 4);
1353 entry
->dw0
= ldq_phys(CPU(cpu
)->as
, patb
);
1354 entry
->dw1
= ldq_phys(CPU(cpu
)->as
, patb
+ 8);
1360 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1361 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1362 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1363 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1364 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1367 * Get the fd to access the kernel htab, re-opening it if necessary
1369 static int get_htab_fd(SpaprMachineState
*spapr
)
1371 Error
*local_err
= NULL
;
1373 if (spapr
->htab_fd
>= 0) {
1374 return spapr
->htab_fd
;
1377 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1378 if (spapr
->htab_fd
< 0) {
1379 error_report_err(local_err
);
1382 return spapr
->htab_fd
;
1385 void close_htab_fd(SpaprMachineState
*spapr
)
1387 if (spapr
->htab_fd
>= 0) {
1388 close(spapr
->htab_fd
);
1390 spapr
->htab_fd
= -1;
1393 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1395 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1397 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1400 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1402 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1404 assert(kvm_enabled());
1410 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1413 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1416 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1417 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1421 * HTAB is controlled by KVM. Fetch into temporary buffer
1423 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1424 kvmppc_read_hptes(hptes
, ptex
, n
);
1429 * HTAB is controlled by QEMU. Just point to the internally
1432 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1435 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1436 const ppc_hash_pte64_t
*hptes
,
1439 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1442 g_free((void *)hptes
);
1445 /* Nothing to do for qemu managed HPT */
1448 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1449 uint64_t pte0
, uint64_t pte1
)
1451 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1452 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1455 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1457 if (pte0
& HPTE64_V_VALID
) {
1458 stq_p(spapr
->htab
+ offset
+ HPTE64_DW1
, pte1
);
1460 * When setting valid, we write PTE1 first. This ensures
1461 * proper synchronization with the reading code in
1462 * ppc_hash64_pteg_search()
1465 stq_p(spapr
->htab
+ offset
, pte0
);
1467 stq_p(spapr
->htab
+ offset
, pte0
);
1469 * When clearing it we set PTE0 first. This ensures proper
1470 * synchronization with the reading code in
1471 * ppc_hash64_pteg_search()
1474 stq_p(spapr
->htab
+ offset
+ HPTE64_DW1
, pte1
);
1479 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1482 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ HPTE64_DW1_C
;
1483 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1486 /* There should always be a hash table when this is called */
1487 error_report("spapr_hpte_set_c called with no hash table !");
1491 /* The HW performs a non-atomic byte update */
1492 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1495 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1498 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ HPTE64_DW1_R
;
1499 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1502 /* There should always be a hash table when this is called */
1503 error_report("spapr_hpte_set_r called with no hash table !");
1507 /* The HW performs a non-atomic byte update */
1508 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1511 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1515 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1516 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1517 * that's much more than is needed for Linux guests */
1518 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1519 shift
= MAX(shift
, 18); /* Minimum architected size */
1520 shift
= MIN(shift
, 46); /* Maximum architected size */
1524 void spapr_free_hpt(SpaprMachineState
*spapr
)
1526 qemu_vfree(spapr
->htab
);
1528 spapr
->htab_shift
= 0;
1529 close_htab_fd(spapr
);
1532 int spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
, Error
**errp
)
1537 /* Clean up any HPT info from a previous boot */
1538 spapr_free_hpt(spapr
);
1540 rc
= kvmppc_reset_htab(shift
);
1542 if (rc
== -EOPNOTSUPP
) {
1543 error_setg(errp
, "HPT not supported in nested guests");
1548 /* kernel-side HPT needed, but couldn't allocate one */
1549 error_setg_errno(errp
, errno
, "Failed to allocate KVM HPT of order %d",
1551 error_append_hint(errp
, "Try smaller maxmem?\n");
1553 } else if (rc
> 0) {
1554 /* kernel-side HPT allocated */
1557 "Requested order %d HPT, but kernel allocated order %ld",
1559 error_append_hint(errp
, "Try smaller maxmem?\n");
1563 spapr
->htab_shift
= shift
;
1566 /* kernel-side HPT not needed, allocate in userspace instead */
1567 size_t size
= 1ULL << shift
;
1570 spapr
->htab
= qemu_memalign(size
, size
);
1571 memset(spapr
->htab
, 0, size
);
1572 spapr
->htab_shift
= shift
;
1574 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1575 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1578 /* We're setting up a hash table, so that means we're not radix */
1579 spapr
->patb_entry
= 0;
1580 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1584 void spapr_setup_hpt(SpaprMachineState
*spapr
)
1588 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
) {
1589 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1591 uint64_t current_ram_size
;
1593 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1594 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1596 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1598 if (kvm_enabled()) {
1599 hwaddr vrma_limit
= kvmppc_vrma_limit(spapr
->htab_shift
);
1601 /* Check our RMA fits in the possible VRMA */
1602 if (vrma_limit
< spapr
->rma_size
) {
1603 error_report("Unable to create %" HWADDR_PRIu
1604 "MiB RMA (VRMA only allows %" HWADDR_PRIu
"MiB",
1605 spapr
->rma_size
/ MiB
, vrma_limit
/ MiB
);
1611 void spapr_check_mmu_mode(bool guest_radix
)
1614 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) {
1615 error_report("Guest requested unavailable MMU mode (radix).");
1619 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()
1620 && !kvmppc_has_cap_mmu_hash_v3()) {
1621 error_report("Guest requested unavailable MMU mode (hash).");
1627 static void spapr_machine_reset(MachineState
*machine
, ShutdownCause reason
)
1629 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1630 PowerPCCPU
*first_ppc_cpu
;
1635 pef_kvm_reset(machine
->cgs
, &error_fatal
);
1636 spapr_caps_apply(spapr
);
1638 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1639 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1640 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1641 spapr
->max_compat_pvr
)) {
1643 * If using KVM with radix mode available, VCPUs can be started
1644 * without a HPT because KVM will start them in radix mode.
1645 * Set the GR bit in PATE so that we know there is no HPT.
1647 spapr
->patb_entry
= PATE1_GR
;
1648 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1650 spapr_setup_hpt(spapr
);
1653 qemu_devices_reset(reason
);
1655 spapr_ovec_cleanup(spapr
->ov5_cas
);
1656 spapr
->ov5_cas
= spapr_ovec_new();
1658 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1661 * This is fixing some of the default configuration of the XIVE
1662 * devices. To be called after the reset of the machine devices.
1664 spapr_irq_reset(spapr
, &error_fatal
);
1667 * There is no CAS under qtest. Simulate one to please the code that
1668 * depends on spapr->ov5_cas. This is especially needed to test device
1669 * unplug, so we do that before resetting the DRCs.
1671 if (qtest_enabled()) {
1672 spapr_ovec_cleanup(spapr
->ov5_cas
);
1673 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1676 spapr_nvdimm_finish_flushes();
1678 /* DRC reset may cause a device to be unplugged. This will cause troubles
1679 * if this device is used by another device (eg, a running vhost backend
1680 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1681 * situations, we reset DRCs after all devices have been reset.
1683 spapr_drc_reset_all(spapr
);
1685 spapr_clear_pending_events(spapr
);
1688 * We place the device tree just below either the top of the RMA,
1689 * or just below 2GB, whichever is lower, so that it can be
1690 * processed with 32-bit real mode code if necessary
1692 fdt_addr
= MIN(spapr
->rma_size
, FDT_MAX_ADDR
) - FDT_MAX_SIZE
;
1694 fdt
= spapr_build_fdt(spapr
, true, FDT_MAX_SIZE
);
1696 spapr_vof_reset(spapr
, fdt
, &error_fatal
);
1698 * Do not pack the FDT as the client may change properties.
1699 * VOF client does not expect the FDT so we do not load it to the VM.
1703 /* Should only fail if we've built a corrupted tree */
1706 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
,
1708 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1710 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1712 g_free(spapr
->fdt_blob
);
1713 spapr
->fdt_size
= fdt_totalsize(fdt
);
1714 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1715 spapr
->fdt_blob
= fdt
;
1717 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
1720 /* Set up the entry state */
1721 first_ppc_cpu
->env
.gpr
[5] = 0;
1723 spapr
->fwnmi_system_reset_addr
= -1;
1724 spapr
->fwnmi_machine_check_addr
= -1;
1725 spapr
->fwnmi_machine_check_interlock
= -1;
1727 /* Signal all vCPUs waiting on this condition */
1728 qemu_cond_broadcast(&spapr
->fwnmi_machine_check_interlock_cond
);
1730 migrate_del_blocker(spapr
->fwnmi_migration_blocker
);
1733 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1735 DeviceState
*dev
= qdev_new("spapr-nvram");
1736 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1739 qdev_prop_set_drive_err(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1743 qdev_realize_and_unref(dev
, &spapr
->vio_bus
->bus
, &error_fatal
);
1745 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1748 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1750 object_initialize_child_with_props(OBJECT(spapr
), "rtc", &spapr
->rtc
,
1751 sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1752 &error_fatal
, NULL
);
1753 qdev_realize(DEVICE(&spapr
->rtc
), NULL
, &error_fatal
);
1754 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1758 /* Returns whether we want to use VGA or not */
1759 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1761 vga_interface_created
= true;
1762 switch (vga_interface_type
) {
1770 return pci_vga_init(pci_bus
) != NULL
;
1773 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1778 static int spapr_pre_load(void *opaque
)
1782 rc
= spapr_caps_pre_load(opaque
);
1790 static int spapr_post_load(void *opaque
, int version_id
)
1792 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1795 err
= spapr_caps_post_migration(spapr
);
1801 * In earlier versions, there was no separate qdev for the PAPR
1802 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1803 * So when migrating from those versions, poke the incoming offset
1804 * value into the RTC device
1806 if (version_id
< 3) {
1807 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1813 if (kvm_enabled() && spapr
->patb_entry
) {
1814 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1815 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1816 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1819 * Update LPCR:HR and UPRT as they may not be set properly in
1822 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1823 LPCR_HR
| LPCR_UPRT
);
1825 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1827 error_report("Process table config unsupported by the host");
1832 err
= spapr_irq_post_load(spapr
, version_id
);
1840 static int spapr_pre_save(void *opaque
)
1844 rc
= spapr_caps_pre_save(opaque
);
1852 static bool version_before_3(void *opaque
, int version_id
)
1854 return version_id
< 3;
1857 static bool spapr_pending_events_needed(void *opaque
)
1859 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1860 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1863 static const VMStateDescription vmstate_spapr_event_entry
= {
1864 .name
= "spapr_event_log_entry",
1866 .minimum_version_id
= 1,
1867 .fields
= (VMStateField
[]) {
1868 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1869 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1870 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1871 NULL
, extended_length
),
1872 VMSTATE_END_OF_LIST()
1876 static const VMStateDescription vmstate_spapr_pending_events
= {
1877 .name
= "spapr_pending_events",
1879 .minimum_version_id
= 1,
1880 .needed
= spapr_pending_events_needed
,
1881 .fields
= (VMStateField
[]) {
1882 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1883 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1884 VMSTATE_END_OF_LIST()
1888 static bool spapr_ov5_cas_needed(void *opaque
)
1890 SpaprMachineState
*spapr
= opaque
;
1891 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1894 /* Prior to the introduction of SpaprOptionVector, we had two option
1895 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1896 * Both of these options encode machine topology into the device-tree
1897 * in such a way that the now-booted OS should still be able to interact
1898 * appropriately with QEMU regardless of what options were actually
1899 * negotiatied on the source side.
1901 * As such, we can avoid migrating the CAS-negotiated options if these
1902 * are the only options available on the current machine/platform.
1903 * Since these are the only options available for pseries-2.7 and
1904 * earlier, this allows us to maintain old->new/new->old migration
1907 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1908 * via default pseries-2.8 machines and explicit command-line parameters.
1909 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1910 * of the actual CAS-negotiated values to continue working properly. For
1911 * example, availability of memory unplug depends on knowing whether
1912 * OV5_HP_EVT was negotiated via CAS.
1914 * Thus, for any cases where the set of available CAS-negotiatable
1915 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1916 * include the CAS-negotiated options in the migration stream, unless
1917 * if they affect boot time behaviour only.
1919 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1920 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1921 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1923 /* We need extra information if we have any bits outside the mask
1925 cas_needed
= !spapr_ovec_subset(spapr
->ov5
, ov5_mask
);
1927 spapr_ovec_cleanup(ov5_mask
);
1932 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1933 .name
= "spapr_option_vector_ov5_cas",
1935 .minimum_version_id
= 1,
1936 .needed
= spapr_ov5_cas_needed
,
1937 .fields
= (VMStateField
[]) {
1938 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1939 vmstate_spapr_ovec
, SpaprOptionVector
),
1940 VMSTATE_END_OF_LIST()
1944 static bool spapr_patb_entry_needed(void *opaque
)
1946 SpaprMachineState
*spapr
= opaque
;
1948 return !!spapr
->patb_entry
;
1951 static const VMStateDescription vmstate_spapr_patb_entry
= {
1952 .name
= "spapr_patb_entry",
1954 .minimum_version_id
= 1,
1955 .needed
= spapr_patb_entry_needed
,
1956 .fields
= (VMStateField
[]) {
1957 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1958 VMSTATE_END_OF_LIST()
1962 static bool spapr_irq_map_needed(void *opaque
)
1964 SpaprMachineState
*spapr
= opaque
;
1966 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1969 static const VMStateDescription vmstate_spapr_irq_map
= {
1970 .name
= "spapr_irq_map",
1972 .minimum_version_id
= 1,
1973 .needed
= spapr_irq_map_needed
,
1974 .fields
= (VMStateField
[]) {
1975 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
1976 VMSTATE_END_OF_LIST()
1980 static bool spapr_dtb_needed(void *opaque
)
1982 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
1984 return smc
->update_dt_enabled
;
1987 static int spapr_dtb_pre_load(void *opaque
)
1989 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1991 g_free(spapr
->fdt_blob
);
1992 spapr
->fdt_blob
= NULL
;
1993 spapr
->fdt_size
= 0;
1998 static const VMStateDescription vmstate_spapr_dtb
= {
1999 .name
= "spapr_dtb",
2001 .minimum_version_id
= 1,
2002 .needed
= spapr_dtb_needed
,
2003 .pre_load
= spapr_dtb_pre_load
,
2004 .fields
= (VMStateField
[]) {
2005 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
2006 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
2007 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
2009 VMSTATE_END_OF_LIST()
2013 static bool spapr_fwnmi_needed(void *opaque
)
2015 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2017 return spapr
->fwnmi_machine_check_addr
!= -1;
2020 static int spapr_fwnmi_pre_save(void *opaque
)
2022 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2025 * Check if machine check handling is in progress and print a
2028 if (spapr
->fwnmi_machine_check_interlock
!= -1) {
2029 warn_report("A machine check is being handled during migration. The"
2030 "handler may run and log hardware error on the destination");
2036 static const VMStateDescription vmstate_spapr_fwnmi
= {
2037 .name
= "spapr_fwnmi",
2039 .minimum_version_id
= 1,
2040 .needed
= spapr_fwnmi_needed
,
2041 .pre_save
= spapr_fwnmi_pre_save
,
2042 .fields
= (VMStateField
[]) {
2043 VMSTATE_UINT64(fwnmi_system_reset_addr
, SpaprMachineState
),
2044 VMSTATE_UINT64(fwnmi_machine_check_addr
, SpaprMachineState
),
2045 VMSTATE_INT32(fwnmi_machine_check_interlock
, SpaprMachineState
),
2046 VMSTATE_END_OF_LIST()
2050 static const VMStateDescription vmstate_spapr
= {
2053 .minimum_version_id
= 1,
2054 .pre_load
= spapr_pre_load
,
2055 .post_load
= spapr_post_load
,
2056 .pre_save
= spapr_pre_save
,
2057 .fields
= (VMStateField
[]) {
2058 /* used to be @next_irq */
2059 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2062 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2064 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2065 VMSTATE_END_OF_LIST()
2067 .subsections
= (const VMStateDescription
*[]) {
2068 &vmstate_spapr_ov5_cas
,
2069 &vmstate_spapr_patb_entry
,
2070 &vmstate_spapr_pending_events
,
2071 &vmstate_spapr_cap_htm
,
2072 &vmstate_spapr_cap_vsx
,
2073 &vmstate_spapr_cap_dfp
,
2074 &vmstate_spapr_cap_cfpc
,
2075 &vmstate_spapr_cap_sbbc
,
2076 &vmstate_spapr_cap_ibs
,
2077 &vmstate_spapr_cap_hpt_maxpagesize
,
2078 &vmstate_spapr_irq_map
,
2079 &vmstate_spapr_cap_nested_kvm_hv
,
2081 &vmstate_spapr_cap_large_decr
,
2082 &vmstate_spapr_cap_ccf_assist
,
2083 &vmstate_spapr_cap_fwnmi
,
2084 &vmstate_spapr_fwnmi
,
2085 &vmstate_spapr_cap_rpt_invalidate
,
2090 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2092 SpaprMachineState
*spapr
= opaque
;
2094 /* "Iteration" header */
2095 if (!spapr
->htab_shift
) {
2096 qemu_put_be32(f
, -1);
2098 qemu_put_be32(f
, spapr
->htab_shift
);
2102 spapr
->htab_save_index
= 0;
2103 spapr
->htab_first_pass
= true;
2105 if (spapr
->htab_shift
) {
2106 assert(kvm_enabled());
2114 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2115 int chunkstart
, int n_valid
, int n_invalid
)
2117 qemu_put_be32(f
, chunkstart
);
2118 qemu_put_be16(f
, n_valid
);
2119 qemu_put_be16(f
, n_invalid
);
2120 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2121 HASH_PTE_SIZE_64
* n_valid
);
2124 static void htab_save_end_marker(QEMUFile
*f
)
2126 qemu_put_be32(f
, 0);
2127 qemu_put_be16(f
, 0);
2128 qemu_put_be16(f
, 0);
2131 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2134 bool has_timeout
= max_ns
!= -1;
2135 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2136 int index
= spapr
->htab_save_index
;
2137 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2139 assert(spapr
->htab_first_pass
);
2144 /* Consume invalid HPTEs */
2145 while ((index
< htabslots
)
2146 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2147 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2151 /* Consume valid HPTEs */
2153 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2154 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2155 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2159 if (index
> chunkstart
) {
2160 int n_valid
= index
- chunkstart
;
2162 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2165 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2169 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2171 if (index
>= htabslots
) {
2172 assert(index
== htabslots
);
2174 spapr
->htab_first_pass
= false;
2176 spapr
->htab_save_index
= index
;
2179 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2182 bool final
= max_ns
< 0;
2183 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2184 int examined
= 0, sent
= 0;
2185 int index
= spapr
->htab_save_index
;
2186 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2188 assert(!spapr
->htab_first_pass
);
2191 int chunkstart
, invalidstart
;
2193 /* Consume non-dirty HPTEs */
2194 while ((index
< htabslots
)
2195 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2201 /* Consume valid dirty HPTEs */
2202 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2203 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2204 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2205 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2210 invalidstart
= index
;
2211 /* Consume invalid dirty HPTEs */
2212 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2213 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2214 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2215 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2220 if (index
> chunkstart
) {
2221 int n_valid
= invalidstart
- chunkstart
;
2222 int n_invalid
= index
- invalidstart
;
2224 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2225 sent
+= index
- chunkstart
;
2227 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2232 if (examined
>= htabslots
) {
2236 if (index
>= htabslots
) {
2237 assert(index
== htabslots
);
2240 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2242 if (index
>= htabslots
) {
2243 assert(index
== htabslots
);
2247 spapr
->htab_save_index
= index
;
2249 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2252 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2253 #define MAX_KVM_BUF_SIZE 2048
2255 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2257 SpaprMachineState
*spapr
= opaque
;
2261 /* Iteration header */
2262 if (!spapr
->htab_shift
) {
2263 qemu_put_be32(f
, -1);
2266 qemu_put_be32(f
, 0);
2270 assert(kvm_enabled());
2272 fd
= get_htab_fd(spapr
);
2277 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2281 } else if (spapr
->htab_first_pass
) {
2282 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2284 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2287 htab_save_end_marker(f
);
2292 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2294 SpaprMachineState
*spapr
= opaque
;
2297 /* Iteration header */
2298 if (!spapr
->htab_shift
) {
2299 qemu_put_be32(f
, -1);
2302 qemu_put_be32(f
, 0);
2308 assert(kvm_enabled());
2310 fd
= get_htab_fd(spapr
);
2315 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2320 if (spapr
->htab_first_pass
) {
2321 htab_save_first_pass(f
, spapr
, -1);
2323 htab_save_later_pass(f
, spapr
, -1);
2327 htab_save_end_marker(f
);
2332 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2334 SpaprMachineState
*spapr
= opaque
;
2335 uint32_t section_hdr
;
2337 Error
*local_err
= NULL
;
2339 if (version_id
< 1 || version_id
> 1) {
2340 error_report("htab_load() bad version");
2344 section_hdr
= qemu_get_be32(f
);
2346 if (section_hdr
== -1) {
2347 spapr_free_hpt(spapr
);
2354 /* First section gives the htab size */
2355 ret
= spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2357 error_report_err(local_err
);
2364 assert(kvm_enabled());
2366 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2368 error_report_err(local_err
);
2375 uint16_t n_valid
, n_invalid
;
2377 index
= qemu_get_be32(f
);
2378 n_valid
= qemu_get_be16(f
);
2379 n_invalid
= qemu_get_be16(f
);
2381 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2386 if ((index
+ n_valid
+ n_invalid
) >
2387 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2388 /* Bad index in stream */
2390 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2391 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2397 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2398 HASH_PTE_SIZE_64
* n_valid
);
2401 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2402 HASH_PTE_SIZE_64
* n_invalid
);
2409 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
,
2412 error_report_err(local_err
);
2426 static void htab_save_cleanup(void *opaque
)
2428 SpaprMachineState
*spapr
= opaque
;
2430 close_htab_fd(spapr
);
2433 static SaveVMHandlers savevm_htab_handlers
= {
2434 .save_setup
= htab_save_setup
,
2435 .save_live_iterate
= htab_save_iterate
,
2436 .save_live_complete_precopy
= htab_save_complete
,
2437 .save_cleanup
= htab_save_cleanup
,
2438 .load_state
= htab_load
,
2441 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2444 SpaprMachineState
*spapr
= SPAPR_MACHINE(opaque
);
2446 g_free(spapr
->boot_device
);
2447 spapr
->boot_device
= g_strdup(boot_device
);
2450 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2452 MachineState
*machine
= MACHINE(spapr
);
2453 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2454 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2457 for (i
= 0; i
< nr_lmbs
; i
++) {
2460 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2461 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2467 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2468 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2469 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2471 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2475 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2476 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2477 " is not aligned to %" PRIu64
" MiB",
2479 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2483 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2484 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2485 " is not aligned to %" PRIu64
" MiB",
2487 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2491 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2492 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2494 "Node %d memory size 0x%" PRIx64
2495 " is not aligned to %" PRIu64
" MiB",
2496 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2497 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2503 /* find cpu slot in machine->possible_cpus by core_id */
2504 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2506 int index
= id
/ ms
->smp
.threads
;
2508 if (index
>= ms
->possible_cpus
->len
) {
2514 return &ms
->possible_cpus
->cpus
[index
];
2517 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2519 MachineState
*ms
= MACHINE(spapr
);
2520 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2521 Error
*local_err
= NULL
;
2522 bool vsmt_user
= !!spapr
->vsmt
;
2523 int kvm_smt
= kvmppc_smt_threads();
2525 unsigned int smp_threads
= ms
->smp
.threads
;
2527 if (!kvm_enabled() && (smp_threads
> 1)) {
2528 error_setg(errp
, "TCG cannot support more than 1 thread/core "
2529 "on a pseries machine");
2532 if (!is_power_of_2(smp_threads
)) {
2533 error_setg(errp
, "Cannot support %d threads/core on a pseries "
2534 "machine because it must be a power of 2", smp_threads
);
2538 /* Detemine the VSMT mode to use: */
2540 if (spapr
->vsmt
< smp_threads
) {
2541 error_setg(errp
, "Cannot support VSMT mode %d"
2542 " because it must be >= threads/core (%d)",
2543 spapr
->vsmt
, smp_threads
);
2546 /* In this case, spapr->vsmt has been set by the command line */
2547 } else if (!smc
->smp_threads_vsmt
) {
2549 * Default VSMT value is tricky, because we need it to be as
2550 * consistent as possible (for migration), but this requires
2551 * changing it for at least some existing cases. We pick 8 as
2552 * the value that we'd get with KVM on POWER8, the
2553 * overwhelmingly common case in production systems.
2555 spapr
->vsmt
= MAX(8, smp_threads
);
2557 spapr
->vsmt
= smp_threads
;
2560 /* KVM: If necessary, set the SMT mode: */
2561 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2562 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2564 /* Looks like KVM isn't able to change VSMT mode */
2565 error_setg(&local_err
,
2566 "Failed to set KVM's VSMT mode to %d (errno %d)",
2568 /* We can live with that if the default one is big enough
2569 * for the number of threads, and a submultiple of the one
2570 * we want. In this case we'll waste some vcpu ids, but
2571 * behaviour will be correct */
2572 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2573 warn_report_err(local_err
);
2576 error_append_hint(&local_err
,
2577 "On PPC, a VM with %d threads/core"
2578 " on a host with %d threads/core"
2579 " requires the use of VSMT mode %d.\n",
2580 smp_threads
, kvm_smt
, spapr
->vsmt
);
2582 kvmppc_error_append_smt_possible_hint(&local_err
);
2583 error_propagate(errp
, local_err
);
2587 /* else TCG: nothing to do currently */
2590 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2592 MachineState
*machine
= MACHINE(spapr
);
2593 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2594 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2595 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2596 const CPUArchIdList
*possible_cpus
;
2597 unsigned int smp_cpus
= machine
->smp
.cpus
;
2598 unsigned int smp_threads
= machine
->smp
.threads
;
2599 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2600 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2603 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2604 if (mc
->has_hotpluggable_cpus
) {
2605 if (smp_cpus
% smp_threads
) {
2606 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2607 smp_cpus
, smp_threads
);
2610 if (max_cpus
% smp_threads
) {
2611 error_report("max_cpus (%u) must be multiple of threads (%u)",
2612 max_cpus
, smp_threads
);
2616 if (max_cpus
!= smp_cpus
) {
2617 error_report("This machine version does not support CPU hotplug");
2620 boot_cores_nr
= possible_cpus
->len
;
2623 if (smc
->pre_2_10_has_unused_icps
) {
2626 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2627 /* Dummy entries get deregistered when real ICPState objects
2628 * are registered during CPU core hotplug.
2630 pre_2_10_vmstate_register_dummy_icp(i
);
2634 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2635 int core_id
= i
* smp_threads
;
2637 if (mc
->has_hotpluggable_cpus
) {
2638 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2639 spapr_vcpu_id(spapr
, core_id
));
2642 if (i
< boot_cores_nr
) {
2643 Object
*core
= object_new(type
);
2644 int nr_threads
= smp_threads
;
2646 /* Handle the partially filled core for older machine types */
2647 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2648 nr_threads
= smp_cpus
- i
* smp_threads
;
2651 object_property_set_int(core
, "nr-threads", nr_threads
,
2653 object_property_set_int(core
, CPU_CORE_PROP_CORE_ID
, core_id
,
2655 qdev_realize(DEVICE(core
), NULL
, &error_fatal
);
2662 static PCIHostState
*spapr_create_default_phb(void)
2666 dev
= qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE
);
2667 qdev_prop_set_uint32(dev
, "index", 0);
2668 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
2670 return PCI_HOST_BRIDGE(dev
);
2673 static hwaddr
spapr_rma_size(SpaprMachineState
*spapr
, Error
**errp
)
2675 MachineState
*machine
= MACHINE(spapr
);
2676 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2677 hwaddr rma_size
= machine
->ram_size
;
2678 hwaddr node0_size
= spapr_node0_size(machine
);
2680 /* RMA has to fit in the first NUMA node */
2681 rma_size
= MIN(rma_size
, node0_size
);
2684 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2687 rma_size
= MIN(rma_size
, 1 * TiB
);
2690 * Clamp the RMA size based on machine type. This is for
2691 * migration compatibility with older qemu versions, which limited
2692 * the RMA size for complicated and mostly bad reasons.
2694 if (smc
->rma_limit
) {
2695 rma_size
= MIN(rma_size
, smc
->rma_limit
);
2698 if (rma_size
< MIN_RMA_SLOF
) {
2700 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2701 "ldMiB guest RMA (Real Mode Area memory)",
2702 MIN_RMA_SLOF
/ MiB
);
2709 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState
*spapr
)
2711 MachineState
*machine
= MACHINE(spapr
);
2714 for (i
= 0; i
< machine
->ram_slots
; i
++) {
2715 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_PMEM
, i
);
2719 /* pSeries LPAR / sPAPR hardware init */
2720 static void spapr_machine_init(MachineState
*machine
)
2722 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2723 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2724 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2725 const char *bios_default
= spapr
->vof
? FW_FILE_NAME_VOF
: FW_FILE_NAME
;
2726 const char *bios_name
= machine
->firmware
?: bios_default
;
2727 g_autofree
char *filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2728 const char *kernel_filename
= machine
->kernel_filename
;
2729 const char *initrd_filename
= machine
->initrd_filename
;
2733 MemoryRegion
*sysmem
= get_system_memory();
2734 long load_limit
, fw_size
;
2735 Error
*resize_hpt_err
= NULL
;
2738 error_report("Could not find LPAR firmware '%s'", bios_name
);
2741 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2743 error_report("Could not load LPAR firmware '%s'", filename
);
2748 * if Secure VM (PEF) support is configured, then initialize it
2750 pef_kvm_init(machine
->cgs
, &error_fatal
);
2752 msi_nonbroken
= true;
2754 QLIST_INIT(&spapr
->phbs
);
2755 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2757 /* Determine capabilities to run with */
2758 spapr_caps_init(spapr
);
2760 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2761 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2763 * If the user explicitly requested a mode we should either
2764 * supply it, or fail completely (which we do below). But if
2765 * it's not set explicitly, we reset our mode to something
2768 if (resize_hpt_err
) {
2769 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2770 error_free(resize_hpt_err
);
2771 resize_hpt_err
= NULL
;
2773 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2777 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2779 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2781 * User requested HPT resize, but this host can't supply it. Bail out
2783 error_report_err(resize_hpt_err
);
2786 error_free(resize_hpt_err
);
2788 spapr
->rma_size
= spapr_rma_size(spapr
, &error_fatal
);
2790 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2791 load_limit
= MIN(spapr
->rma_size
, FDT_MAX_ADDR
) - FW_OVERHEAD
;
2794 * VSMT must be set in order to be able to compute VCPU ids, ie to
2795 * call spapr_max_server_number() or spapr_vcpu_id().
2797 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2799 /* Set up Interrupt Controller before we create the VCPUs */
2800 spapr_irq_init(spapr
, &error_fatal
);
2802 /* Set up containers for ibm,client-architecture-support negotiated options
2804 spapr
->ov5
= spapr_ovec_new();
2805 spapr
->ov5_cas
= spapr_ovec_new();
2807 if (smc
->dr_lmb_enabled
) {
2808 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2809 spapr_validate_node_memory(machine
, &error_fatal
);
2812 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2814 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */
2815 if (!smc
->pre_6_2_numa_affinity
) {
2816 spapr_ovec_set(spapr
->ov5
, OV5_FORM2_AFFINITY
);
2819 /* advertise support for dedicated HP event source to guests */
2820 if (spapr
->use_hotplug_event_source
) {
2821 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2824 /* advertise support for HPT resizing */
2825 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2826 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2829 /* advertise support for ibm,dyamic-memory-v2 */
2830 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2832 /* advertise XIVE on POWER9 machines */
2833 if (spapr
->irq
->xive
) {
2834 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2838 spapr_init_cpus(spapr
);
2840 spapr
->gpu_numa_id
= spapr_numa_initial_nvgpu_numa_id(machine
);
2842 /* Init numa_assoc_array */
2843 spapr_numa_associativity_init(spapr
, machine
);
2845 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2846 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2847 spapr
->max_compat_pvr
)) {
2848 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_300
);
2849 /* KVM and TCG always allow GTSE with radix... */
2850 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2852 /* ... but not with hash (currently). */
2854 if (kvm_enabled()) {
2855 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2856 kvmppc_enable_logical_ci_hcalls();
2857 kvmppc_enable_set_mode_hcall();
2859 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2860 kvmppc_enable_clear_ref_mod_hcalls();
2862 /* Enable H_PAGE_INIT */
2863 kvmppc_enable_h_page_init();
2867 memory_region_add_subregion(sysmem
, 0, machine
->ram
);
2869 /* always allocate the device memory information */
2870 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2872 /* initialize hotplug memory address space */
2873 if (machine
->ram_size
< machine
->maxram_size
) {
2874 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2876 * Limit the number of hotpluggable memory slots to half the number
2877 * slots that KVM supports, leaving the other half for PCI and other
2878 * devices. However ensure that number of slots doesn't drop below 32.
2880 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2881 SPAPR_MAX_RAM_SLOTS
;
2883 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2884 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2886 if (machine
->ram_slots
> max_memslots
) {
2887 error_report("Specified number of memory slots %"
2888 PRIu64
" exceeds max supported %d",
2889 machine
->ram_slots
, max_memslots
);
2893 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2894 SPAPR_DEVICE_MEM_ALIGN
);
2895 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2896 "device-memory", device_mem_size
);
2897 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2898 &machine
->device_memory
->mr
);
2901 if (smc
->dr_lmb_enabled
) {
2902 spapr_create_lmb_dr_connectors(spapr
);
2905 if (spapr_get_cap(spapr
, SPAPR_CAP_FWNMI
) == SPAPR_CAP_ON
) {
2906 /* Create the error string for live migration blocker */
2907 error_setg(&spapr
->fwnmi_migration_blocker
,
2908 "A machine check is being handled during migration. The handler"
2909 "may run and log hardware error on the destination");
2912 if (mc
->nvdimm_supported
) {
2913 spapr_create_nvdimm_dr_connectors(spapr
);
2916 /* Set up RTAS event infrastructure */
2917 spapr_events_init(spapr
);
2919 /* Set up the RTC RTAS interfaces */
2920 spapr_rtc_create(spapr
);
2922 /* Set up VIO bus */
2923 spapr
->vio_bus
= spapr_vio_bus_init();
2925 for (i
= 0; serial_hd(i
); i
++) {
2926 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2929 /* We always have at least the nvram device on VIO */
2930 spapr_create_nvram(spapr
);
2933 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2934 * connectors (described in root DT node's "ibm,drc-types" property)
2935 * are pre-initialized here. additional child connectors (such as
2936 * connectors for a PHBs PCI slots) are added as needed during their
2937 * parent's realization.
2939 if (smc
->dr_phb_enabled
) {
2940 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2941 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2946 spapr_pci_rtas_init();
2948 phb
= spapr_create_default_phb();
2950 for (i
= 0; i
< nb_nics
; i
++) {
2951 NICInfo
*nd
= &nd_table
[i
];
2954 nd
->model
= g_strdup("spapr-vlan");
2957 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2958 g_str_equal(nd
->model
, "ibmveth")) {
2959 spapr_vlan_create(spapr
->vio_bus
, nd
);
2961 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2965 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2966 spapr_vscsi_create(spapr
->vio_bus
);
2970 has_vga
= spapr_vga_init(phb
->bus
, &error_fatal
);
2972 spapr
->want_stdout_path
= !machine
->enable_graphics
;
2973 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2975 spapr
->want_stdout_path
= true;
2979 if (smc
->use_ohci_by_default
) {
2980 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2982 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2986 USBBus
*usb_bus
= usb_bus_find(-1);
2988 usb_create_simple(usb_bus
, "usb-kbd");
2989 usb_create_simple(usb_bus
, "usb-mouse");
2993 if (kernel_filename
) {
2994 uint64_t loaded_addr
= 0;
2996 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2997 translate_kernel_address
, spapr
,
2998 NULL
, &loaded_addr
, NULL
, NULL
, 1,
2999 PPC_ELF_MACHINE
, 0, 0);
3000 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
3001 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3002 translate_kernel_address
, spapr
,
3003 NULL
, &loaded_addr
, NULL
, NULL
, 0,
3004 PPC_ELF_MACHINE
, 0, 0);
3005 spapr
->kernel_le
= spapr
->kernel_size
> 0;
3007 if (spapr
->kernel_size
< 0) {
3008 error_report("error loading %s: %s", kernel_filename
,
3009 load_elf_strerror(spapr
->kernel_size
));
3013 if (spapr
->kernel_addr
!= loaded_addr
) {
3014 warn_report("spapr: kernel_addr changed from 0x%"PRIx64
3016 spapr
->kernel_addr
, loaded_addr
);
3017 spapr
->kernel_addr
= loaded_addr
;
3021 if (initrd_filename
) {
3022 /* Try to locate the initrd in the gap between the kernel
3023 * and the firmware. Add a bit of space just in case
3025 spapr
->initrd_base
= (spapr
->kernel_addr
+ spapr
->kernel_size
3026 + 0x1ffff) & ~0xffff;
3027 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
3030 - spapr
->initrd_base
);
3031 if (spapr
->initrd_size
< 0) {
3032 error_report("could not load initial ram disk '%s'",
3039 /* FIXME: Should register things through the MachineState's qdev
3040 * interface, this is a legacy from the sPAPREnvironment structure
3041 * which predated MachineState but had a similar function */
3042 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3043 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY
, 1,
3044 &savevm_htab_handlers
, spapr
);
3046 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
));
3048 qemu_register_boot_set(spapr_boot_set
, spapr
);
3051 * Nothing needs to be done to resume a suspended guest because
3052 * suspending does not change the machine state, so no need for
3053 * a ->wakeup method.
3055 qemu_register_wakeup_support();
3057 if (kvm_enabled()) {
3058 /* to stop and start vmclock */
3059 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3062 kvmppc_spapr_enable_inkernel_multitce();
3065 qemu_cond_init(&spapr
->fwnmi_machine_check_interlock_cond
);
3067 spapr
->vof
->fw_size
= fw_size
; /* for claim() on itself */
3068 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT
, spapr_h_vof_client
);
3071 spapr_watchdog_init(spapr
);
3074 #define DEFAULT_KVM_TYPE "auto"
3075 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3078 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to
3079 * accomodate the 'HV' and 'PV' formats that exists in the
3080 * wild. The 'auto' mode is being introduced already as
3081 * lower-case, thus we don't need to bother checking for
3084 if (!vm_type
|| !strcmp(vm_type
, DEFAULT_KVM_TYPE
)) {
3088 if (!g_ascii_strcasecmp(vm_type
, "hv")) {
3092 if (!g_ascii_strcasecmp(vm_type
, "pr")) {
3096 error_report("Unknown kvm-type specified '%s'", vm_type
);
3101 * Implementation of an interface to adjust firmware path
3102 * for the bootindex property handling.
3104 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3107 #define CAST(type, obj, name) \
3108 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3109 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3110 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3111 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3112 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3115 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3116 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3117 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3121 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3122 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3123 * 0x8000 | (target << 8) | (bus << 5) | lun
3124 * (see the "Logical unit addressing format" table in SAM5)
3126 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3127 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3128 (uint64_t)id
<< 48);
3129 } else if (virtio
) {
3131 * We use SRP luns of the form 01000000 | (target << 8) | lun
3132 * in the top 32 bits of the 64-bit LUN
3133 * Note: the quote above is from SLOF and it is wrong,
3134 * the actual binding is:
3135 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3137 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3138 if (d
->lun
>= 256) {
3139 /* Use the LUN "flat space addressing method" */
3142 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3143 (uint64_t)id
<< 32);
3146 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3147 * in the top 32 bits of the 64-bit LUN
3149 unsigned usb_port
= atoi(usb
->port
->path
);
3150 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3151 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3152 (uint64_t)id
<< 32);
3157 * SLOF probes the USB devices, and if it recognizes that the device is a
3158 * storage device, it changes its name to "storage" instead of "usb-host",
3159 * and additionally adds a child node for the SCSI LUN, so the correct
3160 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3162 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3163 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3164 if (usb_device_is_scsi_storage(usbdev
)) {
3165 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3170 /* Replace "pci" with "pci@800000020000000" */
3171 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3175 /* Same logic as virtio above */
3176 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3177 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3180 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3181 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3182 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3183 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3187 return spapr_pci_fw_dev_name(pcidev
);
3193 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3195 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3197 return g_strdup(spapr
->kvm_type
);
3200 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3202 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3204 g_free(spapr
->kvm_type
);
3205 spapr
->kvm_type
= g_strdup(value
);
3208 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3210 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3212 return spapr
->use_hotplug_event_source
;
3215 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3218 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3220 spapr
->use_hotplug_event_source
= value
;
3223 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3228 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3230 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3232 switch (spapr
->resize_hpt
) {
3233 case SPAPR_RESIZE_HPT_DEFAULT
:
3234 return g_strdup("default");
3235 case SPAPR_RESIZE_HPT_DISABLED
:
3236 return g_strdup("disabled");
3237 case SPAPR_RESIZE_HPT_ENABLED
:
3238 return g_strdup("enabled");
3239 case SPAPR_RESIZE_HPT_REQUIRED
:
3240 return g_strdup("required");
3242 g_assert_not_reached();
3245 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3247 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3249 if (strcmp(value
, "default") == 0) {
3250 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3251 } else if (strcmp(value
, "disabled") == 0) {
3252 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3253 } else if (strcmp(value
, "enabled") == 0) {
3254 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3255 } else if (strcmp(value
, "required") == 0) {
3256 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3258 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3262 static bool spapr_get_vof(Object
*obj
, Error
**errp
)
3264 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3266 return spapr
->vof
!= NULL
;
3269 static void spapr_set_vof(Object
*obj
, bool value
, Error
**errp
)
3271 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3274 vof_cleanup(spapr
->vof
);
3281 spapr
->vof
= g_malloc0(sizeof(*spapr
->vof
));
3284 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3286 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3288 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3289 return g_strdup("legacy");
3290 } else if (spapr
->irq
== &spapr_irq_xics
) {
3291 return g_strdup("xics");
3292 } else if (spapr
->irq
== &spapr_irq_xive
) {
3293 return g_strdup("xive");
3294 } else if (spapr
->irq
== &spapr_irq_dual
) {
3295 return g_strdup("dual");
3297 g_assert_not_reached();
3300 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3302 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3304 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3305 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3309 /* The legacy IRQ backend can not be set */
3310 if (strcmp(value
, "xics") == 0) {
3311 spapr
->irq
= &spapr_irq_xics
;
3312 } else if (strcmp(value
, "xive") == 0) {
3313 spapr
->irq
= &spapr_irq_xive
;
3314 } else if (strcmp(value
, "dual") == 0) {
3315 spapr
->irq
= &spapr_irq_dual
;
3317 error_setg(errp
, "Bad value for \"ic-mode\" property");
3321 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3323 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3325 return g_strdup(spapr
->host_model
);
3328 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3330 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3332 g_free(spapr
->host_model
);
3333 spapr
->host_model
= g_strdup(value
);
3336 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3338 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3340 return g_strdup(spapr
->host_serial
);
3343 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3345 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3347 g_free(spapr
->host_serial
);
3348 spapr
->host_serial
= g_strdup(value
);
3351 static void spapr_instance_init(Object
*obj
)
3353 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3354 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3355 MachineState
*ms
= MACHINE(spapr
);
3356 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
3359 * NVDIMM support went live in 5.1 without considering that, in
3360 * other archs, the user needs to enable NVDIMM support with the
3361 * 'nvdimm' machine option and the default behavior is NVDIMM
3362 * support disabled. It is too late to roll back to the standard
3363 * behavior without breaking 5.1 guests.
3365 if (mc
->nvdimm_supported
) {
3366 ms
->nvdimms_state
->is_enabled
= true;
3369 spapr
->htab_fd
= -1;
3370 spapr
->use_hotplug_event_source
= true;
3371 spapr
->kvm_type
= g_strdup(DEFAULT_KVM_TYPE
);
3372 object_property_add_str(obj
, "kvm-type",
3373 spapr_get_kvm_type
, spapr_set_kvm_type
);
3374 object_property_set_description(obj
, "kvm-type",
3375 "Specifies the KVM virtualization mode (auto,"
3376 " hv, pr). Defaults to 'auto'. This mode will use"
3377 " any available KVM module loaded in the host,"
3378 " where kvm_hv takes precedence if both kvm_hv and"
3379 " kvm_pr are loaded.");
3380 object_property_add_bool(obj
, "modern-hotplug-events",
3381 spapr_get_modern_hotplug_events
,
3382 spapr_set_modern_hotplug_events
);
3383 object_property_set_description(obj
, "modern-hotplug-events",
3384 "Use dedicated hotplug event mechanism in"
3385 " place of standard EPOW events when possible"
3386 " (required for memory hot-unplug support)");
3387 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3388 "Maximum permitted CPU compatibility mode");
3390 object_property_add_str(obj
, "resize-hpt",
3391 spapr_get_resize_hpt
, spapr_set_resize_hpt
);
3392 object_property_set_description(obj
, "resize-hpt",
3393 "Resizing of the Hash Page Table (enabled, disabled, required)");
3394 object_property_add_uint32_ptr(obj
, "vsmt",
3395 &spapr
->vsmt
, OBJ_PROP_FLAG_READWRITE
);
3396 object_property_set_description(obj
, "vsmt",
3397 "Virtual SMT: KVM behaves as if this were"
3398 " the host's SMT mode");
3400 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3401 spapr_get_msix_emulation
, NULL
);
3403 object_property_add_uint64_ptr(obj
, "kernel-addr",
3404 &spapr
->kernel_addr
, OBJ_PROP_FLAG_READWRITE
);
3405 object_property_set_description(obj
, "kernel-addr",
3406 stringify(KERNEL_LOAD_ADDR
)
3407 " for -kernel is the default");
3408 spapr
->kernel_addr
= KERNEL_LOAD_ADDR
;
3410 object_property_add_bool(obj
, "x-vof", spapr_get_vof
, spapr_set_vof
);
3411 object_property_set_description(obj
, "x-vof",
3412 "Enable Virtual Open Firmware (experimental)");
3414 /* The machine class defines the default interrupt controller mode */
3415 spapr
->irq
= smc
->irq
;
3416 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3418 object_property_set_description(obj
, "ic-mode",
3419 "Specifies the interrupt controller mode (xics, xive, dual)");
3421 object_property_add_str(obj
, "host-model",
3422 spapr_get_host_model
, spapr_set_host_model
);
3423 object_property_set_description(obj
, "host-model",
3424 "Host model to advertise in guest device tree");
3425 object_property_add_str(obj
, "host-serial",
3426 spapr_get_host_serial
, spapr_set_host_serial
);
3427 object_property_set_description(obj
, "host-serial",
3428 "Host serial number to advertise in guest device tree");
3431 static void spapr_machine_finalizefn(Object
*obj
)
3433 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3435 g_free(spapr
->kvm_type
);
3438 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3440 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3441 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3442 CPUPPCState
*env
= &cpu
->env
;
3444 cpu_synchronize_state(cs
);
3445 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
3446 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3447 uint64_t rtas_addr
, addr
;
3449 /* get rtas addr from fdt */
3450 rtas_addr
= spapr_get_rtas_addr();
3452 qemu_system_guest_panicked(NULL
);
3456 addr
= rtas_addr
+ RTAS_ERROR_LOG_MAX
+ cs
->cpu_index
* sizeof(uint64_t)*2;
3457 stq_be_phys(&address_space_memory
, addr
, env
->gpr
[3]);
3458 stq_be_phys(&address_space_memory
, addr
+ sizeof(uint64_t), 0);
3461 ppc_cpu_do_system_reset(cs
);
3462 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3463 env
->nip
= spapr
->fwnmi_system_reset_addr
;
3467 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3472 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3476 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3477 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3482 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3483 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3485 *fdt_start_offset
= spapr_dt_memory_node(spapr
, fdt
, node
, addr
,
3486 SPAPR_MEMORY_BLOCK_SIZE
);
3490 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3491 bool dedicated_hp_event_source
)
3494 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3496 uint64_t addr
= addr_start
;
3497 bool hotplugged
= spapr_drc_hotplugged(dev
);
3499 for (i
= 0; i
< nr_lmbs
; i
++) {
3500 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3501 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3505 * memory_device_get_free_addr() provided a range of free addresses
3506 * that doesn't overlap with any existing mapping at pre-plug. The
3507 * corresponding LMB DRCs are thus assumed to be all attachable.
3509 spapr_drc_attach(drc
, dev
);
3511 spapr_drc_reset(drc
);
3513 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3515 /* send hotplug notification to the
3516 * guest only in case of hotplugged memory
3519 if (dedicated_hp_event_source
) {
3520 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3521 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3523 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3525 spapr_drc_index(drc
));
3527 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3533 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3535 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3536 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3537 uint64_t size
, addr
;
3539 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3541 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3543 pc_dimm_plug(dimm
, MACHINE(ms
));
3546 addr
= object_property_get_uint(OBJECT(dimm
),
3547 PC_DIMM_ADDR_PROP
, &error_abort
);
3548 spapr_add_lmbs(dev
, addr
, size
,
3549 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
));
3551 slot
= object_property_get_int(OBJECT(dimm
),
3552 PC_DIMM_SLOT_PROP
, &error_abort
);
3553 /* We should have valid slot number at this point */
3554 g_assert(slot
>= 0);
3555 spapr_add_nvdimm(dev
, slot
);
3559 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3562 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3563 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3564 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3565 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3566 Error
*local_err
= NULL
;
3571 if (!smc
->dr_lmb_enabled
) {
3572 error_setg(errp
, "Memory hotplug not supported for this machine");
3576 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3578 error_propagate(errp
, local_err
);
3583 if (!spapr_nvdimm_validate(hotplug_dev
, NVDIMM(dev
), size
, errp
)) {
3586 } else if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3587 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3588 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3592 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3594 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3595 if (!spapr_check_pagesize(spapr
, pagesize
, errp
)) {
3599 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3602 struct SpaprDimmState
{
3605 QTAILQ_ENTRY(SpaprDimmState
) next
;
3608 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3611 SpaprDimmState
*dimm_state
= NULL
;
3613 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3614 if (dimm_state
->dimm
== dimm
) {
3621 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3625 SpaprDimmState
*ds
= NULL
;
3628 * If this request is for a DIMM whose removal had failed earlier
3629 * (due to guest's refusal to remove the LMBs), we would have this
3630 * dimm already in the pending_dimm_unplugs list. In that
3631 * case don't add again.
3633 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3635 ds
= g_new0(SpaprDimmState
, 1);
3636 ds
->nr_lmbs
= nr_lmbs
;
3638 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3643 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3644 SpaprDimmState
*dimm_state
)
3646 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3650 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3654 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3656 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3657 uint32_t avail_lmbs
= 0;
3658 uint64_t addr_start
, addr
;
3661 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3665 for (i
= 0; i
< nr_lmbs
; i
++) {
3666 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3667 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3672 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3675 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3678 void spapr_memory_unplug_rollback(SpaprMachineState
*spapr
, DeviceState
*dev
)
3684 uint64_t size
, addr_start
, addr
;
3685 g_autofree
char *qapi_error
= NULL
;
3692 dimm
= PC_DIMM(dev
);
3693 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3696 * 'ds == NULL' would mean that the DIMM doesn't have a pending
3697 * unplug state, but one of its DRC is marked as unplug_requested.
3698 * This is bad and weird enough to g_assert() out.
3702 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3704 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3705 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3707 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3711 for (i
= 0; i
< nr_lmbs
; i
++) {
3712 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3713 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3716 drc
->unplug_requested
= false;
3717 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3721 * Tell QAPI that something happened and the memory
3722 * hotunplug wasn't successful. Keep sending
3723 * MEM_UNPLUG_ERROR even while sending
3724 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of
3725 * MEM_UNPLUG_ERROR is due.
3727 qapi_error
= g_strdup_printf("Memory hotunplug rejected by the guest "
3728 "for device %s", dev
->id
);
3730 qapi_event_send_mem_unplug_error(dev
->id
? : "", qapi_error
);
3732 qapi_event_send_device_unplug_guest_error(dev
->id
,
3733 dev
->canonical_path
);
3736 /* Callback to be called during DRC release. */
3737 void spapr_lmb_release(DeviceState
*dev
)
3739 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3740 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3741 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3743 /* This information will get lost if a migration occurs
3744 * during the unplug process. In this case recover it. */
3746 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3748 /* The DRC being examined by the caller at least must be counted */
3749 g_assert(ds
->nr_lmbs
);
3752 if (--ds
->nr_lmbs
) {
3757 * Now that all the LMBs have been removed by the guest, call the
3758 * unplug handler chain. This can never fail.
3760 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3761 object_unparent(OBJECT(dev
));
3764 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3766 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3767 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3769 /* We really shouldn't get this far without anything to unplug */
3772 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3773 qdev_unrealize(dev
);
3774 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3777 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3778 DeviceState
*dev
, Error
**errp
)
3780 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3781 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3783 uint64_t size
, addr_start
, addr
;
3787 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
3788 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
3792 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3793 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3795 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3799 * An existing pending dimm state for this DIMM means that there is an
3800 * unplug operation in progress, waiting for the spapr_lmb_release
3801 * callback to complete the job (BQL can't cover that far). In this case,
3802 * bail out to avoid detaching DRCs that were already released.
3804 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3805 error_setg(errp
, "Memory unplug already in progress for device %s",
3810 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3813 for (i
= 0; i
< nr_lmbs
; i
++) {
3814 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3815 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3818 spapr_drc_unplug_request(drc
);
3819 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3822 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3823 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3824 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3825 nr_lmbs
, spapr_drc_index(drc
));
3828 /* Callback to be called during DRC release. */
3829 void spapr_core_release(DeviceState
*dev
)
3831 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3833 /* Call the unplug handler chain. This can never fail. */
3834 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3835 object_unparent(OBJECT(dev
));
3838 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3840 MachineState
*ms
= MACHINE(hotplug_dev
);
3841 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3842 CPUCore
*cc
= CPU_CORE(dev
);
3843 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3845 if (smc
->pre_2_10_has_unused_icps
) {
3846 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3849 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3850 CPUState
*cs
= CPU(sc
->threads
[i
]);
3852 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3857 core_slot
->cpu
= NULL
;
3858 qdev_unrealize(dev
);
3862 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3865 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3868 CPUCore
*cc
= CPU_CORE(dev
);
3870 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3871 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3876 error_setg(errp
, "Boot CPU core may not be unplugged");
3880 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3881 spapr_vcpu_id(spapr
, cc
->core_id
));
3884 if (!spapr_drc_unplug_requested(drc
)) {
3885 spapr_drc_unplug_request(drc
);
3889 * spapr_hotplug_req_remove_by_index is left unguarded, out of the
3890 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ
3891 * pulses removing the same CPU. Otherwise, in an failed hotunplug
3892 * attempt (e.g. the kernel will refuse to remove the last online
3893 * CPU), we will never attempt it again because unplug_requested
3894 * will still be 'true' in that case.
3896 spapr_hotplug_req_remove_by_index(drc
);
3899 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3900 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3902 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3903 CPUState
*cs
= CPU(core
->threads
[0]);
3904 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3905 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3906 int id
= spapr_get_vcpu_id(cpu
);
3907 g_autofree
char *nodename
= NULL
;
3910 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3911 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3913 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
3916 * spapr_dt_cpu() does not fill the 'name' property in the
3917 * CPU node. The function is called during boot process, before
3918 * and after CAS, and overwriting the 'name' property written
3919 * by SLOF is not allowed.
3921 * Write it manually after spapr_dt_cpu(). This makes the hotplug
3922 * CPUs more compatible with the coldplugged ones, which have
3923 * the 'name' property. Linux Kernel also relies on this
3924 * property to identify CPU nodes.
3926 _FDT((fdt_setprop_string(fdt
, offset
, "name", nodename
)));
3928 *fdt_start_offset
= offset
;
3932 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3934 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3935 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3936 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3937 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3938 CPUCore
*cc
= CPU_CORE(dev
);
3941 CPUArchId
*core_slot
;
3943 bool hotplugged
= spapr_drc_hotplugged(dev
);
3946 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3947 g_assert(core_slot
); /* Already checked in spapr_core_pre_plug() */
3949 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3950 spapr_vcpu_id(spapr
, cc
->core_id
));
3952 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3956 * spapr_core_pre_plug() already buys us this is a brand new
3957 * core being plugged into a free slot. Nothing should already
3958 * be attached to the corresponding DRC.
3960 spapr_drc_attach(drc
, dev
);
3964 * Send hotplug notification interrupt to the guest only
3965 * in case of hotplugged CPUs.
3967 spapr_hotplug_req_add_by_index(drc
);
3969 spapr_drc_reset(drc
);
3973 core_slot
->cpu
= OBJECT(dev
);
3976 * Set compatibility mode to match the boot CPU, which was either set
3977 * by the machine reset code or by CAS. This really shouldn't fail at
3981 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3982 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3987 if (smc
->pre_2_10_has_unused_icps
) {
3988 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3989 cs
= CPU(core
->threads
[i
]);
3990 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3995 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3998 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3999 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
4000 CPUCore
*cc
= CPU_CORE(dev
);
4001 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4002 const char *type
= object_get_typename(OBJECT(dev
));
4003 CPUArchId
*core_slot
;
4005 unsigned int smp_threads
= machine
->smp
.threads
;
4007 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
4008 error_setg(errp
, "CPU hotplug not supported for this machine");
4012 if (strcmp(base_core_type
, type
)) {
4013 error_setg(errp
, "CPU core type should be %s", base_core_type
);
4017 if (cc
->core_id
% smp_threads
) {
4018 error_setg(errp
, "invalid core id %d", cc
->core_id
);
4023 * In general we should have homogeneous threads-per-core, but old
4024 * (pre hotplug support) machine types allow the last core to have
4025 * reduced threads as a compatibility hack for when we allowed
4026 * total vcpus not a multiple of threads-per-core.
4028 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
4029 error_setg(errp
, "invalid nr-threads %d, must be %d", cc
->nr_threads
,
4034 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
4036 error_setg(errp
, "core id %d out of range", cc
->core_id
);
4040 if (core_slot
->cpu
) {
4041 error_setg(errp
, "core %d already populated", cc
->core_id
);
4045 numa_cpu_pre_plug(core_slot
, dev
, errp
);
4048 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
4049 void *fdt
, int *fdt_start_offset
, Error
**errp
)
4051 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
4054 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
4055 if (intc_phandle
<= 0) {
4059 if (spapr_dt_phb(spapr
, sphb
, intc_phandle
, fdt
, fdt_start_offset
)) {
4060 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
4064 /* generally SLOF creates these, for hotplug it's up to QEMU */
4065 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
4070 static bool spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4073 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4074 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4075 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4076 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
4079 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
4080 error_setg(errp
, "PHB hotplug not supported for this machine");
4084 if (sphb
->index
== (uint32_t)-1) {
4085 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
4089 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4090 if (drc
&& drc
->dev
) {
4091 error_setg(errp
, "PHB %d already attached", sphb
->index
);
4096 * This will check that sphb->index doesn't exceed the maximum number of
4097 * PHBs for the current machine type.
4100 smc
->phb_placement(spapr
, sphb
->index
,
4101 &sphb
->buid
, &sphb
->io_win_addr
,
4102 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
4103 windows_supported
, sphb
->dma_liobn
,
4104 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
4108 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4110 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4111 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4112 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4114 bool hotplugged
= spapr_drc_hotplugged(dev
);
4116 if (!smc
->dr_phb_enabled
) {
4120 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4121 /* hotplug hooks should check it's enabled before getting this far */
4124 /* spapr_phb_pre_plug() already checked the DRC is attachable */
4125 spapr_drc_attach(drc
, dev
);
4128 spapr_hotplug_req_add_by_index(drc
);
4130 spapr_drc_reset(drc
);
4134 void spapr_phb_release(DeviceState
*dev
)
4136 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
4138 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
4139 object_unparent(OBJECT(dev
));
4142 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4144 qdev_unrealize(dev
);
4147 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4148 DeviceState
*dev
, Error
**errp
)
4150 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4153 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4156 if (!spapr_drc_unplug_requested(drc
)) {
4157 spapr_drc_unplug_request(drc
);
4158 spapr_hotplug_req_remove_by_index(drc
);
4161 "PCI Host Bridge unplug already in progress for device %s",
4167 bool spapr_tpm_proxy_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4170 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4172 if (spapr
->tpm_proxy
!= NULL
) {
4173 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4180 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4182 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4183 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4185 /* Already checked in spapr_tpm_proxy_pre_plug() */
4186 g_assert(spapr
->tpm_proxy
== NULL
);
4188 spapr
->tpm_proxy
= tpm_proxy
;
4191 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4193 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4195 qdev_unrealize(dev
);
4196 object_unparent(OBJECT(dev
));
4197 spapr
->tpm_proxy
= NULL
;
4200 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4201 DeviceState
*dev
, Error
**errp
)
4203 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4204 spapr_memory_plug(hotplug_dev
, dev
);
4205 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4206 spapr_core_plug(hotplug_dev
, dev
);
4207 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4208 spapr_phb_plug(hotplug_dev
, dev
);
4209 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4210 spapr_tpm_proxy_plug(hotplug_dev
, dev
);
4214 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4215 DeviceState
*dev
, Error
**errp
)
4217 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4218 spapr_memory_unplug(hotplug_dev
, dev
);
4219 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4220 spapr_core_unplug(hotplug_dev
, dev
);
4221 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4222 spapr_phb_unplug(hotplug_dev
, dev
);
4223 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4224 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4228 bool spapr_memory_hot_unplug_supported(SpaprMachineState
*spapr
)
4230 return spapr_ovec_test(spapr
->ov5_cas
, OV5_HP_EVT
) ||
4232 * CAS will process all pending unplug requests.
4234 * HACK: a guest could theoretically have cleared all bits in OV5,
4235 * but none of the guests we care for do.
4237 spapr_ovec_empty(spapr
->ov5_cas
);
4240 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4241 DeviceState
*dev
, Error
**errp
)
4243 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4244 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4245 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4247 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4248 if (spapr_memory_hot_unplug_supported(sms
)) {
4249 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4251 error_setg(errp
, "Memory hot unplug not supported for this guest");
4253 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4254 if (!mc
->has_hotpluggable_cpus
) {
4255 error_setg(errp
, "CPU hot unplug not supported on this machine");
4258 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4259 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4260 if (!smc
->dr_phb_enabled
) {
4261 error_setg(errp
, "PHB hot unplug not supported on this machine");
4264 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4265 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4266 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4270 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4271 DeviceState
*dev
, Error
**errp
)
4273 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4274 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4275 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4276 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4277 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4278 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4279 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4280 spapr_tpm_proxy_pre_plug(hotplug_dev
, dev
, errp
);
4284 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4287 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4288 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4289 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4290 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4291 return HOTPLUG_HANDLER(machine
);
4293 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4294 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4295 PCIBus
*root
= pci_device_root_bus(pcidev
);
4296 SpaprPhbState
*phb
=
4297 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4298 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4301 return HOTPLUG_HANDLER(phb
);
4307 static CpuInstanceProperties
4308 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4310 CPUArchId
*core_slot
;
4311 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4313 /* make sure possible_cpu are intialized */
4314 mc
->possible_cpu_arch_ids(machine
);
4315 /* get CPU core slot containing thread that matches cpu_index */
4316 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4318 return core_slot
->props
;
4321 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4323 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4326 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4329 unsigned int smp_threads
= machine
->smp
.threads
;
4330 unsigned int smp_cpus
= machine
->smp
.cpus
;
4331 const char *core_type
;
4332 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4333 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4335 if (!mc
->has_hotpluggable_cpus
) {
4336 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4338 if (machine
->possible_cpus
) {
4339 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4340 return machine
->possible_cpus
;
4343 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4345 error_report("Unable to find sPAPR CPU Core definition");
4349 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4350 sizeof(CPUArchId
) * spapr_max_cores
);
4351 machine
->possible_cpus
->len
= spapr_max_cores
;
4352 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4353 int core_id
= i
* smp_threads
;
4355 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4356 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4357 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4358 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4359 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4361 return machine
->possible_cpus
;
4364 static bool spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4365 uint64_t *buid
, hwaddr
*pio
,
4366 hwaddr
*mmio32
, hwaddr
*mmio64
,
4367 unsigned n_dma
, uint32_t *liobns
,
4368 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4371 * New-style PHB window placement.
4373 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4374 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4377 * Some guest kernels can't work with MMIO windows above 1<<46
4378 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4380 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4381 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4382 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4383 * 1TiB 64-bit MMIO windows for each PHB.
4385 const uint64_t base_buid
= 0x800000020000000ULL
;
4388 /* Sanity check natural alignments */
4389 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4390 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4391 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4392 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4393 /* Sanity check bounds */
4394 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4395 SPAPR_PCI_MEM32_WIN_SIZE
);
4396 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4397 SPAPR_PCI_MEM64_WIN_SIZE
);
4399 if (index
>= SPAPR_MAX_PHBS
) {
4400 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4401 SPAPR_MAX_PHBS
- 1);
4405 *buid
= base_buid
+ index
;
4406 for (i
= 0; i
< n_dma
; ++i
) {
4407 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4410 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4411 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4412 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4414 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4415 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4419 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4421 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4423 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4426 static void spapr_ics_resend(XICSFabric
*dev
)
4428 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4430 ics_resend(spapr
->ics
);
4433 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4435 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4437 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4440 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4443 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4445 spapr_irq_print_info(spapr
, mon
);
4446 monitor_printf(mon
, "irqchip: %s\n",
4447 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4451 * This is a XIVE only operation
4453 static int spapr_match_nvt(XiveFabric
*xfb
, uint8_t format
,
4454 uint8_t nvt_blk
, uint32_t nvt_idx
,
4455 bool cam_ignore
, uint8_t priority
,
4456 uint32_t logic_serv
, XiveTCTXMatch
*match
)
4458 SpaprMachineState
*spapr
= SPAPR_MACHINE(xfb
);
4459 XivePresenter
*xptr
= XIVE_PRESENTER(spapr
->active_intc
);
4460 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
4463 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
4464 priority
, logic_serv
, match
);
4470 * When we implement the save and restore of the thread interrupt
4471 * contexts in the enter/exit CPU handlers of the machine and the
4472 * escalations in QEMU, we should be able to handle non dispatched
4475 * Until this is done, the sPAPR machine should find at least one
4476 * matching context always.
4479 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is not dispatched\n",
4486 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4488 return cpu
->vcpu_id
;
4491 bool spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4493 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4494 MachineState
*ms
= MACHINE(spapr
);
4497 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4499 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4500 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4501 error_append_hint(errp
, "Adjust the number of cpus to %d "
4502 "or try to raise the number of threads per core\n",
4503 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4507 cpu
->vcpu_id
= vcpu_id
;
4511 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4516 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4518 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4526 static bool spapr_cpu_in_nested(PowerPCCPU
*cpu
)
4528 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4530 return spapr_cpu
->in_nested
;
4533 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4535 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4537 /* These are only called by TCG, KVM maintains dispatch state */
4539 spapr_cpu
->prod
= false;
4540 if (spapr_cpu
->vpa_addr
) {
4541 CPUState
*cs
= CPU(cpu
);
4544 dispatch
= ldl_be_phys(cs
->as
,
4545 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4547 if ((dispatch
& 1) != 0) {
4548 qemu_log_mask(LOG_GUEST_ERROR
,
4549 "VPA: incorrect dispatch counter value for "
4550 "dispatched partition %u, correcting.\n", dispatch
);
4554 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4558 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4560 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4562 if (spapr_cpu
->vpa_addr
) {
4563 CPUState
*cs
= CPU(cpu
);
4566 dispatch
= ldl_be_phys(cs
->as
,
4567 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4569 if ((dispatch
& 1) != 1) {
4570 qemu_log_mask(LOG_GUEST_ERROR
,
4571 "VPA: incorrect dispatch counter value for "
4572 "preempted partition %u, correcting.\n", dispatch
);
4576 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4580 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4582 MachineClass
*mc
= MACHINE_CLASS(oc
);
4583 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4584 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4585 NMIClass
*nc
= NMI_CLASS(oc
);
4586 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4587 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4588 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4589 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4590 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
4591 VofMachineIfClass
*vmc
= VOF_MACHINE_CLASS(oc
);
4593 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4594 mc
->ignore_boot_device_suffixes
= true;
4597 * We set up the default / latest behaviour here. The class_init
4598 * functions for the specific versioned machine types can override
4599 * these details for backwards compatibility
4601 mc
->init
= spapr_machine_init
;
4602 mc
->reset
= spapr_machine_reset
;
4603 mc
->block_default_type
= IF_SCSI
;
4606 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values
4607 * should be limited by the host capability instead of hardcoded.
4608 * max_cpus for KVM guests will be checked in kvm_init(), and TCG
4609 * guests are welcome to have as many CPUs as the host are capable
4612 mc
->max_cpus
= INT32_MAX
;
4614 mc
->no_parallel
= 1;
4615 mc
->default_boot_order
= "";
4616 mc
->default_ram_size
= 512 * MiB
;
4617 mc
->default_ram_id
= "ppc_spapr.ram";
4618 mc
->default_display
= "std";
4619 mc
->kvm_type
= spapr_kvm_type
;
4620 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4621 mc
->pci_allow_0_address
= true;
4622 assert(!mc
->get_hotplug_handler
);
4623 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4624 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4625 hc
->plug
= spapr_machine_device_plug
;
4626 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4627 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4628 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4629 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4630 hc
->unplug
= spapr_machine_device_unplug
;
4632 smc
->dr_lmb_enabled
= true;
4633 smc
->update_dt_enabled
= true;
4634 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4635 mc
->has_hotpluggable_cpus
= true;
4636 mc
->nvdimm_supported
= true;
4637 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4638 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4639 nc
->nmi_monitor_handler
= spapr_nmi
;
4640 smc
->phb_placement
= spapr_phb_placement
;
4641 vhc
->cpu_in_nested
= spapr_cpu_in_nested
;
4642 vhc
->deliver_hv_excp
= spapr_exit_nested
;
4643 vhc
->hypercall
= emulate_spapr_hypercall
;
4644 vhc
->hpt_mask
= spapr_hpt_mask
;
4645 vhc
->map_hptes
= spapr_map_hptes
;
4646 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4647 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4648 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4649 vhc
->get_pate
= spapr_get_pate
;
4650 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4651 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4652 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4653 xic
->ics_get
= spapr_ics_get
;
4654 xic
->ics_resend
= spapr_ics_resend
;
4655 xic
->icp_get
= spapr_icp_get
;
4656 ispc
->print_info
= spapr_pic_print_info
;
4657 /* Force NUMA node memory size to be a multiple of
4658 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4659 * in which LMBs are represented and hot-added
4661 mc
->numa_mem_align_shift
= 28;
4662 mc
->auto_enable_numa
= true;
4664 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4665 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4666 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4667 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4668 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4669 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4670 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4671 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4672 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4673 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_ON
;
4674 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_ON
;
4675 smc
->default_caps
.caps
[SPAPR_CAP_RPT_INVALIDATE
] = SPAPR_CAP_OFF
;
4676 spapr_caps_add_properties(smc
);
4677 smc
->irq
= &spapr_irq_dual
;
4678 smc
->dr_phb_enabled
= true;
4679 smc
->linux_pci_probe
= true;
4680 smc
->smp_threads_vsmt
= true;
4681 smc
->nr_xirqs
= SPAPR_NR_XIRQS
;
4682 xfc
->match_nvt
= spapr_match_nvt
;
4683 vmc
->client_architecture_support
= spapr_vof_client_architecture_support
;
4684 vmc
->quiesce
= spapr_vof_quiesce
;
4685 vmc
->setprop
= spapr_vof_setprop
;
4688 static const TypeInfo spapr_machine_info
= {
4689 .name
= TYPE_SPAPR_MACHINE
,
4690 .parent
= TYPE_MACHINE
,
4692 .instance_size
= sizeof(SpaprMachineState
),
4693 .instance_init
= spapr_instance_init
,
4694 .instance_finalize
= spapr_machine_finalizefn
,
4695 .class_size
= sizeof(SpaprMachineClass
),
4696 .class_init
= spapr_machine_class_init
,
4697 .interfaces
= (InterfaceInfo
[]) {
4698 { TYPE_FW_PATH_PROVIDER
},
4700 { TYPE_HOTPLUG_HANDLER
},
4701 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4702 { TYPE_XICS_FABRIC
},
4703 { TYPE_INTERRUPT_STATS_PROVIDER
},
4704 { TYPE_XIVE_FABRIC
},
4705 { TYPE_VOF_MACHINE_IF
},
4710 static void spapr_machine_latest_class_options(MachineClass
*mc
)
4712 mc
->alias
= "pseries";
4713 mc
->is_default
= true;
4716 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4717 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4720 MachineClass *mc = MACHINE_CLASS(oc); \
4721 spapr_machine_##suffix##_class_options(mc); \
4723 spapr_machine_latest_class_options(mc); \
4726 static const TypeInfo spapr_machine_##suffix##_info = { \
4727 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4728 .parent = TYPE_SPAPR_MACHINE, \
4729 .class_init = spapr_machine_##suffix##_class_init, \
4731 static void spapr_machine_register_##suffix(void) \
4733 type_register(&spapr_machine_##suffix##_info); \
4735 type_init(spapr_machine_register_##suffix)
4740 static void spapr_machine_7_2_class_options(MachineClass
*mc
)
4742 /* Defaults for the latest behaviour inherited from the base class */
4745 DEFINE_SPAPR_MACHINE(7_2
, "7.2", true);
4750 static void spapr_machine_7_1_class_options(MachineClass
*mc
)
4752 spapr_machine_7_2_class_options(mc
);
4753 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
4756 DEFINE_SPAPR_MACHINE(7_1
, "7.1", false);
4761 static void spapr_machine_7_0_class_options(MachineClass
*mc
)
4763 spapr_machine_7_1_class_options(mc
);
4764 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
4767 DEFINE_SPAPR_MACHINE(7_0
, "7.0", false);
4772 static void spapr_machine_6_2_class_options(MachineClass
*mc
)
4774 spapr_machine_7_0_class_options(mc
);
4775 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
4778 DEFINE_SPAPR_MACHINE(6_2
, "6.2", false);
4783 static void spapr_machine_6_1_class_options(MachineClass
*mc
)
4785 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4787 spapr_machine_6_2_class_options(mc
);
4788 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
4789 smc
->pre_6_2_numa_affinity
= true;
4790 mc
->smp_props
.prefer_sockets
= true;
4793 DEFINE_SPAPR_MACHINE(6_1
, "6.1", false);
4798 static void spapr_machine_6_0_class_options(MachineClass
*mc
)
4800 spapr_machine_6_1_class_options(mc
);
4801 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
4804 DEFINE_SPAPR_MACHINE(6_0
, "6.0", false);
4809 static void spapr_machine_5_2_class_options(MachineClass
*mc
)
4811 spapr_machine_6_0_class_options(mc
);
4812 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
4815 DEFINE_SPAPR_MACHINE(5_2
, "5.2", false);
4820 static void spapr_machine_5_1_class_options(MachineClass
*mc
)
4822 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4824 spapr_machine_5_2_class_options(mc
);
4825 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
4826 smc
->pre_5_2_numa_associativity
= true;
4829 DEFINE_SPAPR_MACHINE(5_1
, "5.1", false);
4834 static void spapr_machine_5_0_class_options(MachineClass
*mc
)
4836 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4837 static GlobalProperty compat
[] = {
4838 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-5.1-associativity", "on" },
4841 spapr_machine_5_1_class_options(mc
);
4842 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
4843 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4844 mc
->numa_mem_supported
= true;
4845 smc
->pre_5_1_assoc_refpoints
= true;
4848 DEFINE_SPAPR_MACHINE(5_0
, "5.0", false);
4853 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4855 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4857 spapr_machine_5_0_class_options(mc
);
4858 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
4859 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4860 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_OFF
;
4861 smc
->rma_limit
= 16 * GiB
;
4862 mc
->nvdimm_supported
= false;
4865 DEFINE_SPAPR_MACHINE(4_2
, "4.2", false);
4870 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4872 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4873 static GlobalProperty compat
[] = {
4874 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4875 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4878 spapr_machine_4_2_class_options(mc
);
4879 smc
->linux_pci_probe
= false;
4880 smc
->smp_threads_vsmt
= false;
4881 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4882 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4885 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4890 static bool phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4891 uint64_t *buid
, hwaddr
*pio
,
4892 hwaddr
*mmio32
, hwaddr
*mmio64
,
4893 unsigned n_dma
, uint32_t *liobns
,
4894 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4896 if (!spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
,
4897 liobns
, nv2gpa
, nv2atsd
, errp
)) {
4905 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4907 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4909 spapr_machine_4_1_class_options(mc
);
4910 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4911 smc
->phb_placement
= phb_placement_4_0
;
4912 smc
->irq
= &spapr_irq_xics
;
4913 smc
->pre_4_1_migration
= true;
4916 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4921 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4923 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4925 spapr_machine_4_0_class_options(mc
);
4926 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4928 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4929 smc
->update_dt_enabled
= false;
4930 smc
->dr_phb_enabled
= false;
4931 smc
->broken_host_serial_model
= true;
4932 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4933 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4934 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4935 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4938 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4944 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4946 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4948 spapr_machine_3_1_class_options(mc
);
4949 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4951 smc
->legacy_irq_allocation
= true;
4952 smc
->nr_xirqs
= 0x400;
4953 smc
->irq
= &spapr_irq_xics_legacy
;
4956 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4961 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4963 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4964 static GlobalProperty compat
[] = {
4965 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4966 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4969 spapr_machine_3_0_class_options(mc
);
4970 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4971 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4973 /* We depend on kvm_enabled() to choose a default value for the
4974 * hpt-max-page-size capability. Of course we can't do it here
4975 * because this is too early and the HW accelerator isn't initialzed
4976 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4978 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4981 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4983 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4985 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4987 spapr_machine_2_12_class_options(mc
);
4988 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4989 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4990 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4993 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4999 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
5001 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5003 spapr_machine_2_12_class_options(mc
);
5004 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
5005 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
5008 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
5014 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
5016 spapr_machine_2_11_class_options(mc
);
5017 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
5020 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
5026 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
5028 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5029 static GlobalProperty compat
[] = {
5030 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
5033 spapr_machine_2_10_class_options(mc
);
5034 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
5035 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5036 smc
->pre_2_10_has_unused_icps
= true;
5037 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
5040 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
5046 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
5048 static GlobalProperty compat
[] = {
5049 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
5052 spapr_machine_2_9_class_options(mc
);
5053 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
5054 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5055 mc
->numa_mem_align_shift
= 23;
5058 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
5064 static bool phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
5065 uint64_t *buid
, hwaddr
*pio
,
5066 hwaddr
*mmio32
, hwaddr
*mmio64
,
5067 unsigned n_dma
, uint32_t *liobns
,
5068 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
5070 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
5071 const uint64_t base_buid
= 0x800000020000000ULL
;
5072 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
5073 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
5074 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
5075 const uint32_t max_index
= 255;
5076 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
5078 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
5079 hwaddr phb0_base
, phb_base
;
5082 /* Do we have device memory? */
5083 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
5084 /* Can't just use maxram_size, because there may be an
5085 * alignment gap between normal and device memory regions
5087 ram_top
= MACHINE(spapr
)->device_memory
->base
+
5088 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
5091 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
5093 if (index
> max_index
) {
5094 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
5099 *buid
= base_buid
+ index
;
5100 for (i
= 0; i
< n_dma
; ++i
) {
5101 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
5104 phb_base
= phb0_base
+ index
* phb_spacing
;
5105 *pio
= phb_base
+ pio_offset
;
5106 *mmio32
= phb_base
+ mmio_offset
;
5108 * We don't set the 64-bit MMIO window, relying on the PHB's
5109 * fallback behaviour of automatically splitting a large "32-bit"
5110 * window into contiguous 32-bit and 64-bit windows
5118 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
5120 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5121 static GlobalProperty compat
[] = {
5122 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
5123 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
5124 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
5125 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
5128 spapr_machine_2_8_class_options(mc
);
5129 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
5130 mc
->default_machine_opts
= "modern-hotplug-events=off";
5131 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
5132 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5133 smc
->phb_placement
= phb_placement_2_7
;
5136 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
5142 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
5144 static GlobalProperty compat
[] = {
5145 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
5148 spapr_machine_2_7_class_options(mc
);
5149 mc
->has_hotpluggable_cpus
= false;
5150 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
5151 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5154 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
5160 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
5162 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5163 static GlobalProperty compat
[] = {
5164 { "spapr-vlan", "use-rx-buffer-pools", "off" },
5167 spapr_machine_2_6_class_options(mc
);
5168 smc
->use_ohci_by_default
= true;
5169 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
5170 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5173 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
5179 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
5181 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5183 spapr_machine_2_5_class_options(mc
);
5184 smc
->dr_lmb_enabled
= false;
5185 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
5188 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
5194 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
5196 static GlobalProperty compat
[] = {
5197 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
5199 spapr_machine_2_4_class_options(mc
);
5200 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
5201 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5203 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
5209 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
5211 static GlobalProperty compat
[] = {
5212 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
5215 spapr_machine_2_3_class_options(mc
);
5216 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
5217 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5218 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
5220 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
5226 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
5228 spapr_machine_2_2_class_options(mc
);
5229 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
5231 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
5233 static void spapr_machine_register_types(void)
5235 type_register_static(&spapr_machine_info
);
5238 type_init(spapr_machine_register_types
)