2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu/datadir.h"
29 #include "qemu/memalign.h"
30 #include "qemu/guest-random.h"
31 #include "qapi/error.h"
32 #include "qapi/qapi-events-machine.h"
33 #include "qapi/qapi-events-qdev.h"
34 #include "qapi/visitor.h"
35 #include "sysemu/sysemu.h"
36 #include "sysemu/hostmem.h"
37 #include "sysemu/numa.h"
38 #include "sysemu/qtest.h"
39 #include "sysemu/reset.h"
40 #include "sysemu/runstate.h"
42 #include "hw/fw-path-provider.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/cpus.h"
47 #include "sysemu/hw_accel.h"
49 #include "migration/misc.h"
50 #include "migration/qemu-file-types.h"
51 #include "migration/global_state.h"
52 #include "migration/register.h"
53 #include "migration/blocker.h"
54 #include "mmu-hash64.h"
55 #include "mmu-book3s-v3.h"
56 #include "cpu-models.h"
57 #include "hw/core/cpu.h"
59 #include "hw/ppc/ppc.h"
60 #include "hw/loader.h"
62 #include "hw/ppc/fdt.h"
63 #include "hw/ppc/spapr.h"
64 #include "hw/ppc/spapr_nested.h"
65 #include "hw/ppc/spapr_vio.h"
66 #include "hw/ppc/vof.h"
67 #include "hw/qdev-properties.h"
68 #include "hw/pci-host/spapr.h"
69 #include "hw/pci/msi.h"
71 #include "hw/pci/pci.h"
72 #include "hw/scsi/scsi.h"
73 #include "hw/virtio/virtio-scsi.h"
74 #include "hw/virtio/vhost-scsi-common.h"
76 #include "exec/ram_addr.h"
78 #include "qemu/config-file.h"
79 #include "qemu/error-report.h"
82 #include "hw/intc/intc.h"
84 #include "hw/ppc/spapr_cpu_core.h"
85 #include "hw/mem/memory-device.h"
86 #include "hw/ppc/spapr_tpm_proxy.h"
87 #include "hw/ppc/spapr_nvdimm.h"
88 #include "hw/ppc/spapr_numa.h"
89 #include "hw/ppc/pef.h"
91 #include "monitor/monitor.h"
95 /* SLOF memory layout:
97 * SLOF raw image loaded at 0, copies its romfs right below the flat
98 * device-tree, then position SLOF itself 31M below that
100 * So we set FW_OVERHEAD to 40MB which should account for all of that
103 * We load our kernel at 4M, leaving space for SLOF initial image
105 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */
106 #define FW_MAX_SIZE 0x400000
107 #define FW_FILE_NAME "slof.bin"
108 #define FW_FILE_NAME_VOF "vof.bin"
109 #define FW_OVERHEAD 0x2800000
110 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
112 #define MIN_RMA_SLOF (128 * MiB)
114 #define PHANDLE_INTC 0x00001111
116 /* These two functions implement the VCPU id numbering: one to compute them
117 * all and one to identify thread 0 of a VCORE. Any change to the first one
118 * is likely to have an impact on the second one, so let's keep them close.
120 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
122 MachineState
*ms
= MACHINE(spapr
);
123 unsigned int smp_threads
= ms
->smp
.threads
;
127 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
129 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
133 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
136 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
138 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
139 * and newer QEMUs don't even have them. In both cases, we don't want
140 * to send anything on the wire.
145 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
146 .name
= "icp/server",
148 .minimum_version_id
= 1,
149 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
150 .fields
= (VMStateField
[]) {
151 VMSTATE_UNUSED(4), /* uint32_t xirr */
152 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
153 VMSTATE_UNUSED(1), /* uint8_t mfrr */
154 VMSTATE_END_OF_LIST()
158 static void pre_2_10_vmstate_register_dummy_icp(int i
)
160 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
161 (void *)(uintptr_t) i
);
164 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
166 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
167 (void *)(uintptr_t) i
);
170 int spapr_max_server_number(SpaprMachineState
*spapr
)
172 MachineState
*ms
= MACHINE(spapr
);
175 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
178 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
182 g_autofree
uint32_t *servers_prop
= g_new(uint32_t, smt_threads
);
183 g_autofree
uint32_t *gservers_prop
= g_new(uint32_t, smt_threads
* 2);
184 int index
= spapr_get_vcpu_id(cpu
);
186 if (cpu
->compat_pvr
) {
187 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
193 /* Build interrupt servers and gservers properties */
194 for (i
= 0; i
< smt_threads
; i
++) {
195 servers_prop
[i
] = cpu_to_be32(index
+ i
);
196 /* Hack, direct the group queues back to cpu 0 */
197 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
198 gservers_prop
[i
*2 + 1] = 0;
200 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
201 servers_prop
, sizeof(*servers_prop
) * smt_threads
);
205 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
206 gservers_prop
, sizeof(*gservers_prop
) * smt_threads
* 2);
211 static void spapr_dt_pa_features(SpaprMachineState
*spapr
,
213 void *fdt
, int offset
)
215 uint8_t pa_features_206
[] = { 6, 0,
216 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
217 uint8_t pa_features_207
[] = { 24, 0,
218 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
219 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
220 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
221 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
222 uint8_t pa_features_300
[] = { 66, 0,
223 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
224 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
225 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
227 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
230 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
232 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
234 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
235 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
236 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
238 /* 42: PM, 44: PC RA, 46: SC vec'd */
239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
240 /* 48: SIMD, 50: QP BFP, 52: String */
241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
242 /* 54: DecFP, 56: DecI, 58: SHA */
243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
244 /* 60: NM atomic, 62: RNG */
245 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
247 uint8_t *pa_features
= NULL
;
250 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
251 pa_features
= pa_features_206
;
252 pa_size
= sizeof(pa_features_206
);
254 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
255 pa_features
= pa_features_207
;
256 pa_size
= sizeof(pa_features_207
);
258 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
259 pa_features
= pa_features_300
;
260 pa_size
= sizeof(pa_features_300
);
266 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
268 * Note: we keep CI large pages off by default because a 64K capable
269 * guest provisioned with large pages might otherwise try to map a qemu
270 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
271 * even if that qemu runs on a 4k host.
272 * We dd this bit back here if we are confident this is not an issue
274 pa_features
[3] |= 0x20;
276 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
277 pa_features
[24] |= 0x80; /* Transactional memory support */
279 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
280 /* Workaround for broken kernels that attempt (guest) radix
281 * mode when they can't handle it, if they see the radix bit set
282 * in pa-features. So hide it from them. */
283 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
286 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
289 static hwaddr
spapr_node0_size(MachineState
*machine
)
291 if (machine
->numa_state
->num_nodes
) {
293 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
294 if (machine
->numa_state
->nodes
[i
].node_mem
) {
295 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
300 return machine
->ram_size
;
303 static void add_str(GString
*s
, const gchar
*s1
)
305 g_string_append_len(s
, s1
, strlen(s1
) + 1);
308 static int spapr_dt_memory_node(SpaprMachineState
*spapr
, void *fdt
, int nodeid
,
309 hwaddr start
, hwaddr size
)
312 uint64_t mem_reg_property
[2];
315 mem_reg_property
[0] = cpu_to_be64(start
);
316 mem_reg_property
[1] = cpu_to_be64(size
);
318 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
319 off
= fdt_add_subnode(fdt
, 0, mem_name
);
321 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
322 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
323 sizeof(mem_reg_property
))));
324 spapr_numa_write_associativity_dt(spapr
, fdt
, off
, nodeid
);
328 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
330 MemoryDeviceInfoList
*info
;
332 for (info
= list
; info
; info
= info
->next
) {
333 MemoryDeviceInfo
*value
= info
->value
;
335 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
336 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
338 if (addr
>= pcdimm_info
->addr
&&
339 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
340 return pcdimm_info
->node
;
348 struct sPAPRDrconfCellV2
{
356 typedef struct DrconfCellQueue
{
357 struct sPAPRDrconfCellV2 cell
;
358 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
361 static DrconfCellQueue
*
362 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
363 uint32_t drc_index
, uint32_t aa_index
,
366 DrconfCellQueue
*elem
;
368 elem
= g_malloc0(sizeof(*elem
));
369 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
370 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
371 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
372 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
373 elem
->cell
.flags
= cpu_to_be32(flags
);
378 static int spapr_dt_dynamic_memory_v2(SpaprMachineState
*spapr
, void *fdt
,
379 int offset
, MemoryDeviceInfoList
*dimms
)
381 MachineState
*machine
= MACHINE(spapr
);
382 uint8_t *int_buf
, *cur_index
;
384 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
385 uint64_t addr
, cur_addr
, size
;
386 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
387 uint64_t mem_end
= machine
->device_memory
->base
+
388 memory_region_size(&machine
->device_memory
->mr
);
389 uint32_t node
, buf_len
, nr_entries
= 0;
391 DrconfCellQueue
*elem
, *next
;
392 MemoryDeviceInfoList
*info
;
393 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
394 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
396 /* Entry to cover RAM and the gap area */
397 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
398 SPAPR_LMB_FLAGS_RESERVED
|
399 SPAPR_LMB_FLAGS_DRC_INVALID
);
400 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
403 cur_addr
= machine
->device_memory
->base
;
404 for (info
= dimms
; info
; info
= info
->next
) {
405 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
412 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
413 * area is marked hotpluggable in the next iteration for the bigger
414 * chunk including the NVDIMM occupied area.
416 if (info
->value
->type
== MEMORY_DEVICE_INFO_KIND_NVDIMM
)
419 /* Entry for hot-pluggable area */
420 if (cur_addr
< addr
) {
421 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
423 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
424 cur_addr
, spapr_drc_index(drc
), -1, 0);
425 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
430 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
432 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
433 spapr_drc_index(drc
), node
,
434 (SPAPR_LMB_FLAGS_ASSIGNED
|
435 SPAPR_LMB_FLAGS_HOTREMOVABLE
));
436 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
438 cur_addr
= addr
+ size
;
441 /* Entry for remaining hotpluggable area */
442 if (cur_addr
< mem_end
) {
443 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
445 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
446 cur_addr
, spapr_drc_index(drc
), -1, 0);
447 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
451 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
452 int_buf
= cur_index
= g_malloc0(buf_len
);
453 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
454 cur_index
+= sizeof(nr_entries
);
456 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
457 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
458 cur_index
+= sizeof(elem
->cell
);
459 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
463 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
471 static int spapr_dt_dynamic_memory(SpaprMachineState
*spapr
, void *fdt
,
472 int offset
, MemoryDeviceInfoList
*dimms
)
474 MachineState
*machine
= MACHINE(spapr
);
476 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
477 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
478 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
479 memory_region_size(&machine
->device_memory
->mr
)) /
481 uint32_t *int_buf
, *cur_index
, buf_len
;
484 * Allocate enough buffer size to fit in ibm,dynamic-memory
486 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
487 cur_index
= int_buf
= g_malloc0(buf_len
);
488 int_buf
[0] = cpu_to_be32(nr_lmbs
);
490 for (i
= 0; i
< nr_lmbs
; i
++) {
491 uint64_t addr
= i
* lmb_size
;
492 uint32_t *dynamic_memory
= cur_index
;
494 if (i
>= device_lmb_start
) {
497 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
500 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
501 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
502 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
503 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
504 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
505 if (memory_region_present(get_system_memory(), addr
)) {
506 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
508 dynamic_memory
[5] = cpu_to_be32(0);
512 * LMB information for RMA, boot time RAM and gap b/n RAM and
513 * device memory region -- all these are marked as reserved
514 * and as having no valid DRC.
516 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
517 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
518 dynamic_memory
[2] = cpu_to_be32(0);
519 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
520 dynamic_memory
[4] = cpu_to_be32(-1);
521 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
522 SPAPR_LMB_FLAGS_DRC_INVALID
);
525 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
527 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
536 * Adds ibm,dynamic-reconfiguration-memory node.
537 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
538 * of this device tree node.
540 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState
*spapr
,
543 MachineState
*machine
= MACHINE(spapr
);
545 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
546 uint32_t prop_lmb_size
[] = {cpu_to_be32(lmb_size
>> 32),
547 cpu_to_be32(lmb_size
& 0xffffffff)};
548 MemoryDeviceInfoList
*dimms
= NULL
;
550 /* Don't create the node if there is no device memory. */
551 if (!machine
->device_memory
) {
555 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
557 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
558 sizeof(prop_lmb_size
));
563 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
568 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
573 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
574 dimms
= qmp_memory_device_list();
575 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
576 ret
= spapr_dt_dynamic_memory_v2(spapr
, fdt
, offset
, dimms
);
578 ret
= spapr_dt_dynamic_memory(spapr
, fdt
, offset
, dimms
);
580 qapi_free_MemoryDeviceInfoList(dimms
);
586 ret
= spapr_numa_write_assoc_lookup_arrays(spapr
, fdt
, offset
);
591 static int spapr_dt_memory(SpaprMachineState
*spapr
, void *fdt
)
593 MachineState
*machine
= MACHINE(spapr
);
594 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
595 hwaddr mem_start
, node_size
;
596 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
597 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
599 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
600 if (!nodes
[i
].node_mem
) {
603 if (mem_start
>= machine
->ram_size
) {
606 node_size
= nodes
[i
].node_mem
;
607 if (node_size
> machine
->ram_size
- mem_start
) {
608 node_size
= machine
->ram_size
- mem_start
;
612 /* spapr_machine_init() checks for rma_size <= node0_size
614 spapr_dt_memory_node(spapr
, fdt
, i
, 0, spapr
->rma_size
);
615 mem_start
+= spapr
->rma_size
;
616 node_size
-= spapr
->rma_size
;
618 for ( ; node_size
; ) {
619 hwaddr sizetmp
= pow2floor(node_size
);
621 /* mem_start != 0 here */
622 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
623 sizetmp
= 1ULL << ctzl(mem_start
);
626 spapr_dt_memory_node(spapr
, fdt
, i
, mem_start
, sizetmp
);
627 node_size
-= sizetmp
;
628 mem_start
+= sizetmp
;
632 /* Generate ibm,dynamic-reconfiguration-memory node if required */
633 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRCONF_MEMORY
)) {
636 g_assert(smc
->dr_lmb_enabled
);
637 ret
= spapr_dt_dynamic_reconfiguration_memory(spapr
, fdt
);
646 static void spapr_dt_cpu(CPUState
*cs
, void *fdt
, int offset
,
647 SpaprMachineState
*spapr
)
649 MachineState
*ms
= MACHINE(spapr
);
650 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
651 CPUPPCState
*env
= &cpu
->env
;
652 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
653 int index
= spapr_get_vcpu_id(cpu
);
654 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
655 0xffffffff, 0xffffffff};
656 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
657 : SPAPR_TIMEBASE_FREQ
;
658 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
659 uint32_t page_sizes_prop
[64];
660 size_t page_sizes_prop_size
;
661 unsigned int smp_threads
= ms
->smp
.threads
;
662 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
663 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
664 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
667 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
670 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
672 drc_index
= spapr_drc_index(drc
);
673 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
676 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
677 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
679 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
680 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
681 env
->dcache_line_size
)));
682 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
683 env
->dcache_line_size
)));
684 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
685 env
->icache_line_size
)));
686 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
687 env
->icache_line_size
)));
689 if (pcc
->l1_dcache_size
) {
690 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
691 pcc
->l1_dcache_size
)));
693 warn_report("Unknown L1 dcache size for cpu");
695 if (pcc
->l1_icache_size
) {
696 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
697 pcc
->l1_icache_size
)));
699 warn_report("Unknown L1 icache size for cpu");
702 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
703 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
704 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
705 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
706 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
707 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
709 if (ppc_has_spr(cpu
, SPR_PURR
)) {
710 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
712 if (ppc_has_spr(cpu
, SPR_PURR
)) {
713 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
716 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
717 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
718 segs
, sizeof(segs
))));
721 /* Advertise VSX (vector extensions) if available
722 * 1 == VMX / Altivec available
725 * Only CPUs for which we create core types in spapr_cpu_core.c
726 * are possible, and all of those have VMX */
727 if (env
->insns_flags
& PPC_ALTIVEC
) {
728 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
729 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
731 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
735 /* Advertise DFP (Decimal Floating Point) if available
736 * 0 / no property == no DFP
737 * 1 == DFP available */
738 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
739 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
742 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
743 sizeof(page_sizes_prop
));
744 if (page_sizes_prop_size
) {
745 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
746 page_sizes_prop
, page_sizes_prop_size
)));
749 spapr_dt_pa_features(spapr
, cpu
, fdt
, offset
);
751 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
752 cs
->cpu_index
/ vcpus_per_socket
)));
754 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
755 pft_size_prop
, sizeof(pft_size_prop
))));
757 if (ms
->numa_state
->num_nodes
> 1) {
758 _FDT(spapr_numa_fixup_cpu_dt(spapr
, fdt
, offset
, cpu
));
761 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
763 if (pcc
->radix_page_info
) {
764 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
765 radix_AP_encodings
[i
] =
766 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
768 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
770 pcc
->radix_page_info
->count
*
771 sizeof(radix_AP_encodings
[0]))));
775 * We set this property to let the guest know that it can use the large
776 * decrementer and its width in bits.
778 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
779 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
780 pcc
->lrg_decr_bits
)));
783 static void spapr_dt_cpus(void *fdt
, SpaprMachineState
*spapr
)
791 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
793 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
794 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
797 * We walk the CPUs in reverse order to ensure that CPU DT nodes
798 * created by fdt_add_subnode() end up in the right order in FDT
799 * for the guest kernel the enumerate the CPUs correctly.
801 * The CPU list cannot be traversed in reverse order, so we need
807 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
811 for (i
= n_cpus
- 1; i
>= 0; i
--) {
812 CPUState
*cs
= rev
[i
];
813 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
814 int index
= spapr_get_vcpu_id(cpu
);
815 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
816 g_autofree
char *nodename
= NULL
;
819 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
823 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
824 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
826 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
832 static int spapr_dt_rng(void *fdt
)
837 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
841 ret
= fdt_setprop_string(fdt
, node
, "device_type",
842 "ibm,platform-facilities");
843 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
844 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
846 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
850 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
855 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
857 MachineState
*ms
= MACHINE(spapr
);
859 GString
*hypertas
= g_string_sized_new(256);
860 GString
*qemu_hypertas
= g_string_sized_new(256);
861 uint32_t lrdr_capacity
[] = {
864 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
>> 32),
865 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
& 0xffffffff),
866 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
869 /* Do we have device memory? */
870 if (MACHINE(spapr
)->device_memory
) {
871 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
872 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
874 lrdr_capacity
[0] = cpu_to_be32(max_device_addr
>> 32);
875 lrdr_capacity
[1] = cpu_to_be32(max_device_addr
& 0xffffffff);
878 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
881 add_str(hypertas
, "hcall-pft");
882 add_str(hypertas
, "hcall-term");
883 add_str(hypertas
, "hcall-dabr");
884 add_str(hypertas
, "hcall-interrupt");
885 add_str(hypertas
, "hcall-tce");
886 add_str(hypertas
, "hcall-vio");
887 add_str(hypertas
, "hcall-splpar");
888 add_str(hypertas
, "hcall-join");
889 add_str(hypertas
, "hcall-bulk");
890 add_str(hypertas
, "hcall-set-mode");
891 add_str(hypertas
, "hcall-sprg0");
892 add_str(hypertas
, "hcall-copy");
893 add_str(hypertas
, "hcall-debug");
894 add_str(hypertas
, "hcall-vphn");
895 if (spapr_get_cap(spapr
, SPAPR_CAP_RPT_INVALIDATE
) == SPAPR_CAP_ON
) {
896 add_str(hypertas
, "hcall-rpt-invalidate");
899 add_str(qemu_hypertas
, "hcall-memop1");
901 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
902 add_str(hypertas
, "hcall-multi-tce");
905 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
906 add_str(hypertas
, "hcall-hpt-resize");
909 add_str(hypertas
, "hcall-watchdog");
911 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
912 hypertas
->str
, hypertas
->len
));
913 g_string_free(hypertas
, TRUE
);
914 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
915 qemu_hypertas
->str
, qemu_hypertas
->len
));
916 g_string_free(qemu_hypertas
, TRUE
);
918 spapr_numa_write_rtas_dt(spapr
, fdt
, rtas
);
921 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
922 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
924 * The system reset requirements are driven by existing Linux and PowerVM
925 * implementation which (contrary to PAPR) saves r3 in the error log
926 * structure like machine check, so Linux expects to find the saved r3
927 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
928 * does not look at the error value).
930 * System reset interrupts are not subject to interlock like machine
931 * check, so this memory area could be corrupted if the sreset is
932 * interrupted by a machine check (or vice versa) if it was shared. To
933 * prevent this, system reset uses per-CPU areas for the sreset save
934 * area. A system reset that interrupts a system reset handler could
935 * still overwrite this area, but Linux doesn't try to recover in that
938 * The extra 8 bytes is required because Linux's FWNMI error log check
941 * RTAS_MIN_SIZE is required for the RTAS blob itself.
943 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-size", RTAS_MIN_SIZE
+
945 ms
->smp
.max_cpus
* sizeof(uint64_t) * 2 +
947 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
948 RTAS_ERROR_LOG_MAX
));
949 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
950 RTAS_EVENT_SCAN_RATE
));
952 g_assert(msi_nonbroken
);
953 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
956 * According to PAPR, rtas ibm,os-term does not guarantee a return
957 * back to the guest cpu.
959 * While an additional ibm,extended-os-term property indicates
960 * that rtas call return will always occur. Set this property.
962 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
964 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
965 lrdr_capacity
, sizeof(lrdr_capacity
)));
967 spapr_dt_rtas_tokens(fdt
, rtas
);
971 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
972 * and the XIVE features that the guest may request and thus the valid
973 * values for bytes 23..26 of option vector 5:
975 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
978 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
981 23, 0x00, /* XICS / XIVE mode */
982 24, 0x00, /* Hash/Radix, filled in below. */
983 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
984 26, 0x40, /* Radix options: GTSE == yes. */
987 if (spapr
->irq
->xics
&& spapr
->irq
->xive
) {
988 val
[1] = SPAPR_OV5_XIVE_BOTH
;
989 } else if (spapr
->irq
->xive
) {
990 val
[1] = SPAPR_OV5_XIVE_EXPLOIT
;
992 assert(spapr
->irq
->xics
);
993 val
[1] = SPAPR_OV5_XIVE_LEGACY
;
996 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
997 first_ppc_cpu
->compat_pvr
)) {
999 * If we're in a pre POWER9 compat mode then the guest should
1000 * do hash and use the legacy interrupt mode
1002 val
[1] = SPAPR_OV5_XIVE_LEGACY
; /* XICS */
1003 val
[3] = 0x00; /* Hash */
1004 spapr_check_mmu_mode(false);
1005 } else if (kvm_enabled()) {
1006 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1007 val
[3] = 0x80; /* OV5_MMU_BOTH */
1008 } else if (kvmppc_has_cap_mmu_radix()) {
1009 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1011 val
[3] = 0x00; /* Hash */
1014 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1017 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1021 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
, bool reset
)
1023 MachineState
*machine
= MACHINE(spapr
);
1024 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1027 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1030 const char *boot_device
= spapr
->boot_device
;
1031 g_autofree
char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1033 g_autofree
char *bootlist
= get_boot_devices_list(&cb
);
1035 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1036 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1037 machine
->kernel_cmdline
));
1040 if (spapr
->initrd_size
) {
1041 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1042 spapr
->initrd_base
));
1043 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1044 spapr
->initrd_base
+ spapr
->initrd_size
));
1047 if (spapr
->kernel_size
) {
1048 uint64_t kprop
[2] = { cpu_to_be64(spapr
->kernel_addr
),
1049 cpu_to_be64(spapr
->kernel_size
) };
1051 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1052 &kprop
, sizeof(kprop
)));
1053 if (spapr
->kernel_le
) {
1054 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1057 if (machine
->boot_config
.has_menu
&& machine
->boot_config
.menu
) {
1058 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", true)));
1060 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1061 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1062 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1064 if (cb
&& bootlist
) {
1067 for (i
= 0; i
< cb
; i
++) {
1068 if (bootlist
[i
] == '\n') {
1072 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1075 if (boot_device
&& strlen(boot_device
)) {
1076 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1079 if (spapr
->want_stdout_path
&& stdout_path
) {
1081 * "linux,stdout-path" and "stdout" properties are
1082 * deprecated by linux kernel. New platforms should only
1083 * use the "stdout-path" property. Set the new property
1084 * and continue using older property to remain compatible
1085 * with the existing firmware.
1087 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1088 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1092 * We can deal with BAR reallocation just fine, advertise it
1095 if (smc
->linux_pci_probe
) {
1096 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1099 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1102 _FDT(fdt_setprop(fdt
, chosen
, "rng-seed", spapr
->fdt_rng_seed
, 32));
1104 _FDT(spapr_dt_ovec(fdt
, chosen
, spapr
->ov5_cas
, "ibm,architecture-vec-5"));
1107 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1109 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1110 * KVM to work under pHyp with some guest co-operation */
1112 uint8_t hypercall
[16];
1114 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1115 /* indicate KVM hypercall interface */
1116 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1117 if (kvmppc_has_cap_fixup_hcalls()) {
1119 * Older KVM versions with older guest kernels were broken
1120 * with the magic page, don't allow the guest to map it.
1122 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1123 sizeof(hypercall
))) {
1124 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1125 hypercall
, sizeof(hypercall
)));
1130 void *spapr_build_fdt(SpaprMachineState
*spapr
, bool reset
, size_t space
)
1132 MachineState
*machine
= MACHINE(spapr
);
1133 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1134 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1135 uint32_t root_drc_type_mask
= 0;
1141 fdt
= g_malloc0(space
);
1142 _FDT((fdt_create_empty_tree(fdt
, space
)));
1145 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1146 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1147 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1149 /* Guest UUID & Name*/
1150 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1151 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1152 if (qemu_uuid_set
) {
1153 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1157 if (qemu_get_vm_name()) {
1158 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1159 qemu_get_vm_name()));
1162 /* Host Model & Serial Number */
1163 if (spapr
->host_model
) {
1164 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1165 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1166 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1170 if (spapr
->host_serial
) {
1171 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1172 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1173 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1177 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1178 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1180 /* /interrupt controller */
1181 spapr_irq_dt(spapr
, spapr_max_server_number(spapr
), fdt
, PHANDLE_INTC
);
1183 ret
= spapr_dt_memory(spapr
, fdt
);
1185 error_report("couldn't setup memory nodes in fdt");
1190 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1192 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1193 ret
= spapr_dt_rng(fdt
);
1195 error_report("could not set up rng device in the fdt");
1200 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1201 ret
= spapr_dt_phb(spapr
, phb
, PHANDLE_INTC
, fdt
, NULL
);
1203 error_report("couldn't setup PCI devices in fdt");
1208 spapr_dt_cpus(fdt
, spapr
);
1210 /* ibm,drc-indexes and friends */
1211 if (smc
->dr_lmb_enabled
) {
1212 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_LMB
;
1214 if (smc
->dr_phb_enabled
) {
1215 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_PHB
;
1217 if (mc
->nvdimm_supported
) {
1218 root_drc_type_mask
|= SPAPR_DR_CONNECTOR_TYPE_PMEM
;
1220 if (root_drc_type_mask
) {
1221 _FDT(spapr_dt_drc(fdt
, 0, NULL
, root_drc_type_mask
));
1224 if (mc
->has_hotpluggable_cpus
) {
1225 int offset
= fdt_path_offset(fdt
, "/cpus");
1226 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1228 error_report("Couldn't set up CPU DR device tree properties");
1233 /* /event-sources */
1234 spapr_dt_events(spapr
, fdt
);
1237 spapr_dt_rtas(spapr
, fdt
);
1240 spapr_dt_chosen(spapr
, fdt
, reset
);
1243 if (kvm_enabled()) {
1244 spapr_dt_hypervisor(spapr
, fdt
);
1247 /* Build memory reserve map */
1249 if (spapr
->kernel_size
) {
1250 _FDT((fdt_add_mem_rsv(fdt
, spapr
->kernel_addr
,
1251 spapr
->kernel_size
)));
1253 if (spapr
->initrd_size
) {
1254 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
,
1255 spapr
->initrd_size
)));
1259 /* NVDIMM devices */
1260 if (mc
->nvdimm_supported
) {
1261 spapr_dt_persistent_memory(spapr
, fdt
);
1267 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1269 SpaprMachineState
*spapr
= opaque
;
1271 return (addr
& 0x0fffffff) + spapr
->kernel_addr
;
1274 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1277 CPUPPCState
*env
= &cpu
->env
;
1279 /* The TCG path should also be holding the BQL at this point */
1280 g_assert(qemu_mutex_iothread_locked());
1282 g_assert(!vhyp_cpu_in_nested(cpu
));
1284 if (FIELD_EX64(env
->msr
, MSR
, PR
)) {
1285 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1286 env
->gpr
[3] = H_PRIVILEGE
;
1288 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1292 struct LPCRSyncState
{
1297 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1299 struct LPCRSyncState
*s
= arg
.host_ptr
;
1300 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1301 CPUPPCState
*env
= &cpu
->env
;
1304 cpu_synchronize_state(cs
);
1305 lpcr
= env
->spr
[SPR_LPCR
];
1308 ppc_store_lpcr(cpu
, lpcr
);
1311 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1314 struct LPCRSyncState s
= {
1319 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1323 /* May be used when the machine is not running */
1324 void spapr_init_all_lpcrs(target_ulong value
, target_ulong mask
)
1328 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1329 CPUPPCState
*env
= &cpu
->env
;
1332 lpcr
= env
->spr
[SPR_LPCR
];
1333 lpcr
&= ~(LPCR_HR
| LPCR_UPRT
);
1334 ppc_store_lpcr(cpu
, lpcr
);
1339 static bool spapr_get_pate(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
,
1340 target_ulong lpid
, ppc_v3_pate_t
*entry
)
1342 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1343 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
1345 if (!spapr_cpu
->in_nested
) {
1348 /* Copy PATE1:GR into PATE0:HR */
1349 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1350 entry
->dw1
= spapr
->patb_entry
;
1353 uint64_t patb
, pats
;
1357 patb
= spapr
->nested_ptcr
& PTCR_PATB
;
1358 pats
= spapr
->nested_ptcr
& PTCR_PATS
;
1360 /* Check if partition table is properly aligned */
1361 if (patb
& MAKE_64BIT_MASK(0, pats
+ 12)) {
1365 /* Calculate number of entries */
1366 pats
= 1ull << (pats
+ 12 - 4);
1373 entry
->dw0
= ldq_phys(CPU(cpu
)->as
, patb
);
1374 entry
->dw1
= ldq_phys(CPU(cpu
)->as
, patb
+ 8);
1380 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1381 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1382 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1383 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1384 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1387 * Get the fd to access the kernel htab, re-opening it if necessary
1389 static int get_htab_fd(SpaprMachineState
*spapr
)
1391 Error
*local_err
= NULL
;
1393 if (spapr
->htab_fd
>= 0) {
1394 return spapr
->htab_fd
;
1397 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1398 if (spapr
->htab_fd
< 0) {
1399 error_report_err(local_err
);
1402 return spapr
->htab_fd
;
1405 void close_htab_fd(SpaprMachineState
*spapr
)
1407 if (spapr
->htab_fd
>= 0) {
1408 close(spapr
->htab_fd
);
1410 spapr
->htab_fd
= -1;
1413 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1415 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1417 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1420 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1422 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1424 assert(kvm_enabled());
1430 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1433 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1436 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1437 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1441 * HTAB is controlled by KVM. Fetch into temporary buffer
1443 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1444 kvmppc_read_hptes(hptes
, ptex
, n
);
1449 * HTAB is controlled by QEMU. Just point to the internally
1452 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1455 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1456 const ppc_hash_pte64_t
*hptes
,
1459 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1462 g_free((void *)hptes
);
1465 /* Nothing to do for qemu managed HPT */
1468 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1469 uint64_t pte0
, uint64_t pte1
)
1471 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1472 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1475 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1477 if (pte0
& HPTE64_V_VALID
) {
1478 stq_p(spapr
->htab
+ offset
+ HPTE64_DW1
, pte1
);
1480 * When setting valid, we write PTE1 first. This ensures
1481 * proper synchronization with the reading code in
1482 * ppc_hash64_pteg_search()
1485 stq_p(spapr
->htab
+ offset
, pte0
);
1487 stq_p(spapr
->htab
+ offset
, pte0
);
1489 * When clearing it we set PTE0 first. This ensures proper
1490 * synchronization with the reading code in
1491 * ppc_hash64_pteg_search()
1494 stq_p(spapr
->htab
+ offset
+ HPTE64_DW1
, pte1
);
1499 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1502 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ HPTE64_DW1_C
;
1503 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1506 /* There should always be a hash table when this is called */
1507 error_report("spapr_hpte_set_c called with no hash table !");
1511 /* The HW performs a non-atomic byte update */
1512 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1515 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1518 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ HPTE64_DW1_R
;
1519 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1522 /* There should always be a hash table when this is called */
1523 error_report("spapr_hpte_set_r called with no hash table !");
1527 /* The HW performs a non-atomic byte update */
1528 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1531 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1535 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1536 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1537 * that's much more than is needed for Linux guests */
1538 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1539 shift
= MAX(shift
, 18); /* Minimum architected size */
1540 shift
= MIN(shift
, 46); /* Maximum architected size */
1544 void spapr_free_hpt(SpaprMachineState
*spapr
)
1546 qemu_vfree(spapr
->htab
);
1548 spapr
->htab_shift
= 0;
1549 close_htab_fd(spapr
);
1552 int spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
, Error
**errp
)
1557 /* Clean up any HPT info from a previous boot */
1558 spapr_free_hpt(spapr
);
1560 rc
= kvmppc_reset_htab(shift
);
1562 if (rc
== -EOPNOTSUPP
) {
1563 error_setg(errp
, "HPT not supported in nested guests");
1568 /* kernel-side HPT needed, but couldn't allocate one */
1569 error_setg_errno(errp
, errno
, "Failed to allocate KVM HPT of order %d",
1571 error_append_hint(errp
, "Try smaller maxmem?\n");
1573 } else if (rc
> 0) {
1574 /* kernel-side HPT allocated */
1577 "Requested order %d HPT, but kernel allocated order %ld",
1579 error_append_hint(errp
, "Try smaller maxmem?\n");
1583 spapr
->htab_shift
= shift
;
1586 /* kernel-side HPT not needed, allocate in userspace instead */
1587 size_t size
= 1ULL << shift
;
1590 spapr
->htab
= qemu_memalign(size
, size
);
1591 memset(spapr
->htab
, 0, size
);
1592 spapr
->htab_shift
= shift
;
1594 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1595 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1598 /* We're setting up a hash table, so that means we're not radix */
1599 spapr
->patb_entry
= 0;
1600 spapr_init_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1604 void spapr_setup_hpt(SpaprMachineState
*spapr
)
1608 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
) {
1609 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1611 uint64_t current_ram_size
;
1613 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1614 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1616 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1618 if (kvm_enabled()) {
1619 hwaddr vrma_limit
= kvmppc_vrma_limit(spapr
->htab_shift
);
1621 /* Check our RMA fits in the possible VRMA */
1622 if (vrma_limit
< spapr
->rma_size
) {
1623 error_report("Unable to create %" HWADDR_PRIu
1624 "MiB RMA (VRMA only allows %" HWADDR_PRIu
"MiB",
1625 spapr
->rma_size
/ MiB
, vrma_limit
/ MiB
);
1631 void spapr_check_mmu_mode(bool guest_radix
)
1634 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) {
1635 error_report("Guest requested unavailable MMU mode (radix).");
1639 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()
1640 && !kvmppc_has_cap_mmu_hash_v3()) {
1641 error_report("Guest requested unavailable MMU mode (hash).");
1647 static void spapr_machine_reset(MachineState
*machine
, ShutdownCause reason
)
1649 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1650 PowerPCCPU
*first_ppc_cpu
;
1655 if (reason
!= SHUTDOWN_CAUSE_SNAPSHOT_LOAD
) {
1657 * Record-replay snapshot load must not consume random, this was
1658 * already replayed from initial machine reset.
1660 qemu_guest_getrandom_nofail(spapr
->fdt_rng_seed
, 32);
1663 pef_kvm_reset(machine
->cgs
, &error_fatal
);
1664 spapr_caps_apply(spapr
);
1666 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1667 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1668 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1669 spapr
->max_compat_pvr
)) {
1671 * If using KVM with radix mode available, VCPUs can be started
1672 * without a HPT because KVM will start them in radix mode.
1673 * Set the GR bit in PATE so that we know there is no HPT.
1675 spapr
->patb_entry
= PATE1_GR
;
1676 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1678 spapr_setup_hpt(spapr
);
1681 qemu_devices_reset(reason
);
1683 spapr_ovec_cleanup(spapr
->ov5_cas
);
1684 spapr
->ov5_cas
= spapr_ovec_new();
1686 ppc_init_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1689 * This is fixing some of the default configuration of the XIVE
1690 * devices. To be called after the reset of the machine devices.
1692 spapr_irq_reset(spapr
, &error_fatal
);
1695 * There is no CAS under qtest. Simulate one to please the code that
1696 * depends on spapr->ov5_cas. This is especially needed to test device
1697 * unplug, so we do that before resetting the DRCs.
1699 if (qtest_enabled()) {
1700 spapr_ovec_cleanup(spapr
->ov5_cas
);
1701 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1704 spapr_nvdimm_finish_flushes();
1706 /* DRC reset may cause a device to be unplugged. This will cause troubles
1707 * if this device is used by another device (eg, a running vhost backend
1708 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1709 * situations, we reset DRCs after all devices have been reset.
1711 spapr_drc_reset_all(spapr
);
1713 spapr_clear_pending_events(spapr
);
1716 * We place the device tree just below either the top of the RMA,
1717 * or just below 2GB, whichever is lower, so that it can be
1718 * processed with 32-bit real mode code if necessary
1720 fdt_addr
= MIN(spapr
->rma_size
, FDT_MAX_ADDR
) - FDT_MAX_SIZE
;
1722 fdt
= spapr_build_fdt(spapr
, true, FDT_MAX_SIZE
);
1724 spapr_vof_reset(spapr
, fdt
, &error_fatal
);
1726 * Do not pack the FDT as the client may change properties.
1727 * VOF client does not expect the FDT so we do not load it to the VM.
1731 /* Should only fail if we've built a corrupted tree */
1734 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
,
1736 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1738 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1740 g_free(spapr
->fdt_blob
);
1741 spapr
->fdt_size
= fdt_totalsize(fdt
);
1742 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1743 spapr
->fdt_blob
= fdt
;
1745 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
1748 /* Set up the entry state */
1749 first_ppc_cpu
->env
.gpr
[5] = 0;
1751 spapr
->fwnmi_system_reset_addr
= -1;
1752 spapr
->fwnmi_machine_check_addr
= -1;
1753 spapr
->fwnmi_machine_check_interlock
= -1;
1755 /* Signal all vCPUs waiting on this condition */
1756 qemu_cond_broadcast(&spapr
->fwnmi_machine_check_interlock_cond
);
1758 migrate_del_blocker(spapr
->fwnmi_migration_blocker
);
1761 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1763 DeviceState
*dev
= qdev_new("spapr-nvram");
1764 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1767 qdev_prop_set_drive_err(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1771 qdev_realize_and_unref(dev
, &spapr
->vio_bus
->bus
, &error_fatal
);
1773 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1776 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1778 object_initialize_child_with_props(OBJECT(spapr
), "rtc", &spapr
->rtc
,
1779 sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1780 &error_fatal
, NULL
);
1781 qdev_realize(DEVICE(&spapr
->rtc
), NULL
, &error_fatal
);
1782 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1786 /* Returns whether we want to use VGA or not */
1787 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1789 vga_interface_created
= true;
1790 switch (vga_interface_type
) {
1798 return pci_vga_init(pci_bus
) != NULL
;
1801 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1806 static int spapr_pre_load(void *opaque
)
1810 rc
= spapr_caps_pre_load(opaque
);
1818 static int spapr_post_load(void *opaque
, int version_id
)
1820 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1823 err
= spapr_caps_post_migration(spapr
);
1829 * In earlier versions, there was no separate qdev for the PAPR
1830 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1831 * So when migrating from those versions, poke the incoming offset
1832 * value into the RTC device
1834 if (version_id
< 3) {
1835 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1841 if (kvm_enabled() && spapr
->patb_entry
) {
1842 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1843 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1844 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1847 * Update LPCR:HR and UPRT as they may not be set properly in
1850 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1851 LPCR_HR
| LPCR_UPRT
);
1853 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1855 error_report("Process table config unsupported by the host");
1860 err
= spapr_irq_post_load(spapr
, version_id
);
1868 static int spapr_pre_save(void *opaque
)
1872 rc
= spapr_caps_pre_save(opaque
);
1880 static bool version_before_3(void *opaque
, int version_id
)
1882 return version_id
< 3;
1885 static bool spapr_pending_events_needed(void *opaque
)
1887 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1888 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1891 static const VMStateDescription vmstate_spapr_event_entry
= {
1892 .name
= "spapr_event_log_entry",
1894 .minimum_version_id
= 1,
1895 .fields
= (VMStateField
[]) {
1896 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1897 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1898 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1899 NULL
, extended_length
),
1900 VMSTATE_END_OF_LIST()
1904 static const VMStateDescription vmstate_spapr_pending_events
= {
1905 .name
= "spapr_pending_events",
1907 .minimum_version_id
= 1,
1908 .needed
= spapr_pending_events_needed
,
1909 .fields
= (VMStateField
[]) {
1910 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1911 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1912 VMSTATE_END_OF_LIST()
1916 static bool spapr_ov5_cas_needed(void *opaque
)
1918 SpaprMachineState
*spapr
= opaque
;
1919 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1922 /* Prior to the introduction of SpaprOptionVector, we had two option
1923 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1924 * Both of these options encode machine topology into the device-tree
1925 * in such a way that the now-booted OS should still be able to interact
1926 * appropriately with QEMU regardless of what options were actually
1927 * negotiatied on the source side.
1929 * As such, we can avoid migrating the CAS-negotiated options if these
1930 * are the only options available on the current machine/platform.
1931 * Since these are the only options available for pseries-2.7 and
1932 * earlier, this allows us to maintain old->new/new->old migration
1935 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1936 * via default pseries-2.8 machines and explicit command-line parameters.
1937 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1938 * of the actual CAS-negotiated values to continue working properly. For
1939 * example, availability of memory unplug depends on knowing whether
1940 * OV5_HP_EVT was negotiated via CAS.
1942 * Thus, for any cases where the set of available CAS-negotiatable
1943 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1944 * include the CAS-negotiated options in the migration stream, unless
1945 * if they affect boot time behaviour only.
1947 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1948 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1949 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1951 /* We need extra information if we have any bits outside the mask
1953 cas_needed
= !spapr_ovec_subset(spapr
->ov5
, ov5_mask
);
1955 spapr_ovec_cleanup(ov5_mask
);
1960 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1961 .name
= "spapr_option_vector_ov5_cas",
1963 .minimum_version_id
= 1,
1964 .needed
= spapr_ov5_cas_needed
,
1965 .fields
= (VMStateField
[]) {
1966 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1967 vmstate_spapr_ovec
, SpaprOptionVector
),
1968 VMSTATE_END_OF_LIST()
1972 static bool spapr_patb_entry_needed(void *opaque
)
1974 SpaprMachineState
*spapr
= opaque
;
1976 return !!spapr
->patb_entry
;
1979 static const VMStateDescription vmstate_spapr_patb_entry
= {
1980 .name
= "spapr_patb_entry",
1982 .minimum_version_id
= 1,
1983 .needed
= spapr_patb_entry_needed
,
1984 .fields
= (VMStateField
[]) {
1985 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1986 VMSTATE_END_OF_LIST()
1990 static bool spapr_irq_map_needed(void *opaque
)
1992 SpaprMachineState
*spapr
= opaque
;
1994 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1997 static const VMStateDescription vmstate_spapr_irq_map
= {
1998 .name
= "spapr_irq_map",
2000 .minimum_version_id
= 1,
2001 .needed
= spapr_irq_map_needed
,
2002 .fields
= (VMStateField
[]) {
2003 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
2004 VMSTATE_END_OF_LIST()
2008 static bool spapr_dtb_needed(void *opaque
)
2010 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
2012 return smc
->update_dt_enabled
;
2015 static int spapr_dtb_pre_load(void *opaque
)
2017 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2019 g_free(spapr
->fdt_blob
);
2020 spapr
->fdt_blob
= NULL
;
2021 spapr
->fdt_size
= 0;
2026 static const VMStateDescription vmstate_spapr_dtb
= {
2027 .name
= "spapr_dtb",
2029 .minimum_version_id
= 1,
2030 .needed
= spapr_dtb_needed
,
2031 .pre_load
= spapr_dtb_pre_load
,
2032 .fields
= (VMStateField
[]) {
2033 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
2034 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
2035 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
2037 VMSTATE_END_OF_LIST()
2041 static bool spapr_fwnmi_needed(void *opaque
)
2043 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2045 return spapr
->fwnmi_machine_check_addr
!= -1;
2048 static int spapr_fwnmi_pre_save(void *opaque
)
2050 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2053 * Check if machine check handling is in progress and print a
2056 if (spapr
->fwnmi_machine_check_interlock
!= -1) {
2057 warn_report("A machine check is being handled during migration. The"
2058 "handler may run and log hardware error on the destination");
2064 static const VMStateDescription vmstate_spapr_fwnmi
= {
2065 .name
= "spapr_fwnmi",
2067 .minimum_version_id
= 1,
2068 .needed
= spapr_fwnmi_needed
,
2069 .pre_save
= spapr_fwnmi_pre_save
,
2070 .fields
= (VMStateField
[]) {
2071 VMSTATE_UINT64(fwnmi_system_reset_addr
, SpaprMachineState
),
2072 VMSTATE_UINT64(fwnmi_machine_check_addr
, SpaprMachineState
),
2073 VMSTATE_INT32(fwnmi_machine_check_interlock
, SpaprMachineState
),
2074 VMSTATE_END_OF_LIST()
2078 static const VMStateDescription vmstate_spapr
= {
2081 .minimum_version_id
= 1,
2082 .pre_load
= spapr_pre_load
,
2083 .post_load
= spapr_post_load
,
2084 .pre_save
= spapr_pre_save
,
2085 .fields
= (VMStateField
[]) {
2086 /* used to be @next_irq */
2087 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2090 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2092 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2093 VMSTATE_END_OF_LIST()
2095 .subsections
= (const VMStateDescription
*[]) {
2096 &vmstate_spapr_ov5_cas
,
2097 &vmstate_spapr_patb_entry
,
2098 &vmstate_spapr_pending_events
,
2099 &vmstate_spapr_cap_htm
,
2100 &vmstate_spapr_cap_vsx
,
2101 &vmstate_spapr_cap_dfp
,
2102 &vmstate_spapr_cap_cfpc
,
2103 &vmstate_spapr_cap_sbbc
,
2104 &vmstate_spapr_cap_ibs
,
2105 &vmstate_spapr_cap_hpt_maxpagesize
,
2106 &vmstate_spapr_irq_map
,
2107 &vmstate_spapr_cap_nested_kvm_hv
,
2109 &vmstate_spapr_cap_large_decr
,
2110 &vmstate_spapr_cap_ccf_assist
,
2111 &vmstate_spapr_cap_fwnmi
,
2112 &vmstate_spapr_fwnmi
,
2113 &vmstate_spapr_cap_rpt_invalidate
,
2118 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2120 SpaprMachineState
*spapr
= opaque
;
2122 /* "Iteration" header */
2123 if (!spapr
->htab_shift
) {
2124 qemu_put_be32(f
, -1);
2126 qemu_put_be32(f
, spapr
->htab_shift
);
2130 spapr
->htab_save_index
= 0;
2131 spapr
->htab_first_pass
= true;
2133 if (spapr
->htab_shift
) {
2134 assert(kvm_enabled());
2142 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2143 int chunkstart
, int n_valid
, int n_invalid
)
2145 qemu_put_be32(f
, chunkstart
);
2146 qemu_put_be16(f
, n_valid
);
2147 qemu_put_be16(f
, n_invalid
);
2148 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2149 HASH_PTE_SIZE_64
* n_valid
);
2152 static void htab_save_end_marker(QEMUFile
*f
)
2154 qemu_put_be32(f
, 0);
2155 qemu_put_be16(f
, 0);
2156 qemu_put_be16(f
, 0);
2159 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2162 bool has_timeout
= max_ns
!= -1;
2163 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2164 int index
= spapr
->htab_save_index
;
2165 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2167 assert(spapr
->htab_first_pass
);
2172 /* Consume invalid HPTEs */
2173 while ((index
< htabslots
)
2174 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2175 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2179 /* Consume valid HPTEs */
2181 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2182 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2183 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2187 if (index
> chunkstart
) {
2188 int n_valid
= index
- chunkstart
;
2190 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2193 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2197 } while ((index
< htabslots
) && !migration_rate_exceeded(f
));
2199 if (index
>= htabslots
) {
2200 assert(index
== htabslots
);
2202 spapr
->htab_first_pass
= false;
2204 spapr
->htab_save_index
= index
;
2207 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2210 bool final
= max_ns
< 0;
2211 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2212 int examined
= 0, sent
= 0;
2213 int index
= spapr
->htab_save_index
;
2214 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2216 assert(!spapr
->htab_first_pass
);
2219 int chunkstart
, invalidstart
;
2221 /* Consume non-dirty HPTEs */
2222 while ((index
< htabslots
)
2223 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2229 /* Consume valid dirty HPTEs */
2230 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2231 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2232 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2233 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2238 invalidstart
= index
;
2239 /* Consume invalid dirty HPTEs */
2240 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2241 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2242 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2243 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2248 if (index
> chunkstart
) {
2249 int n_valid
= invalidstart
- chunkstart
;
2250 int n_invalid
= index
- invalidstart
;
2252 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2253 sent
+= index
- chunkstart
;
2255 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2260 if (examined
>= htabslots
) {
2264 if (index
>= htabslots
) {
2265 assert(index
== htabslots
);
2268 } while ((examined
< htabslots
) && (!migration_rate_exceeded(f
) || final
));
2270 if (index
>= htabslots
) {
2271 assert(index
== htabslots
);
2275 spapr
->htab_save_index
= index
;
2277 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2280 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2281 #define MAX_KVM_BUF_SIZE 2048
2283 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2285 SpaprMachineState
*spapr
= opaque
;
2289 /* Iteration header */
2290 if (!spapr
->htab_shift
) {
2291 qemu_put_be32(f
, -1);
2294 qemu_put_be32(f
, 0);
2298 assert(kvm_enabled());
2300 fd
= get_htab_fd(spapr
);
2305 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2309 } else if (spapr
->htab_first_pass
) {
2310 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2312 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2315 htab_save_end_marker(f
);
2320 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2322 SpaprMachineState
*spapr
= opaque
;
2325 /* Iteration header */
2326 if (!spapr
->htab_shift
) {
2327 qemu_put_be32(f
, -1);
2330 qemu_put_be32(f
, 0);
2336 assert(kvm_enabled());
2338 fd
= get_htab_fd(spapr
);
2343 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2348 if (spapr
->htab_first_pass
) {
2349 htab_save_first_pass(f
, spapr
, -1);
2351 htab_save_later_pass(f
, spapr
, -1);
2355 htab_save_end_marker(f
);
2360 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2362 SpaprMachineState
*spapr
= opaque
;
2363 uint32_t section_hdr
;
2365 Error
*local_err
= NULL
;
2367 if (version_id
< 1 || version_id
> 1) {
2368 error_report("htab_load() bad version");
2372 section_hdr
= qemu_get_be32(f
);
2374 if (section_hdr
== -1) {
2375 spapr_free_hpt(spapr
);
2382 /* First section gives the htab size */
2383 ret
= spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2385 error_report_err(local_err
);
2392 assert(kvm_enabled());
2394 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2396 error_report_err(local_err
);
2403 uint16_t n_valid
, n_invalid
;
2405 index
= qemu_get_be32(f
);
2406 n_valid
= qemu_get_be16(f
);
2407 n_invalid
= qemu_get_be16(f
);
2409 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2414 if ((index
+ n_valid
+ n_invalid
) >
2415 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2416 /* Bad index in stream */
2418 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2419 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2425 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2426 HASH_PTE_SIZE_64
* n_valid
);
2429 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2430 HASH_PTE_SIZE_64
* n_invalid
);
2437 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
,
2440 error_report_err(local_err
);
2454 static void htab_save_cleanup(void *opaque
)
2456 SpaprMachineState
*spapr
= opaque
;
2458 close_htab_fd(spapr
);
2461 static SaveVMHandlers savevm_htab_handlers
= {
2462 .save_setup
= htab_save_setup
,
2463 .save_live_iterate
= htab_save_iterate
,
2464 .save_live_complete_precopy
= htab_save_complete
,
2465 .save_cleanup
= htab_save_cleanup
,
2466 .load_state
= htab_load
,
2469 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2472 SpaprMachineState
*spapr
= SPAPR_MACHINE(opaque
);
2474 g_free(spapr
->boot_device
);
2475 spapr
->boot_device
= g_strdup(boot_device
);
2478 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2480 MachineState
*machine
= MACHINE(spapr
);
2481 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2482 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2485 g_assert(!nr_lmbs
|| machine
->device_memory
);
2486 for (i
= 0; i
< nr_lmbs
; i
++) {
2489 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2490 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2496 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2497 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2498 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2500 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2504 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2505 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2506 " is not aligned to %" PRIu64
" MiB",
2508 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2512 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2513 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2514 " is not aligned to %" PRIu64
" MiB",
2516 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2520 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2521 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2523 "Node %d memory size 0x%" PRIx64
2524 " is not aligned to %" PRIu64
" MiB",
2525 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2526 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2532 /* find cpu slot in machine->possible_cpus by core_id */
2533 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2535 int index
= id
/ ms
->smp
.threads
;
2537 if (index
>= ms
->possible_cpus
->len
) {
2543 return &ms
->possible_cpus
->cpus
[index
];
2546 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2548 MachineState
*ms
= MACHINE(spapr
);
2549 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2550 Error
*local_err
= NULL
;
2551 bool vsmt_user
= !!spapr
->vsmt
;
2552 int kvm_smt
= kvmppc_smt_threads();
2554 unsigned int smp_threads
= ms
->smp
.threads
;
2556 if (tcg_enabled()) {
2557 if (smp_threads
> 1 &&
2558 !ppc_type_check_compat(ms
->cpu_type
, CPU_POWERPC_LOGICAL_2_07
, 0,
2559 spapr
->max_compat_pvr
)) {
2560 error_setg(errp
, "TCG only supports SMT on POWER8 or newer CPUs");
2564 if (smp_threads
> 8) {
2565 error_setg(errp
, "TCG cannot support more than 8 threads/core "
2566 "on a pseries machine");
2570 if (!is_power_of_2(smp_threads
)) {
2571 error_setg(errp
, "Cannot support %d threads/core on a pseries "
2572 "machine because it must be a power of 2", smp_threads
);
2576 /* Detemine the VSMT mode to use: */
2578 if (spapr
->vsmt
< smp_threads
) {
2579 error_setg(errp
, "Cannot support VSMT mode %d"
2580 " because it must be >= threads/core (%d)",
2581 spapr
->vsmt
, smp_threads
);
2584 /* In this case, spapr->vsmt has been set by the command line */
2585 } else if (!smc
->smp_threads_vsmt
) {
2587 * Default VSMT value is tricky, because we need it to be as
2588 * consistent as possible (for migration), but this requires
2589 * changing it for at least some existing cases. We pick 8 as
2590 * the value that we'd get with KVM on POWER8, the
2591 * overwhelmingly common case in production systems.
2593 spapr
->vsmt
= MAX(8, smp_threads
);
2595 spapr
->vsmt
= smp_threads
;
2598 /* KVM: If necessary, set the SMT mode: */
2599 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2600 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2602 /* Looks like KVM isn't able to change VSMT mode */
2603 error_setg(&local_err
,
2604 "Failed to set KVM's VSMT mode to %d (errno %d)",
2606 /* We can live with that if the default one is big enough
2607 * for the number of threads, and a submultiple of the one
2608 * we want. In this case we'll waste some vcpu ids, but
2609 * behaviour will be correct */
2610 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2611 warn_report_err(local_err
);
2614 error_append_hint(&local_err
,
2615 "On PPC, a VM with %d threads/core"
2616 " on a host with %d threads/core"
2617 " requires the use of VSMT mode %d.\n",
2618 smp_threads
, kvm_smt
, spapr
->vsmt
);
2620 kvmppc_error_append_smt_possible_hint(&local_err
);
2621 error_propagate(errp
, local_err
);
2625 /* else TCG: nothing to do currently */
2628 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2630 MachineState
*machine
= MACHINE(spapr
);
2631 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2632 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2633 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2634 const CPUArchIdList
*possible_cpus
;
2635 unsigned int smp_cpus
= machine
->smp
.cpus
;
2636 unsigned int smp_threads
= machine
->smp
.threads
;
2637 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2638 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2641 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2642 if (mc
->has_hotpluggable_cpus
) {
2643 if (smp_cpus
% smp_threads
) {
2644 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2645 smp_cpus
, smp_threads
);
2648 if (max_cpus
% smp_threads
) {
2649 error_report("max_cpus (%u) must be multiple of threads (%u)",
2650 max_cpus
, smp_threads
);
2654 if (max_cpus
!= smp_cpus
) {
2655 error_report("This machine version does not support CPU hotplug");
2658 boot_cores_nr
= possible_cpus
->len
;
2661 if (smc
->pre_2_10_has_unused_icps
) {
2664 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2665 /* Dummy entries get deregistered when real ICPState objects
2666 * are registered during CPU core hotplug.
2668 pre_2_10_vmstate_register_dummy_icp(i
);
2672 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2673 int core_id
= i
* smp_threads
;
2675 if (mc
->has_hotpluggable_cpus
) {
2676 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2677 spapr_vcpu_id(spapr
, core_id
));
2680 if (i
< boot_cores_nr
) {
2681 Object
*core
= object_new(type
);
2682 int nr_threads
= smp_threads
;
2684 /* Handle the partially filled core for older machine types */
2685 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2686 nr_threads
= smp_cpus
- i
* smp_threads
;
2689 object_property_set_int(core
, "nr-threads", nr_threads
,
2691 object_property_set_int(core
, CPU_CORE_PROP_CORE_ID
, core_id
,
2693 qdev_realize(DEVICE(core
), NULL
, &error_fatal
);
2700 static PCIHostState
*spapr_create_default_phb(void)
2704 dev
= qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE
);
2705 qdev_prop_set_uint32(dev
, "index", 0);
2706 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
2708 return PCI_HOST_BRIDGE(dev
);
2711 static hwaddr
spapr_rma_size(SpaprMachineState
*spapr
, Error
**errp
)
2713 MachineState
*machine
= MACHINE(spapr
);
2714 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2715 hwaddr rma_size
= machine
->ram_size
;
2716 hwaddr node0_size
= spapr_node0_size(machine
);
2718 /* RMA has to fit in the first NUMA node */
2719 rma_size
= MIN(rma_size
, node0_size
);
2722 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2725 rma_size
= MIN(rma_size
, 1 * TiB
);
2728 * Clamp the RMA size based on machine type. This is for
2729 * migration compatibility with older qemu versions, which limited
2730 * the RMA size for complicated and mostly bad reasons.
2732 if (smc
->rma_limit
) {
2733 rma_size
= MIN(rma_size
, smc
->rma_limit
);
2736 if (rma_size
< MIN_RMA_SLOF
) {
2738 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2739 "ldMiB guest RMA (Real Mode Area memory)",
2740 MIN_RMA_SLOF
/ MiB
);
2747 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState
*spapr
)
2749 MachineState
*machine
= MACHINE(spapr
);
2752 for (i
= 0; i
< machine
->ram_slots
; i
++) {
2753 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_PMEM
, i
);
2757 /* pSeries LPAR / sPAPR hardware init */
2758 static void spapr_machine_init(MachineState
*machine
)
2760 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2761 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2762 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2763 const char *bios_default
= spapr
->vof
? FW_FILE_NAME_VOF
: FW_FILE_NAME
;
2764 const char *bios_name
= machine
->firmware
?: bios_default
;
2765 g_autofree
char *filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2766 const char *kernel_filename
= machine
->kernel_filename
;
2767 const char *initrd_filename
= machine
->initrd_filename
;
2771 MemoryRegion
*sysmem
= get_system_memory();
2772 long load_limit
, fw_size
;
2773 Error
*resize_hpt_err
= NULL
;
2776 error_report("Could not find LPAR firmware '%s'", bios_name
);
2779 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2781 error_report("Could not load LPAR firmware '%s'", filename
);
2786 * if Secure VM (PEF) support is configured, then initialize it
2788 pef_kvm_init(machine
->cgs
, &error_fatal
);
2790 msi_nonbroken
= true;
2792 QLIST_INIT(&spapr
->phbs
);
2793 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2795 /* Determine capabilities to run with */
2796 spapr_caps_init(spapr
);
2798 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2799 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2801 * If the user explicitly requested a mode we should either
2802 * supply it, or fail completely (which we do below). But if
2803 * it's not set explicitly, we reset our mode to something
2806 if (resize_hpt_err
) {
2807 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2808 error_free(resize_hpt_err
);
2809 resize_hpt_err
= NULL
;
2811 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2815 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2817 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2819 * User requested HPT resize, but this host can't supply it. Bail out
2821 error_report_err(resize_hpt_err
);
2824 error_free(resize_hpt_err
);
2826 spapr
->rma_size
= spapr_rma_size(spapr
, &error_fatal
);
2828 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2829 load_limit
= MIN(spapr
->rma_size
, FDT_MAX_ADDR
) - FW_OVERHEAD
;
2832 * VSMT must be set in order to be able to compute VCPU ids, ie to
2833 * call spapr_max_server_number() or spapr_vcpu_id().
2835 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2837 /* Set up Interrupt Controller before we create the VCPUs */
2838 spapr_irq_init(spapr
, &error_fatal
);
2840 /* Set up containers for ibm,client-architecture-support negotiated options
2842 spapr
->ov5
= spapr_ovec_new();
2843 spapr
->ov5_cas
= spapr_ovec_new();
2845 if (smc
->dr_lmb_enabled
) {
2846 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2847 spapr_validate_node_memory(machine
, &error_fatal
);
2850 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2852 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */
2853 if (!smc
->pre_6_2_numa_affinity
) {
2854 spapr_ovec_set(spapr
->ov5
, OV5_FORM2_AFFINITY
);
2857 /* advertise support for dedicated HP event source to guests */
2858 if (spapr
->use_hotplug_event_source
) {
2859 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2862 /* advertise support for HPT resizing */
2863 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2864 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2867 /* advertise support for ibm,dyamic-memory-v2 */
2868 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2870 /* advertise XIVE on POWER9 machines */
2871 if (spapr
->irq
->xive
) {
2872 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2876 spapr_init_cpus(spapr
);
2878 /* Init numa_assoc_array */
2879 spapr_numa_associativity_init(spapr
, machine
);
2881 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2882 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2883 spapr
->max_compat_pvr
)) {
2884 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_300
);
2885 /* KVM and TCG always allow GTSE with radix... */
2886 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2888 /* ... but not with hash (currently). */
2890 if (kvm_enabled()) {
2891 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2892 kvmppc_enable_logical_ci_hcalls();
2893 kvmppc_enable_set_mode_hcall();
2895 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2896 kvmppc_enable_clear_ref_mod_hcalls();
2898 /* Enable H_PAGE_INIT */
2899 kvmppc_enable_h_page_init();
2903 memory_region_add_subregion(sysmem
, 0, machine
->ram
);
2905 /* initialize hotplug memory address space */
2906 if (machine
->ram_size
< machine
->maxram_size
) {
2907 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2908 hwaddr device_mem_base
;
2911 * Limit the number of hotpluggable memory slots to half the number
2912 * slots that KVM supports, leaving the other half for PCI and other
2913 * devices. However ensure that number of slots doesn't drop below 32.
2915 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2916 SPAPR_MAX_RAM_SLOTS
;
2918 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2919 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2921 if (machine
->ram_slots
> max_memslots
) {
2922 error_report("Specified number of memory slots %"
2923 PRIu64
" exceeds max supported %d",
2924 machine
->ram_slots
, max_memslots
);
2928 device_mem_base
= ROUND_UP(machine
->ram_size
, SPAPR_DEVICE_MEM_ALIGN
);
2929 machine_memory_devices_init(machine
, device_mem_base
, device_mem_size
);
2932 if (smc
->dr_lmb_enabled
) {
2933 spapr_create_lmb_dr_connectors(spapr
);
2936 if (spapr_get_cap(spapr
, SPAPR_CAP_FWNMI
) == SPAPR_CAP_ON
) {
2937 /* Create the error string for live migration blocker */
2938 error_setg(&spapr
->fwnmi_migration_blocker
,
2939 "A machine check is being handled during migration. The handler"
2940 "may run and log hardware error on the destination");
2943 if (mc
->nvdimm_supported
) {
2944 spapr_create_nvdimm_dr_connectors(spapr
);
2947 /* Set up RTAS event infrastructure */
2948 spapr_events_init(spapr
);
2950 /* Set up the RTC RTAS interfaces */
2951 spapr_rtc_create(spapr
);
2953 /* Set up VIO bus */
2954 spapr
->vio_bus
= spapr_vio_bus_init();
2956 for (i
= 0; serial_hd(i
); i
++) {
2957 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2960 /* We always have at least the nvram device on VIO */
2961 spapr_create_nvram(spapr
);
2964 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2965 * connectors (described in root DT node's "ibm,drc-types" property)
2966 * are pre-initialized here. additional child connectors (such as
2967 * connectors for a PHBs PCI slots) are added as needed during their
2968 * parent's realization.
2970 if (smc
->dr_phb_enabled
) {
2971 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2972 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2977 spapr_pci_rtas_init();
2979 phb
= spapr_create_default_phb();
2981 for (i
= 0; i
< nb_nics
; i
++) {
2982 NICInfo
*nd
= &nd_table
[i
];
2985 nd
->model
= g_strdup("spapr-vlan");
2988 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2989 g_str_equal(nd
->model
, "ibmveth")) {
2990 spapr_vlan_create(spapr
->vio_bus
, nd
);
2992 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2996 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2997 spapr_vscsi_create(spapr
->vio_bus
);
3001 has_vga
= spapr_vga_init(phb
->bus
, &error_fatal
);
3003 spapr
->want_stdout_path
= !machine
->enable_graphics
;
3004 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
3006 spapr
->want_stdout_path
= true;
3010 if (smc
->use_ohci_by_default
) {
3011 pci_create_simple(phb
->bus
, -1, "pci-ohci");
3013 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
3017 USBBus
*usb_bus
= usb_bus_find(-1);
3019 usb_create_simple(usb_bus
, "usb-kbd");
3020 usb_create_simple(usb_bus
, "usb-mouse");
3024 if (kernel_filename
) {
3025 uint64_t loaded_addr
= 0;
3027 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3028 translate_kernel_address
, spapr
,
3029 NULL
, &loaded_addr
, NULL
, NULL
, 1,
3030 PPC_ELF_MACHINE
, 0, 0);
3031 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
3032 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3033 translate_kernel_address
, spapr
,
3034 NULL
, &loaded_addr
, NULL
, NULL
, 0,
3035 PPC_ELF_MACHINE
, 0, 0);
3036 spapr
->kernel_le
= spapr
->kernel_size
> 0;
3038 if (spapr
->kernel_size
< 0) {
3039 error_report("error loading %s: %s", kernel_filename
,
3040 load_elf_strerror(spapr
->kernel_size
));
3044 if (spapr
->kernel_addr
!= loaded_addr
) {
3045 warn_report("spapr: kernel_addr changed from 0x%"PRIx64
3047 spapr
->kernel_addr
, loaded_addr
);
3048 spapr
->kernel_addr
= loaded_addr
;
3052 if (initrd_filename
) {
3053 /* Try to locate the initrd in the gap between the kernel
3054 * and the firmware. Add a bit of space just in case
3056 spapr
->initrd_base
= (spapr
->kernel_addr
+ spapr
->kernel_size
3057 + 0x1ffff) & ~0xffff;
3058 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
3061 - spapr
->initrd_base
);
3062 if (spapr
->initrd_size
< 0) {
3063 error_report("could not load initial ram disk '%s'",
3070 /* FIXME: Should register things through the MachineState's qdev
3071 * interface, this is a legacy from the sPAPREnvironment structure
3072 * which predated MachineState but had a similar function */
3073 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3074 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY
, 1,
3075 &savevm_htab_handlers
, spapr
);
3077 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
));
3079 qemu_register_boot_set(spapr_boot_set
, spapr
);
3082 * Nothing needs to be done to resume a suspended guest because
3083 * suspending does not change the machine state, so no need for
3084 * a ->wakeup method.
3086 qemu_register_wakeup_support();
3088 if (kvm_enabled()) {
3089 /* to stop and start vmclock */
3090 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3093 kvmppc_spapr_enable_inkernel_multitce();
3096 qemu_cond_init(&spapr
->fwnmi_machine_check_interlock_cond
);
3098 spapr
->vof
->fw_size
= fw_size
; /* for claim() on itself */
3099 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT
, spapr_h_vof_client
);
3102 spapr_watchdog_init(spapr
);
3105 #define DEFAULT_KVM_TYPE "auto"
3106 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3109 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to
3110 * accomodate the 'HV' and 'PV' formats that exists in the
3111 * wild. The 'auto' mode is being introduced already as
3112 * lower-case, thus we don't need to bother checking for
3115 if (!vm_type
|| !strcmp(vm_type
, DEFAULT_KVM_TYPE
)) {
3119 if (!g_ascii_strcasecmp(vm_type
, "hv")) {
3123 if (!g_ascii_strcasecmp(vm_type
, "pr")) {
3127 error_report("Unknown kvm-type specified '%s'", vm_type
);
3132 * Implementation of an interface to adjust firmware path
3133 * for the bootindex property handling.
3135 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3138 #define CAST(type, obj, name) \
3139 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3140 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3141 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3142 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3143 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3146 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3147 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3148 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3152 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3153 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3154 * 0x8000 | (target << 8) | (bus << 5) | lun
3155 * (see the "Logical unit addressing format" table in SAM5)
3157 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3158 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3159 (uint64_t)id
<< 48);
3160 } else if (virtio
) {
3162 * We use SRP luns of the form 01000000 | (target << 8) | lun
3163 * in the top 32 bits of the 64-bit LUN
3164 * Note: the quote above is from SLOF and it is wrong,
3165 * the actual binding is:
3166 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3168 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3169 if (d
->lun
>= 256) {
3170 /* Use the LUN "flat space addressing method" */
3173 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3174 (uint64_t)id
<< 32);
3177 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3178 * in the top 32 bits of the 64-bit LUN
3180 unsigned usb_port
= atoi(usb
->port
->path
);
3181 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3182 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3183 (uint64_t)id
<< 32);
3188 * SLOF probes the USB devices, and if it recognizes that the device is a
3189 * storage device, it changes its name to "storage" instead of "usb-host",
3190 * and additionally adds a child node for the SCSI LUN, so the correct
3191 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3193 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3194 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3195 if (usb_device_is_scsi_storage(usbdev
)) {
3196 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3201 /* Replace "pci" with "pci@800000020000000" */
3202 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3206 /* Same logic as virtio above */
3207 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3208 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3211 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3212 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3213 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3214 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3218 return spapr_pci_fw_dev_name(pcidev
);
3224 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3226 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3228 return g_strdup(spapr
->kvm_type
);
3231 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3233 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3235 g_free(spapr
->kvm_type
);
3236 spapr
->kvm_type
= g_strdup(value
);
3239 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3241 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3243 return spapr
->use_hotplug_event_source
;
3246 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3249 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3251 spapr
->use_hotplug_event_source
= value
;
3254 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3259 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3261 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3263 switch (spapr
->resize_hpt
) {
3264 case SPAPR_RESIZE_HPT_DEFAULT
:
3265 return g_strdup("default");
3266 case SPAPR_RESIZE_HPT_DISABLED
:
3267 return g_strdup("disabled");
3268 case SPAPR_RESIZE_HPT_ENABLED
:
3269 return g_strdup("enabled");
3270 case SPAPR_RESIZE_HPT_REQUIRED
:
3271 return g_strdup("required");
3273 g_assert_not_reached();
3276 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3278 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3280 if (strcmp(value
, "default") == 0) {
3281 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3282 } else if (strcmp(value
, "disabled") == 0) {
3283 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3284 } else if (strcmp(value
, "enabled") == 0) {
3285 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3286 } else if (strcmp(value
, "required") == 0) {
3287 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3289 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3293 static bool spapr_get_vof(Object
*obj
, Error
**errp
)
3295 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3297 return spapr
->vof
!= NULL
;
3300 static void spapr_set_vof(Object
*obj
, bool value
, Error
**errp
)
3302 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3305 vof_cleanup(spapr
->vof
);
3312 spapr
->vof
= g_malloc0(sizeof(*spapr
->vof
));
3315 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3317 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3319 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3320 return g_strdup("legacy");
3321 } else if (spapr
->irq
== &spapr_irq_xics
) {
3322 return g_strdup("xics");
3323 } else if (spapr
->irq
== &spapr_irq_xive
) {
3324 return g_strdup("xive");
3325 } else if (spapr
->irq
== &spapr_irq_dual
) {
3326 return g_strdup("dual");
3328 g_assert_not_reached();
3331 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3333 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3335 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3336 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3340 /* The legacy IRQ backend can not be set */
3341 if (strcmp(value
, "xics") == 0) {
3342 spapr
->irq
= &spapr_irq_xics
;
3343 } else if (strcmp(value
, "xive") == 0) {
3344 spapr
->irq
= &spapr_irq_xive
;
3345 } else if (strcmp(value
, "dual") == 0) {
3346 spapr
->irq
= &spapr_irq_dual
;
3348 error_setg(errp
, "Bad value for \"ic-mode\" property");
3352 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3354 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3356 return g_strdup(spapr
->host_model
);
3359 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3361 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3363 g_free(spapr
->host_model
);
3364 spapr
->host_model
= g_strdup(value
);
3367 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3369 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3371 return g_strdup(spapr
->host_serial
);
3374 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3376 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3378 g_free(spapr
->host_serial
);
3379 spapr
->host_serial
= g_strdup(value
);
3382 static void spapr_instance_init(Object
*obj
)
3384 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3385 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3386 MachineState
*ms
= MACHINE(spapr
);
3387 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
3390 * NVDIMM support went live in 5.1 without considering that, in
3391 * other archs, the user needs to enable NVDIMM support with the
3392 * 'nvdimm' machine option and the default behavior is NVDIMM
3393 * support disabled. It is too late to roll back to the standard
3394 * behavior without breaking 5.1 guests.
3396 if (mc
->nvdimm_supported
) {
3397 ms
->nvdimms_state
->is_enabled
= true;
3400 spapr
->htab_fd
= -1;
3401 spapr
->use_hotplug_event_source
= true;
3402 spapr
->kvm_type
= g_strdup(DEFAULT_KVM_TYPE
);
3403 object_property_add_str(obj
, "kvm-type",
3404 spapr_get_kvm_type
, spapr_set_kvm_type
);
3405 object_property_set_description(obj
, "kvm-type",
3406 "Specifies the KVM virtualization mode (auto,"
3407 " hv, pr). Defaults to 'auto'. This mode will use"
3408 " any available KVM module loaded in the host,"
3409 " where kvm_hv takes precedence if both kvm_hv and"
3410 " kvm_pr are loaded.");
3411 object_property_add_bool(obj
, "modern-hotplug-events",
3412 spapr_get_modern_hotplug_events
,
3413 spapr_set_modern_hotplug_events
);
3414 object_property_set_description(obj
, "modern-hotplug-events",
3415 "Use dedicated hotplug event mechanism in"
3416 " place of standard EPOW events when possible"
3417 " (required for memory hot-unplug support)");
3418 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3419 "Maximum permitted CPU compatibility mode");
3421 object_property_add_str(obj
, "resize-hpt",
3422 spapr_get_resize_hpt
, spapr_set_resize_hpt
);
3423 object_property_set_description(obj
, "resize-hpt",
3424 "Resizing of the Hash Page Table (enabled, disabled, required)");
3425 object_property_add_uint32_ptr(obj
, "vsmt",
3426 &spapr
->vsmt
, OBJ_PROP_FLAG_READWRITE
);
3427 object_property_set_description(obj
, "vsmt",
3428 "Virtual SMT: KVM behaves as if this were"
3429 " the host's SMT mode");
3431 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3432 spapr_get_msix_emulation
, NULL
);
3434 object_property_add_uint64_ptr(obj
, "kernel-addr",
3435 &spapr
->kernel_addr
, OBJ_PROP_FLAG_READWRITE
);
3436 object_property_set_description(obj
, "kernel-addr",
3437 stringify(KERNEL_LOAD_ADDR
)
3438 " for -kernel is the default");
3439 spapr
->kernel_addr
= KERNEL_LOAD_ADDR
;
3441 object_property_add_bool(obj
, "x-vof", spapr_get_vof
, spapr_set_vof
);
3442 object_property_set_description(obj
, "x-vof",
3443 "Enable Virtual Open Firmware (experimental)");
3445 /* The machine class defines the default interrupt controller mode */
3446 spapr
->irq
= smc
->irq
;
3447 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3449 object_property_set_description(obj
, "ic-mode",
3450 "Specifies the interrupt controller mode (xics, xive, dual)");
3452 object_property_add_str(obj
, "host-model",
3453 spapr_get_host_model
, spapr_set_host_model
);
3454 object_property_set_description(obj
, "host-model",
3455 "Host model to advertise in guest device tree");
3456 object_property_add_str(obj
, "host-serial",
3457 spapr_get_host_serial
, spapr_set_host_serial
);
3458 object_property_set_description(obj
, "host-serial",
3459 "Host serial number to advertise in guest device tree");
3462 static void spapr_machine_finalizefn(Object
*obj
)
3464 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3466 g_free(spapr
->kvm_type
);
3469 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3471 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3472 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3473 CPUPPCState
*env
= &cpu
->env
;
3475 cpu_synchronize_state(cs
);
3476 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
3477 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3478 uint64_t rtas_addr
, addr
;
3480 /* get rtas addr from fdt */
3481 rtas_addr
= spapr_get_rtas_addr();
3483 qemu_system_guest_panicked(NULL
);
3487 addr
= rtas_addr
+ RTAS_ERROR_LOG_MAX
+ cs
->cpu_index
* sizeof(uint64_t)*2;
3488 stq_be_phys(&address_space_memory
, addr
, env
->gpr
[3]);
3489 stq_be_phys(&address_space_memory
, addr
+ sizeof(uint64_t), 0);
3492 ppc_cpu_do_system_reset(cs
);
3493 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3494 env
->nip
= spapr
->fwnmi_system_reset_addr
;
3498 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3503 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3507 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3508 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3513 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3514 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3516 *fdt_start_offset
= spapr_dt_memory_node(spapr
, fdt
, node
, addr
,
3517 SPAPR_MEMORY_BLOCK_SIZE
);
3521 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3522 bool dedicated_hp_event_source
)
3525 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3527 uint64_t addr
= addr_start
;
3528 bool hotplugged
= spapr_drc_hotplugged(dev
);
3530 for (i
= 0; i
< nr_lmbs
; i
++) {
3531 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3532 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3536 * memory_device_get_free_addr() provided a range of free addresses
3537 * that doesn't overlap with any existing mapping at pre-plug. The
3538 * corresponding LMB DRCs are thus assumed to be all attachable.
3540 spapr_drc_attach(drc
, dev
);
3542 spapr_drc_reset(drc
);
3544 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3546 /* send hotplug notification to the
3547 * guest only in case of hotplugged memory
3550 if (dedicated_hp_event_source
) {
3551 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3552 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3554 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3556 spapr_drc_index(drc
));
3558 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3564 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3566 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3567 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3568 uint64_t size
, addr
;
3570 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3572 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3574 pc_dimm_plug(dimm
, MACHINE(ms
));
3577 addr
= object_property_get_uint(OBJECT(dimm
),
3578 PC_DIMM_ADDR_PROP
, &error_abort
);
3579 spapr_add_lmbs(dev
, addr
, size
,
3580 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
));
3582 slot
= object_property_get_int(OBJECT(dimm
),
3583 PC_DIMM_SLOT_PROP
, &error_abort
);
3584 /* We should have valid slot number at this point */
3585 g_assert(slot
>= 0);
3586 spapr_add_nvdimm(dev
, slot
);
3590 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3593 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3594 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3595 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3596 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3597 Error
*local_err
= NULL
;
3602 if (!smc
->dr_lmb_enabled
) {
3603 error_setg(errp
, "Memory hotplug not supported for this machine");
3607 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3609 error_propagate(errp
, local_err
);
3614 if (!spapr_nvdimm_validate(hotplug_dev
, NVDIMM(dev
), size
, errp
)) {
3617 } else if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3618 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3619 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3623 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3625 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3626 if (!spapr_check_pagesize(spapr
, pagesize
, errp
)) {
3630 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3633 struct SpaprDimmState
{
3636 QTAILQ_ENTRY(SpaprDimmState
) next
;
3639 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3642 SpaprDimmState
*dimm_state
= NULL
;
3644 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3645 if (dimm_state
->dimm
== dimm
) {
3652 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3656 SpaprDimmState
*ds
= NULL
;
3659 * If this request is for a DIMM whose removal had failed earlier
3660 * (due to guest's refusal to remove the LMBs), we would have this
3661 * dimm already in the pending_dimm_unplugs list. In that
3662 * case don't add again.
3664 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3666 ds
= g_new0(SpaprDimmState
, 1);
3667 ds
->nr_lmbs
= nr_lmbs
;
3669 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3674 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3675 SpaprDimmState
*dimm_state
)
3677 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3681 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3685 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3687 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3688 uint32_t avail_lmbs
= 0;
3689 uint64_t addr_start
, addr
;
3692 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3696 for (i
= 0; i
< nr_lmbs
; i
++) {
3697 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3698 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3703 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3706 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3709 void spapr_memory_unplug_rollback(SpaprMachineState
*spapr
, DeviceState
*dev
)
3715 uint64_t size
, addr_start
, addr
;
3716 g_autofree
char *qapi_error
= NULL
;
3723 dimm
= PC_DIMM(dev
);
3724 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3727 * 'ds == NULL' would mean that the DIMM doesn't have a pending
3728 * unplug state, but one of its DRC is marked as unplug_requested.
3729 * This is bad and weird enough to g_assert() out.
3733 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3735 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3736 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3738 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3742 for (i
= 0; i
< nr_lmbs
; i
++) {
3743 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3744 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3747 drc
->unplug_requested
= false;
3748 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3752 * Tell QAPI that something happened and the memory
3753 * hotunplug wasn't successful. Keep sending
3754 * MEM_UNPLUG_ERROR even while sending
3755 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of
3756 * MEM_UNPLUG_ERROR is due.
3758 qapi_error
= g_strdup_printf("Memory hotunplug rejected by the guest "
3759 "for device %s", dev
->id
);
3761 qapi_event_send_mem_unplug_error(dev
->id
? : "", qapi_error
);
3763 qapi_event_send_device_unplug_guest_error(dev
->id
,
3764 dev
->canonical_path
);
3767 /* Callback to be called during DRC release. */
3768 void spapr_lmb_release(DeviceState
*dev
)
3770 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3771 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3772 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3774 /* This information will get lost if a migration occurs
3775 * during the unplug process. In this case recover it. */
3777 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3779 /* The DRC being examined by the caller at least must be counted */
3780 g_assert(ds
->nr_lmbs
);
3783 if (--ds
->nr_lmbs
) {
3788 * Now that all the LMBs have been removed by the guest, call the
3789 * unplug handler chain. This can never fail.
3791 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3792 object_unparent(OBJECT(dev
));
3795 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3797 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3798 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3800 /* We really shouldn't get this far without anything to unplug */
3803 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3804 qdev_unrealize(dev
);
3805 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3808 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3809 DeviceState
*dev
, Error
**errp
)
3811 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3812 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3814 uint64_t size
, addr_start
, addr
;
3818 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
3819 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
3823 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3824 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3826 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3830 * An existing pending dimm state for this DIMM means that there is an
3831 * unplug operation in progress, waiting for the spapr_lmb_release
3832 * callback to complete the job (BQL can't cover that far). In this case,
3833 * bail out to avoid detaching DRCs that were already released.
3835 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3836 error_setg(errp
, "Memory unplug already in progress for device %s",
3841 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3844 for (i
= 0; i
< nr_lmbs
; i
++) {
3845 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3846 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3849 spapr_drc_unplug_request(drc
);
3850 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3853 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3854 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3855 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3856 nr_lmbs
, spapr_drc_index(drc
));
3859 /* Callback to be called during DRC release. */
3860 void spapr_core_release(DeviceState
*dev
)
3862 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3864 /* Call the unplug handler chain. This can never fail. */
3865 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3866 object_unparent(OBJECT(dev
));
3869 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3871 MachineState
*ms
= MACHINE(hotplug_dev
);
3872 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3873 CPUCore
*cc
= CPU_CORE(dev
);
3874 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3876 if (smc
->pre_2_10_has_unused_icps
) {
3877 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3880 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3881 CPUState
*cs
= CPU(sc
->threads
[i
]);
3883 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3888 core_slot
->cpu
= NULL
;
3889 qdev_unrealize(dev
);
3893 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3896 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3899 CPUCore
*cc
= CPU_CORE(dev
);
3901 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3902 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3907 error_setg(errp
, "Boot CPU core may not be unplugged");
3911 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3912 spapr_vcpu_id(spapr
, cc
->core_id
));
3915 if (!spapr_drc_unplug_requested(drc
)) {
3916 spapr_drc_unplug_request(drc
);
3920 * spapr_hotplug_req_remove_by_index is left unguarded, out of the
3921 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ
3922 * pulses removing the same CPU. Otherwise, in an failed hotunplug
3923 * attempt (e.g. the kernel will refuse to remove the last online
3924 * CPU), we will never attempt it again because unplug_requested
3925 * will still be 'true' in that case.
3927 spapr_hotplug_req_remove_by_index(drc
);
3930 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3931 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3933 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3934 CPUState
*cs
= CPU(core
->threads
[0]);
3935 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3936 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3937 int id
= spapr_get_vcpu_id(cpu
);
3938 g_autofree
char *nodename
= NULL
;
3941 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3942 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3944 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
3947 * spapr_dt_cpu() does not fill the 'name' property in the
3948 * CPU node. The function is called during boot process, before
3949 * and after CAS, and overwriting the 'name' property written
3950 * by SLOF is not allowed.
3952 * Write it manually after spapr_dt_cpu(). This makes the hotplug
3953 * CPUs more compatible with the coldplugged ones, which have
3954 * the 'name' property. Linux Kernel also relies on this
3955 * property to identify CPU nodes.
3957 _FDT((fdt_setprop_string(fdt
, offset
, "name", nodename
)));
3959 *fdt_start_offset
= offset
;
3963 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3965 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3966 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3967 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3968 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3969 CPUCore
*cc
= CPU_CORE(dev
);
3972 CPUArchId
*core_slot
;
3974 bool hotplugged
= spapr_drc_hotplugged(dev
);
3977 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3978 g_assert(core_slot
); /* Already checked in spapr_core_pre_plug() */
3980 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3981 spapr_vcpu_id(spapr
, cc
->core_id
));
3983 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3987 * spapr_core_pre_plug() already buys us this is a brand new
3988 * core being plugged into a free slot. Nothing should already
3989 * be attached to the corresponding DRC.
3991 spapr_drc_attach(drc
, dev
);
3995 * Send hotplug notification interrupt to the guest only
3996 * in case of hotplugged CPUs.
3998 spapr_hotplug_req_add_by_index(drc
);
4000 spapr_drc_reset(drc
);
4004 core_slot
->cpu
= OBJECT(dev
);
4007 * Set compatibility mode to match the boot CPU, which was either set
4008 * by the machine reset code or by CAS. This really shouldn't fail at
4012 for (i
= 0; i
< cc
->nr_threads
; i
++) {
4013 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
4018 if (smc
->pre_2_10_has_unused_icps
) {
4019 for (i
= 0; i
< cc
->nr_threads
; i
++) {
4020 cs
= CPU(core
->threads
[i
]);
4021 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
4026 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4029 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
4030 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
4031 CPUCore
*cc
= CPU_CORE(dev
);
4032 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4033 const char *type
= object_get_typename(OBJECT(dev
));
4034 CPUArchId
*core_slot
;
4036 unsigned int smp_threads
= machine
->smp
.threads
;
4038 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
4039 error_setg(errp
, "CPU hotplug not supported for this machine");
4043 if (strcmp(base_core_type
, type
)) {
4044 error_setg(errp
, "CPU core type should be %s", base_core_type
);
4048 if (cc
->core_id
% smp_threads
) {
4049 error_setg(errp
, "invalid core id %d", cc
->core_id
);
4054 * In general we should have homogeneous threads-per-core, but old
4055 * (pre hotplug support) machine types allow the last core to have
4056 * reduced threads as a compatibility hack for when we allowed
4057 * total vcpus not a multiple of threads-per-core.
4059 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
4060 error_setg(errp
, "invalid nr-threads %d, must be %d", cc
->nr_threads
,
4065 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
4067 error_setg(errp
, "core id %d out of range", cc
->core_id
);
4071 if (core_slot
->cpu
) {
4072 error_setg(errp
, "core %d already populated", cc
->core_id
);
4076 numa_cpu_pre_plug(core_slot
, dev
, errp
);
4079 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
4080 void *fdt
, int *fdt_start_offset
, Error
**errp
)
4082 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
4085 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
4086 if (intc_phandle
<= 0) {
4090 if (spapr_dt_phb(spapr
, sphb
, intc_phandle
, fdt
, fdt_start_offset
)) {
4091 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
4095 /* generally SLOF creates these, for hotplug it's up to QEMU */
4096 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
4101 static bool spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4104 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4105 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4106 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4107 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
4110 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
4111 error_setg(errp
, "PHB hotplug not supported for this machine");
4115 if (sphb
->index
== (uint32_t)-1) {
4116 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
4120 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4121 if (drc
&& drc
->dev
) {
4122 error_setg(errp
, "PHB %d already attached", sphb
->index
);
4127 * This will check that sphb->index doesn't exceed the maximum number of
4128 * PHBs for the current machine type.
4131 smc
->phb_placement(spapr
, sphb
->index
,
4132 &sphb
->buid
, &sphb
->io_win_addr
,
4133 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
4134 windows_supported
, sphb
->dma_liobn
,
4138 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4140 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4141 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
4142 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4144 bool hotplugged
= spapr_drc_hotplugged(dev
);
4146 if (!smc
->dr_phb_enabled
) {
4150 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4151 /* hotplug hooks should check it's enabled before getting this far */
4154 /* spapr_phb_pre_plug() already checked the DRC is attachable */
4155 spapr_drc_attach(drc
, dev
);
4158 spapr_hotplug_req_add_by_index(drc
);
4160 spapr_drc_reset(drc
);
4164 void spapr_phb_release(DeviceState
*dev
)
4166 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
4168 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
4169 object_unparent(OBJECT(dev
));
4172 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4174 qdev_unrealize(dev
);
4177 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4178 DeviceState
*dev
, Error
**errp
)
4180 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4183 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4186 if (!spapr_drc_unplug_requested(drc
)) {
4187 spapr_drc_unplug_request(drc
);
4188 spapr_hotplug_req_remove_by_index(drc
);
4191 "PCI Host Bridge unplug already in progress for device %s",
4197 bool spapr_tpm_proxy_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4200 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4202 if (spapr
->tpm_proxy
!= NULL
) {
4203 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4210 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4212 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4213 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4215 /* Already checked in spapr_tpm_proxy_pre_plug() */
4216 g_assert(spapr
->tpm_proxy
== NULL
);
4218 spapr
->tpm_proxy
= tpm_proxy
;
4221 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4223 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4225 qdev_unrealize(dev
);
4226 object_unparent(OBJECT(dev
));
4227 spapr
->tpm_proxy
= NULL
;
4230 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4231 DeviceState
*dev
, Error
**errp
)
4233 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4234 spapr_memory_plug(hotplug_dev
, dev
);
4235 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4236 spapr_core_plug(hotplug_dev
, dev
);
4237 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4238 spapr_phb_plug(hotplug_dev
, dev
);
4239 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4240 spapr_tpm_proxy_plug(hotplug_dev
, dev
);
4244 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4245 DeviceState
*dev
, Error
**errp
)
4247 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4248 spapr_memory_unplug(hotplug_dev
, dev
);
4249 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4250 spapr_core_unplug(hotplug_dev
, dev
);
4251 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4252 spapr_phb_unplug(hotplug_dev
, dev
);
4253 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4254 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4258 bool spapr_memory_hot_unplug_supported(SpaprMachineState
*spapr
)
4260 return spapr_ovec_test(spapr
->ov5_cas
, OV5_HP_EVT
) ||
4262 * CAS will process all pending unplug requests.
4264 * HACK: a guest could theoretically have cleared all bits in OV5,
4265 * but none of the guests we care for do.
4267 spapr_ovec_empty(spapr
->ov5_cas
);
4270 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4271 DeviceState
*dev
, Error
**errp
)
4273 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4274 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4275 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4277 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4278 if (spapr_memory_hot_unplug_supported(sms
)) {
4279 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4281 error_setg(errp
, "Memory hot unplug not supported for this guest");
4283 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4284 if (!mc
->has_hotpluggable_cpus
) {
4285 error_setg(errp
, "CPU hot unplug not supported on this machine");
4288 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4289 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4290 if (!smc
->dr_phb_enabled
) {
4291 error_setg(errp
, "PHB hot unplug not supported on this machine");
4294 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4295 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4296 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4300 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4301 DeviceState
*dev
, Error
**errp
)
4303 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4304 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4305 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4306 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4307 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4308 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4309 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4310 spapr_tpm_proxy_pre_plug(hotplug_dev
, dev
, errp
);
4314 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4317 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4318 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4319 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4320 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4321 return HOTPLUG_HANDLER(machine
);
4323 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4324 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4325 PCIBus
*root
= pci_device_root_bus(pcidev
);
4326 SpaprPhbState
*phb
=
4327 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4328 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4331 return HOTPLUG_HANDLER(phb
);
4337 static CpuInstanceProperties
4338 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4340 CPUArchId
*core_slot
;
4341 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4343 /* make sure possible_cpu are intialized */
4344 mc
->possible_cpu_arch_ids(machine
);
4345 /* get CPU core slot containing thread that matches cpu_index */
4346 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4348 return core_slot
->props
;
4351 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4353 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4356 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4359 unsigned int smp_threads
= machine
->smp
.threads
;
4360 unsigned int smp_cpus
= machine
->smp
.cpus
;
4361 const char *core_type
;
4362 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4363 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4365 if (!mc
->has_hotpluggable_cpus
) {
4366 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4368 if (machine
->possible_cpus
) {
4369 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4370 return machine
->possible_cpus
;
4373 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4375 error_report("Unable to find sPAPR CPU Core definition");
4379 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4380 sizeof(CPUArchId
) * spapr_max_cores
);
4381 machine
->possible_cpus
->len
= spapr_max_cores
;
4382 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4383 int core_id
= i
* smp_threads
;
4385 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4386 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4387 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4388 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4389 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4391 return machine
->possible_cpus
;
4394 static bool spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4395 uint64_t *buid
, hwaddr
*pio
,
4396 hwaddr
*mmio32
, hwaddr
*mmio64
,
4397 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
4400 * New-style PHB window placement.
4402 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4403 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4406 * Some guest kernels can't work with MMIO windows above 1<<46
4407 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4409 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4410 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4411 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4412 * 1TiB 64-bit MMIO windows for each PHB.
4414 const uint64_t base_buid
= 0x800000020000000ULL
;
4417 /* Sanity check natural alignments */
4418 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4419 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4420 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4421 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4422 /* Sanity check bounds */
4423 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4424 SPAPR_PCI_MEM32_WIN_SIZE
);
4425 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4426 SPAPR_PCI_MEM64_WIN_SIZE
);
4428 if (index
>= SPAPR_MAX_PHBS
) {
4429 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4430 SPAPR_MAX_PHBS
- 1);
4434 *buid
= base_buid
+ index
;
4435 for (i
= 0; i
< n_dma
; ++i
) {
4436 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4439 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4440 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4441 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4445 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4447 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4449 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4452 static void spapr_ics_resend(XICSFabric
*dev
)
4454 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4456 ics_resend(spapr
->ics
);
4459 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4461 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4463 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4466 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4469 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4471 spapr_irq_print_info(spapr
, mon
);
4472 monitor_printf(mon
, "irqchip: %s\n",
4473 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4477 * This is a XIVE only operation
4479 static int spapr_match_nvt(XiveFabric
*xfb
, uint8_t format
,
4480 uint8_t nvt_blk
, uint32_t nvt_idx
,
4481 bool cam_ignore
, uint8_t priority
,
4482 uint32_t logic_serv
, XiveTCTXMatch
*match
)
4484 SpaprMachineState
*spapr
= SPAPR_MACHINE(xfb
);
4485 XivePresenter
*xptr
= XIVE_PRESENTER(spapr
->active_intc
);
4486 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
4489 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
4490 priority
, logic_serv
, match
);
4496 * When we implement the save and restore of the thread interrupt
4497 * contexts in the enter/exit CPU handlers of the machine and the
4498 * escalations in QEMU, we should be able to handle non dispatched
4501 * Until this is done, the sPAPR machine should find at least one
4502 * matching context always.
4505 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is not dispatched\n",
4512 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4514 return cpu
->vcpu_id
;
4517 bool spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4519 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4520 MachineState
*ms
= MACHINE(spapr
);
4523 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4525 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4526 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4527 error_append_hint(errp
, "Adjust the number of cpus to %d "
4528 "or try to raise the number of threads per core\n",
4529 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4533 cpu
->vcpu_id
= vcpu_id
;
4537 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4542 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4544 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4552 static bool spapr_cpu_in_nested(PowerPCCPU
*cpu
)
4554 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4556 return spapr_cpu
->in_nested
;
4559 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4561 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4563 /* These are only called by TCG, KVM maintains dispatch state */
4565 spapr_cpu
->prod
= false;
4566 if (spapr_cpu
->vpa_addr
) {
4567 CPUState
*cs
= CPU(cpu
);
4570 dispatch
= ldl_be_phys(cs
->as
,
4571 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4573 if ((dispatch
& 1) != 0) {
4574 qemu_log_mask(LOG_GUEST_ERROR
,
4575 "VPA: incorrect dispatch counter value for "
4576 "dispatched partition %u, correcting.\n", dispatch
);
4580 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4584 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4586 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4588 if (spapr_cpu
->vpa_addr
) {
4589 CPUState
*cs
= CPU(cpu
);
4592 dispatch
= ldl_be_phys(cs
->as
,
4593 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4595 if ((dispatch
& 1) != 1) {
4596 qemu_log_mask(LOG_GUEST_ERROR
,
4597 "VPA: incorrect dispatch counter value for "
4598 "preempted partition %u, correcting.\n", dispatch
);
4602 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4606 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4608 MachineClass
*mc
= MACHINE_CLASS(oc
);
4609 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4610 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4611 NMIClass
*nc
= NMI_CLASS(oc
);
4612 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4613 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4614 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4615 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4616 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
4617 VofMachineIfClass
*vmc
= VOF_MACHINE_CLASS(oc
);
4619 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4620 mc
->ignore_boot_device_suffixes
= true;
4623 * We set up the default / latest behaviour here. The class_init
4624 * functions for the specific versioned machine types can override
4625 * these details for backwards compatibility
4627 mc
->init
= spapr_machine_init
;
4628 mc
->reset
= spapr_machine_reset
;
4629 mc
->block_default_type
= IF_SCSI
;
4632 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values
4633 * should be limited by the host capability instead of hardcoded.
4634 * max_cpus for KVM guests will be checked in kvm_init(), and TCG
4635 * guests are welcome to have as many CPUs as the host are capable
4638 mc
->max_cpus
= INT32_MAX
;
4640 mc
->no_parallel
= 1;
4641 mc
->default_boot_order
= "";
4642 mc
->default_ram_size
= 512 * MiB
;
4643 mc
->default_ram_id
= "ppc_spapr.ram";
4644 mc
->default_display
= "std";
4645 mc
->kvm_type
= spapr_kvm_type
;
4646 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4647 mc
->pci_allow_0_address
= true;
4648 assert(!mc
->get_hotplug_handler
);
4649 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4650 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4651 hc
->plug
= spapr_machine_device_plug
;
4652 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4653 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4654 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4655 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4656 hc
->unplug
= spapr_machine_device_unplug
;
4658 smc
->dr_lmb_enabled
= true;
4659 smc
->update_dt_enabled
= true;
4660 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.2");
4661 mc
->has_hotpluggable_cpus
= true;
4662 mc
->nvdimm_supported
= true;
4663 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4664 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4665 nc
->nmi_monitor_handler
= spapr_nmi
;
4666 smc
->phb_placement
= spapr_phb_placement
;
4667 vhc
->cpu_in_nested
= spapr_cpu_in_nested
;
4668 vhc
->deliver_hv_excp
= spapr_exit_nested
;
4669 vhc
->hypercall
= emulate_spapr_hypercall
;
4670 vhc
->hpt_mask
= spapr_hpt_mask
;
4671 vhc
->map_hptes
= spapr_map_hptes
;
4672 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4673 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4674 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4675 vhc
->get_pate
= spapr_get_pate
;
4676 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4677 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4678 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4679 xic
->ics_get
= spapr_ics_get
;
4680 xic
->ics_resend
= spapr_ics_resend
;
4681 xic
->icp_get
= spapr_icp_get
;
4682 ispc
->print_info
= spapr_pic_print_info
;
4683 /* Force NUMA node memory size to be a multiple of
4684 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4685 * in which LMBs are represented and hot-added
4687 mc
->numa_mem_align_shift
= 28;
4688 mc
->auto_enable_numa
= true;
4690 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4691 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4692 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4693 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4694 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4695 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4696 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4697 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4698 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4699 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_ON
;
4700 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_ON
;
4701 smc
->default_caps
.caps
[SPAPR_CAP_RPT_INVALIDATE
] = SPAPR_CAP_OFF
;
4704 * This cap specifies whether the AIL 3 mode for
4705 * H_SET_RESOURCE is supported. The default is modified
4706 * by default_caps_with_cpu().
4708 smc
->default_caps
.caps
[SPAPR_CAP_AIL_MODE_3
] = SPAPR_CAP_ON
;
4709 spapr_caps_add_properties(smc
);
4710 smc
->irq
= &spapr_irq_dual
;
4711 smc
->dr_phb_enabled
= true;
4712 smc
->linux_pci_probe
= true;
4713 smc
->smp_threads_vsmt
= true;
4714 smc
->nr_xirqs
= SPAPR_NR_XIRQS
;
4715 xfc
->match_nvt
= spapr_match_nvt
;
4716 vmc
->client_architecture_support
= spapr_vof_client_architecture_support
;
4717 vmc
->quiesce
= spapr_vof_quiesce
;
4718 vmc
->setprop
= spapr_vof_setprop
;
4721 static const TypeInfo spapr_machine_info
= {
4722 .name
= TYPE_SPAPR_MACHINE
,
4723 .parent
= TYPE_MACHINE
,
4725 .instance_size
= sizeof(SpaprMachineState
),
4726 .instance_init
= spapr_instance_init
,
4727 .instance_finalize
= spapr_machine_finalizefn
,
4728 .class_size
= sizeof(SpaprMachineClass
),
4729 .class_init
= spapr_machine_class_init
,
4730 .interfaces
= (InterfaceInfo
[]) {
4731 { TYPE_FW_PATH_PROVIDER
},
4733 { TYPE_HOTPLUG_HANDLER
},
4734 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4735 { TYPE_XICS_FABRIC
},
4736 { TYPE_INTERRUPT_STATS_PROVIDER
},
4737 { TYPE_XIVE_FABRIC
},
4738 { TYPE_VOF_MACHINE_IF
},
4743 static void spapr_machine_latest_class_options(MachineClass
*mc
)
4745 mc
->alias
= "pseries";
4746 mc
->is_default
= true;
4749 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4750 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4753 MachineClass *mc = MACHINE_CLASS(oc); \
4754 spapr_machine_##suffix##_class_options(mc); \
4756 spapr_machine_latest_class_options(mc); \
4759 static const TypeInfo spapr_machine_##suffix##_info = { \
4760 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4761 .parent = TYPE_SPAPR_MACHINE, \
4762 .class_init = spapr_machine_##suffix##_class_init, \
4764 static void spapr_machine_register_##suffix(void) \
4766 type_register(&spapr_machine_##suffix##_info); \
4768 type_init(spapr_machine_register_##suffix)
4773 static void spapr_machine_8_2_class_options(MachineClass
*mc
)
4775 /* Defaults for the latest behaviour inherited from the base class */
4778 DEFINE_SPAPR_MACHINE(8_2
, "8.2", true);
4783 static void spapr_machine_8_1_class_options(MachineClass
*mc
)
4785 spapr_machine_8_2_class_options(mc
);
4786 compat_props_add(mc
->compat_props
, hw_compat_8_1
, hw_compat_8_1_len
);
4789 DEFINE_SPAPR_MACHINE(8_1
, "8.1", false);
4794 static void spapr_machine_8_0_class_options(MachineClass
*mc
)
4796 spapr_machine_8_1_class_options(mc
);
4797 compat_props_add(mc
->compat_props
, hw_compat_8_0
, hw_compat_8_0_len
);
4800 DEFINE_SPAPR_MACHINE(8_0
, "8.0", false);
4805 static void spapr_machine_7_2_class_options(MachineClass
*mc
)
4807 spapr_machine_8_0_class_options(mc
);
4808 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
4811 DEFINE_SPAPR_MACHINE(7_2
, "7.2", false);
4816 static void spapr_machine_7_1_class_options(MachineClass
*mc
)
4818 spapr_machine_7_2_class_options(mc
);
4819 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
4822 DEFINE_SPAPR_MACHINE(7_1
, "7.1", false);
4827 static void spapr_machine_7_0_class_options(MachineClass
*mc
)
4829 spapr_machine_7_1_class_options(mc
);
4830 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
4833 DEFINE_SPAPR_MACHINE(7_0
, "7.0", false);
4838 static void spapr_machine_6_2_class_options(MachineClass
*mc
)
4840 spapr_machine_7_0_class_options(mc
);
4841 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
4844 DEFINE_SPAPR_MACHINE(6_2
, "6.2", false);
4849 static void spapr_machine_6_1_class_options(MachineClass
*mc
)
4851 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4853 spapr_machine_6_2_class_options(mc
);
4854 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
4855 smc
->pre_6_2_numa_affinity
= true;
4856 mc
->smp_props
.prefer_sockets
= true;
4859 DEFINE_SPAPR_MACHINE(6_1
, "6.1", false);
4864 static void spapr_machine_6_0_class_options(MachineClass
*mc
)
4866 spapr_machine_6_1_class_options(mc
);
4867 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
4870 DEFINE_SPAPR_MACHINE(6_0
, "6.0", false);
4875 static void spapr_machine_5_2_class_options(MachineClass
*mc
)
4877 spapr_machine_6_0_class_options(mc
);
4878 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
4881 DEFINE_SPAPR_MACHINE(5_2
, "5.2", false);
4886 static void spapr_machine_5_1_class_options(MachineClass
*mc
)
4888 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4890 spapr_machine_5_2_class_options(mc
);
4891 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
4892 smc
->pre_5_2_numa_associativity
= true;
4895 DEFINE_SPAPR_MACHINE(5_1
, "5.1", false);
4900 static void spapr_machine_5_0_class_options(MachineClass
*mc
)
4902 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4903 static GlobalProperty compat
[] = {
4904 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-5.1-associativity", "on" },
4907 spapr_machine_5_1_class_options(mc
);
4908 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
4909 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4910 mc
->numa_mem_supported
= true;
4911 smc
->pre_5_1_assoc_refpoints
= true;
4914 DEFINE_SPAPR_MACHINE(5_0
, "5.0", false);
4919 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4921 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4923 spapr_machine_5_0_class_options(mc
);
4924 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
4925 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4926 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_OFF
;
4927 smc
->rma_limit
= 16 * GiB
;
4928 mc
->nvdimm_supported
= false;
4931 DEFINE_SPAPR_MACHINE(4_2
, "4.2", false);
4936 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4938 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4939 static GlobalProperty compat
[] = {
4940 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4941 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4944 spapr_machine_4_2_class_options(mc
);
4945 smc
->linux_pci_probe
= false;
4946 smc
->smp_threads_vsmt
= false;
4947 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4948 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4951 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4956 static bool phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4957 uint64_t *buid
, hwaddr
*pio
,
4958 hwaddr
*mmio32
, hwaddr
*mmio64
,
4959 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
4961 if (!spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
,
4967 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4969 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4971 spapr_machine_4_1_class_options(mc
);
4972 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4973 smc
->phb_placement
= phb_placement_4_0
;
4974 smc
->irq
= &spapr_irq_xics
;
4975 smc
->pre_4_1_migration
= true;
4978 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4983 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4985 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4987 spapr_machine_4_0_class_options(mc
);
4988 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4990 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4991 smc
->update_dt_enabled
= false;
4992 smc
->dr_phb_enabled
= false;
4993 smc
->broken_host_serial_model
= true;
4994 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4995 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4996 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4997 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
5000 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
5006 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
5008 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5010 spapr_machine_3_1_class_options(mc
);
5011 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
5013 smc
->legacy_irq_allocation
= true;
5014 smc
->nr_xirqs
= 0x400;
5015 smc
->irq
= &spapr_irq_xics_legacy
;
5018 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
5023 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
5025 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5026 static GlobalProperty compat
[] = {
5027 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
5028 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
5031 spapr_machine_3_0_class_options(mc
);
5032 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
5033 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5035 /* We depend on kvm_enabled() to choose a default value for the
5036 * hpt-max-page-size capability. Of course we can't do it here
5037 * because this is too early and the HW accelerator isn't initialzed
5038 * yet. Postpone this to machine init (see default_caps_with_cpu()).
5040 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
5043 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
5045 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
5047 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5049 spapr_machine_2_12_class_options(mc
);
5050 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
5051 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
5052 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
5055 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
5061 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
5063 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5065 spapr_machine_2_12_class_options(mc
);
5066 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
5067 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
5070 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
5076 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
5078 spapr_machine_2_11_class_options(mc
);
5079 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
5082 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
5088 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
5090 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5091 static GlobalProperty compat
[] = {
5092 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
5095 spapr_machine_2_10_class_options(mc
);
5096 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
5097 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5098 smc
->pre_2_10_has_unused_icps
= true;
5099 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
5102 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
5108 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
5110 static GlobalProperty compat
[] = {
5111 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
5114 spapr_machine_2_9_class_options(mc
);
5115 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
5116 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5117 mc
->numa_mem_align_shift
= 23;
5120 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
5126 static bool phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
5127 uint64_t *buid
, hwaddr
*pio
,
5128 hwaddr
*mmio32
, hwaddr
*mmio64
,
5129 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
5131 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
5132 const uint64_t base_buid
= 0x800000020000000ULL
;
5133 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
5134 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
5135 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
5136 const uint32_t max_index
= 255;
5137 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
5139 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
5140 hwaddr phb0_base
, phb_base
;
5143 /* Do we have device memory? */
5144 if (MACHINE(spapr
)->device_memory
) {
5145 /* Can't just use maxram_size, because there may be an
5146 * alignment gap between normal and device memory regions
5148 ram_top
= MACHINE(spapr
)->device_memory
->base
+
5149 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
5152 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
5154 if (index
> max_index
) {
5155 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
5160 *buid
= base_buid
+ index
;
5161 for (i
= 0; i
< n_dma
; ++i
) {
5162 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
5165 phb_base
= phb0_base
+ index
* phb_spacing
;
5166 *pio
= phb_base
+ pio_offset
;
5167 *mmio32
= phb_base
+ mmio_offset
;
5169 * We don't set the 64-bit MMIO window, relying on the PHB's
5170 * fallback behaviour of automatically splitting a large "32-bit"
5171 * window into contiguous 32-bit and 64-bit windows
5177 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
5179 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5180 static GlobalProperty compat
[] = {
5181 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
5182 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
5183 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
5184 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
5187 spapr_machine_2_8_class_options(mc
);
5188 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
5189 mc
->default_machine_opts
= "modern-hotplug-events=off";
5190 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
5191 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5192 smc
->phb_placement
= phb_placement_2_7
;
5195 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
5201 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
5203 static GlobalProperty compat
[] = {
5204 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
5207 spapr_machine_2_7_class_options(mc
);
5208 mc
->has_hotpluggable_cpus
= false;
5209 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
5210 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5213 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
5219 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
5221 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5222 static GlobalProperty compat
[] = {
5223 { "spapr-vlan", "use-rx-buffer-pools", "off" },
5226 spapr_machine_2_6_class_options(mc
);
5227 smc
->use_ohci_by_default
= true;
5228 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
5229 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5232 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
5238 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
5240 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
5242 spapr_machine_2_5_class_options(mc
);
5243 smc
->dr_lmb_enabled
= false;
5244 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
5247 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
5253 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
5255 static GlobalProperty compat
[] = {
5256 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
5258 spapr_machine_2_4_class_options(mc
);
5259 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
5260 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5262 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
5268 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
5270 static GlobalProperty compat
[] = {
5271 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
5274 spapr_machine_2_3_class_options(mc
);
5275 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
5276 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
5277 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
5279 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
5285 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
5287 spapr_machine_2_2_class_options(mc
);
5288 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
5290 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
5292 static void spapr_machine_register_types(void)
5294 type_register_static(&spapr_machine_info
);
5297 type_init(spapr_machine_register_types
)