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[mirror_qemu.git] / hw / ppc / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
40 #include "kvm_ppc.h"
41 #include "migration/migration.h"
42 #include "mmu-hash64.h"
43 #include "qom/cpu.h"
44
45 #include "hw/boards.h"
46 #include "hw/ppc/ppc.h"
47 #include "hw/loader.h"
48
49 #include "hw/ppc/fdt.h"
50 #include "hw/ppc/spapr.h"
51 #include "hw/ppc/spapr_vio.h"
52 #include "hw/pci-host/spapr.h"
53 #include "hw/ppc/xics.h"
54 #include "hw/pci/msi.h"
55
56 #include "hw/pci/pci.h"
57 #include "hw/scsi/scsi.h"
58 #include "hw/virtio/virtio-scsi.h"
59
60 #include "exec/address-spaces.h"
61 #include "hw/usb.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "trace.h"
65 #include "hw/nmi.h"
66
67 #include "hw/compat.h"
68 #include "qemu/cutils.h"
69 #include "hw/ppc/spapr_cpu_core.h"
70 #include "qmp-commands.h"
71
72 #include <libfdt.h>
73
74 /* SLOF memory layout:
75 *
76 * SLOF raw image loaded at 0, copies its romfs right below the flat
77 * device-tree, then position SLOF itself 31M below that
78 *
79 * So we set FW_OVERHEAD to 40MB which should account for all of that
80 * and more
81 *
82 * We load our kernel at 4M, leaving space for SLOF initial image
83 */
84 #define FDT_MAX_SIZE 0x100000
85 #define RTAS_MAX_SIZE 0x10000
86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
87 #define FW_MAX_SIZE 0x400000
88 #define FW_FILE_NAME "slof.bin"
89 #define FW_OVERHEAD 0x2800000
90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
91
92 #define MIN_RMA_SLOF 128UL
93
94 #define PHANDLE_XICP 0x00001111
95
96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
97
98 static XICSState *try_create_xics(const char *type, int nr_servers,
99 int nr_irqs, Error **errp)
100 {
101 Error *err = NULL;
102 DeviceState *dev;
103
104 dev = qdev_create(NULL, type);
105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
107 object_property_set_bool(OBJECT(dev), true, "realized", &err);
108 if (err) {
109 error_propagate(errp, err);
110 object_unparent(OBJECT(dev));
111 return NULL;
112 }
113 return XICS_COMMON(dev);
114 }
115
116 static XICSState *xics_system_init(MachineState *machine,
117 int nr_servers, int nr_irqs, Error **errp)
118 {
119 XICSState *xics = NULL;
120
121 if (kvm_enabled()) {
122 Error *err = NULL;
123
124 if (machine_kernel_irqchip_allowed(machine)) {
125 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
126 &err);
127 }
128 if (machine_kernel_irqchip_required(machine) && !xics) {
129 error_reportf_err(err,
130 "kernel_irqchip requested but unavailable: ");
131 } else {
132 error_free(err);
133 }
134 }
135
136 if (!xics) {
137 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
138 }
139
140 return xics;
141 }
142
143 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
144 int smt_threads)
145 {
146 int i, ret = 0;
147 uint32_t servers_prop[smt_threads];
148 uint32_t gservers_prop[smt_threads * 2];
149 int index = ppc_get_vcpu_dt_id(cpu);
150
151 if (cpu->compat_pvr) {
152 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
153 if (ret < 0) {
154 return ret;
155 }
156 }
157
158 /* Build interrupt servers and gservers properties */
159 for (i = 0; i < smt_threads; i++) {
160 servers_prop[i] = cpu_to_be32(index + i);
161 /* Hack, direct the group queues back to cpu 0 */
162 gservers_prop[i*2] = cpu_to_be32(index + i);
163 gservers_prop[i*2 + 1] = 0;
164 }
165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
166 servers_prop, sizeof(servers_prop));
167 if (ret < 0) {
168 return ret;
169 }
170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
171 gservers_prop, sizeof(gservers_prop));
172
173 return ret;
174 }
175
176 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
177 {
178 int ret = 0;
179 PowerPCCPU *cpu = POWERPC_CPU(cs);
180 int index = ppc_get_vcpu_dt_id(cpu);
181 uint32_t associativity[] = {cpu_to_be32(0x5),
182 cpu_to_be32(0x0),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(cs->numa_node),
186 cpu_to_be32(index)};
187
188 /* Advertise NUMA via ibm,associativity */
189 if (nb_numa_nodes > 1) {
190 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
191 sizeof(associativity));
192 }
193
194 return ret;
195 }
196
197 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
198 {
199 int ret = 0, offset, cpus_offset;
200 CPUState *cs;
201 char cpu_model[32];
202 int smt = kvmppc_smt_threads();
203 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
204
205 CPU_FOREACH(cs) {
206 PowerPCCPU *cpu = POWERPC_CPU(cs);
207 DeviceClass *dc = DEVICE_GET_CLASS(cs);
208 int index = ppc_get_vcpu_dt_id(cpu);
209 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
210
211 if ((index % smt) != 0) {
212 continue;
213 }
214
215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
216
217 cpus_offset = fdt_path_offset(fdt, "/cpus");
218 if (cpus_offset < 0) {
219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
220 "cpus");
221 if (cpus_offset < 0) {
222 return cpus_offset;
223 }
224 }
225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
228 if (offset < 0) {
229 return offset;
230 }
231 }
232
233 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
234 pft_size_prop, sizeof(pft_size_prop));
235 if (ret < 0) {
236 return ret;
237 }
238
239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
240 if (ret < 0) {
241 return ret;
242 }
243
244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
245 if (ret < 0) {
246 return ret;
247 }
248 }
249 return ret;
250 }
251
252 static hwaddr spapr_node0_size(void)
253 {
254 MachineState *machine = MACHINE(qdev_get_machine());
255
256 if (nb_numa_nodes) {
257 int i;
258 for (i = 0; i < nb_numa_nodes; ++i) {
259 if (numa_info[i].node_mem) {
260 return MIN(pow2floor(numa_info[i].node_mem),
261 machine->ram_size);
262 }
263 }
264 }
265 return machine->ram_size;
266 }
267
268 static void add_str(GString *s, const gchar *s1)
269 {
270 g_string_append_len(s, s1, strlen(s1) + 1);
271 }
272
273 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
274 hwaddr size)
275 {
276 uint32_t associativity[] = {
277 cpu_to_be32(0x4), /* length */
278 cpu_to_be32(0x0), cpu_to_be32(0x0),
279 cpu_to_be32(0x0), cpu_to_be32(nodeid)
280 };
281 char mem_name[32];
282 uint64_t mem_reg_property[2];
283 int off;
284
285 mem_reg_property[0] = cpu_to_be64(start);
286 mem_reg_property[1] = cpu_to_be64(size);
287
288 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
289 off = fdt_add_subnode(fdt, 0, mem_name);
290 _FDT(off);
291 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
292 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
293 sizeof(mem_reg_property))));
294 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
295 sizeof(associativity))));
296 return off;
297 }
298
299 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
300 {
301 MachineState *machine = MACHINE(spapr);
302 hwaddr mem_start, node_size;
303 int i, nb_nodes = nb_numa_nodes;
304 NodeInfo *nodes = numa_info;
305 NodeInfo ramnode;
306
307 /* No NUMA nodes, assume there is just one node with whole RAM */
308 if (!nb_numa_nodes) {
309 nb_nodes = 1;
310 ramnode.node_mem = machine->ram_size;
311 nodes = &ramnode;
312 }
313
314 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
315 if (!nodes[i].node_mem) {
316 continue;
317 }
318 if (mem_start >= machine->ram_size) {
319 node_size = 0;
320 } else {
321 node_size = nodes[i].node_mem;
322 if (node_size > machine->ram_size - mem_start) {
323 node_size = machine->ram_size - mem_start;
324 }
325 }
326 if (!mem_start) {
327 /* ppc_spapr_init() checks for rma_size <= node0_size already */
328 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
329 mem_start += spapr->rma_size;
330 node_size -= spapr->rma_size;
331 }
332 for ( ; node_size; ) {
333 hwaddr sizetmp = pow2floor(node_size);
334
335 /* mem_start != 0 here */
336 if (ctzl(mem_start) < ctzl(sizetmp)) {
337 sizetmp = 1ULL << ctzl(mem_start);
338 }
339
340 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
341 node_size -= sizetmp;
342 mem_start += sizetmp;
343 }
344 }
345
346 return 0;
347 }
348
349 /* Populate the "ibm,pa-features" property */
350 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
351 {
352 uint8_t pa_features_206[] = { 6, 0,
353 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
354 uint8_t pa_features_207[] = { 24, 0,
355 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
356 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
357 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
358 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
359 uint8_t *pa_features;
360 size_t pa_size;
361
362 switch (env->mmu_model) {
363 case POWERPC_MMU_2_06:
364 case POWERPC_MMU_2_06a:
365 pa_features = pa_features_206;
366 pa_size = sizeof(pa_features_206);
367 break;
368 case POWERPC_MMU_2_07:
369 case POWERPC_MMU_2_07a:
370 pa_features = pa_features_207;
371 pa_size = sizeof(pa_features_207);
372 break;
373 default:
374 return;
375 }
376
377 if (env->ci_large_pages) {
378 /*
379 * Note: we keep CI large pages off by default because a 64K capable
380 * guest provisioned with large pages might otherwise try to map a qemu
381 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
382 * even if that qemu runs on a 4k host.
383 * We dd this bit back here if we are confident this is not an issue
384 */
385 pa_features[3] |= 0x20;
386 }
387 if (kvmppc_has_cap_htm() && pa_size > 24) {
388 pa_features[24] |= 0x80; /* Transactional memory support */
389 }
390
391 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
392 }
393
394 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
395 sPAPRMachineState *spapr)
396 {
397 PowerPCCPU *cpu = POWERPC_CPU(cs);
398 CPUPPCState *env = &cpu->env;
399 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
400 int index = ppc_get_vcpu_dt_id(cpu);
401 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
402 0xffffffff, 0xffffffff};
403 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
404 : SPAPR_TIMEBASE_FREQ;
405 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
406 uint32_t page_sizes_prop[64];
407 size_t page_sizes_prop_size;
408 uint32_t vcpus_per_socket = smp_threads * smp_cores;
409 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
410 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
411 sPAPRDRConnector *drc;
412 sPAPRDRConnectorClass *drck;
413 int drc_index;
414
415 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
416 if (drc) {
417 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
418 drc_index = drck->get_index(drc);
419 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
420 }
421
422 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
423 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
424
425 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
426 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
427 env->dcache_line_size)));
428 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
429 env->dcache_line_size)));
430 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
431 env->icache_line_size)));
432 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
433 env->icache_line_size)));
434
435 if (pcc->l1_dcache_size) {
436 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
437 pcc->l1_dcache_size)));
438 } else {
439 error_report("Warning: Unknown L1 dcache size for cpu");
440 }
441 if (pcc->l1_icache_size) {
442 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
443 pcc->l1_icache_size)));
444 } else {
445 error_report("Warning: Unknown L1 icache size for cpu");
446 }
447
448 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
449 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
450 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
451 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
452 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
453 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
454
455 if (env->spr_cb[SPR_PURR].oea_read) {
456 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
457 }
458
459 if (env->mmu_model & POWERPC_MMU_1TSEG) {
460 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
461 segs, sizeof(segs))));
462 }
463
464 /* Advertise VMX/VSX (vector extensions) if available
465 * 0 / no property == no vector extensions
466 * 1 == VMX / Altivec available
467 * 2 == VSX available */
468 if (env->insns_flags & PPC_ALTIVEC) {
469 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
470
471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
472 }
473
474 /* Advertise DFP (Decimal Floating Point) if available
475 * 0 / no property == no DFP
476 * 1 == DFP available */
477 if (env->insns_flags2 & PPC2_DFP) {
478 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
479 }
480
481 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
482 sizeof(page_sizes_prop));
483 if (page_sizes_prop_size) {
484 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
485 page_sizes_prop, page_sizes_prop_size)));
486 }
487
488 spapr_populate_pa_features(env, fdt, offset);
489
490 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
491 cs->cpu_index / vcpus_per_socket)));
492
493 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
494 pft_size_prop, sizeof(pft_size_prop))));
495
496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
497
498 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
499 }
500
501 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
502 {
503 CPUState *cs;
504 int cpus_offset;
505 char *nodename;
506 int smt = kvmppc_smt_threads();
507
508 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
509 _FDT(cpus_offset);
510 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
511 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
512
513 /*
514 * We walk the CPUs in reverse order to ensure that CPU DT nodes
515 * created by fdt_add_subnode() end up in the right order in FDT
516 * for the guest kernel the enumerate the CPUs correctly.
517 */
518 CPU_FOREACH_REVERSE(cs) {
519 PowerPCCPU *cpu = POWERPC_CPU(cs);
520 int index = ppc_get_vcpu_dt_id(cpu);
521 DeviceClass *dc = DEVICE_GET_CLASS(cs);
522 int offset;
523
524 if ((index % smt) != 0) {
525 continue;
526 }
527
528 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
529 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
530 g_free(nodename);
531 _FDT(offset);
532 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
533 }
534
535 }
536
537 /*
538 * Adds ibm,dynamic-reconfiguration-memory node.
539 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
540 * of this device tree node.
541 */
542 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
543 {
544 MachineState *machine = MACHINE(spapr);
545 int ret, i, offset;
546 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
547 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
548 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
549 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
550 memory_region_size(&spapr->hotplug_memory.mr)) /
551 lmb_size;
552 uint32_t *int_buf, *cur_index, buf_len;
553 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
554
555 /*
556 * Don't create the node if there is no hotpluggable memory
557 */
558 if (machine->ram_size == machine->maxram_size) {
559 return 0;
560 }
561
562 /*
563 * Allocate enough buffer size to fit in ibm,dynamic-memory
564 * or ibm,associativity-lookup-arrays
565 */
566 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
567 * sizeof(uint32_t);
568 cur_index = int_buf = g_malloc0(buf_len);
569
570 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
571
572 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
573 sizeof(prop_lmb_size));
574 if (ret < 0) {
575 goto out;
576 }
577
578 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
579 if (ret < 0) {
580 goto out;
581 }
582
583 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
584 if (ret < 0) {
585 goto out;
586 }
587
588 /* ibm,dynamic-memory */
589 int_buf[0] = cpu_to_be32(nr_lmbs);
590 cur_index++;
591 for (i = 0; i < nr_lmbs; i++) {
592 uint64_t addr = i * lmb_size;
593 uint32_t *dynamic_memory = cur_index;
594
595 if (i >= hotplug_lmb_start) {
596 sPAPRDRConnector *drc;
597 sPAPRDRConnectorClass *drck;
598
599 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
600 g_assert(drc);
601 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
602
603 dynamic_memory[0] = cpu_to_be32(addr >> 32);
604 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
605 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
606 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
607 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
608 if (memory_region_present(get_system_memory(), addr)) {
609 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
610 } else {
611 dynamic_memory[5] = cpu_to_be32(0);
612 }
613 } else {
614 /*
615 * LMB information for RMA, boot time RAM and gap b/n RAM and
616 * hotplug memory region -- all these are marked as reserved
617 * and as having no valid DRC.
618 */
619 dynamic_memory[0] = cpu_to_be32(addr >> 32);
620 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
621 dynamic_memory[2] = cpu_to_be32(0);
622 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
623 dynamic_memory[4] = cpu_to_be32(-1);
624 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
625 SPAPR_LMB_FLAGS_DRC_INVALID);
626 }
627
628 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
629 }
630 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
631 if (ret < 0) {
632 goto out;
633 }
634
635 /* ibm,associativity-lookup-arrays */
636 cur_index = int_buf;
637 int_buf[0] = cpu_to_be32(nr_nodes);
638 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
639 cur_index += 2;
640 for (i = 0; i < nr_nodes; i++) {
641 uint32_t associativity[] = {
642 cpu_to_be32(0x0),
643 cpu_to_be32(0x0),
644 cpu_to_be32(0x0),
645 cpu_to_be32(i)
646 };
647 memcpy(cur_index, associativity, sizeof(associativity));
648 cur_index += 4;
649 }
650 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
651 (cur_index - int_buf) * sizeof(uint32_t));
652 out:
653 g_free(int_buf);
654 return ret;
655 }
656
657 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
658 sPAPROptionVector *ov5_updates)
659 {
660 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
661 int ret = 0, offset;
662
663 /* Generate ibm,dynamic-reconfiguration-memory node if required */
664 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
665 g_assert(smc->dr_lmb_enabled);
666 ret = spapr_populate_drconf_memory(spapr, fdt);
667 if (ret) {
668 goto out;
669 }
670 }
671
672 offset = fdt_path_offset(fdt, "/chosen");
673 if (offset < 0) {
674 offset = fdt_add_subnode(fdt, 0, "chosen");
675 if (offset < 0) {
676 return offset;
677 }
678 }
679 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
680 "ibm,architecture-vec-5");
681
682 out:
683 return ret;
684 }
685
686 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
687 target_ulong addr, target_ulong size,
688 sPAPROptionVector *ov5_updates)
689 {
690 void *fdt, *fdt_skel;
691 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
692
693 size -= sizeof(hdr);
694
695 /* Create sceleton */
696 fdt_skel = g_malloc0(size);
697 _FDT((fdt_create(fdt_skel, size)));
698 _FDT((fdt_begin_node(fdt_skel, "")));
699 _FDT((fdt_end_node(fdt_skel)));
700 _FDT((fdt_finish(fdt_skel)));
701 fdt = g_malloc0(size);
702 _FDT((fdt_open_into(fdt_skel, fdt, size)));
703 g_free(fdt_skel);
704
705 /* Fixup cpu nodes */
706 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
707
708 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
709 return -1;
710 }
711
712 /* Pack resulting tree */
713 _FDT((fdt_pack(fdt)));
714
715 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
716 trace_spapr_cas_failed(size);
717 return -1;
718 }
719
720 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
721 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
722 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
723 g_free(fdt);
724
725 return 0;
726 }
727
728 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
729 {
730 int rtas;
731 GString *hypertas = g_string_sized_new(256);
732 GString *qemu_hypertas = g_string_sized_new(256);
733 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
734 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
735 memory_region_size(&spapr->hotplug_memory.mr);
736 uint32_t lrdr_capacity[] = {
737 cpu_to_be32(max_hotplug_addr >> 32),
738 cpu_to_be32(max_hotplug_addr & 0xffffffff),
739 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
740 cpu_to_be32(max_cpus / smp_threads),
741 };
742
743 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
744
745 /* hypertas */
746 add_str(hypertas, "hcall-pft");
747 add_str(hypertas, "hcall-term");
748 add_str(hypertas, "hcall-dabr");
749 add_str(hypertas, "hcall-interrupt");
750 add_str(hypertas, "hcall-tce");
751 add_str(hypertas, "hcall-vio");
752 add_str(hypertas, "hcall-splpar");
753 add_str(hypertas, "hcall-bulk");
754 add_str(hypertas, "hcall-set-mode");
755 add_str(hypertas, "hcall-sprg0");
756 add_str(hypertas, "hcall-copy");
757 add_str(hypertas, "hcall-debug");
758 add_str(qemu_hypertas, "hcall-memop1");
759
760 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
761 add_str(hypertas, "hcall-multi-tce");
762 }
763 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
764 hypertas->str, hypertas->len));
765 g_string_free(hypertas, TRUE);
766 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
767 qemu_hypertas->str, qemu_hypertas->len));
768 g_string_free(qemu_hypertas, TRUE);
769
770 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
771 refpoints, sizeof(refpoints)));
772
773 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
774 RTAS_ERROR_LOG_MAX));
775 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
776 RTAS_EVENT_SCAN_RATE));
777
778 if (msi_nonbroken) {
779 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
780 }
781
782 /*
783 * According to PAPR, rtas ibm,os-term does not guarantee a return
784 * back to the guest cpu.
785 *
786 * While an additional ibm,extended-os-term property indicates
787 * that rtas call return will always occur. Set this property.
788 */
789 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
790
791 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
792 lrdr_capacity, sizeof(lrdr_capacity)));
793
794 spapr_dt_rtas_tokens(fdt, rtas);
795 }
796
797 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
798 {
799 MachineState *machine = MACHINE(spapr);
800 int chosen;
801 const char *boot_device = machine->boot_order;
802 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
803 size_t cb = 0;
804 char *bootlist = get_boot_devices_list(&cb, true);
805
806 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
807
808 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
809 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
810 spapr->initrd_base));
811 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
812 spapr->initrd_base + spapr->initrd_size));
813
814 if (spapr->kernel_size) {
815 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
816 cpu_to_be64(spapr->kernel_size) };
817
818 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
819 &kprop, sizeof(kprop)));
820 if (spapr->kernel_le) {
821 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
822 }
823 }
824 if (boot_menu) {
825 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
826 }
827 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
828 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
829 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
830
831 if (cb && bootlist) {
832 int i;
833
834 for (i = 0; i < cb; i++) {
835 if (bootlist[i] == '\n') {
836 bootlist[i] = ' ';
837 }
838 }
839 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
840 }
841
842 if (boot_device && strlen(boot_device)) {
843 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
844 }
845
846 if (!spapr->has_graphics && stdout_path) {
847 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
848 }
849
850 g_free(stdout_path);
851 g_free(bootlist);
852 }
853
854 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
855 {
856 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
857 * KVM to work under pHyp with some guest co-operation */
858 int hypervisor;
859 uint8_t hypercall[16];
860
861 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
862 /* indicate KVM hypercall interface */
863 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
864 if (kvmppc_has_cap_fixup_hcalls()) {
865 /*
866 * Older KVM versions with older guest kernels were broken
867 * with the magic page, don't allow the guest to map it.
868 */
869 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
870 sizeof(hypercall))) {
871 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
872 hypercall, sizeof(hypercall)));
873 }
874 }
875 }
876
877 static void *spapr_build_fdt(sPAPRMachineState *spapr,
878 hwaddr rtas_addr,
879 hwaddr rtas_size)
880 {
881 MachineState *machine = MACHINE(qdev_get_machine());
882 MachineClass *mc = MACHINE_GET_CLASS(machine);
883 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
884 int ret;
885 void *fdt;
886 sPAPRPHBState *phb;
887 char *buf;
888
889 fdt = g_malloc0(FDT_MAX_SIZE);
890 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
891
892 /* Root node */
893 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
894 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
895 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
896
897 /*
898 * Add info to guest to indentify which host is it being run on
899 * and what is the uuid of the guest
900 */
901 if (kvmppc_get_host_model(&buf)) {
902 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
903 g_free(buf);
904 }
905 if (kvmppc_get_host_serial(&buf)) {
906 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
907 g_free(buf);
908 }
909
910 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
911
912 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
913 if (qemu_uuid_set) {
914 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
915 }
916 g_free(buf);
917
918 if (qemu_get_vm_name()) {
919 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
920 qemu_get_vm_name()));
921 }
922
923 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
924 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
925
926 /* /interrupt controller */
927 spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP);
928
929 ret = spapr_populate_memory(spapr, fdt);
930 if (ret < 0) {
931 error_report("couldn't setup memory nodes in fdt");
932 exit(1);
933 }
934
935 /* /vdevice */
936 spapr_dt_vdevice(spapr->vio_bus, fdt);
937
938 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
939 ret = spapr_rng_populate_dt(fdt);
940 if (ret < 0) {
941 error_report("could not set up rng device in the fdt");
942 exit(1);
943 }
944 }
945
946 QLIST_FOREACH(phb, &spapr->phbs, list) {
947 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
948 if (ret < 0) {
949 error_report("couldn't setup PCI devices in fdt");
950 exit(1);
951 }
952 }
953
954 /* cpus */
955 spapr_populate_cpus_dt_node(fdt, spapr);
956
957 if (smc->dr_lmb_enabled) {
958 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
959 }
960
961 if (mc->has_hotpluggable_cpus) {
962 int offset = fdt_path_offset(fdt, "/cpus");
963 ret = spapr_drc_populate_dt(fdt, offset, NULL,
964 SPAPR_DR_CONNECTOR_TYPE_CPU);
965 if (ret < 0) {
966 error_report("Couldn't set up CPU DR device tree properties");
967 exit(1);
968 }
969 }
970
971 /* /event-sources */
972 spapr_dt_events(spapr, fdt);
973
974 /* /rtas */
975 spapr_dt_rtas(spapr, fdt);
976
977 /* /chosen */
978 spapr_dt_chosen(spapr, fdt);
979
980 /* /hypervisor */
981 if (kvm_enabled()) {
982 spapr_dt_hypervisor(spapr, fdt);
983 }
984
985 /* Build memory reserve map */
986 if (spapr->kernel_size) {
987 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
988 }
989 if (spapr->initrd_size) {
990 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
991 }
992
993 /* ibm,client-architecture-support updates */
994 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
995 if (ret < 0) {
996 error_report("couldn't setup CAS properties fdt");
997 exit(1);
998 }
999
1000 return fdt;
1001 }
1002
1003 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1004 {
1005 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1006 }
1007
1008 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1009 PowerPCCPU *cpu)
1010 {
1011 CPUPPCState *env = &cpu->env;
1012
1013 /* The TCG path should also be holding the BQL at this point */
1014 g_assert(qemu_mutex_iothread_locked());
1015
1016 if (msr_pr) {
1017 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1018 env->gpr[3] = H_PRIVILEGE;
1019 } else {
1020 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1021 }
1022 }
1023
1024 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1025 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1026 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1027 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1028 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1029
1030 /*
1031 * Get the fd to access the kernel htab, re-opening it if necessary
1032 */
1033 static int get_htab_fd(sPAPRMachineState *spapr)
1034 {
1035 if (spapr->htab_fd >= 0) {
1036 return spapr->htab_fd;
1037 }
1038
1039 spapr->htab_fd = kvmppc_get_htab_fd(false);
1040 if (spapr->htab_fd < 0) {
1041 error_report("Unable to open fd for reading hash table from KVM: %s",
1042 strerror(errno));
1043 }
1044
1045 return spapr->htab_fd;
1046 }
1047
1048 static void close_htab_fd(sPAPRMachineState *spapr)
1049 {
1050 if (spapr->htab_fd >= 0) {
1051 close(spapr->htab_fd);
1052 }
1053 spapr->htab_fd = -1;
1054 }
1055
1056 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1057 {
1058 int shift;
1059
1060 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1061 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1062 * that's much more than is needed for Linux guests */
1063 shift = ctz64(pow2ceil(ramsize)) - 7;
1064 shift = MAX(shift, 18); /* Minimum architected size */
1065 shift = MIN(shift, 46); /* Maximum architected size */
1066 return shift;
1067 }
1068
1069 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1070 Error **errp)
1071 {
1072 long rc;
1073
1074 /* Clean up any HPT info from a previous boot */
1075 g_free(spapr->htab);
1076 spapr->htab = NULL;
1077 spapr->htab_shift = 0;
1078 close_htab_fd(spapr);
1079
1080 rc = kvmppc_reset_htab(shift);
1081 if (rc < 0) {
1082 /* kernel-side HPT needed, but couldn't allocate one */
1083 error_setg_errno(errp, errno,
1084 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1085 shift);
1086 /* This is almost certainly fatal, but if the caller really
1087 * wants to carry on with shift == 0, it's welcome to try */
1088 } else if (rc > 0) {
1089 /* kernel-side HPT allocated */
1090 if (rc != shift) {
1091 error_setg(errp,
1092 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1093 shift, rc);
1094 }
1095
1096 spapr->htab_shift = shift;
1097 spapr->htab = NULL;
1098 } else {
1099 /* kernel-side HPT not needed, allocate in userspace instead */
1100 size_t size = 1ULL << shift;
1101 int i;
1102
1103 spapr->htab = qemu_memalign(size, size);
1104 if (!spapr->htab) {
1105 error_setg_errno(errp, errno,
1106 "Could not allocate HPT of order %d", shift);
1107 return;
1108 }
1109
1110 memset(spapr->htab, 0, size);
1111 spapr->htab_shift = shift;
1112
1113 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1114 DIRTY_HPTE(HPTE(spapr->htab, i));
1115 }
1116 }
1117 }
1118
1119 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1120 {
1121 bool matched = false;
1122
1123 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1124 matched = true;
1125 }
1126
1127 if (!matched) {
1128 error_report("Device %s is not supported by this machine yet.",
1129 qdev_fw_name(DEVICE(sbdev)));
1130 exit(1);
1131 }
1132 }
1133
1134 static void ppc_spapr_reset(void)
1135 {
1136 MachineState *machine = MACHINE(qdev_get_machine());
1137 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1138 PowerPCCPU *first_ppc_cpu;
1139 uint32_t rtas_limit;
1140 hwaddr rtas_addr, fdt_addr;
1141 void *fdt;
1142 int rc;
1143
1144 /* Check for unknown sysbus devices */
1145 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1146
1147 /* Allocate and/or reset the hash page table */
1148 spapr_reallocate_hpt(spapr,
1149 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1150 &error_fatal);
1151
1152 /* Update the RMA size if necessary */
1153 if (spapr->vrma_adjust) {
1154 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1155 spapr->htab_shift);
1156 }
1157
1158 qemu_devices_reset();
1159
1160 /*
1161 * We place the device tree and RTAS just below either the top of the RMA,
1162 * or just below 2GB, whichever is lowere, so that it can be
1163 * processed with 32-bit real mode code if necessary
1164 */
1165 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1166 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1167 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1168
1169 /* if this reset wasn't generated by CAS, we should reset our
1170 * negotiated options and start from scratch */
1171 if (!spapr->cas_reboot) {
1172 spapr_ovec_cleanup(spapr->ov5_cas);
1173 spapr->ov5_cas = spapr_ovec_new();
1174 }
1175
1176 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1177
1178 spapr_load_rtas(spapr, fdt, rtas_addr);
1179
1180 rc = fdt_pack(fdt);
1181
1182 /* Should only fail if we've built a corrupted tree */
1183 assert(rc == 0);
1184
1185 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1186 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1187 fdt_totalsize(fdt), FDT_MAX_SIZE);
1188 exit(1);
1189 }
1190
1191 /* Load the fdt */
1192 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1193 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1194 g_free(fdt);
1195
1196 /* Set up the entry state */
1197 first_ppc_cpu = POWERPC_CPU(first_cpu);
1198 first_ppc_cpu->env.gpr[3] = fdt_addr;
1199 first_ppc_cpu->env.gpr[5] = 0;
1200 first_cpu->halted = 0;
1201 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1202
1203 spapr->cas_reboot = false;
1204 }
1205
1206 static void spapr_create_nvram(sPAPRMachineState *spapr)
1207 {
1208 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1209 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1210
1211 if (dinfo) {
1212 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1213 &error_fatal);
1214 }
1215
1216 qdev_init_nofail(dev);
1217
1218 spapr->nvram = (struct sPAPRNVRAM *)dev;
1219 }
1220
1221 static void spapr_rtc_create(sPAPRMachineState *spapr)
1222 {
1223 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1224
1225 qdev_init_nofail(dev);
1226 spapr->rtc = dev;
1227
1228 object_property_add_alias(qdev_get_machine(), "rtc-time",
1229 OBJECT(spapr->rtc), "date", NULL);
1230 }
1231
1232 /* Returns whether we want to use VGA or not */
1233 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1234 {
1235 switch (vga_interface_type) {
1236 case VGA_NONE:
1237 return false;
1238 case VGA_DEVICE:
1239 return true;
1240 case VGA_STD:
1241 case VGA_VIRTIO:
1242 return pci_vga_init(pci_bus) != NULL;
1243 default:
1244 error_setg(errp,
1245 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1246 return false;
1247 }
1248 }
1249
1250 static int spapr_post_load(void *opaque, int version_id)
1251 {
1252 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1253 int err = 0;
1254
1255 /* In earlier versions, there was no separate qdev for the PAPR
1256 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1257 * So when migrating from those versions, poke the incoming offset
1258 * value into the RTC device */
1259 if (version_id < 3) {
1260 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1261 }
1262
1263 return err;
1264 }
1265
1266 static bool version_before_3(void *opaque, int version_id)
1267 {
1268 return version_id < 3;
1269 }
1270
1271 static bool spapr_ov5_cas_needed(void *opaque)
1272 {
1273 sPAPRMachineState *spapr = opaque;
1274 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1275 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1276 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1277 bool cas_needed;
1278
1279 /* Prior to the introduction of sPAPROptionVector, we had two option
1280 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1281 * Both of these options encode machine topology into the device-tree
1282 * in such a way that the now-booted OS should still be able to interact
1283 * appropriately with QEMU regardless of what options were actually
1284 * negotiatied on the source side.
1285 *
1286 * As such, we can avoid migrating the CAS-negotiated options if these
1287 * are the only options available on the current machine/platform.
1288 * Since these are the only options available for pseries-2.7 and
1289 * earlier, this allows us to maintain old->new/new->old migration
1290 * compatibility.
1291 *
1292 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1293 * via default pseries-2.8 machines and explicit command-line parameters.
1294 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1295 * of the actual CAS-negotiated values to continue working properly. For
1296 * example, availability of memory unplug depends on knowing whether
1297 * OV5_HP_EVT was negotiated via CAS.
1298 *
1299 * Thus, for any cases where the set of available CAS-negotiatable
1300 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1301 * include the CAS-negotiated options in the migration stream.
1302 */
1303 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1304 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1305
1306 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1307 * the mask itself since in the future it's possible "legacy" bits may be
1308 * removed via machine options, which could generate a false positive
1309 * that breaks migration.
1310 */
1311 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1312 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1313
1314 spapr_ovec_cleanup(ov5_mask);
1315 spapr_ovec_cleanup(ov5_legacy);
1316 spapr_ovec_cleanup(ov5_removed);
1317
1318 return cas_needed;
1319 }
1320
1321 static const VMStateDescription vmstate_spapr_ov5_cas = {
1322 .name = "spapr_option_vector_ov5_cas",
1323 .version_id = 1,
1324 .minimum_version_id = 1,
1325 .needed = spapr_ov5_cas_needed,
1326 .fields = (VMStateField[]) {
1327 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1328 vmstate_spapr_ovec, sPAPROptionVector),
1329 VMSTATE_END_OF_LIST()
1330 },
1331 };
1332
1333 static const VMStateDescription vmstate_spapr = {
1334 .name = "spapr",
1335 .version_id = 3,
1336 .minimum_version_id = 1,
1337 .post_load = spapr_post_load,
1338 .fields = (VMStateField[]) {
1339 /* used to be @next_irq */
1340 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1341
1342 /* RTC offset */
1343 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1344
1345 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1346 VMSTATE_END_OF_LIST()
1347 },
1348 .subsections = (const VMStateDescription*[]) {
1349 &vmstate_spapr_ov5_cas,
1350 NULL
1351 }
1352 };
1353
1354 static int htab_save_setup(QEMUFile *f, void *opaque)
1355 {
1356 sPAPRMachineState *spapr = opaque;
1357
1358 /* "Iteration" header */
1359 qemu_put_be32(f, spapr->htab_shift);
1360
1361 if (spapr->htab) {
1362 spapr->htab_save_index = 0;
1363 spapr->htab_first_pass = true;
1364 } else {
1365 assert(kvm_enabled());
1366 }
1367
1368
1369 return 0;
1370 }
1371
1372 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1373 int64_t max_ns)
1374 {
1375 bool has_timeout = max_ns != -1;
1376 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1377 int index = spapr->htab_save_index;
1378 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1379
1380 assert(spapr->htab_first_pass);
1381
1382 do {
1383 int chunkstart;
1384
1385 /* Consume invalid HPTEs */
1386 while ((index < htabslots)
1387 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1388 index++;
1389 CLEAN_HPTE(HPTE(spapr->htab, index));
1390 }
1391
1392 /* Consume valid HPTEs */
1393 chunkstart = index;
1394 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1395 && HPTE_VALID(HPTE(spapr->htab, index))) {
1396 index++;
1397 CLEAN_HPTE(HPTE(spapr->htab, index));
1398 }
1399
1400 if (index > chunkstart) {
1401 int n_valid = index - chunkstart;
1402
1403 qemu_put_be32(f, chunkstart);
1404 qemu_put_be16(f, n_valid);
1405 qemu_put_be16(f, 0);
1406 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1407 HASH_PTE_SIZE_64 * n_valid);
1408
1409 if (has_timeout &&
1410 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1411 break;
1412 }
1413 }
1414 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1415
1416 if (index >= htabslots) {
1417 assert(index == htabslots);
1418 index = 0;
1419 spapr->htab_first_pass = false;
1420 }
1421 spapr->htab_save_index = index;
1422 }
1423
1424 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1425 int64_t max_ns)
1426 {
1427 bool final = max_ns < 0;
1428 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1429 int examined = 0, sent = 0;
1430 int index = spapr->htab_save_index;
1431 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1432
1433 assert(!spapr->htab_first_pass);
1434
1435 do {
1436 int chunkstart, invalidstart;
1437
1438 /* Consume non-dirty HPTEs */
1439 while ((index < htabslots)
1440 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1441 index++;
1442 examined++;
1443 }
1444
1445 chunkstart = index;
1446 /* Consume valid dirty HPTEs */
1447 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1448 && HPTE_DIRTY(HPTE(spapr->htab, index))
1449 && HPTE_VALID(HPTE(spapr->htab, index))) {
1450 CLEAN_HPTE(HPTE(spapr->htab, index));
1451 index++;
1452 examined++;
1453 }
1454
1455 invalidstart = index;
1456 /* Consume invalid dirty HPTEs */
1457 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1458 && HPTE_DIRTY(HPTE(spapr->htab, index))
1459 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1460 CLEAN_HPTE(HPTE(spapr->htab, index));
1461 index++;
1462 examined++;
1463 }
1464
1465 if (index > chunkstart) {
1466 int n_valid = invalidstart - chunkstart;
1467 int n_invalid = index - invalidstart;
1468
1469 qemu_put_be32(f, chunkstart);
1470 qemu_put_be16(f, n_valid);
1471 qemu_put_be16(f, n_invalid);
1472 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1473 HASH_PTE_SIZE_64 * n_valid);
1474 sent += index - chunkstart;
1475
1476 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1477 break;
1478 }
1479 }
1480
1481 if (examined >= htabslots) {
1482 break;
1483 }
1484
1485 if (index >= htabslots) {
1486 assert(index == htabslots);
1487 index = 0;
1488 }
1489 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1490
1491 if (index >= htabslots) {
1492 assert(index == htabslots);
1493 index = 0;
1494 }
1495
1496 spapr->htab_save_index = index;
1497
1498 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1499 }
1500
1501 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1502 #define MAX_KVM_BUF_SIZE 2048
1503
1504 static int htab_save_iterate(QEMUFile *f, void *opaque)
1505 {
1506 sPAPRMachineState *spapr = opaque;
1507 int fd;
1508 int rc = 0;
1509
1510 /* Iteration header */
1511 qemu_put_be32(f, 0);
1512
1513 if (!spapr->htab) {
1514 assert(kvm_enabled());
1515
1516 fd = get_htab_fd(spapr);
1517 if (fd < 0) {
1518 return fd;
1519 }
1520
1521 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1522 if (rc < 0) {
1523 return rc;
1524 }
1525 } else if (spapr->htab_first_pass) {
1526 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1527 } else {
1528 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1529 }
1530
1531 /* End marker */
1532 qemu_put_be32(f, 0);
1533 qemu_put_be16(f, 0);
1534 qemu_put_be16(f, 0);
1535
1536 return rc;
1537 }
1538
1539 static int htab_save_complete(QEMUFile *f, void *opaque)
1540 {
1541 sPAPRMachineState *spapr = opaque;
1542 int fd;
1543
1544 /* Iteration header */
1545 qemu_put_be32(f, 0);
1546
1547 if (!spapr->htab) {
1548 int rc;
1549
1550 assert(kvm_enabled());
1551
1552 fd = get_htab_fd(spapr);
1553 if (fd < 0) {
1554 return fd;
1555 }
1556
1557 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1558 if (rc < 0) {
1559 return rc;
1560 }
1561 } else {
1562 if (spapr->htab_first_pass) {
1563 htab_save_first_pass(f, spapr, -1);
1564 }
1565 htab_save_later_pass(f, spapr, -1);
1566 }
1567
1568 /* End marker */
1569 qemu_put_be32(f, 0);
1570 qemu_put_be16(f, 0);
1571 qemu_put_be16(f, 0);
1572
1573 return 0;
1574 }
1575
1576 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1577 {
1578 sPAPRMachineState *spapr = opaque;
1579 uint32_t section_hdr;
1580 int fd = -1;
1581
1582 if (version_id < 1 || version_id > 1) {
1583 error_report("htab_load() bad version");
1584 return -EINVAL;
1585 }
1586
1587 section_hdr = qemu_get_be32(f);
1588
1589 if (section_hdr) {
1590 Error *local_err = NULL;
1591
1592 /* First section gives the htab size */
1593 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1594 if (local_err) {
1595 error_report_err(local_err);
1596 return -EINVAL;
1597 }
1598 return 0;
1599 }
1600
1601 if (!spapr->htab) {
1602 assert(kvm_enabled());
1603
1604 fd = kvmppc_get_htab_fd(true);
1605 if (fd < 0) {
1606 error_report("Unable to open fd to restore KVM hash table: %s",
1607 strerror(errno));
1608 }
1609 }
1610
1611 while (true) {
1612 uint32_t index;
1613 uint16_t n_valid, n_invalid;
1614
1615 index = qemu_get_be32(f);
1616 n_valid = qemu_get_be16(f);
1617 n_invalid = qemu_get_be16(f);
1618
1619 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1620 /* End of Stream */
1621 break;
1622 }
1623
1624 if ((index + n_valid + n_invalid) >
1625 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1626 /* Bad index in stream */
1627 error_report(
1628 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1629 index, n_valid, n_invalid, spapr->htab_shift);
1630 return -EINVAL;
1631 }
1632
1633 if (spapr->htab) {
1634 if (n_valid) {
1635 qemu_get_buffer(f, HPTE(spapr->htab, index),
1636 HASH_PTE_SIZE_64 * n_valid);
1637 }
1638 if (n_invalid) {
1639 memset(HPTE(spapr->htab, index + n_valid), 0,
1640 HASH_PTE_SIZE_64 * n_invalid);
1641 }
1642 } else {
1643 int rc;
1644
1645 assert(fd >= 0);
1646
1647 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1648 if (rc < 0) {
1649 return rc;
1650 }
1651 }
1652 }
1653
1654 if (!spapr->htab) {
1655 assert(fd >= 0);
1656 close(fd);
1657 }
1658
1659 return 0;
1660 }
1661
1662 static void htab_cleanup(void *opaque)
1663 {
1664 sPAPRMachineState *spapr = opaque;
1665
1666 close_htab_fd(spapr);
1667 }
1668
1669 static SaveVMHandlers savevm_htab_handlers = {
1670 .save_live_setup = htab_save_setup,
1671 .save_live_iterate = htab_save_iterate,
1672 .save_live_complete_precopy = htab_save_complete,
1673 .cleanup = htab_cleanup,
1674 .load_state = htab_load,
1675 };
1676
1677 static void spapr_boot_set(void *opaque, const char *boot_device,
1678 Error **errp)
1679 {
1680 MachineState *machine = MACHINE(qdev_get_machine());
1681 machine->boot_order = g_strdup(boot_device);
1682 }
1683
1684 /*
1685 * Reset routine for LMB DR devices.
1686 *
1687 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1688 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1689 * when it walks all its children devices. LMB devices reset occurs
1690 * as part of spapr_ppc_reset().
1691 */
1692 static void spapr_drc_reset(void *opaque)
1693 {
1694 sPAPRDRConnector *drc = opaque;
1695 DeviceState *d = DEVICE(drc);
1696
1697 if (d) {
1698 device_reset(d);
1699 }
1700 }
1701
1702 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1703 {
1704 MachineState *machine = MACHINE(spapr);
1705 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1706 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1707 int i;
1708
1709 for (i = 0; i < nr_lmbs; i++) {
1710 sPAPRDRConnector *drc;
1711 uint64_t addr;
1712
1713 addr = i * lmb_size + spapr->hotplug_memory.base;
1714 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1715 addr/lmb_size);
1716 qemu_register_reset(spapr_drc_reset, drc);
1717 }
1718 }
1719
1720 /*
1721 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1722 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1723 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1724 */
1725 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1726 {
1727 int i;
1728
1729 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1730 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1731 " is not aligned to %llu MiB",
1732 machine->ram_size,
1733 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1734 return;
1735 }
1736
1737 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1738 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1739 " is not aligned to %llu MiB",
1740 machine->ram_size,
1741 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1742 return;
1743 }
1744
1745 for (i = 0; i < nb_numa_nodes; i++) {
1746 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1747 error_setg(errp,
1748 "Node %d memory size 0x%" PRIx64
1749 " is not aligned to %llu MiB",
1750 i, numa_info[i].node_mem,
1751 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1752 return;
1753 }
1754 }
1755 }
1756
1757 /* find cpu slot in machine->possible_cpus by core_id */
1758 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1759 {
1760 int index = id / smp_threads;
1761
1762 if (index >= ms->possible_cpus->len) {
1763 return NULL;
1764 }
1765 if (idx) {
1766 *idx = index;
1767 }
1768 return &ms->possible_cpus->cpus[index];
1769 }
1770
1771 static void spapr_init_cpus(sPAPRMachineState *spapr)
1772 {
1773 MachineState *machine = MACHINE(spapr);
1774 MachineClass *mc = MACHINE_GET_CLASS(machine);
1775 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1776 int smt = kvmppc_smt_threads();
1777 const CPUArchIdList *possible_cpus;
1778 int boot_cores_nr = smp_cpus / smp_threads;
1779 int i;
1780
1781 if (!type) {
1782 error_report("Unable to find sPAPR CPU Core definition");
1783 exit(1);
1784 }
1785
1786 possible_cpus = mc->possible_cpu_arch_ids(machine);
1787 if (mc->has_hotpluggable_cpus) {
1788 if (smp_cpus % smp_threads) {
1789 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1790 smp_cpus, smp_threads);
1791 exit(1);
1792 }
1793 if (max_cpus % smp_threads) {
1794 error_report("max_cpus (%u) must be multiple of threads (%u)",
1795 max_cpus, smp_threads);
1796 exit(1);
1797 }
1798 } else {
1799 if (max_cpus != smp_cpus) {
1800 error_report("This machine version does not support CPU hotplug");
1801 exit(1);
1802 }
1803 boot_cores_nr = possible_cpus->len;
1804 }
1805
1806 for (i = 0; i < possible_cpus->len; i++) {
1807 int core_id = i * smp_threads;
1808
1809 if (mc->has_hotpluggable_cpus) {
1810 sPAPRDRConnector *drc =
1811 spapr_dr_connector_new(OBJECT(spapr),
1812 SPAPR_DR_CONNECTOR_TYPE_CPU,
1813 (core_id / smp_threads) * smt);
1814
1815 qemu_register_reset(spapr_drc_reset, drc);
1816 }
1817
1818 if (i < boot_cores_nr) {
1819 Object *core = object_new(type);
1820 int nr_threads = smp_threads;
1821
1822 /* Handle the partially filled core for older machine types */
1823 if ((i + 1) * smp_threads >= smp_cpus) {
1824 nr_threads = smp_cpus - i * smp_threads;
1825 }
1826
1827 object_property_set_int(core, nr_threads, "nr-threads",
1828 &error_fatal);
1829 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
1830 &error_fatal);
1831 object_property_set_bool(core, true, "realized", &error_fatal);
1832 }
1833 }
1834 g_free(type);
1835 }
1836
1837 /* pSeries LPAR / sPAPR hardware init */
1838 static void ppc_spapr_init(MachineState *machine)
1839 {
1840 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1841 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1842 const char *kernel_filename = machine->kernel_filename;
1843 const char *initrd_filename = machine->initrd_filename;
1844 PCIHostState *phb;
1845 int i;
1846 MemoryRegion *sysmem = get_system_memory();
1847 MemoryRegion *ram = g_new(MemoryRegion, 1);
1848 MemoryRegion *rma_region;
1849 void *rma = NULL;
1850 hwaddr rma_alloc_size;
1851 hwaddr node0_size = spapr_node0_size();
1852 long load_limit, fw_size;
1853 char *filename;
1854 int smt = kvmppc_smt_threads();
1855
1856 msi_nonbroken = true;
1857
1858 QLIST_INIT(&spapr->phbs);
1859
1860 /* Allocate RMA if necessary */
1861 rma_alloc_size = kvmppc_alloc_rma(&rma);
1862
1863 if (rma_alloc_size == -1) {
1864 error_report("Unable to create RMA");
1865 exit(1);
1866 }
1867
1868 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1869 spapr->rma_size = rma_alloc_size;
1870 } else {
1871 spapr->rma_size = node0_size;
1872
1873 /* With KVM, we don't actually know whether KVM supports an
1874 * unbounded RMA (PR KVM) or is limited by the hash table size
1875 * (HV KVM using VRMA), so we always assume the latter
1876 *
1877 * In that case, we also limit the initial allocations for RTAS
1878 * etc... to 256M since we have no way to know what the VRMA size
1879 * is going to be as it depends on the size of the hash table
1880 * isn't determined yet.
1881 */
1882 if (kvm_enabled()) {
1883 spapr->vrma_adjust = 1;
1884 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1885 }
1886
1887 /* Actually we don't support unbounded RMA anymore since we
1888 * added proper emulation of HV mode. The max we can get is
1889 * 16G which also happens to be what we configure for PAPR
1890 * mode so make sure we don't do anything bigger than that
1891 */
1892 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
1893 }
1894
1895 if (spapr->rma_size > node0_size) {
1896 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1897 spapr->rma_size);
1898 exit(1);
1899 }
1900
1901 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1902 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1903
1904 /* Set up Interrupt Controller before we create the VCPUs */
1905 spapr->xics = xics_system_init(machine,
1906 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1907 XICS_IRQS_SPAPR, &error_fatal);
1908
1909 /* Set up containers for ibm,client-set-architecture negotiated options */
1910 spapr->ov5 = spapr_ovec_new();
1911 spapr->ov5_cas = spapr_ovec_new();
1912
1913 if (smc->dr_lmb_enabled) {
1914 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
1915 spapr_validate_node_memory(machine, &error_fatal);
1916 }
1917
1918 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
1919
1920 /* advertise support for dedicated HP event source to guests */
1921 if (spapr->use_hotplug_event_source) {
1922 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
1923 }
1924
1925 /* init CPUs */
1926 if (machine->cpu_model == NULL) {
1927 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
1928 }
1929
1930 ppc_cpu_parse_features(machine->cpu_model);
1931
1932 spapr_init_cpus(spapr);
1933
1934 if (kvm_enabled()) {
1935 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1936 kvmppc_enable_logical_ci_hcalls();
1937 kvmppc_enable_set_mode_hcall();
1938
1939 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
1940 kvmppc_enable_clear_ref_mod_hcalls();
1941 }
1942
1943 /* allocate RAM */
1944 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1945 machine->ram_size);
1946 memory_region_add_subregion(sysmem, 0, ram);
1947
1948 if (rma_alloc_size && rma) {
1949 rma_region = g_new(MemoryRegion, 1);
1950 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1951 rma_alloc_size, rma);
1952 vmstate_register_ram_global(rma_region);
1953 memory_region_add_subregion(sysmem, 0, rma_region);
1954 }
1955
1956 /* initialize hotplug memory address space */
1957 if (machine->ram_size < machine->maxram_size) {
1958 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1959 /*
1960 * Limit the number of hotpluggable memory slots to half the number
1961 * slots that KVM supports, leaving the other half for PCI and other
1962 * devices. However ensure that number of slots doesn't drop below 32.
1963 */
1964 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1965 SPAPR_MAX_RAM_SLOTS;
1966
1967 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1968 max_memslots = SPAPR_MAX_RAM_SLOTS;
1969 }
1970 if (machine->ram_slots > max_memslots) {
1971 error_report("Specified number of memory slots %"
1972 PRIu64" exceeds max supported %d",
1973 machine->ram_slots, max_memslots);
1974 exit(1);
1975 }
1976
1977 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1978 SPAPR_HOTPLUG_MEM_ALIGN);
1979 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1980 "hotplug-memory", hotplug_mem_size);
1981 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1982 &spapr->hotplug_memory.mr);
1983 }
1984
1985 if (smc->dr_lmb_enabled) {
1986 spapr_create_lmb_dr_connectors(spapr);
1987 }
1988
1989 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1990 if (!filename) {
1991 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1992 exit(1);
1993 }
1994 spapr->rtas_size = get_image_size(filename);
1995 if (spapr->rtas_size < 0) {
1996 error_report("Could not get size of LPAR rtas '%s'", filename);
1997 exit(1);
1998 }
1999 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2000 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2001 error_report("Could not load LPAR rtas '%s'", filename);
2002 exit(1);
2003 }
2004 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2005 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2006 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2007 exit(1);
2008 }
2009 g_free(filename);
2010
2011 /* Set up RTAS event infrastructure */
2012 spapr_events_init(spapr);
2013
2014 /* Set up the RTC RTAS interfaces */
2015 spapr_rtc_create(spapr);
2016
2017 /* Set up VIO bus */
2018 spapr->vio_bus = spapr_vio_bus_init();
2019
2020 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2021 if (serial_hds[i]) {
2022 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2023 }
2024 }
2025
2026 /* We always have at least the nvram device on VIO */
2027 spapr_create_nvram(spapr);
2028
2029 /* Set up PCI */
2030 spapr_pci_rtas_init();
2031
2032 phb = spapr_create_phb(spapr, 0);
2033
2034 for (i = 0; i < nb_nics; i++) {
2035 NICInfo *nd = &nd_table[i];
2036
2037 if (!nd->model) {
2038 nd->model = g_strdup("ibmveth");
2039 }
2040
2041 if (strcmp(nd->model, "ibmveth") == 0) {
2042 spapr_vlan_create(spapr->vio_bus, nd);
2043 } else {
2044 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2045 }
2046 }
2047
2048 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2049 spapr_vscsi_create(spapr->vio_bus);
2050 }
2051
2052 /* Graphics */
2053 if (spapr_vga_init(phb->bus, &error_fatal)) {
2054 spapr->has_graphics = true;
2055 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2056 }
2057
2058 if (machine->usb) {
2059 if (smc->use_ohci_by_default) {
2060 pci_create_simple(phb->bus, -1, "pci-ohci");
2061 } else {
2062 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2063 }
2064
2065 if (spapr->has_graphics) {
2066 USBBus *usb_bus = usb_bus_find(-1);
2067
2068 usb_create_simple(usb_bus, "usb-kbd");
2069 usb_create_simple(usb_bus, "usb-mouse");
2070 }
2071 }
2072
2073 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2074 error_report(
2075 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2076 MIN_RMA_SLOF);
2077 exit(1);
2078 }
2079
2080 if (kernel_filename) {
2081 uint64_t lowaddr = 0;
2082
2083 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2084 NULL, NULL, &lowaddr, NULL, 1,
2085 PPC_ELF_MACHINE, 0, 0);
2086 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2087 spapr->kernel_size = load_elf(kernel_filename,
2088 translate_kernel_address, NULL, NULL,
2089 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2090 0, 0);
2091 spapr->kernel_le = spapr->kernel_size > 0;
2092 }
2093 if (spapr->kernel_size < 0) {
2094 error_report("error loading %s: %s", kernel_filename,
2095 load_elf_strerror(spapr->kernel_size));
2096 exit(1);
2097 }
2098
2099 /* load initrd */
2100 if (initrd_filename) {
2101 /* Try to locate the initrd in the gap between the kernel
2102 * and the firmware. Add a bit of space just in case
2103 */
2104 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2105 + 0x1ffff) & ~0xffff;
2106 spapr->initrd_size = load_image_targphys(initrd_filename,
2107 spapr->initrd_base,
2108 load_limit
2109 - spapr->initrd_base);
2110 if (spapr->initrd_size < 0) {
2111 error_report("could not load initial ram disk '%s'",
2112 initrd_filename);
2113 exit(1);
2114 }
2115 }
2116 }
2117
2118 if (bios_name == NULL) {
2119 bios_name = FW_FILE_NAME;
2120 }
2121 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2122 if (!filename) {
2123 error_report("Could not find LPAR firmware '%s'", bios_name);
2124 exit(1);
2125 }
2126 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2127 if (fw_size <= 0) {
2128 error_report("Could not load LPAR firmware '%s'", filename);
2129 exit(1);
2130 }
2131 g_free(filename);
2132
2133 /* FIXME: Should register things through the MachineState's qdev
2134 * interface, this is a legacy from the sPAPREnvironment structure
2135 * which predated MachineState but had a similar function */
2136 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2137 register_savevm_live(NULL, "spapr/htab", -1, 1,
2138 &savevm_htab_handlers, spapr);
2139
2140 /* used by RTAS */
2141 QTAILQ_INIT(&spapr->ccs_list);
2142 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2143
2144 qemu_register_boot_set(spapr_boot_set, spapr);
2145
2146 /* to stop and start vmclock */
2147 if (kvm_enabled()) {
2148 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2149 &spapr->tb);
2150 }
2151 }
2152
2153 static int spapr_kvm_type(const char *vm_type)
2154 {
2155 if (!vm_type) {
2156 return 0;
2157 }
2158
2159 if (!strcmp(vm_type, "HV")) {
2160 return 1;
2161 }
2162
2163 if (!strcmp(vm_type, "PR")) {
2164 return 2;
2165 }
2166
2167 error_report("Unknown kvm-type specified '%s'", vm_type);
2168 exit(1);
2169 }
2170
2171 /*
2172 * Implementation of an interface to adjust firmware path
2173 * for the bootindex property handling.
2174 */
2175 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2176 DeviceState *dev)
2177 {
2178 #define CAST(type, obj, name) \
2179 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2180 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2181 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2182
2183 if (d) {
2184 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2185 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2186 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2187
2188 if (spapr) {
2189 /*
2190 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2191 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2192 * in the top 16 bits of the 64-bit LUN
2193 */
2194 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2195 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2196 (uint64_t)id << 48);
2197 } else if (virtio) {
2198 /*
2199 * We use SRP luns of the form 01000000 | (target << 8) | lun
2200 * in the top 32 bits of the 64-bit LUN
2201 * Note: the quote above is from SLOF and it is wrong,
2202 * the actual binding is:
2203 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2204 */
2205 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2206 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2207 (uint64_t)id << 32);
2208 } else if (usb) {
2209 /*
2210 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2211 * in the top 32 bits of the 64-bit LUN
2212 */
2213 unsigned usb_port = atoi(usb->port->path);
2214 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2215 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2216 (uint64_t)id << 32);
2217 }
2218 }
2219
2220 /*
2221 * SLOF probes the USB devices, and if it recognizes that the device is a
2222 * storage device, it changes its name to "storage" instead of "usb-host",
2223 * and additionally adds a child node for the SCSI LUN, so the correct
2224 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2225 */
2226 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2227 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2228 if (usb_host_dev_is_scsi_storage(usbdev)) {
2229 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2230 }
2231 }
2232
2233 if (phb) {
2234 /* Replace "pci" with "pci@800000020000000" */
2235 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2236 }
2237
2238 return NULL;
2239 }
2240
2241 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2242 {
2243 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2244
2245 return g_strdup(spapr->kvm_type);
2246 }
2247
2248 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2249 {
2250 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2251
2252 g_free(spapr->kvm_type);
2253 spapr->kvm_type = g_strdup(value);
2254 }
2255
2256 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2257 {
2258 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2259
2260 return spapr->use_hotplug_event_source;
2261 }
2262
2263 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2264 Error **errp)
2265 {
2266 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2267
2268 spapr->use_hotplug_event_source = value;
2269 }
2270
2271 static void spapr_machine_initfn(Object *obj)
2272 {
2273 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2274
2275 spapr->htab_fd = -1;
2276 spapr->use_hotplug_event_source = true;
2277 object_property_add_str(obj, "kvm-type",
2278 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2279 object_property_set_description(obj, "kvm-type",
2280 "Specifies the KVM virtualization mode (HV, PR)",
2281 NULL);
2282 object_property_add_bool(obj, "modern-hotplug-events",
2283 spapr_get_modern_hotplug_events,
2284 spapr_set_modern_hotplug_events,
2285 NULL);
2286 object_property_set_description(obj, "modern-hotplug-events",
2287 "Use dedicated hotplug event mechanism in"
2288 " place of standard EPOW events when possible"
2289 " (required for memory hot-unplug support)",
2290 NULL);
2291 }
2292
2293 static void spapr_machine_finalizefn(Object *obj)
2294 {
2295 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2296
2297 g_free(spapr->kvm_type);
2298 }
2299
2300 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2301 {
2302 cpu_synchronize_state(cs);
2303 ppc_cpu_do_system_reset(cs);
2304 }
2305
2306 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2307 {
2308 CPUState *cs;
2309
2310 CPU_FOREACH(cs) {
2311 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2312 }
2313 }
2314
2315 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2316 uint32_t node, bool dedicated_hp_event_source,
2317 Error **errp)
2318 {
2319 sPAPRDRConnector *drc;
2320 sPAPRDRConnectorClass *drck;
2321 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2322 int i, fdt_offset, fdt_size;
2323 void *fdt;
2324 uint64_t addr = addr_start;
2325
2326 for (i = 0; i < nr_lmbs; i++) {
2327 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2328 addr/SPAPR_MEMORY_BLOCK_SIZE);
2329 g_assert(drc);
2330
2331 fdt = create_device_tree(&fdt_size);
2332 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2333 SPAPR_MEMORY_BLOCK_SIZE);
2334
2335 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2336 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2337 addr += SPAPR_MEMORY_BLOCK_SIZE;
2338 if (!dev->hotplugged) {
2339 /* guests expect coldplugged LMBs to be pre-allocated */
2340 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2341 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2342 }
2343 }
2344 /* send hotplug notification to the
2345 * guest only in case of hotplugged memory
2346 */
2347 if (dev->hotplugged) {
2348 if (dedicated_hp_event_source) {
2349 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2350 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2351 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2352 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2353 nr_lmbs,
2354 drck->get_index(drc));
2355 } else {
2356 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2357 nr_lmbs);
2358 }
2359 }
2360 }
2361
2362 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2363 uint32_t node, Error **errp)
2364 {
2365 Error *local_err = NULL;
2366 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2367 PCDIMMDevice *dimm = PC_DIMM(dev);
2368 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2369 MemoryRegion *mr = ddc->get_memory_region(dimm);
2370 uint64_t align = memory_region_get_alignment(mr);
2371 uint64_t size = memory_region_size(mr);
2372 uint64_t addr;
2373 char *mem_dev;
2374
2375 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2376 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2377 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2378 goto out;
2379 }
2380
2381 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2382 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2383 error_setg(&local_err, "Memory backend has bad page size. "
2384 "Use 'memory-backend-file' with correct mem-path.");
2385 goto out;
2386 }
2387
2388 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2389 if (local_err) {
2390 goto out;
2391 }
2392
2393 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2394 if (local_err) {
2395 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2396 goto out;
2397 }
2398
2399 spapr_add_lmbs(dev, addr, size, node,
2400 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2401 &error_abort);
2402
2403 out:
2404 error_propagate(errp, local_err);
2405 }
2406
2407 typedef struct sPAPRDIMMState {
2408 uint32_t nr_lmbs;
2409 } sPAPRDIMMState;
2410
2411 static void spapr_lmb_release(DeviceState *dev, void *opaque)
2412 {
2413 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque;
2414 HotplugHandler *hotplug_ctrl;
2415
2416 if (--ds->nr_lmbs) {
2417 return;
2418 }
2419
2420 g_free(ds);
2421
2422 /*
2423 * Now that all the LMBs have been removed by the guest, call the
2424 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2425 */
2426 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2427 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2428 }
2429
2430 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2431 Error **errp)
2432 {
2433 sPAPRDRConnector *drc;
2434 sPAPRDRConnectorClass *drck;
2435 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2436 int i;
2437 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState));
2438 uint64_t addr = addr_start;
2439
2440 ds->nr_lmbs = nr_lmbs;
2441 for (i = 0; i < nr_lmbs; i++) {
2442 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2443 addr / SPAPR_MEMORY_BLOCK_SIZE);
2444 g_assert(drc);
2445
2446 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2447 drck->detach(drc, dev, spapr_lmb_release, ds, errp);
2448 addr += SPAPR_MEMORY_BLOCK_SIZE;
2449 }
2450
2451 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2452 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2453 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2454 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2455 nr_lmbs,
2456 drck->get_index(drc));
2457 }
2458
2459 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2460 Error **errp)
2461 {
2462 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2463 PCDIMMDevice *dimm = PC_DIMM(dev);
2464 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2465 MemoryRegion *mr = ddc->get_memory_region(dimm);
2466
2467 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2468 object_unparent(OBJECT(dev));
2469 }
2470
2471 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
2472 DeviceState *dev, Error **errp)
2473 {
2474 Error *local_err = NULL;
2475 PCDIMMDevice *dimm = PC_DIMM(dev);
2476 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2477 MemoryRegion *mr = ddc->get_memory_region(dimm);
2478 uint64_t size = memory_region_size(mr);
2479 uint64_t addr;
2480
2481 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2482 if (local_err) {
2483 goto out;
2484 }
2485
2486 spapr_del_lmbs(dev, addr, size, &error_abort);
2487 out:
2488 error_propagate(errp, local_err);
2489 }
2490
2491 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2492 sPAPRMachineState *spapr)
2493 {
2494 PowerPCCPU *cpu = POWERPC_CPU(cs);
2495 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2496 int id = ppc_get_vcpu_dt_id(cpu);
2497 void *fdt;
2498 int offset, fdt_size;
2499 char *nodename;
2500
2501 fdt = create_device_tree(&fdt_size);
2502 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2503 offset = fdt_add_subnode(fdt, 0, nodename);
2504
2505 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2506 g_free(nodename);
2507
2508 *fdt_offset = offset;
2509 return fdt;
2510 }
2511
2512 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2513 Error **errp)
2514 {
2515 MachineState *ms = MACHINE(qdev_get_machine());
2516 CPUCore *cc = CPU_CORE(dev);
2517 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
2518
2519 core_slot->cpu = NULL;
2520 object_unparent(OBJECT(dev));
2521 }
2522
2523 static void spapr_core_release(DeviceState *dev, void *opaque)
2524 {
2525 HotplugHandler *hotplug_ctrl;
2526
2527 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2528 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2529 }
2530
2531 static
2532 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
2533 Error **errp)
2534 {
2535 int index;
2536 sPAPRDRConnector *drc;
2537 sPAPRDRConnectorClass *drck;
2538 Error *local_err = NULL;
2539 CPUCore *cc = CPU_CORE(dev);
2540 int smt = kvmppc_smt_threads();
2541
2542 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
2543 error_setg(errp, "Unable to find CPU core with core-id: %d",
2544 cc->core_id);
2545 return;
2546 }
2547 if (index == 0) {
2548 error_setg(errp, "Boot CPU core may not be unplugged");
2549 return;
2550 }
2551
2552 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2553 g_assert(drc);
2554
2555 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2556 drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
2557 if (local_err) {
2558 error_propagate(errp, local_err);
2559 return;
2560 }
2561
2562 spapr_hotplug_req_remove_by_index(drc);
2563 }
2564
2565 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2566 Error **errp)
2567 {
2568 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
2569 MachineClass *mc = MACHINE_GET_CLASS(spapr);
2570 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
2571 CPUCore *cc = CPU_CORE(dev);
2572 CPUState *cs = CPU(core->threads);
2573 sPAPRDRConnector *drc;
2574 Error *local_err = NULL;
2575 void *fdt = NULL;
2576 int fdt_offset = 0;
2577 int smt = kvmppc_smt_threads();
2578 CPUArchId *core_slot;
2579 int index;
2580
2581 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2582 if (!core_slot) {
2583 error_setg(errp, "Unable to find CPU core with core-id: %d",
2584 cc->core_id);
2585 return;
2586 }
2587 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2588
2589 g_assert(drc || !mc->has_hotpluggable_cpus);
2590
2591 /*
2592 * Setup CPU DT entries only for hotplugged CPUs. For boot time or
2593 * coldplugged CPUs DT entries are setup in spapr_build_fdt().
2594 */
2595 if (dev->hotplugged) {
2596 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
2597 }
2598
2599 if (drc) {
2600 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2601 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
2602 if (local_err) {
2603 g_free(fdt);
2604 error_propagate(errp, local_err);
2605 return;
2606 }
2607 }
2608
2609 if (dev->hotplugged) {
2610 /*
2611 * Send hotplug notification interrupt to the guest only in case
2612 * of hotplugged CPUs.
2613 */
2614 spapr_hotplug_req_add_by_index(drc);
2615 } else {
2616 /*
2617 * Set the right DRC states for cold plugged CPU.
2618 */
2619 if (drc) {
2620 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2621 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2622 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2623 }
2624 }
2625 core_slot->cpu = OBJECT(dev);
2626 }
2627
2628 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2629 Error **errp)
2630 {
2631 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
2632 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
2633 Error *local_err = NULL;
2634 CPUCore *cc = CPU_CORE(dev);
2635 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
2636 const char *type = object_get_typename(OBJECT(dev));
2637 CPUArchId *core_slot;
2638 int index;
2639
2640 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
2641 error_setg(&local_err, "CPU hotplug not supported for this machine");
2642 goto out;
2643 }
2644
2645 if (strcmp(base_core_type, type)) {
2646 error_setg(&local_err, "CPU core type should be %s", base_core_type);
2647 goto out;
2648 }
2649
2650 if (cc->core_id % smp_threads) {
2651 error_setg(&local_err, "invalid core id %d", cc->core_id);
2652 goto out;
2653 }
2654
2655 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2656 if (!core_slot) {
2657 error_setg(&local_err, "core id %d out of range", cc->core_id);
2658 goto out;
2659 }
2660
2661 if (core_slot->cpu) {
2662 error_setg(&local_err, "core %d already populated", cc->core_id);
2663 goto out;
2664 }
2665
2666 out:
2667 g_free(base_core_type);
2668 error_propagate(errp, local_err);
2669 }
2670
2671 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2672 DeviceState *dev, Error **errp)
2673 {
2674 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2675
2676 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2677 int node;
2678
2679 if (!smc->dr_lmb_enabled) {
2680 error_setg(errp, "Memory hotplug not supported for this machine");
2681 return;
2682 }
2683 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2684 if (*errp) {
2685 return;
2686 }
2687 if (node < 0 || node >= MAX_NODES) {
2688 error_setg(errp, "Invaild node %d", node);
2689 return;
2690 }
2691
2692 /*
2693 * Currently PowerPC kernel doesn't allow hot-adding memory to
2694 * memory-less node, but instead will silently add the memory
2695 * to the first node that has some memory. This causes two
2696 * unexpected behaviours for the user.
2697 *
2698 * - Memory gets hotplugged to a different node than what the user
2699 * specified.
2700 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2701 * to memory-less node, a reboot will set things accordingly
2702 * and the previously hotplugged memory now ends in the right node.
2703 * This appears as if some memory moved from one node to another.
2704 *
2705 * So until kernel starts supporting memory hotplug to memory-less
2706 * nodes, just prevent such attempts upfront in QEMU.
2707 */
2708 if (nb_numa_nodes && !numa_info[node].node_mem) {
2709 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2710 node);
2711 return;
2712 }
2713
2714 spapr_memory_plug(hotplug_dev, dev, node, errp);
2715 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2716 spapr_core_plug(hotplug_dev, dev, errp);
2717 }
2718 }
2719
2720 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2721 DeviceState *dev, Error **errp)
2722 {
2723 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2724 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2725
2726 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2727 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2728 spapr_memory_unplug(hotplug_dev, dev, errp);
2729 } else {
2730 error_setg(errp, "Memory hot unplug not supported for this guest");
2731 }
2732 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2733 if (!mc->has_hotpluggable_cpus) {
2734 error_setg(errp, "CPU hot unplug not supported on this machine");
2735 return;
2736 }
2737 spapr_core_unplug(hotplug_dev, dev, errp);
2738 }
2739 }
2740
2741 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
2742 DeviceState *dev, Error **errp)
2743 {
2744 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2745 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2746
2747 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2748 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2749 spapr_memory_unplug_request(hotplug_dev, dev, errp);
2750 } else {
2751 /* NOTE: this means there is a window after guest reset, prior to
2752 * CAS negotiation, where unplug requests will fail due to the
2753 * capability not being detected yet. This is a bit different than
2754 * the case with PCI unplug, where the events will be queued and
2755 * eventually handled by the guest after boot
2756 */
2757 error_setg(errp, "Memory hot unplug not supported for this guest");
2758 }
2759 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2760 if (!mc->has_hotpluggable_cpus) {
2761 error_setg(errp, "CPU hot unplug not supported on this machine");
2762 return;
2763 }
2764 spapr_core_unplug_request(hotplug_dev, dev, errp);
2765 }
2766 }
2767
2768 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2769 DeviceState *dev, Error **errp)
2770 {
2771 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2772 spapr_core_pre_plug(hotplug_dev, dev, errp);
2773 }
2774 }
2775
2776 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2777 DeviceState *dev)
2778 {
2779 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2780 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2781 return HOTPLUG_HANDLER(machine);
2782 }
2783 return NULL;
2784 }
2785
2786 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2787 {
2788 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2789 * socket means much for the paravirtualized PAPR platform) */
2790 return cpu_index / smp_threads / smp_cores;
2791 }
2792
2793 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
2794 {
2795 int i;
2796 int spapr_max_cores = max_cpus / smp_threads;
2797 MachineClass *mc = MACHINE_GET_CLASS(machine);
2798
2799 if (!mc->has_hotpluggable_cpus) {
2800 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
2801 }
2802 if (machine->possible_cpus) {
2803 assert(machine->possible_cpus->len == spapr_max_cores);
2804 return machine->possible_cpus;
2805 }
2806
2807 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2808 sizeof(CPUArchId) * spapr_max_cores);
2809 machine->possible_cpus->len = spapr_max_cores;
2810 for (i = 0; i < machine->possible_cpus->len; i++) {
2811 int core_id = i * smp_threads;
2812
2813 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
2814 machine->possible_cpus->cpus[i].arch_id = core_id;
2815 machine->possible_cpus->cpus[i].props.has_core_id = true;
2816 machine->possible_cpus->cpus[i].props.core_id = core_id;
2817 /* TODO: add 'has_node/node' here to describe
2818 to which node core belongs */
2819 }
2820 return machine->possible_cpus;
2821 }
2822
2823 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
2824 uint64_t *buid, hwaddr *pio,
2825 hwaddr *mmio32, hwaddr *mmio64,
2826 unsigned n_dma, uint32_t *liobns, Error **errp)
2827 {
2828 /*
2829 * New-style PHB window placement.
2830 *
2831 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
2832 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
2833 * windows.
2834 *
2835 * Some guest kernels can't work with MMIO windows above 1<<46
2836 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
2837 *
2838 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
2839 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
2840 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
2841 * 1TiB 64-bit MMIO windows for each PHB.
2842 */
2843 const uint64_t base_buid = 0x800000020000000ULL;
2844 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
2845 SPAPR_PCI_MEM64_WIN_SIZE - 1)
2846 int i;
2847
2848 /* Sanity check natural alignments */
2849 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2850 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2851 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
2852 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
2853 /* Sanity check bounds */
2854 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
2855 SPAPR_PCI_MEM32_WIN_SIZE);
2856 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
2857 SPAPR_PCI_MEM64_WIN_SIZE);
2858
2859 if (index >= SPAPR_MAX_PHBS) {
2860 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
2861 SPAPR_MAX_PHBS - 1);
2862 return;
2863 }
2864
2865 *buid = base_buid + index;
2866 for (i = 0; i < n_dma; ++i) {
2867 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2868 }
2869
2870 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
2871 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
2872 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
2873 }
2874
2875 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2876 {
2877 MachineClass *mc = MACHINE_CLASS(oc);
2878 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2879 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2880 NMIClass *nc = NMI_CLASS(oc);
2881 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2882 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
2883
2884 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2885
2886 /*
2887 * We set up the default / latest behaviour here. The class_init
2888 * functions for the specific versioned machine types can override
2889 * these details for backwards compatibility
2890 */
2891 mc->init = ppc_spapr_init;
2892 mc->reset = ppc_spapr_reset;
2893 mc->block_default_type = IF_SCSI;
2894 mc->max_cpus = 255;
2895 mc->no_parallel = 1;
2896 mc->default_boot_order = "";
2897 mc->default_ram_size = 512 * M_BYTE;
2898 mc->kvm_type = spapr_kvm_type;
2899 mc->has_dynamic_sysbus = true;
2900 mc->pci_allow_0_address = true;
2901 mc->get_hotplug_handler = spapr_get_hotplug_handler;
2902 hc->pre_plug = spapr_machine_device_pre_plug;
2903 hc->plug = spapr_machine_device_plug;
2904 hc->unplug = spapr_machine_device_unplug;
2905 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2906 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
2907 hc->unplug_request = spapr_machine_device_unplug_request;
2908
2909 smc->dr_lmb_enabled = true;
2910 smc->tcg_default_cpu = "POWER8";
2911 mc->has_hotpluggable_cpus = true;
2912 fwc->get_dev_path = spapr_get_fw_dev_path;
2913 nc->nmi_monitor_handler = spapr_nmi;
2914 smc->phb_placement = spapr_phb_placement;
2915 vhc->hypercall = emulate_spapr_hypercall;
2916 }
2917
2918 static const TypeInfo spapr_machine_info = {
2919 .name = TYPE_SPAPR_MACHINE,
2920 .parent = TYPE_MACHINE,
2921 .abstract = true,
2922 .instance_size = sizeof(sPAPRMachineState),
2923 .instance_init = spapr_machine_initfn,
2924 .instance_finalize = spapr_machine_finalizefn,
2925 .class_size = sizeof(sPAPRMachineClass),
2926 .class_init = spapr_machine_class_init,
2927 .interfaces = (InterfaceInfo[]) {
2928 { TYPE_FW_PATH_PROVIDER },
2929 { TYPE_NMI },
2930 { TYPE_HOTPLUG_HANDLER },
2931 { TYPE_PPC_VIRTUAL_HYPERVISOR },
2932 { }
2933 },
2934 };
2935
2936 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2937 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2938 void *data) \
2939 { \
2940 MachineClass *mc = MACHINE_CLASS(oc); \
2941 spapr_machine_##suffix##_class_options(mc); \
2942 if (latest) { \
2943 mc->alias = "pseries"; \
2944 mc->is_default = 1; \
2945 } \
2946 } \
2947 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2948 { \
2949 MachineState *machine = MACHINE(obj); \
2950 spapr_machine_##suffix##_instance_options(machine); \
2951 } \
2952 static const TypeInfo spapr_machine_##suffix##_info = { \
2953 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2954 .parent = TYPE_SPAPR_MACHINE, \
2955 .class_init = spapr_machine_##suffix##_class_init, \
2956 .instance_init = spapr_machine_##suffix##_instance_init, \
2957 }; \
2958 static void spapr_machine_register_##suffix(void) \
2959 { \
2960 type_register(&spapr_machine_##suffix##_info); \
2961 } \
2962 type_init(spapr_machine_register_##suffix)
2963
2964 /*
2965 * pseries-2.9
2966 */
2967 static void spapr_machine_2_9_instance_options(MachineState *machine)
2968 {
2969 }
2970
2971 static void spapr_machine_2_9_class_options(MachineClass *mc)
2972 {
2973 /* Defaults for the latest behaviour inherited from the base class */
2974 }
2975
2976 DEFINE_SPAPR_MACHINE(2_9, "2.9", true);
2977
2978 /*
2979 * pseries-2.8
2980 */
2981 #define SPAPR_COMPAT_2_8 \
2982 HW_COMPAT_2_8
2983
2984 static void spapr_machine_2_8_instance_options(MachineState *machine)
2985 {
2986 spapr_machine_2_9_instance_options(machine);
2987 }
2988
2989 static void spapr_machine_2_8_class_options(MachineClass *mc)
2990 {
2991 spapr_machine_2_9_class_options(mc);
2992 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
2993 }
2994
2995 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
2996
2997 /*
2998 * pseries-2.7
2999 */
3000 #define SPAPR_COMPAT_2_7 \
3001 HW_COMPAT_2_7 \
3002 { \
3003 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3004 .property = "mem_win_size", \
3005 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3006 }, \
3007 { \
3008 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3009 .property = "mem64_win_size", \
3010 .value = "0", \
3011 }, \
3012 { \
3013 .driver = TYPE_POWERPC_CPU, \
3014 .property = "pre-2.8-migration", \
3015 .value = "on", \
3016 }, \
3017 { \
3018 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3019 .property = "pre-2.8-migration", \
3020 .value = "on", \
3021 },
3022
3023 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3024 uint64_t *buid, hwaddr *pio,
3025 hwaddr *mmio32, hwaddr *mmio64,
3026 unsigned n_dma, uint32_t *liobns, Error **errp)
3027 {
3028 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3029 const uint64_t base_buid = 0x800000020000000ULL;
3030 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
3031 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
3032 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
3033 const uint32_t max_index = 255;
3034 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
3035
3036 uint64_t ram_top = MACHINE(spapr)->ram_size;
3037 hwaddr phb0_base, phb_base;
3038 int i;
3039
3040 /* Do we have hotpluggable memory? */
3041 if (MACHINE(spapr)->maxram_size > ram_top) {
3042 /* Can't just use maxram_size, because there may be an
3043 * alignment gap between normal and hotpluggable memory
3044 * regions */
3045 ram_top = spapr->hotplug_memory.base +
3046 memory_region_size(&spapr->hotplug_memory.mr);
3047 }
3048
3049 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3050
3051 if (index > max_index) {
3052 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3053 max_index);
3054 return;
3055 }
3056
3057 *buid = base_buid + index;
3058 for (i = 0; i < n_dma; ++i) {
3059 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3060 }
3061
3062 phb_base = phb0_base + index * phb_spacing;
3063 *pio = phb_base + pio_offset;
3064 *mmio32 = phb_base + mmio_offset;
3065 /*
3066 * We don't set the 64-bit MMIO window, relying on the PHB's
3067 * fallback behaviour of automatically splitting a large "32-bit"
3068 * window into contiguous 32-bit and 64-bit windows
3069 */
3070 }
3071
3072 static void spapr_machine_2_7_instance_options(MachineState *machine)
3073 {
3074 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3075
3076 spapr_machine_2_8_instance_options(machine);
3077 spapr->use_hotplug_event_source = false;
3078 }
3079
3080 static void spapr_machine_2_7_class_options(MachineClass *mc)
3081 {
3082 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3083
3084 spapr_machine_2_8_class_options(mc);
3085 smc->tcg_default_cpu = "POWER7";
3086 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3087 smc->phb_placement = phb_placement_2_7;
3088 }
3089
3090 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3091
3092 /*
3093 * pseries-2.6
3094 */
3095 #define SPAPR_COMPAT_2_6 \
3096 HW_COMPAT_2_6 \
3097 { \
3098 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3099 .property = "ddw",\
3100 .value = stringify(off),\
3101 },
3102
3103 static void spapr_machine_2_6_instance_options(MachineState *machine)
3104 {
3105 spapr_machine_2_7_instance_options(machine);
3106 }
3107
3108 static void spapr_machine_2_6_class_options(MachineClass *mc)
3109 {
3110 spapr_machine_2_7_class_options(mc);
3111 mc->has_hotpluggable_cpus = false;
3112 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3113 }
3114
3115 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3116
3117 /*
3118 * pseries-2.5
3119 */
3120 #define SPAPR_COMPAT_2_5 \
3121 HW_COMPAT_2_5 \
3122 { \
3123 .driver = "spapr-vlan", \
3124 .property = "use-rx-buffer-pools", \
3125 .value = "off", \
3126 },
3127
3128 static void spapr_machine_2_5_instance_options(MachineState *machine)
3129 {
3130 spapr_machine_2_6_instance_options(machine);
3131 }
3132
3133 static void spapr_machine_2_5_class_options(MachineClass *mc)
3134 {
3135 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3136
3137 spapr_machine_2_6_class_options(mc);
3138 smc->use_ohci_by_default = true;
3139 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3140 }
3141
3142 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3143
3144 /*
3145 * pseries-2.4
3146 */
3147 #define SPAPR_COMPAT_2_4 \
3148 HW_COMPAT_2_4
3149
3150 static void spapr_machine_2_4_instance_options(MachineState *machine)
3151 {
3152 spapr_machine_2_5_instance_options(machine);
3153 }
3154
3155 static void spapr_machine_2_4_class_options(MachineClass *mc)
3156 {
3157 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3158
3159 spapr_machine_2_5_class_options(mc);
3160 smc->dr_lmb_enabled = false;
3161 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3162 }
3163
3164 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3165
3166 /*
3167 * pseries-2.3
3168 */
3169 #define SPAPR_COMPAT_2_3 \
3170 HW_COMPAT_2_3 \
3171 {\
3172 .driver = "spapr-pci-host-bridge",\
3173 .property = "dynamic-reconfiguration",\
3174 .value = "off",\
3175 },
3176
3177 static void spapr_machine_2_3_instance_options(MachineState *machine)
3178 {
3179 spapr_machine_2_4_instance_options(machine);
3180 savevm_skip_section_footers();
3181 global_state_set_optional();
3182 savevm_skip_configuration();
3183 }
3184
3185 static void spapr_machine_2_3_class_options(MachineClass *mc)
3186 {
3187 spapr_machine_2_4_class_options(mc);
3188 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3189 }
3190 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3191
3192 /*
3193 * pseries-2.2
3194 */
3195
3196 #define SPAPR_COMPAT_2_2 \
3197 HW_COMPAT_2_2 \
3198 {\
3199 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3200 .property = "mem_win_size",\
3201 .value = "0x20000000",\
3202 },
3203
3204 static void spapr_machine_2_2_instance_options(MachineState *machine)
3205 {
3206 spapr_machine_2_3_instance_options(machine);
3207 machine->suppress_vmdesc = true;
3208 }
3209
3210 static void spapr_machine_2_2_class_options(MachineClass *mc)
3211 {
3212 spapr_machine_2_3_class_options(mc);
3213 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
3214 }
3215 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
3216
3217 /*
3218 * pseries-2.1
3219 */
3220 #define SPAPR_COMPAT_2_1 \
3221 HW_COMPAT_2_1
3222
3223 static void spapr_machine_2_1_instance_options(MachineState *machine)
3224 {
3225 spapr_machine_2_2_instance_options(machine);
3226 }
3227
3228 static void spapr_machine_2_1_class_options(MachineClass *mc)
3229 {
3230 spapr_machine_2_2_class_options(mc);
3231 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
3232 }
3233 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
3234
3235 static void spapr_machine_register_types(void)
3236 {
3237 type_register_static(&spapr_machine_info);
3238 }
3239
3240 type_init(spapr_machine_register_types)
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