2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "sysemu/sysemu.h"
29 #include "hw/fw-path-provider.h"
32 #include "sysemu/block-backend.h"
33 #include "sysemu/cpus.h"
34 #include "sysemu/kvm.h"
36 #include "mmu-hash64.h"
39 #include "hw/boards.h"
40 #include "hw/ppc/ppc.h"
41 #include "hw/loader.h"
43 #include "hw/ppc/spapr.h"
44 #include "hw/ppc/spapr_vio.h"
45 #include "hw/pci-host/spapr.h"
46 #include "hw/ppc/xics.h"
47 #include "hw/pci/msi.h"
49 #include "hw/pci/pci.h"
50 #include "hw/scsi/scsi.h"
51 #include "hw/virtio/virtio-scsi.h"
53 #include "exec/address-spaces.h"
55 #include "qemu/config-file.h"
56 #include "qemu/error-report.h"
60 #include "hw/compat.h"
64 /* SLOF memory layout:
66 * SLOF raw image loaded at 0, copies its romfs right below the flat
67 * device-tree, then position SLOF itself 31M below that
69 * So we set FW_OVERHEAD to 40MB which should account for all of that
72 * We load our kernel at 4M, leaving space for SLOF initial image
74 #define FDT_MAX_SIZE 0x40000
75 #define RTAS_MAX_SIZE 0x10000
76 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
77 #define FW_MAX_SIZE 0x400000
78 #define FW_FILE_NAME "slof.bin"
79 #define FW_OVERHEAD 0x2800000
80 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
82 #define MIN_RMA_SLOF 128UL
84 #define TIMEBASE_FREQ 512000000ULL
88 #define PHANDLE_XICP 0x00001111
90 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
92 typedef struct sPAPRMachineState sPAPRMachineState
;
94 #define TYPE_SPAPR_MACHINE "spapr-machine"
95 #define SPAPR_MACHINE(obj) \
96 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
101 struct sPAPRMachineState
{
103 MachineState parent_obj
;
109 sPAPREnvironment
*spapr
;
111 static XICSState
*try_create_xics(const char *type
, int nr_servers
,
116 dev
= qdev_create(NULL
, type
);
117 qdev_prop_set_uint32(dev
, "nr_servers", nr_servers
);
118 qdev_prop_set_uint32(dev
, "nr_irqs", nr_irqs
);
119 if (qdev_init(dev
) < 0) {
123 return XICS_COMMON(dev
);
126 static XICSState
*xics_system_init(int nr_servers
, int nr_irqs
)
128 XICSState
*icp
= NULL
;
131 QemuOpts
*machine_opts
= qemu_get_machine_opts();
132 bool irqchip_allowed
= qemu_opt_get_bool(machine_opts
,
133 "kernel_irqchip", true);
134 bool irqchip_required
= qemu_opt_get_bool(machine_opts
,
135 "kernel_irqchip", false);
136 if (irqchip_allowed
) {
137 icp
= try_create_xics(TYPE_KVM_XICS
, nr_servers
, nr_irqs
);
140 if (irqchip_required
&& !icp
) {
141 perror("Failed to create in-kernel XICS\n");
147 icp
= try_create_xics(TYPE_XICS
, nr_servers
, nr_irqs
);
151 perror("Failed to create XICS\n");
158 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
162 uint32_t servers_prop
[smt_threads
];
163 uint32_t gservers_prop
[smt_threads
* 2];
164 int index
= ppc_get_vcpu_dt_id(cpu
);
166 if (cpu
->cpu_version
) {
167 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->cpu_version
);
173 /* Build interrupt servers and gservers properties */
174 for (i
= 0; i
< smt_threads
; i
++) {
175 servers_prop
[i
] = cpu_to_be32(index
+ i
);
176 /* Hack, direct the group queues back to cpu 0 */
177 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
178 gservers_prop
[i
*2 + 1] = 0;
180 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
181 servers_prop
, sizeof(servers_prop
));
185 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
186 gservers_prop
, sizeof(gservers_prop
));
191 static int spapr_fixup_cpu_dt(void *fdt
, sPAPREnvironment
*spapr
)
193 int ret
= 0, offset
, cpus_offset
;
196 int smt
= kvmppc_smt_threads();
197 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
200 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
201 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
202 int index
= ppc_get_vcpu_dt_id(cpu
);
203 uint32_t associativity
[] = {cpu_to_be32(0x5),
207 cpu_to_be32(cs
->numa_node
),
210 if ((index
% smt
) != 0) {
214 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
216 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
217 if (cpus_offset
< 0) {
218 cpus_offset
= fdt_add_subnode(fdt
, fdt_path_offset(fdt
, "/"),
220 if (cpus_offset
< 0) {
224 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
226 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
232 if (nb_numa_nodes
> 1) {
233 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
234 sizeof(associativity
));
240 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
241 pft_size_prop
, sizeof(pft_size_prop
));
246 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
,
247 ppc_get_compat_smt_threads(cpu
));
256 static size_t create_page_sizes_prop(CPUPPCState
*env
, uint32_t *prop
,
259 size_t maxcells
= maxsize
/ sizeof(uint32_t);
263 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
264 struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
266 if (!sps
->page_shift
) {
269 for (count
= 0; count
< PPC_PAGE_SIZES_MAX_SZ
; count
++) {
270 if (sps
->enc
[count
].page_shift
== 0) {
274 if ((p
- prop
) >= (maxcells
- 3 - count
* 2)) {
277 *(p
++) = cpu_to_be32(sps
->page_shift
);
278 *(p
++) = cpu_to_be32(sps
->slb_enc
);
279 *(p
++) = cpu_to_be32(count
);
280 for (j
= 0; j
< count
; j
++) {
281 *(p
++) = cpu_to_be32(sps
->enc
[j
].page_shift
);
282 *(p
++) = cpu_to_be32(sps
->enc
[j
].pte_enc
);
286 return (p
- prop
) * sizeof(uint32_t);
289 static hwaddr
spapr_node0_size(void)
293 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
294 if (numa_info
[i
].node_mem
) {
295 return MIN(pow2floor(numa_info
[i
].node_mem
), ram_size
);
306 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
307 #exp, fdt_strerror(ret)); \
312 static void add_str(GString
*s
, const gchar
*s1
)
314 g_string_append_len(s
, s1
, strlen(s1
) + 1);
317 static void *spapr_create_fdt_skel(hwaddr initrd_base
,
321 const char *boot_device
,
322 const char *kernel_cmdline
,
327 uint32_t start_prop
= cpu_to_be32(initrd_base
);
328 uint32_t end_prop
= cpu_to_be32(initrd_base
+ initrd_size
);
329 GString
*hypertas
= g_string_sized_new(256);
330 GString
*qemu_hypertas
= g_string_sized_new(256);
331 uint32_t refpoints
[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
332 uint32_t interrupt_server_ranges_prop
[] = {0, cpu_to_be32(smp_cpus
)};
333 int smt
= kvmppc_smt_threads();
334 unsigned char vec5
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
335 QemuOpts
*opts
= qemu_opts_find(qemu_find_opts("smp-opts"), NULL
);
336 unsigned sockets
= opts
? qemu_opt_get_number(opts
, "sockets", 0) : 0;
337 uint32_t cpus_per_socket
= sockets
? (smp_cpus
/ sockets
) : 1;
340 add_str(hypertas
, "hcall-pft");
341 add_str(hypertas
, "hcall-term");
342 add_str(hypertas
, "hcall-dabr");
343 add_str(hypertas
, "hcall-interrupt");
344 add_str(hypertas
, "hcall-tce");
345 add_str(hypertas
, "hcall-vio");
346 add_str(hypertas
, "hcall-splpar");
347 add_str(hypertas
, "hcall-bulk");
348 add_str(hypertas
, "hcall-set-mode");
349 add_str(qemu_hypertas
, "hcall-memop1");
351 fdt
= g_malloc0(FDT_MAX_SIZE
);
352 _FDT((fdt_create(fdt
, FDT_MAX_SIZE
)));
355 _FDT((fdt_add_reservemap_entry(fdt
, KERNEL_LOAD_ADDR
, kernel_size
)));
358 _FDT((fdt_add_reservemap_entry(fdt
, initrd_base
, initrd_size
)));
360 _FDT((fdt_finish_reservemap(fdt
)));
363 _FDT((fdt_begin_node(fdt
, "")));
364 _FDT((fdt_property_string(fdt
, "device_type", "chrp")));
365 _FDT((fdt_property_string(fdt
, "model", "IBM pSeries (emulated by qemu)")));
366 _FDT((fdt_property_string(fdt
, "compatible", "qemu,pseries")));
369 * Add info to guest to indentify which host is it being run on
370 * and what is the uuid of the guest
372 if (kvmppc_get_host_model(&buf
)) {
373 _FDT((fdt_property_string(fdt
, "host-model", buf
)));
376 if (kvmppc_get_host_serial(&buf
)) {
377 _FDT((fdt_property_string(fdt
, "host-serial", buf
)));
381 buf
= g_strdup_printf(UUID_FMT
, qemu_uuid
[0], qemu_uuid
[1],
382 qemu_uuid
[2], qemu_uuid
[3], qemu_uuid
[4],
383 qemu_uuid
[5], qemu_uuid
[6], qemu_uuid
[7],
384 qemu_uuid
[8], qemu_uuid
[9], qemu_uuid
[10],
385 qemu_uuid
[11], qemu_uuid
[12], qemu_uuid
[13],
386 qemu_uuid
[14], qemu_uuid
[15]);
388 _FDT((fdt_property_string(fdt
, "vm,uuid", buf
)));
391 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x2)));
392 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x2)));
395 _FDT((fdt_begin_node(fdt
, "chosen")));
397 /* Set Form1_affinity */
398 _FDT((fdt_property(fdt
, "ibm,architecture-vec-5", vec5
, sizeof(vec5
))));
400 _FDT((fdt_property_string(fdt
, "bootargs", kernel_cmdline
)));
401 _FDT((fdt_property(fdt
, "linux,initrd-start",
402 &start_prop
, sizeof(start_prop
))));
403 _FDT((fdt_property(fdt
, "linux,initrd-end",
404 &end_prop
, sizeof(end_prop
))));
406 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
407 cpu_to_be64(kernel_size
) };
409 _FDT((fdt_property(fdt
, "qemu,boot-kernel", &kprop
, sizeof(kprop
))));
411 _FDT((fdt_property(fdt
, "qemu,boot-kernel-le", NULL
, 0)));
415 _FDT((fdt_property_string(fdt
, "qemu,boot-device", boot_device
)));
418 _FDT((fdt_property_cell(fdt
, "qemu,boot-menu", boot_menu
)));
420 _FDT((fdt_property_cell(fdt
, "qemu,graphic-width", graphic_width
)));
421 _FDT((fdt_property_cell(fdt
, "qemu,graphic-height", graphic_height
)));
422 _FDT((fdt_property_cell(fdt
, "qemu,graphic-depth", graphic_depth
)));
424 _FDT((fdt_end_node(fdt
)));
427 _FDT((fdt_begin_node(fdt
, "cpus")));
429 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
430 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
433 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
434 CPUPPCState
*env
= &cpu
->env
;
435 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
436 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
437 int index
= ppc_get_vcpu_dt_id(cpu
);
439 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
440 0xffffffff, 0xffffffff};
441 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ
;
442 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
443 uint32_t page_sizes_prop
[64];
444 size_t page_sizes_prop_size
;
446 if ((index
% smt
) != 0) {
450 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
452 _FDT((fdt_begin_node(fdt
, nodename
)));
456 _FDT((fdt_property_cell(fdt
, "reg", index
)));
457 _FDT((fdt_property_string(fdt
, "device_type", "cpu")));
459 _FDT((fdt_property_cell(fdt
, "cpu-version", env
->spr
[SPR_PVR
])));
460 _FDT((fdt_property_cell(fdt
, "d-cache-block-size",
461 env
->dcache_line_size
)));
462 _FDT((fdt_property_cell(fdt
, "d-cache-line-size",
463 env
->dcache_line_size
)));
464 _FDT((fdt_property_cell(fdt
, "i-cache-block-size",
465 env
->icache_line_size
)));
466 _FDT((fdt_property_cell(fdt
, "i-cache-line-size",
467 env
->icache_line_size
)));
469 if (pcc
->l1_dcache_size
) {
470 _FDT((fdt_property_cell(fdt
, "d-cache-size", pcc
->l1_dcache_size
)));
472 fprintf(stderr
, "Warning: Unknown L1 dcache size for cpu\n");
474 if (pcc
->l1_icache_size
) {
475 _FDT((fdt_property_cell(fdt
, "i-cache-size", pcc
->l1_icache_size
)));
477 fprintf(stderr
, "Warning: Unknown L1 icache size for cpu\n");
480 _FDT((fdt_property_cell(fdt
, "timebase-frequency", tbfreq
)));
481 _FDT((fdt_property_cell(fdt
, "clock-frequency", cpufreq
)));
482 _FDT((fdt_property_cell(fdt
, "ibm,slb-size", env
->slb_nr
)));
483 _FDT((fdt_property_string(fdt
, "status", "okay")));
484 _FDT((fdt_property(fdt
, "64-bit", NULL
, 0)));
486 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
487 _FDT((fdt_property(fdt
, "ibm,purr", NULL
, 0)));
490 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
491 _FDT((fdt_property(fdt
, "ibm,processor-segment-sizes",
492 segs
, sizeof(segs
))));
495 /* Advertise VMX/VSX (vector extensions) if available
496 * 0 / no property == no vector extensions
497 * 1 == VMX / Altivec available
498 * 2 == VSX available */
499 if (env
->insns_flags
& PPC_ALTIVEC
) {
500 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
502 _FDT((fdt_property_cell(fdt
, "ibm,vmx", vmx
)));
505 /* Advertise DFP (Decimal Floating Point) if available
506 * 0 / no property == no DFP
507 * 1 == DFP available */
508 if (env
->insns_flags2
& PPC2_DFP
) {
509 _FDT((fdt_property_cell(fdt
, "ibm,dfp", 1)));
512 page_sizes_prop_size
= create_page_sizes_prop(env
, page_sizes_prop
,
513 sizeof(page_sizes_prop
));
514 if (page_sizes_prop_size
) {
515 _FDT((fdt_property(fdt
, "ibm,segment-page-sizes",
516 page_sizes_prop
, page_sizes_prop_size
)));
519 _FDT((fdt_property_cell(fdt
, "ibm,chip-id",
520 cs
->cpu_index
/ cpus_per_socket
)));
522 _FDT((fdt_end_node(fdt
)));
525 _FDT((fdt_end_node(fdt
)));
528 _FDT((fdt_begin_node(fdt
, "rtas")));
530 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
531 add_str(hypertas
, "hcall-multi-tce");
533 _FDT((fdt_property(fdt
, "ibm,hypertas-functions", hypertas
->str
,
535 g_string_free(hypertas
, TRUE
);
536 _FDT((fdt_property(fdt
, "qemu,hypertas-functions", qemu_hypertas
->str
,
537 qemu_hypertas
->len
)));
538 g_string_free(qemu_hypertas
, TRUE
);
540 _FDT((fdt_property(fdt
, "ibm,associativity-reference-points",
541 refpoints
, sizeof(refpoints
))));
543 _FDT((fdt_property_cell(fdt
, "rtas-error-log-max", RTAS_ERROR_LOG_MAX
)));
546 * According to PAPR, rtas ibm,os-term does not guarantee a return
547 * back to the guest cpu.
549 * While an additional ibm,extended-os-term property indicates that
550 * rtas call return will always occur. Set this property.
552 _FDT((fdt_property(fdt
, "ibm,extended-os-term", NULL
, 0)));
554 _FDT((fdt_end_node(fdt
)));
556 /* interrupt controller */
557 _FDT((fdt_begin_node(fdt
, "interrupt-controller")));
559 _FDT((fdt_property_string(fdt
, "device_type",
560 "PowerPC-External-Interrupt-Presentation")));
561 _FDT((fdt_property_string(fdt
, "compatible", "IBM,ppc-xicp")));
562 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
563 _FDT((fdt_property(fdt
, "ibm,interrupt-server-ranges",
564 interrupt_server_ranges_prop
,
565 sizeof(interrupt_server_ranges_prop
))));
566 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 2)));
567 _FDT((fdt_property_cell(fdt
, "linux,phandle", PHANDLE_XICP
)));
568 _FDT((fdt_property_cell(fdt
, "phandle", PHANDLE_XICP
)));
570 _FDT((fdt_end_node(fdt
)));
573 _FDT((fdt_begin_node(fdt
, "vdevice")));
575 _FDT((fdt_property_string(fdt
, "device_type", "vdevice")));
576 _FDT((fdt_property_string(fdt
, "compatible", "IBM,vdevice")));
577 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
578 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
579 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 0x2)));
580 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
582 _FDT((fdt_end_node(fdt
)));
585 spapr_events_fdt_skel(fdt
, epow_irq
);
587 /* /hypervisor node */
589 uint8_t hypercall
[16];
591 /* indicate KVM hypercall interface */
592 _FDT((fdt_begin_node(fdt
, "hypervisor")));
593 _FDT((fdt_property_string(fdt
, "compatible", "linux,kvm")));
594 if (kvmppc_has_cap_fixup_hcalls()) {
596 * Older KVM versions with older guest kernels were broken with the
597 * magic page, don't allow the guest to map it.
599 kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
601 _FDT((fdt_property(fdt
, "hcall-instructions", hypercall
,
602 sizeof(hypercall
))));
604 _FDT((fdt_end_node(fdt
)));
607 _FDT((fdt_end_node(fdt
))); /* close root node */
608 _FDT((fdt_finish(fdt
)));
613 int spapr_h_cas_compose_response(target_ulong addr
, target_ulong size
)
615 void *fdt
, *fdt_skel
;
616 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
620 /* Create sceleton */
621 fdt_skel
= g_malloc0(size
);
622 _FDT((fdt_create(fdt_skel
, size
)));
623 _FDT((fdt_begin_node(fdt_skel
, "")));
624 _FDT((fdt_end_node(fdt_skel
)));
625 _FDT((fdt_finish(fdt_skel
)));
626 fdt
= g_malloc0(size
);
627 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
630 /* Fix skeleton up */
631 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
633 /* Pack resulting tree */
634 _FDT((fdt_pack(fdt
)));
636 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
637 trace_spapr_cas_failed(size
);
641 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
642 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
643 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
649 static void spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
652 uint32_t associativity
[] = {
653 cpu_to_be32(0x4), /* length */
654 cpu_to_be32(0x0), cpu_to_be32(0x0),
655 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
658 uint64_t mem_reg_property
[2];
661 mem_reg_property
[0] = cpu_to_be64(start
);
662 mem_reg_property
[1] = cpu_to_be64(size
);
664 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
665 off
= fdt_add_subnode(fdt
, 0, mem_name
);
667 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
668 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
669 sizeof(mem_reg_property
))));
670 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
671 sizeof(associativity
))));
674 static int spapr_populate_memory(sPAPREnvironment
*spapr
, void *fdt
)
676 hwaddr mem_start
, node_size
;
677 int i
, nb_nodes
= nb_numa_nodes
;
678 NodeInfo
*nodes
= numa_info
;
681 /* No NUMA nodes, assume there is just one node with whole RAM */
682 if (!nb_numa_nodes
) {
684 ramnode
.node_mem
= ram_size
;
688 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
689 if (!nodes
[i
].node_mem
) {
692 if (mem_start
>= ram_size
) {
695 node_size
= nodes
[i
].node_mem
;
696 if (node_size
> ram_size
- mem_start
) {
697 node_size
= ram_size
- mem_start
;
701 /* ppc_spapr_init() checks for rma_size <= node0_size already */
702 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
703 mem_start
+= spapr
->rma_size
;
704 node_size
-= spapr
->rma_size
;
706 for ( ; node_size
; ) {
707 hwaddr sizetmp
= pow2floor(node_size
);
709 /* mem_start != 0 here */
710 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
711 sizetmp
= 1ULL << ctzl(mem_start
);
714 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
715 node_size
-= sizetmp
;
716 mem_start
+= sizetmp
;
723 static void spapr_finalize_fdt(sPAPREnvironment
*spapr
,
734 fdt
= g_malloc(FDT_MAX_SIZE
);
736 /* open out the base tree into a temp buffer for the final tweaks */
737 _FDT((fdt_open_into(spapr
->fdt_skel
, fdt
, FDT_MAX_SIZE
)));
739 ret
= spapr_populate_memory(spapr
, fdt
);
741 fprintf(stderr
, "couldn't setup memory nodes in fdt\n");
745 ret
= spapr_populate_vdevice(spapr
->vio_bus
, fdt
);
747 fprintf(stderr
, "couldn't setup vio devices in fdt\n");
751 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
752 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
756 fprintf(stderr
, "couldn't setup PCI devices in fdt\n");
761 ret
= spapr_rtas_device_tree_setup(fdt
, rtas_addr
, rtas_size
);
763 fprintf(stderr
, "Couldn't set up RTAS device tree properties\n");
766 /* Advertise NUMA via ibm,associativity */
767 ret
= spapr_fixup_cpu_dt(fdt
, spapr
);
769 fprintf(stderr
, "Couldn't finalize CPU device tree properties\n");
772 bootlist
= get_boot_devices_list(&cb
, true);
773 if (cb
&& bootlist
) {
774 int offset
= fdt_path_offset(fdt
, "/chosen");
778 for (i
= 0; i
< cb
; i
++) {
779 if (bootlist
[i
] == '\n') {
784 ret
= fdt_setprop_string(fdt
, offset
, "qemu,boot-list", bootlist
);
787 if (!spapr
->has_graphics
) {
788 spapr_populate_chosen_stdout(fdt
, spapr
->vio_bus
);
791 _FDT((fdt_pack(fdt
)));
793 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
794 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
795 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
799 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
805 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
807 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
810 static void emulate_spapr_hypercall(PowerPCCPU
*cpu
)
812 CPUPPCState
*env
= &cpu
->env
;
815 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
816 env
->gpr
[3] = H_PRIVILEGE
;
818 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
822 static void spapr_reset_htab(sPAPREnvironment
*spapr
)
826 /* allocate hash page table. For now we always make this 16mb,
827 * later we should probably make it scale to the size of guest
830 shift
= kvmppc_reset_htab(spapr
->htab_shift
);
833 /* Kernel handles htab, we don't need to allocate one */
834 spapr
->htab_shift
= shift
;
835 kvmppc_kern_htab
= true;
838 /* Allocate an htab if we don't yet have one */
839 spapr
->htab
= qemu_memalign(HTAB_SIZE(spapr
), HTAB_SIZE(spapr
));
843 memset(spapr
->htab
, 0, HTAB_SIZE(spapr
));
846 /* Update the RMA size if necessary */
847 if (spapr
->vrma_adjust
) {
848 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(),
853 static void ppc_spapr_reset(void)
855 PowerPCCPU
*first_ppc_cpu
;
858 /* Reset the hash table & recalc the RMA */
859 spapr_reset_htab(spapr
);
861 qemu_devices_reset();
864 * We place the device tree and RTAS just below either the top of the RMA,
865 * or just below 2GB, whichever is lowere, so that it can be
866 * processed with 32-bit real mode code if necessary
868 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
869 spapr
->rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
870 spapr
->fdt_addr
= spapr
->rtas_addr
- FDT_MAX_SIZE
;
873 spapr_finalize_fdt(spapr
, spapr
->fdt_addr
, spapr
->rtas_addr
,
877 cpu_physical_memory_write(spapr
->rtas_addr
, spapr
->rtas_blob
,
880 /* Set up the entry state */
881 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
882 first_ppc_cpu
->env
.gpr
[3] = spapr
->fdt_addr
;
883 first_ppc_cpu
->env
.gpr
[5] = 0;
884 first_cpu
->halted
= 0;
885 first_ppc_cpu
->env
.nip
= spapr
->entry_point
;
889 static void spapr_cpu_reset(void *opaque
)
891 PowerPCCPU
*cpu
= opaque
;
892 CPUState
*cs
= CPU(cpu
);
893 CPUPPCState
*env
= &cpu
->env
;
897 /* All CPUs start halted. CPU0 is unhalted from the machine level
898 * reset code and the rest are explicitly started up by the guest
899 * using an RTAS call */
902 env
->spr
[SPR_HIOR
] = 0;
904 env
->external_htab
= (uint8_t *)spapr
->htab
;
905 if (kvm_enabled() && !env
->external_htab
) {
907 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
908 * functions do the right thing.
910 env
->external_htab
= (void *)1;
914 * htab_mask is the mask used to normalize hash value to PTEG index.
915 * htab_shift is log2 of hash table size.
916 * We have 8 hpte per group, and each hpte is 16 bytes.
917 * ie have 128 bytes per hpte entry.
919 env
->htab_mask
= (1ULL << ((spapr
)->htab_shift
- 7)) - 1;
920 env
->spr
[SPR_SDR1
] = (target_ulong
)(uintptr_t)spapr
->htab
|
921 (spapr
->htab_shift
- 18);
924 static void spapr_create_nvram(sPAPREnvironment
*spapr
)
926 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
927 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
930 qdev_prop_set_drive_nofail(dev
, "drive", blk_by_legacy_dinfo(dinfo
));
933 qdev_init_nofail(dev
);
935 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
938 /* Returns whether we want to use VGA or not */
939 static int spapr_vga_init(PCIBus
*pci_bus
)
941 switch (vga_interface_type
) {
947 return pci_vga_init(pci_bus
) != NULL
;
949 fprintf(stderr
, "This vga model is not supported,"
950 "currently it only supports -vga std\n");
955 static const VMStateDescription vmstate_spapr
= {
958 .minimum_version_id
= 1,
959 .fields
= (VMStateField
[]) {
960 VMSTATE_UNUSED(4), /* used to be @next_irq */
963 VMSTATE_UINT64(rtc_offset
, sPAPREnvironment
),
964 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPREnvironment
, 2),
965 VMSTATE_END_OF_LIST()
969 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
970 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
971 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
972 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
974 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
976 sPAPREnvironment
*spapr
= opaque
;
978 /* "Iteration" header */
979 qemu_put_be32(f
, spapr
->htab_shift
);
982 spapr
->htab_save_index
= 0;
983 spapr
->htab_first_pass
= true;
985 assert(kvm_enabled());
987 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
988 if (spapr
->htab_fd
< 0) {
989 fprintf(stderr
, "Unable to open fd for reading hash table from KVM: %s\n",
999 static void htab_save_first_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
1002 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1003 int index
= spapr
->htab_save_index
;
1004 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1006 assert(spapr
->htab_first_pass
);
1011 /* Consume invalid HPTEs */
1012 while ((index
< htabslots
)
1013 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1015 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1018 /* Consume valid HPTEs */
1020 while ((index
< htabslots
)
1021 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1023 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1026 if (index
> chunkstart
) {
1027 int n_valid
= index
- chunkstart
;
1029 qemu_put_be32(f
, chunkstart
);
1030 qemu_put_be16(f
, n_valid
);
1031 qemu_put_be16(f
, 0);
1032 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1033 HASH_PTE_SIZE_64
* n_valid
);
1035 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1039 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
1041 if (index
>= htabslots
) {
1042 assert(index
== htabslots
);
1044 spapr
->htab_first_pass
= false;
1046 spapr
->htab_save_index
= index
;
1049 static int htab_save_later_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
1052 bool final
= max_ns
< 0;
1053 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1054 int examined
= 0, sent
= 0;
1055 int index
= spapr
->htab_save_index
;
1056 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1058 assert(!spapr
->htab_first_pass
);
1061 int chunkstart
, invalidstart
;
1063 /* Consume non-dirty HPTEs */
1064 while ((index
< htabslots
)
1065 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
1071 /* Consume valid dirty HPTEs */
1072 while ((index
< htabslots
)
1073 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1074 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1075 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1080 invalidstart
= index
;
1081 /* Consume invalid dirty HPTEs */
1082 while ((index
< htabslots
)
1083 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1084 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1085 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1090 if (index
> chunkstart
) {
1091 int n_valid
= invalidstart
- chunkstart
;
1092 int n_invalid
= index
- invalidstart
;
1094 qemu_put_be32(f
, chunkstart
);
1095 qemu_put_be16(f
, n_valid
);
1096 qemu_put_be16(f
, n_invalid
);
1097 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1098 HASH_PTE_SIZE_64
* n_valid
);
1099 sent
+= index
- chunkstart
;
1101 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1106 if (examined
>= htabslots
) {
1110 if (index
>= htabslots
) {
1111 assert(index
== htabslots
);
1114 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
1116 if (index
>= htabslots
) {
1117 assert(index
== htabslots
);
1121 spapr
->htab_save_index
= index
;
1123 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
1126 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1127 #define MAX_KVM_BUF_SIZE 2048
1129 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
1131 sPAPREnvironment
*spapr
= opaque
;
1134 /* Iteration header */
1135 qemu_put_be32(f
, 0);
1138 assert(kvm_enabled());
1140 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
,
1141 MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
1145 } else if (spapr
->htab_first_pass
) {
1146 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
1148 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
1152 qemu_put_be32(f
, 0);
1153 qemu_put_be16(f
, 0);
1154 qemu_put_be16(f
, 0);
1159 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
1161 sPAPREnvironment
*spapr
= opaque
;
1163 /* Iteration header */
1164 qemu_put_be32(f
, 0);
1169 assert(kvm_enabled());
1171 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
, MAX_KVM_BUF_SIZE
, -1);
1175 close(spapr
->htab_fd
);
1176 spapr
->htab_fd
= -1;
1178 htab_save_later_pass(f
, spapr
, -1);
1182 qemu_put_be32(f
, 0);
1183 qemu_put_be16(f
, 0);
1184 qemu_put_be16(f
, 0);
1189 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
1191 sPAPREnvironment
*spapr
= opaque
;
1192 uint32_t section_hdr
;
1195 if (version_id
< 1 || version_id
> 1) {
1196 fprintf(stderr
, "htab_load() bad version\n");
1200 section_hdr
= qemu_get_be32(f
);
1203 /* First section, just the hash shift */
1204 if (spapr
->htab_shift
!= section_hdr
) {
1211 assert(kvm_enabled());
1213 fd
= kvmppc_get_htab_fd(true);
1215 fprintf(stderr
, "Unable to open fd to restore KVM hash table: %s\n",
1222 uint16_t n_valid
, n_invalid
;
1224 index
= qemu_get_be32(f
);
1225 n_valid
= qemu_get_be16(f
);
1226 n_invalid
= qemu_get_be16(f
);
1228 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1233 if ((index
+ n_valid
+ n_invalid
) >
1234 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1235 /* Bad index in stream */
1236 fprintf(stderr
, "htab_load() bad index %d (%hd+%hd entries) "
1237 "in htab stream (htab_shift=%d)\n", index
, n_valid
, n_invalid
,
1244 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1245 HASH_PTE_SIZE_64
* n_valid
);
1248 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1249 HASH_PTE_SIZE_64
* n_invalid
);
1256 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1271 static SaveVMHandlers savevm_htab_handlers
= {
1272 .save_live_setup
= htab_save_setup
,
1273 .save_live_iterate
= htab_save_iterate
,
1274 .save_live_complete
= htab_save_complete
,
1275 .load_state
= htab_load
,
1278 /* pSeries LPAR / sPAPR hardware init */
1279 static void ppc_spapr_init(MachineState
*machine
)
1281 ram_addr_t ram_size
= machine
->ram_size
;
1282 const char *cpu_model
= machine
->cpu_model
;
1283 const char *kernel_filename
= machine
->kernel_filename
;
1284 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1285 const char *initrd_filename
= machine
->initrd_filename
;
1286 const char *boot_device
= machine
->boot_order
;
1291 MemoryRegion
*sysmem
= get_system_memory();
1292 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1293 MemoryRegion
*rma_region
;
1295 hwaddr rma_alloc_size
;
1296 hwaddr node0_size
= spapr_node0_size();
1297 uint32_t initrd_base
= 0;
1298 long kernel_size
= 0, initrd_size
= 0;
1299 long load_limit
, fw_size
;
1300 bool kernel_le
= false;
1303 msi_supported
= true;
1305 spapr
= g_malloc0(sizeof(*spapr
));
1306 QLIST_INIT(&spapr
->phbs
);
1308 cpu_ppc_hypercall
= emulate_spapr_hypercall
;
1310 /* Allocate RMA if necessary */
1311 rma_alloc_size
= kvmppc_alloc_rma(&rma
);
1313 if (rma_alloc_size
== -1) {
1314 hw_error("qemu: Unable to create RMA\n");
1318 if (rma_alloc_size
&& (rma_alloc_size
< node0_size
)) {
1319 spapr
->rma_size
= rma_alloc_size
;
1321 spapr
->rma_size
= node0_size
;
1323 /* With KVM, we don't actually know whether KVM supports an
1324 * unbounded RMA (PR KVM) or is limited by the hash table size
1325 * (HV KVM using VRMA), so we always assume the latter
1327 * In that case, we also limit the initial allocations for RTAS
1328 * etc... to 256M since we have no way to know what the VRMA size
1329 * is going to be as it depends on the size of the hash table
1330 * isn't determined yet.
1332 if (kvm_enabled()) {
1333 spapr
->vrma_adjust
= 1;
1334 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
1338 if (spapr
->rma_size
> node0_size
) {
1339 fprintf(stderr
, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")\n",
1344 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1345 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
1347 /* We aim for a hash table of size 1/128 the size of RAM. The
1348 * normal rule of thumb is 1/64 the size of RAM, but that's much
1349 * more than needed for the Linux guests we support. */
1350 spapr
->htab_shift
= 18; /* Minimum architected size */
1351 while (spapr
->htab_shift
<= 46) {
1352 if ((1ULL << (spapr
->htab_shift
+ 7)) >= ram_size
) {
1355 spapr
->htab_shift
++;
1358 /* Set up Interrupt Controller before we create the VCPUs */
1359 spapr
->icp
= xics_system_init(smp_cpus
* kvmppc_smt_threads() / smp_threads
,
1363 if (cpu_model
== NULL
) {
1364 cpu_model
= kvm_enabled() ? "host" : "POWER7";
1366 for (i
= 0; i
< smp_cpus
; i
++) {
1367 cpu
= cpu_ppc_init(cpu_model
);
1369 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
1374 /* Set time-base frequency to 512 MHz */
1375 cpu_ppc_tb_init(env
, TIMEBASE_FREQ
);
1377 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1378 * MSR[IP] should never be set.
1380 env
->msr_mask
&= ~(1 << 6);
1382 /* Tell KVM that we're in PAPR mode */
1383 if (kvm_enabled()) {
1384 kvmppc_set_papr(cpu
);
1387 if (cpu
->max_compat
) {
1388 if (ppc_set_compat(cpu
, cpu
->max_compat
) < 0) {
1393 xics_cpu_setup(spapr
->icp
, cpu
);
1395 qemu_register_reset(spapr_cpu_reset
, cpu
);
1399 spapr
->ram_limit
= ram_size
;
1400 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
1402 memory_region_add_subregion(sysmem
, 0, ram
);
1404 if (rma_alloc_size
&& rma
) {
1405 rma_region
= g_new(MemoryRegion
, 1);
1406 memory_region_init_ram_ptr(rma_region
, NULL
, "ppc_spapr.rma",
1407 rma_alloc_size
, rma
);
1408 vmstate_register_ram_global(rma_region
);
1409 memory_region_add_subregion(sysmem
, 0, rma_region
);
1412 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
1413 spapr
->rtas_size
= get_image_size(filename
);
1414 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
1415 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
1416 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1419 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
1420 hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n",
1421 spapr
->rtas_size
, RTAS_MAX_SIZE
);
1426 /* Set up EPOW events infrastructure */
1427 spapr_events_init(spapr
);
1429 /* Set up VIO bus */
1430 spapr
->vio_bus
= spapr_vio_bus_init();
1432 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1433 if (serial_hds
[i
]) {
1434 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
1438 /* We always have at least the nvram device on VIO */
1439 spapr_create_nvram(spapr
);
1442 spapr_pci_rtas_init();
1444 phb
= spapr_create_phb(spapr
, 0);
1446 for (i
= 0; i
< nb_nics
; i
++) {
1447 NICInfo
*nd
= &nd_table
[i
];
1450 nd
->model
= g_strdup("ibmveth");
1453 if (strcmp(nd
->model
, "ibmveth") == 0) {
1454 spapr_vlan_create(spapr
->vio_bus
, nd
);
1456 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
1460 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
1461 spapr_vscsi_create(spapr
->vio_bus
);
1465 if (spapr_vga_init(phb
->bus
)) {
1466 spapr
->has_graphics
= true;
1469 if (usb_enabled(spapr
->has_graphics
)) {
1470 pci_create_simple(phb
->bus
, -1, "pci-ohci");
1471 if (spapr
->has_graphics
) {
1472 usbdevice_create("keyboard");
1473 usbdevice_create("mouse");
1477 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
1478 fprintf(stderr
, "qemu: pSeries SLOF firmware requires >= "
1479 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF
);
1483 if (kernel_filename
) {
1484 uint64_t lowaddr
= 0;
1486 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
1487 NULL
, &lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
1488 if (kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
1489 kernel_size
= load_elf(kernel_filename
,
1490 translate_kernel_address
, NULL
,
1491 NULL
, &lowaddr
, NULL
, 0, ELF_MACHINE
, 0);
1492 kernel_le
= kernel_size
> 0;
1494 if (kernel_size
< 0) {
1495 fprintf(stderr
, "qemu: error loading %s: %s\n",
1496 kernel_filename
, load_elf_strerror(kernel_size
));
1501 if (initrd_filename
) {
1502 /* Try to locate the initrd in the gap between the kernel
1503 * and the firmware. Add a bit of space just in case
1505 initrd_base
= (KERNEL_LOAD_ADDR
+ kernel_size
+ 0x1ffff) & ~0xffff;
1506 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
1507 load_limit
- initrd_base
);
1508 if (initrd_size
< 0) {
1509 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
1519 if (bios_name
== NULL
) {
1520 bios_name
= FW_FILE_NAME
;
1522 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1523 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
1525 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1530 spapr
->entry_point
= 0x100;
1532 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
1533 register_savevm_live(NULL
, "spapr/htab", -1, 1,
1534 &savevm_htab_handlers
, spapr
);
1536 /* Prepare the device tree */
1537 spapr
->fdt_skel
= spapr_create_fdt_skel(initrd_base
, initrd_size
,
1538 kernel_size
, kernel_le
,
1539 boot_device
, kernel_cmdline
,
1541 assert(spapr
->fdt_skel
!= NULL
);
1544 static int spapr_kvm_type(const char *vm_type
)
1550 if (!strcmp(vm_type
, "HV")) {
1554 if (!strcmp(vm_type
, "PR")) {
1558 error_report("Unknown kvm-type specified '%s'", vm_type
);
1563 * Implementation of an interface to adjust firmware patch
1564 * for the bootindex property handling.
1566 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
1569 #define CAST(type, obj, name) \
1570 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1571 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
1572 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1575 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
1576 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
1577 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
1581 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1582 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
1583 * in the top 16 bits of the 64-bit LUN
1585 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
1586 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1587 (uint64_t)id
<< 48);
1588 } else if (virtio
) {
1590 * We use SRP luns of the form 01000000 | (target << 8) | lun
1591 * in the top 32 bits of the 64-bit LUN
1592 * Note: the quote above is from SLOF and it is wrong,
1593 * the actual binding is:
1594 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
1596 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
1597 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1598 (uint64_t)id
<< 32);
1601 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
1602 * in the top 32 bits of the 64-bit LUN
1604 unsigned usb_port
= atoi(usb
->port
->path
);
1605 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
1606 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1607 (uint64_t)id
<< 32);
1612 /* Replace "pci" with "pci@800000020000000" */
1613 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
1619 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
1621 sPAPRMachineState
*sm
= SPAPR_MACHINE(obj
);
1623 return g_strdup(sm
->kvm_type
);
1626 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
1628 sPAPRMachineState
*sm
= SPAPR_MACHINE(obj
);
1630 g_free(sm
->kvm_type
);
1631 sm
->kvm_type
= g_strdup(value
);
1634 static void spapr_machine_initfn(Object
*obj
)
1636 object_property_add_str(obj
, "kvm-type",
1637 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
1640 static void ppc_cpu_do_nmi_on_cpu(void *arg
)
1644 cpu_synchronize_state(cs
);
1645 ppc_cpu_do_system_reset(cs
);
1648 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
1653 async_run_on_cpu(cs
, ppc_cpu_do_nmi_on_cpu
, cs
);
1657 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
1659 MachineClass
*mc
= MACHINE_CLASS(oc
);
1660 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
1661 NMIClass
*nc
= NMI_CLASS(oc
);
1663 mc
->name
= "pseries";
1664 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
1666 mc
->init
= ppc_spapr_init
;
1667 mc
->reset
= ppc_spapr_reset
;
1668 mc
->block_default_type
= IF_SCSI
;
1669 mc
->max_cpus
= MAX_CPUS
;
1670 mc
->no_parallel
= 1;
1671 mc
->default_boot_order
= NULL
;
1672 mc
->kvm_type
= spapr_kvm_type
;
1674 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
1675 nc
->nmi_monitor_handler
= spapr_nmi
;
1678 static const TypeInfo spapr_machine_info
= {
1679 .name
= TYPE_SPAPR_MACHINE
,
1680 .parent
= TYPE_MACHINE
,
1681 .instance_size
= sizeof(sPAPRMachineState
),
1682 .instance_init
= spapr_machine_initfn
,
1683 .class_init
= spapr_machine_class_init
,
1684 .interfaces
= (InterfaceInfo
[]) {
1685 { TYPE_FW_PATH_PROVIDER
},
1691 static void spapr_machine_2_1_class_init(ObjectClass
*oc
, void *data
)
1693 MachineClass
*mc
= MACHINE_CLASS(oc
);
1694 static GlobalProperty compat_props
[] = {
1696 { /* end of list */ }
1699 mc
->name
= "pseries-2.1";
1700 mc
->desc
= "pSeries Logical Partition (PAPR compliant) v2.1";
1702 mc
->compat_props
= compat_props
;
1705 static const TypeInfo spapr_machine_2_1_info
= {
1706 .name
= TYPE_SPAPR_MACHINE
"2.1",
1707 .parent
= TYPE_SPAPR_MACHINE
,
1708 .class_init
= spapr_machine_2_1_class_init
,
1711 static void spapr_machine_register_types(void)
1713 type_register_static(&spapr_machine_info
);
1714 type_register_static(&spapr_machine_2_1_info
);
1717 type_init(spapr_machine_register_types
)