hw/ppc/spapr.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  * Copyright (c) 2010 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27 #include "sysemu/sysemu.h"
  28 #include "hw/hw.h"
  29 #include "hw/fw-path-provider.h"
  30 #include "elf.h"
  31 #include "net/net.h"
  32 #include "sysemu/blockdev.h"
  33 #include "sysemu/cpus.h"
  34 #include "sysemu/kvm.h"
  35 #include "kvm_ppc.h"
  36 #include "mmu-hash64.h"
  37 #include "qom/cpu.h"
  38
  39 #include "hw/boards.h"
  40 #include "hw/ppc/ppc.h"
  41 #include "hw/loader.h"
  42
  43 #include "hw/ppc/spapr.h"
  44 #include "hw/ppc/spapr_vio.h"
  45 #include "hw/pci-host/spapr.h"
  46 #include "hw/ppc/xics.h"
  47 #include "hw/pci/msi.h"
  48
  49 #include "hw/pci/pci.h"
  50 #include "hw/scsi/scsi.h"
  51 #include "hw/virtio/virtio-scsi.h"
  52
  53 #include "exec/address-spaces.h"
  54 #include "hw/usb.h"
  55 #include "qemu/config-file.h"
  56 #include "qemu/error-report.h"
  57 #include "trace.h"
  58
  59 #include <libfdt.h>
  60
  61 /* SLOF memory layout:
  62  *
  63  * SLOF raw image loaded at 0, copies its romfs right below the flat
  64  * device-tree, then position SLOF itself 31M below that
  65  *
  66  * So we set FW_OVERHEAD to 40MB which should account for all of that
  67  * and more
  68  *
  69  * We load our kernel at 4M, leaving space for SLOF initial image
  70  */
  71 #define FDT_MAX_SIZE            0x40000
  72 #define RTAS_MAX_SIZE           0x10000
  73 #define FW_MAX_SIZE             0x400000
  74 #define FW_FILE_NAME            "slof.bin"
  75 #define FW_OVERHEAD             0x2800000
  76 #define KERNEL_LOAD_ADDR        FW_MAX_SIZE
  77
  78 #define MIN_RMA_SLOF            128UL
  79
  80 #define TIMEBASE_FREQ           512000000ULL
  81
  82 #define MAX_CPUS                256
  83
  84 #define PHANDLE_XICP            0x00001111
  85
  86 #define HTAB_SIZE(spapr)        (1ULL << ((spapr)->htab_shift))
  87
  88 typedef struct sPAPRMachineState sPAPRMachineState;
  89
  90 #define TYPE_SPAPR_MACHINE      "spapr-machine"
  91 #define SPAPR_MACHINE(obj) \
  92     OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
  93
  94 /**
  95  * sPAPRMachineState:
  96  */
  97 struct sPAPRMachineState {
  98     /*< private >*/
  99     MachineState parent_obj;
 100
 101     /*< public >*/
 102     char *kvm_type;
 103 };
 104
 105 sPAPREnvironment *spapr;
 106
 107 int spapr_allocate_irq(int hint, bool lsi)
 108 {
 109     int irq;
 110
 111     if (hint) {
 112         irq = hint;
 113         if (hint >= spapr->next_irq) {
 114             spapr->next_irq = hint + 1;
 115         }
 116         /* FIXME: we should probably check for collisions somehow */
 117     } else {
 118         irq = spapr->next_irq++;
 119     }
 120
 121     /* Configure irq type */
 122     if (!xics_get_qirq(spapr->icp, irq)) {
 123         return 0;
 124     }
 125
 126     xics_set_irq_type(spapr->icp, irq, lsi);
 127
 128     return irq;
 129 }
 130
 131 /*
 132  * Allocate block of consequtive IRQs, returns a number of the first.
 133  * If msi==true, aligns the first IRQ number to num.
 134  */
 135 int spapr_allocate_irq_block(int num, bool lsi, bool msi)
 136 {
 137     int first = -1;
 138     int i, hint = 0;
 139
 140     /*
 141      * MSIMesage::data is used for storing VIRQ so
 142      * it has to be aligned to num to support multiple
 143      * MSI vectors. MSI-X is not affected by this.
 144      * The hint is used for the first IRQ, the rest should
 145      * be allocated continuously.
 146      */
 147     if (msi) {
 148         assert((num == 1) || (num == 2) || (num == 4) ||
 149                (num == 8) || (num == 16) || (num == 32));
 150         hint = (spapr->next_irq + num - 1) & ~(num - 1);
 151     }
 152
 153     for (i = 0; i < num; ++i) {
 154         int irq;
 155
 156         irq = spapr_allocate_irq(hint, lsi);
 157         if (!irq) {
 158             return -1;
 159         }
 160
 161         if (0 == i) {
 162             first = irq;
 163             hint = 0;
 164         }
 165
 166         /* If the above doesn't create a consecutive block then that's
 167          * an internal bug */
 168         assert(irq == (first + i));
 169     }
 170
 171     return first;
 172 }
 173
 174 static XICSState *try_create_xics(const char *type, int nr_servers,
 175                                   int nr_irqs)
 176 {
 177     DeviceState *dev;
 178
 179     dev = qdev_create(NULL, type);
 180     qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
 181     qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
 182     if (qdev_init(dev) < 0) {
 183         return NULL;
 184     }
 185
 186     return XICS_COMMON(dev);
 187 }
 188
 189 static XICSState *xics_system_init(int nr_servers, int nr_irqs)
 190 {
 191     XICSState *icp = NULL;
 192
 193     if (kvm_enabled()) {
 194         QemuOpts *machine_opts = qemu_get_machine_opts();
 195         bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
 196                                                 "kernel_irqchip", true);
 197         bool irqchip_required = qemu_opt_get_bool(machine_opts,
 198                                                   "kernel_irqchip", false);
 199         if (irqchip_allowed) {
 200             icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs);
 201         }
 202
 203         if (irqchip_required && !icp) {
 204             perror("Failed to create in-kernel XICS\n");
 205             abort();
 206         }
 207     }
 208
 209     if (!icp) {
 210         icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs);
 211     }
 212
 213     if (!icp) {
 214         perror("Failed to create XICS\n");
 215         abort();
 216     }
 217
 218     return icp;
 219 }
 220
 221 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
 222                                   int smt_threads)
 223 {
 224     int i, ret = 0;
 225     uint32_t servers_prop[smt_threads];
 226     uint32_t gservers_prop[smt_threads * 2];
 227     int index = ppc_get_vcpu_dt_id(cpu);
 228
 229     if (cpu->cpu_version) {
 230         ret = fdt_setprop(fdt, offset, "cpu-version",
 231                           &cpu->cpu_version, sizeof(cpu->cpu_version));
 232         if (ret < 0) {
 233             return ret;
 234         }
 235     }
 236
 237     /* Build interrupt servers and gservers properties */
 238     for (i = 0; i < smt_threads; i++) {
 239         servers_prop[i] = cpu_to_be32(index + i);
 240         /* Hack, direct the group queues back to cpu 0 */
 241         gservers_prop[i*2] = cpu_to_be32(index + i);
 242         gservers_prop[i*2 + 1] = 0;
 243     }
 244     ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
 245                       servers_prop, sizeof(servers_prop));
 246     if (ret < 0) {
 247         return ret;
 248     }
 249     ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
 250                       gservers_prop, sizeof(gservers_prop));
 251
 252     return ret;
 253 }
 254
 255 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr)
 256 {
 257     int ret = 0, offset, cpus_offset;
 258     CPUState *cs;
 259     char cpu_model[32];
 260     int smt = kvmppc_smt_threads();
 261     uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
 262
 263     CPU_FOREACH(cs) {
 264         PowerPCCPU *cpu = POWERPC_CPU(cs);
 265         DeviceClass *dc = DEVICE_GET_CLASS(cs);
 266         int index = ppc_get_vcpu_dt_id(cpu);
 267         uint32_t associativity[] = {cpu_to_be32(0x5),
 268                                     cpu_to_be32(0x0),
 269                                     cpu_to_be32(0x0),
 270                                     cpu_to_be32(0x0),
 271                                     cpu_to_be32(cs->numa_node),
 272                                     cpu_to_be32(index)};
 273
 274         if ((index % smt) != 0) {
 275             continue;
 276         }
 277
 278         snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
 279
 280         cpus_offset = fdt_path_offset(fdt, "/cpus");
 281         if (cpus_offset < 0) {
 282             cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
 283                                           "cpus");
 284             if (cpus_offset < 0) {
 285                 return cpus_offset;
 286             }
 287         }
 288         offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
 289         if (offset < 0) {
 290             offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
 291             if (offset < 0) {
 292                 return offset;
 293             }
 294         }
 295
 296         if (nb_numa_nodes > 1) {
 297             ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
 298                               sizeof(associativity));
 299             if (ret < 0) {
 300                 return ret;
 301             }
 302         }
 303
 304         ret = fdt_setprop(fdt, offset, "ibm,pft-size",
 305                           pft_size_prop, sizeof(pft_size_prop));
 306         if (ret < 0) {
 307             return ret;
 308         }
 309
 310         ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
 311                                      ppc_get_compat_smt_threads(cpu));
 312         if (ret < 0) {
 313             return ret;
 314         }
 315     }
 316     return ret;
 317 }
 318
 319
 320 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
 321                                      size_t maxsize)
 322 {
 323     size_t maxcells = maxsize / sizeof(uint32_t);
 324     int i, j, count;
 325     uint32_t *p = prop;
 326
 327     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 328         struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
 329
 330         if (!sps->page_shift) {
 331             break;
 332         }
 333         for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
 334             if (sps->enc[count].page_shift == 0) {
 335                 break;
 336             }
 337         }
 338         if ((p - prop) >= (maxcells - 3 - count * 2)) {
 339             break;
 340         }
 341         *(p++) = cpu_to_be32(sps->page_shift);
 342         *(p++) = cpu_to_be32(sps->slb_enc);
 343         *(p++) = cpu_to_be32(count);
 344         for (j = 0; j < count; j++) {
 345             *(p++) = cpu_to_be32(sps->enc[j].page_shift);
 346             *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
 347         }
 348     }
 349
 350     return (p - prop) * sizeof(uint32_t);
 351 }
 352
 353 #define _FDT(exp) \
 354     do { \
 355         int ret = (exp);                                           \
 356         if (ret < 0) {                                             \
 357             fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
 358                     #exp, fdt_strerror(ret));                      \
 359             exit(1);                                               \
 360         }                                                          \
 361     } while (0)
 362
 363 static void add_str(GString *s, const gchar *s1)
 364 {
 365     g_string_append_len(s, s1, strlen(s1) + 1);
 366 }
 367
 368 static void *spapr_create_fdt_skel(hwaddr initrd_base,
 369                                    hwaddr initrd_size,
 370                                    hwaddr kernel_size,
 371                                    bool little_endian,
 372                                    const char *boot_device,
 373                                    const char *kernel_cmdline,
 374                                    uint32_t epow_irq)
 375 {
 376     void *fdt;
 377     CPUState *cs;
 378     uint32_t start_prop = cpu_to_be32(initrd_base);
 379     uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
 380     GString *hypertas = g_string_sized_new(256);
 381     GString *qemu_hypertas = g_string_sized_new(256);
 382     uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
 383     uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
 384     int smt = kvmppc_smt_threads();
 385     unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
 386     QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL);
 387     unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0;
 388     uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1;
 389
 390     add_str(hypertas, "hcall-pft");
 391     add_str(hypertas, "hcall-term");
 392     add_str(hypertas, "hcall-dabr");
 393     add_str(hypertas, "hcall-interrupt");
 394     add_str(hypertas, "hcall-tce");
 395     add_str(hypertas, "hcall-vio");
 396     add_str(hypertas, "hcall-splpar");
 397     add_str(hypertas, "hcall-bulk");
 398     add_str(hypertas, "hcall-set-mode");
 399     add_str(qemu_hypertas, "hcall-memop1");
 400
 401     fdt = g_malloc0(FDT_MAX_SIZE);
 402     _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
 403
 404     if (kernel_size) {
 405         _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
 406     }
 407     if (initrd_size) {
 408         _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
 409     }
 410     _FDT((fdt_finish_reservemap(fdt)));
 411
 412     /* Root node */
 413     _FDT((fdt_begin_node(fdt, "")));
 414     _FDT((fdt_property_string(fdt, "device_type", "chrp")));
 415     _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
 416     _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
 417
 418     _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
 419     _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
 420
 421     /* /chosen */
 422     _FDT((fdt_begin_node(fdt, "chosen")));
 423
 424     /* Set Form1_affinity */
 425     _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
 426
 427     _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
 428     _FDT((fdt_property(fdt, "linux,initrd-start",
 429                        &start_prop, sizeof(start_prop))));
 430     _FDT((fdt_property(fdt, "linux,initrd-end",
 431                        &end_prop, sizeof(end_prop))));
 432     if (kernel_size) {
 433         uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
 434                               cpu_to_be64(kernel_size) };
 435
 436         _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
 437         if (little_endian) {
 438             _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
 439         }
 440     }
 441     if (boot_device) {
 442         _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
 443     }
 444     if (boot_menu) {
 445         _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
 446     }
 447     _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
 448     _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
 449     _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
 450
 451     _FDT((fdt_end_node(fdt)));
 452
 453     /* cpus */
 454     _FDT((fdt_begin_node(fdt, "cpus")));
 455
 456     _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
 457     _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
 458
 459     CPU_FOREACH(cs) {
 460         PowerPCCPU *cpu = POWERPC_CPU(cs);
 461         CPUPPCState *env = &cpu->env;
 462         DeviceClass *dc = DEVICE_GET_CLASS(cs);
 463         PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
 464         int index = ppc_get_vcpu_dt_id(cpu);
 465         char *nodename;
 466         uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
 467                            0xffffffff, 0xffffffff};
 468         uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
 469         uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
 470         uint32_t page_sizes_prop[64];
 471         size_t page_sizes_prop_size;
 472
 473         if ((index % smt) != 0) {
 474             continue;
 475         }
 476
 477         nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
 478
 479         _FDT((fdt_begin_node(fdt, nodename)));
 480
 481         g_free(nodename);
 482
 483         _FDT((fdt_property_cell(fdt, "reg", index)));
 484         _FDT((fdt_property_string(fdt, "device_type", "cpu")));
 485
 486         _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
 487         _FDT((fdt_property_cell(fdt, "d-cache-block-size",
 488                                 env->dcache_line_size)));
 489         _FDT((fdt_property_cell(fdt, "d-cache-line-size",
 490                                 env->dcache_line_size)));
 491         _FDT((fdt_property_cell(fdt, "i-cache-block-size",
 492                                 env->icache_line_size)));
 493         _FDT((fdt_property_cell(fdt, "i-cache-line-size",
 494                                 env->icache_line_size)));
 495
 496         if (pcc->l1_dcache_size) {
 497             _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size)));
 498         } else {
 499             fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
 500         }
 501         if (pcc->l1_icache_size) {
 502             _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size)));
 503         } else {
 504             fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
 505         }
 506
 507         _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
 508         _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
 509         _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
 510         _FDT((fdt_property_string(fdt, "status", "okay")));
 511         _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
 512
 513         if (env->spr_cb[SPR_PURR].oea_read) {
 514             _FDT((fdt_property(fdt, "ibm,purr", NULL, 0)));
 515         }
 516
 517         if (env->mmu_model & POWERPC_MMU_1TSEG) {
 518             _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
 519                                segs, sizeof(segs))));
 520         }
 521
 522         /* Advertise VMX/VSX (vector extensions) if available
 523          *   0 / no property == no vector extensions
 524          *   1               == VMX / Altivec available
 525          *   2               == VSX available */
 526         if (env->insns_flags & PPC_ALTIVEC) {
 527             uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
 528
 529             _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
 530         }
 531
 532         /* Advertise DFP (Decimal Floating Point) if available
 533          *   0 / no property == no DFP
 534          *   1               == DFP available */
 535         if (env->insns_flags2 & PPC2_DFP) {
 536             _FDT((fdt_property_cell(fdt, "ibm,dfp", 1)));
 537         }
 538
 539         page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
 540                                                       sizeof(page_sizes_prop));
 541         if (page_sizes_prop_size) {
 542             _FDT((fdt_property(fdt, "ibm,segment-page-sizes",
 543                                page_sizes_prop, page_sizes_prop_size)));
 544         }
 545
 546         _FDT((fdt_property_cell(fdt, "ibm,chip-id",
 547                                 cs->cpu_index / cpus_per_socket)));
 548
 549         _FDT((fdt_end_node(fdt)));
 550     }
 551
 552     _FDT((fdt_end_node(fdt)));
 553
 554     /* RTAS */
 555     _FDT((fdt_begin_node(fdt, "rtas")));
 556
 557     if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
 558         add_str(hypertas, "hcall-multi-tce");
 559     }
 560     _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
 561                        hypertas->len)));
 562     g_string_free(hypertas, TRUE);
 563     _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
 564                        qemu_hypertas->len)));
 565     g_string_free(qemu_hypertas, TRUE);
 566
 567     _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
 568         refpoints, sizeof(refpoints))));
 569
 570     _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
 571
 572     _FDT((fdt_end_node(fdt)));
 573
 574     /* interrupt controller */
 575     _FDT((fdt_begin_node(fdt, "interrupt-controller")));
 576
 577     _FDT((fdt_property_string(fdt, "device_type",
 578                               "PowerPC-External-Interrupt-Presentation")));
 579     _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
 580     _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
 581     _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
 582                        interrupt_server_ranges_prop,
 583                        sizeof(interrupt_server_ranges_prop))));
 584     _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
 585     _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
 586     _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
 587
 588     _FDT((fdt_end_node(fdt)));
 589
 590     /* vdevice */
 591     _FDT((fdt_begin_node(fdt, "vdevice")));
 592
 593     _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
 594     _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
 595     _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
 596     _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
 597     _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
 598     _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
 599
 600     _FDT((fdt_end_node(fdt)));
 601
 602     /* event-sources */
 603     spapr_events_fdt_skel(fdt, epow_irq);
 604
 605     /* /hypervisor node */
 606     if (kvm_enabled()) {
 607         uint8_t hypercall[16];
 608
 609         /* indicate KVM hypercall interface */
 610         _FDT((fdt_begin_node(fdt, "hypervisor")));
 611         _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
 612         if (kvmppc_has_cap_fixup_hcalls()) {
 613             /*
 614              * Older KVM versions with older guest kernels were broken with the
 615              * magic page, don't allow the guest to map it.
 616              */
 617             kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
 618                                  sizeof(hypercall));
 619             _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
 620                               sizeof(hypercall))));
 621         }
 622         _FDT((fdt_end_node(fdt)));
 623     }
 624
 625     _FDT((fdt_end_node(fdt))); /* close root node */
 626     _FDT((fdt_finish(fdt)));
 627
 628     return fdt;
 629 }
 630
 631 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size)
 632 {
 633     void *fdt, *fdt_skel;
 634     sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
 635
 636     size -= sizeof(hdr);
 637
 638     /* Create sceleton */
 639     fdt_skel = g_malloc0(size);
 640     _FDT((fdt_create(fdt_skel, size)));
 641     _FDT((fdt_begin_node(fdt_skel, "")));
 642     _FDT((fdt_end_node(fdt_skel)));
 643     _FDT((fdt_finish(fdt_skel)));
 644     fdt = g_malloc0(size);
 645     _FDT((fdt_open_into(fdt_skel, fdt, size)));
 646     g_free(fdt_skel);
 647
 648     /* Fix skeleton up */
 649     _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
 650
 651     /* Pack resulting tree */
 652     _FDT((fdt_pack(fdt)));
 653
 654     if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
 655         trace_spapr_cas_failed(size);
 656         return -1;
 657     }
 658
 659     cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
 660     cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
 661     trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
 662     g_free(fdt);
 663
 664     return 0;
 665 }
 666
 667 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt)
 668 {
 669     uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
 670                                 cpu_to_be32(0x0), cpu_to_be32(0x0),
 671                                 cpu_to_be32(0x0)};
 672     char mem_name[32];
 673     hwaddr node0_size, mem_start, node_size;
 674     uint64_t mem_reg_property[2];
 675     int i, off;
 676
 677     /* memory node(s) */
 678     if (nb_numa_nodes > 1 && numa_info[0].node_mem < ram_size) {
 679         node0_size = numa_info[0].node_mem;
 680     } else {
 681         node0_size = ram_size;
 682     }
 683
 684     /* RMA */
 685     mem_reg_property[0] = 0;
 686     mem_reg_property[1] = cpu_to_be64(spapr->rma_size);
 687     off = fdt_add_subnode(fdt, 0, "memory@0");
 688     _FDT(off);
 689     _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
 690     _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
 691                       sizeof(mem_reg_property))));
 692     _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
 693                       sizeof(associativity))));
 694
 695     /* RAM: Node 0 */
 696     if (node0_size > spapr->rma_size) {
 697         mem_reg_property[0] = cpu_to_be64(spapr->rma_size);
 698         mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size);
 699
 700         sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size);
 701         off = fdt_add_subnode(fdt, 0, mem_name);
 702         _FDT(off);
 703         _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
 704         _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
 705                           sizeof(mem_reg_property))));
 706         _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
 707                           sizeof(associativity))));
 708     }
 709
 710     /* RAM: Node 1 and beyond */
 711     mem_start = node0_size;
 712     for (i = 1; i < nb_numa_nodes; i++) {
 713         mem_reg_property[0] = cpu_to_be64(mem_start);
 714         if (mem_start >= ram_size) {
 715             node_size = 0;
 716         } else {
 717             node_size = numa_info[i].node_mem;
 718             if (node_size > ram_size - mem_start) {
 719                 node_size = ram_size - mem_start;
 720             }
 721         }
 722         mem_reg_property[1] = cpu_to_be64(node_size);
 723         associativity[3] = associativity[4] = cpu_to_be32(i);
 724         sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
 725         off = fdt_add_subnode(fdt, 0, mem_name);
 726         _FDT(off);
 727         _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
 728         _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
 729                           sizeof(mem_reg_property))));
 730         _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
 731                           sizeof(associativity))));
 732         mem_start += node_size;
 733     }
 734
 735     return 0;
 736 }
 737
 738 static void spapr_finalize_fdt(sPAPREnvironment *spapr,
 739                                hwaddr fdt_addr,
 740                                hwaddr rtas_addr,
 741                                hwaddr rtas_size)
 742 {
 743     int ret, i;
 744     size_t cb = 0;
 745     char *bootlist;
 746     void *fdt;
 747     sPAPRPHBState *phb;
 748
 749     fdt = g_malloc(FDT_MAX_SIZE);
 750
 751     /* open out the base tree into a temp buffer for the final tweaks */
 752     _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
 753
 754     ret = spapr_populate_memory(spapr, fdt);
 755     if (ret < 0) {
 756         fprintf(stderr, "couldn't setup memory nodes in fdt\n");
 757         exit(1);
 758     }
 759
 760     ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
 761     if (ret < 0) {
 762         fprintf(stderr, "couldn't setup vio devices in fdt\n");
 763         exit(1);
 764     }
 765
 766     QLIST_FOREACH(phb, &spapr->phbs, list) {
 767         ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
 768     }
 769
 770     if (ret < 0) {
 771         fprintf(stderr, "couldn't setup PCI devices in fdt\n");
 772         exit(1);
 773     }
 774
 775     /* RTAS */
 776     ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
 777     if (ret < 0) {
 778         fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
 779     }
 780
 781     /* Advertise NUMA via ibm,associativity */
 782     ret = spapr_fixup_cpu_dt(fdt, spapr);
 783     if (ret < 0) {
 784         fprintf(stderr, "Couldn't finalize CPU device tree properties\n");
 785     }
 786
 787     bootlist = get_boot_devices_list(&cb, true);
 788     if (cb && bootlist) {
 789         int offset = fdt_path_offset(fdt, "/chosen");
 790         if (offset < 0) {
 791             exit(1);
 792         }
 793         for (i = 0; i < cb; i++) {
 794             if (bootlist[i] == '\n') {
 795                 bootlist[i] = ' ';
 796             }
 797
 798         }
 799         ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
 800     }
 801
 802     if (!spapr->has_graphics) {
 803         spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
 804     }
 805
 806     _FDT((fdt_pack(fdt)));
 807
 808     if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
 809         hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
 810                  fdt_totalsize(fdt), FDT_MAX_SIZE);
 811         exit(1);
 812     }
 813
 814     cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
 815
 816     g_free(fdt);
 817 }
 818
 819 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 820 {
 821     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
 822 }
 823
 824 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
 825 {
 826     CPUPPCState *env = &cpu->env;
 827
 828     if (msr_pr) {
 829         hcall_dprintf("Hypercall made with MSR[PR]=1\n");
 830         env->gpr[3] = H_PRIVILEGE;
 831     } else {
 832         env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
 833     }
 834 }
 835
 836 static void spapr_reset_htab(sPAPREnvironment *spapr)
 837 {
 838     long shift;
 839
 840     /* allocate hash page table.  For now we always make this 16mb,
 841      * later we should probably make it scale to the size of guest
 842      * RAM */
 843
 844     shift = kvmppc_reset_htab(spapr->htab_shift);
 845
 846     if (shift > 0) {
 847         /* Kernel handles htab, we don't need to allocate one */
 848         spapr->htab_shift = shift;
 849         kvmppc_kern_htab = true;
 850     } else {
 851         if (!spapr->htab) {
 852             /* Allocate an htab if we don't yet have one */
 853             spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr));
 854         }
 855
 856         /* And clear it */
 857         memset(spapr->htab, 0, HTAB_SIZE(spapr));
 858     }
 859
 860     /* Update the RMA size if necessary */
 861     if (spapr->vrma_adjust) {
 862         hwaddr node0_size = (nb_numa_nodes > 1) ?
 863             numa_info[0].node_mem : ram_size;
 864         spapr->rma_size = kvmppc_rma_size(node0_size, spapr->htab_shift);
 865     }
 866 }
 867
 868 static void ppc_spapr_reset(void)
 869 {
 870     PowerPCCPU *first_ppc_cpu;
 871
 872     /* Reset the hash table & recalc the RMA */
 873     spapr_reset_htab(spapr);
 874
 875     qemu_devices_reset();
 876
 877     /* Load the fdt */
 878     spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
 879                        spapr->rtas_size);
 880
 881     /* Set up the entry state */
 882     first_ppc_cpu = POWERPC_CPU(first_cpu);
 883     first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
 884     first_ppc_cpu->env.gpr[5] = 0;
 885     first_cpu->halted = 0;
 886     first_ppc_cpu->env.nip = spapr->entry_point;
 887
 888 }
 889
 890 static void spapr_cpu_reset(void *opaque)
 891 {
 892     PowerPCCPU *cpu = opaque;
 893     CPUState *cs = CPU(cpu);
 894     CPUPPCState *env = &cpu->env;
 895
 896     cpu_reset(cs);
 897
 898     /* All CPUs start halted.  CPU0 is unhalted from the machine level
 899      * reset code and the rest are explicitly started up by the guest
 900      * using an RTAS call */
 901     cs->halted = 1;
 902
 903     env->spr[SPR_HIOR] = 0;
 904
 905     env->external_htab = (uint8_t *)spapr->htab;
 906     if (kvm_enabled() && !env->external_htab) {
 907         /*
 908          * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
 909          * functions do the right thing.
 910          */
 911         env->external_htab = (void *)1;
 912     }
 913     env->htab_base = -1;
 914     /*
 915      * htab_mask is the mask used to normalize hash value to PTEG index.
 916      * htab_shift is log2 of hash table size.
 917      * We have 8 hpte per group, and each hpte is 16 bytes.
 918      * ie have 128 bytes per hpte entry.
 919      */
 920     env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1;
 921     env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab |
 922         (spapr->htab_shift - 18);
 923 }
 924
 925 static void spapr_create_nvram(sPAPREnvironment *spapr)
 926 {
 927     DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
 928     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
 929
 930     if (dinfo) {
 931         qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv);
 932     }
 933
 934     qdev_init_nofail(dev);
 935
 936     spapr->nvram = (struct sPAPRNVRAM *)dev;
 937 }
 938
 939 /* Returns whether we want to use VGA or not */
 940 static int spapr_vga_init(PCIBus *pci_bus)
 941 {
 942     switch (vga_interface_type) {
 943     case VGA_NONE:
 944         return false;
 945     case VGA_DEVICE:
 946         return true;
 947     case VGA_STD:
 948         return pci_vga_init(pci_bus) != NULL;
 949     default:
 950         fprintf(stderr, "This vga model is not supported,"
 951                 "currently it only supports -vga std\n");
 952         exit(0);
 953     }
 954 }
 955
 956 static const VMStateDescription vmstate_spapr = {
 957     .name = "spapr",
 958     .version_id = 2,
 959     .minimum_version_id = 1,
 960     .fields = (VMStateField[]) {
 961         VMSTATE_UINT32(next_irq, sPAPREnvironment),
 962
 963         /* RTC offset */
 964         VMSTATE_UINT64(rtc_offset, sPAPREnvironment),
 965         VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2),
 966         VMSTATE_END_OF_LIST()
 967     },
 968 };
 969
 970 #define HPTE(_table, _i)   (void *)(((uint64_t *)(_table)) + ((_i) * 2))
 971 #define HPTE_VALID(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
 972 #define HPTE_DIRTY(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
 973 #define CLEAN_HPTE(_hpte)  ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
 974
 975 static int htab_save_setup(QEMUFile *f, void *opaque)
 976 {
 977     sPAPREnvironment *spapr = opaque;
 978
 979     /* "Iteration" header */
 980     qemu_put_be32(f, spapr->htab_shift);
 981
 982     if (spapr->htab) {
 983         spapr->htab_save_index = 0;
 984         spapr->htab_first_pass = true;
 985     } else {
 986         assert(kvm_enabled());
 987
 988         spapr->htab_fd = kvmppc_get_htab_fd(false);
 989         if (spapr->htab_fd < 0) {
 990             fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n",
 991                     strerror(errno));
 992             return -1;
 993         }
 994     }
 995
 996
 997     return 0;
 998 }
 999
1000 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr,
1001                                  int64_t max_ns)
1002 {
1003     int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1004     int index = spapr->htab_save_index;
1005     int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1006
1007     assert(spapr->htab_first_pass);
1008
1009     do {
1010         int chunkstart;
1011
1012         /* Consume invalid HPTEs */
1013         while ((index < htabslots)
1014                && !HPTE_VALID(HPTE(spapr->htab, index))) {
1015             index++;
1016             CLEAN_HPTE(HPTE(spapr->htab, index));
1017         }
1018
1019         /* Consume valid HPTEs */
1020         chunkstart = index;
1021         while ((index < htabslots)
1022                && HPTE_VALID(HPTE(spapr->htab, index))) {
1023             index++;
1024             CLEAN_HPTE(HPTE(spapr->htab, index));
1025         }
1026
1027         if (index > chunkstart) {
1028             int n_valid = index - chunkstart;
1029
1030             qemu_put_be32(f, chunkstart);
1031             qemu_put_be16(f, n_valid);
1032             qemu_put_be16(f, 0);
1033             qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1034                             HASH_PTE_SIZE_64 * n_valid);
1035
1036             if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1037                 break;
1038             }
1039         }
1040     } while ((index < htabslots) && !qemu_file_rate_limit(f));
1041
1042     if (index >= htabslots) {
1043         assert(index == htabslots);
1044         index = 0;
1045         spapr->htab_first_pass = false;
1046     }
1047     spapr->htab_save_index = index;
1048 }
1049
1050 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr,
1051                                 int64_t max_ns)
1052 {
1053     bool final = max_ns < 0;
1054     int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1055     int examined = 0, sent = 0;
1056     int index = spapr->htab_save_index;
1057     int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1058
1059     assert(!spapr->htab_first_pass);
1060
1061     do {
1062         int chunkstart, invalidstart;
1063
1064         /* Consume non-dirty HPTEs */
1065         while ((index < htabslots)
1066                && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1067             index++;
1068             examined++;
1069         }
1070
1071         chunkstart = index;
1072         /* Consume valid dirty HPTEs */
1073         while ((index < htabslots)
1074                && HPTE_DIRTY(HPTE(spapr->htab, index))
1075                && HPTE_VALID(HPTE(spapr->htab, index))) {
1076             CLEAN_HPTE(HPTE(spapr->htab, index));
1077             index++;
1078             examined++;
1079         }
1080
1081         invalidstart = index;
1082         /* Consume invalid dirty HPTEs */
1083         while ((index < htabslots)
1084                && HPTE_DIRTY(HPTE(spapr->htab, index))
1085                && !HPTE_VALID(HPTE(spapr->htab, index))) {
1086             CLEAN_HPTE(HPTE(spapr->htab, index));
1087             index++;
1088             examined++;
1089         }
1090
1091         if (index > chunkstart) {
1092             int n_valid = invalidstart - chunkstart;
1093             int n_invalid = index - invalidstart;
1094
1095             qemu_put_be32(f, chunkstart);
1096             qemu_put_be16(f, n_valid);
1097             qemu_put_be16(f, n_invalid);
1098             qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1099                             HASH_PTE_SIZE_64 * n_valid);
1100             sent += index - chunkstart;
1101
1102             if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1103                 break;
1104             }
1105         }
1106
1107         if (examined >= htabslots) {
1108             break;
1109         }
1110
1111         if (index >= htabslots) {
1112             assert(index == htabslots);
1113             index = 0;
1114         }
1115     } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1116
1117     if (index >= htabslots) {
1118         assert(index == htabslots);
1119         index = 0;
1120     }
1121
1122     spapr->htab_save_index = index;
1123
1124     return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1125 }
1126
1127 #define MAX_ITERATION_NS    5000000 /* 5 ms */
1128 #define MAX_KVM_BUF_SIZE    2048
1129
1130 static int htab_save_iterate(QEMUFile *f, void *opaque)
1131 {
1132     sPAPREnvironment *spapr = opaque;
1133     int rc = 0;
1134
1135     /* Iteration header */
1136     qemu_put_be32(f, 0);
1137
1138     if (!spapr->htab) {
1139         assert(kvm_enabled());
1140
1141         rc = kvmppc_save_htab(f, spapr->htab_fd,
1142                               MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1143         if (rc < 0) {
1144             return rc;
1145         }
1146     } else  if (spapr->htab_first_pass) {
1147         htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1148     } else {
1149         rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1150     }
1151
1152     /* End marker */
1153     qemu_put_be32(f, 0);
1154     qemu_put_be16(f, 0);
1155     qemu_put_be16(f, 0);
1156
1157     return rc;
1158 }
1159
1160 static int htab_save_complete(QEMUFile *f, void *opaque)
1161 {
1162     sPAPREnvironment *spapr = opaque;
1163
1164     /* Iteration header */
1165     qemu_put_be32(f, 0);
1166
1167     if (!spapr->htab) {
1168         int rc;
1169
1170         assert(kvm_enabled());
1171
1172         rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1);
1173         if (rc < 0) {
1174             return rc;
1175         }
1176         close(spapr->htab_fd);
1177         spapr->htab_fd = -1;
1178     } else {
1179         htab_save_later_pass(f, spapr, -1);
1180     }
1181
1182     /* End marker */
1183     qemu_put_be32(f, 0);
1184     qemu_put_be16(f, 0);
1185     qemu_put_be16(f, 0);
1186
1187     return 0;
1188 }
1189
1190 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1191 {
1192     sPAPREnvironment *spapr = opaque;
1193     uint32_t section_hdr;
1194     int fd = -1;
1195
1196     if (version_id < 1 || version_id > 1) {
1197         fprintf(stderr, "htab_load() bad version\n");
1198         return -EINVAL;
1199     }
1200
1201     section_hdr = qemu_get_be32(f);
1202
1203     if (section_hdr) {
1204         /* First section, just the hash shift */
1205         if (spapr->htab_shift != section_hdr) {
1206             return -EINVAL;
1207         }
1208         return 0;
1209     }
1210
1211     if (!spapr->htab) {
1212         assert(kvm_enabled());
1213
1214         fd = kvmppc_get_htab_fd(true);
1215         if (fd < 0) {
1216             fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n",
1217                     strerror(errno));
1218         }
1219     }
1220
1221     while (true) {
1222         uint32_t index;
1223         uint16_t n_valid, n_invalid;
1224
1225         index = qemu_get_be32(f);
1226         n_valid = qemu_get_be16(f);
1227         n_invalid = qemu_get_be16(f);
1228
1229         if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1230             /* End of Stream */
1231             break;
1232         }
1233
1234         if ((index + n_valid + n_invalid) >
1235             (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1236             /* Bad index in stream */
1237             fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) "
1238                     "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid,
1239                     spapr->htab_shift);
1240             return -EINVAL;
1241         }
1242
1243         if (spapr->htab) {
1244             if (n_valid) {
1245                 qemu_get_buffer(f, HPTE(spapr->htab, index),
1246                                 HASH_PTE_SIZE_64 * n_valid);
1247             }
1248             if (n_invalid) {
1249                 memset(HPTE(spapr->htab, index + n_valid), 0,
1250                        HASH_PTE_SIZE_64 * n_invalid);
1251             }
1252         } else {
1253             int rc;
1254
1255             assert(fd >= 0);
1256
1257             rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1258             if (rc < 0) {
1259                 return rc;
1260             }
1261         }
1262     }
1263
1264     if (!spapr->htab) {
1265         assert(fd >= 0);
1266         close(fd);
1267     }
1268
1269     return 0;
1270 }
1271
1272 static SaveVMHandlers savevm_htab_handlers = {
1273     .save_live_setup = htab_save_setup,
1274     .save_live_iterate = htab_save_iterate,
1275     .save_live_complete = htab_save_complete,
1276     .load_state = htab_load,
1277 };
1278
1279 /* pSeries LPAR / sPAPR hardware init */
1280 static void ppc_spapr_init(MachineState *machine)
1281 {
1282     ram_addr_t ram_size = machine->ram_size;
1283     const char *cpu_model = machine->cpu_model;
1284     const char *kernel_filename = machine->kernel_filename;
1285     const char *kernel_cmdline = machine->kernel_cmdline;
1286     const char *initrd_filename = machine->initrd_filename;
1287     const char *boot_device = machine->boot_order;
1288     PowerPCCPU *cpu;
1289     CPUPPCState *env;
1290     PCIHostState *phb;
1291     int i;
1292     MemoryRegion *sysmem = get_system_memory();
1293     MemoryRegion *ram = g_new(MemoryRegion, 1);
1294     hwaddr rma_alloc_size;
1295     hwaddr node0_size = (nb_numa_nodes > 1) ? numa_info[0].node_mem : ram_size;
1296     uint32_t initrd_base = 0;
1297     long kernel_size = 0, initrd_size = 0;
1298     long load_limit, rtas_limit, fw_size;
1299     bool kernel_le = false;
1300     char *filename;
1301
1302     msi_supported = true;
1303
1304     spapr = g_malloc0(sizeof(*spapr));
1305     QLIST_INIT(&spapr->phbs);
1306
1307     cpu_ppc_hypercall = emulate_spapr_hypercall;
1308
1309     /* Allocate RMA if necessary */
1310     rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
1311
1312     if (rma_alloc_size == -1) {
1313         hw_error("qemu: Unable to create RMA\n");
1314         exit(1);
1315     }
1316
1317     if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1318         spapr->rma_size = rma_alloc_size;
1319     } else {
1320         spapr->rma_size = node0_size;
1321
1322         /* With KVM, we don't actually know whether KVM supports an
1323          * unbounded RMA (PR KVM) or is limited by the hash table size
1324          * (HV KVM using VRMA), so we always assume the latter
1325          *
1326          * In that case, we also limit the initial allocations for RTAS
1327          * etc... to 256M since we have no way to know what the VRMA size
1328          * is going to be as it depends on the size of the hash table
1329          * isn't determined yet.
1330          */
1331         if (kvm_enabled()) {
1332             spapr->vrma_adjust = 1;
1333             spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1334         }
1335     }
1336
1337     if (spapr->rma_size > node0_size) {
1338         fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n",
1339                 spapr->rma_size);
1340         exit(1);
1341     }
1342
1343     /* We place the device tree and RTAS just below either the top of the RMA,
1344      * or just below 2GB, whichever is lowere, so that it can be
1345      * processed with 32-bit real mode code if necessary */
1346     rtas_limit = MIN(spapr->rma_size, 0x80000000);
1347     spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1348     spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1349     load_limit = spapr->fdt_addr - FW_OVERHEAD;
1350
1351     /* We aim for a hash table of size 1/128 the size of RAM.  The
1352      * normal rule of thumb is 1/64 the size of RAM, but that's much
1353      * more than needed for the Linux guests we support. */
1354     spapr->htab_shift = 18; /* Minimum architected size */
1355     while (spapr->htab_shift <= 46) {
1356         if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) {
1357             break;
1358         }
1359         spapr->htab_shift++;
1360     }
1361
1362     /* Set up Interrupt Controller before we create the VCPUs */
1363     spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads,
1364                                   XICS_IRQS);
1365     spapr->next_irq = XICS_IRQ_BASE;
1366
1367     /* init CPUs */
1368     if (cpu_model == NULL) {
1369         cpu_model = kvm_enabled() ? "host" : "POWER7";
1370     }
1371     for (i = 0; i < smp_cpus; i++) {
1372         cpu = cpu_ppc_init(cpu_model);
1373         if (cpu == NULL) {
1374             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
1375             exit(1);
1376         }
1377         env = &cpu->env;
1378
1379         /* Set time-base frequency to 512 MHz */
1380         cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1381
1382         /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1383          * MSR[IP] should never be set.
1384          */
1385         env->msr_mask &= ~(1 << 6);
1386
1387         /* Tell KVM that we're in PAPR mode */
1388         if (kvm_enabled()) {
1389             kvmppc_set_papr(cpu);
1390         }
1391
1392         if (cpu->max_compat) {
1393             if (ppc_set_compat(cpu, cpu->max_compat) < 0) {
1394                 exit(1);
1395             }
1396         }
1397
1398         xics_cpu_setup(spapr->icp, cpu);
1399
1400         qemu_register_reset(spapr_cpu_reset, cpu);
1401     }
1402
1403     /* allocate RAM */
1404     spapr->ram_limit = ram_size;
1405     if (spapr->ram_limit > rma_alloc_size) {
1406         ram_addr_t nonrma_base = rma_alloc_size;
1407         ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size;
1408
1409         memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size);
1410         vmstate_register_ram_global(ram);
1411         memory_region_add_subregion(sysmem, nonrma_base, ram);
1412     }
1413
1414     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1415     spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
1416                                            rtas_limit - spapr->rtas_addr);
1417     if (spapr->rtas_size < 0) {
1418         hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
1419         exit(1);
1420     }
1421     if (spapr->rtas_size > RTAS_MAX_SIZE) {
1422         hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
1423                  spapr->rtas_size, RTAS_MAX_SIZE);
1424         exit(1);
1425     }
1426     g_free(filename);
1427
1428     /* Set up EPOW events infrastructure */
1429     spapr_events_init(spapr);
1430
1431     /* Set up VIO bus */
1432     spapr->vio_bus = spapr_vio_bus_init();
1433
1434     for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1435         if (serial_hds[i]) {
1436             spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1437         }
1438     }
1439
1440     /* We always have at least the nvram device on VIO */
1441     spapr_create_nvram(spapr);
1442
1443     /* Set up PCI */
1444     spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW);
1445     spapr_pci_rtas_init();
1446
1447     phb = spapr_create_phb(spapr, 0);
1448
1449     for (i = 0; i < nb_nics; i++) {
1450         NICInfo *nd = &nd_table[i];
1451
1452         if (!nd->model) {
1453             nd->model = g_strdup("ibmveth");
1454         }
1455
1456         if (strcmp(nd->model, "ibmveth") == 0) {
1457             spapr_vlan_create(spapr->vio_bus, nd);
1458         } else {
1459             pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1460         }
1461     }
1462
1463     for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1464         spapr_vscsi_create(spapr->vio_bus);
1465     }
1466
1467     /* Graphics */
1468     if (spapr_vga_init(phb->bus)) {
1469         spapr->has_graphics = true;
1470     }
1471
1472     if (usb_enabled(spapr->has_graphics)) {
1473         pci_create_simple(phb->bus, -1, "pci-ohci");
1474         if (spapr->has_graphics) {
1475             usbdevice_create("keyboard");
1476             usbdevice_create("mouse");
1477         }
1478     }
1479
1480     if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1481         fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
1482                 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
1483         exit(1);
1484     }
1485
1486     if (kernel_filename) {
1487         uint64_t lowaddr = 0;
1488
1489         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1490                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
1491         if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1492             kernel_size = load_elf(kernel_filename,
1493                                    translate_kernel_address, NULL,
1494                                    NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0);
1495             kernel_le = kernel_size > 0;
1496         }
1497         if (kernel_size < 0) {
1498             fprintf(stderr, "qemu: error loading %s: %s\n",
1499                     kernel_filename, load_elf_strerror(kernel_size));
1500             exit(1);
1501         }
1502
1503         /* load initrd */
1504         if (initrd_filename) {
1505             /* Try to locate the initrd in the gap between the kernel
1506              * and the firmware. Add a bit of space just in case
1507              */
1508             initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1509             initrd_size = load_image_targphys(initrd_filename, initrd_base,
1510                                               load_limit - initrd_base);
1511             if (initrd_size < 0) {
1512                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
1513                         initrd_filename);
1514                 exit(1);
1515             }
1516         } else {
1517             initrd_base = 0;
1518             initrd_size = 0;
1519         }
1520     }
1521
1522     if (bios_name == NULL) {
1523         bios_name = FW_FILE_NAME;
1524     }
1525     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1526     fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
1527     if (fw_size < 0) {
1528         hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
1529         exit(1);
1530     }
1531     g_free(filename);
1532
1533     spapr->entry_point = 0x100;
1534
1535     vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1536     register_savevm_live(NULL, "spapr/htab", -1, 1,
1537                          &savevm_htab_handlers, spapr);
1538
1539     /* Prepare the device tree */
1540     spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
1541                                             kernel_size, kernel_le,
1542                                             boot_device, kernel_cmdline,
1543                                             spapr->epow_irq);
1544     assert(spapr->fdt_skel != NULL);
1545 }
1546
1547 static int spapr_kvm_type(const char *vm_type)
1548 {
1549     if (!vm_type) {
1550         return 0;
1551     }
1552
1553     if (!strcmp(vm_type, "HV")) {
1554         return 1;
1555     }
1556
1557     if (!strcmp(vm_type, "PR")) {
1558         return 2;
1559     }
1560
1561     error_report("Unknown kvm-type specified '%s'", vm_type);
1562     exit(1);
1563 }
1564
1565 /*
1566  * Implementation of an interface to adjust firmware patch
1567  * for the bootindex property handling.
1568  */
1569 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
1570                                    DeviceState *dev)
1571 {
1572 #define CAST(type, obj, name) \
1573     ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1574     SCSIDevice *d = CAST(SCSIDevice,  dev, TYPE_SCSI_DEVICE);
1575     sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
1576
1577     if (d) {
1578         void *spapr = CAST(void, bus->parent, "spapr-vscsi");
1579         VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
1580         USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
1581
1582         if (spapr) {
1583             /*
1584              * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1585              * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
1586              * in the top 16 bits of the 64-bit LUN
1587              */
1588             unsigned id = 0x8000 | (d->id << 8) | d->lun;
1589             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
1590                                    (uint64_t)id << 48);
1591         } else if (virtio) {
1592             /*
1593              * We use SRP luns of the form 01000000 | (target << 8) | lun
1594              * in the top 32 bits of the 64-bit LUN
1595              * Note: the quote above is from SLOF and it is wrong,
1596              * the actual binding is:
1597              * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
1598              */
1599             unsigned id = 0x1000000 | (d->id << 16) | d->lun;
1600             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
1601                                    (uint64_t)id << 32);
1602         } else if (usb) {
1603             /*
1604              * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
1605              * in the top 32 bits of the 64-bit LUN
1606              */
1607             unsigned usb_port = atoi(usb->port->path);
1608             unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
1609             return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
1610                                    (uint64_t)id << 32);
1611         }
1612     }
1613
1614     if (phb) {
1615         /* Replace "pci" with "pci@800000020000000" */
1616         return g_strdup_printf("pci@%"PRIX64, phb->buid);
1617     }
1618
1619     return NULL;
1620 }
1621
1622 static char *spapr_get_kvm_type(Object *obj, Error **errp)
1623 {
1624     sPAPRMachineState *sm = SPAPR_MACHINE(obj);
1625
1626     return g_strdup(sm->kvm_type);
1627 }
1628
1629 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
1630 {
1631     sPAPRMachineState *sm = SPAPR_MACHINE(obj);
1632
1633     g_free(sm->kvm_type);
1634     sm->kvm_type = g_strdup(value);
1635 }
1636
1637 static void spapr_machine_initfn(Object *obj)
1638 {
1639     object_property_add_str(obj, "kvm-type",
1640                             spapr_get_kvm_type, spapr_set_kvm_type, NULL);
1641 }
1642
1643 static void spapr_machine_class_init(ObjectClass *oc, void *data)
1644 {
1645     MachineClass *mc = MACHINE_CLASS(oc);
1646     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
1647
1648     mc->name = "pseries";
1649     mc->desc = "pSeries Logical Partition (PAPR compliant)";
1650     mc->is_default = 1;
1651     mc->init = ppc_spapr_init;
1652     mc->reset = ppc_spapr_reset;
1653     mc->block_default_type = IF_SCSI;
1654     mc->max_cpus = MAX_CPUS;
1655     mc->no_parallel = 1;
1656     mc->default_boot_order = NULL;
1657     mc->kvm_type = spapr_kvm_type;
1658
1659     fwc->get_dev_path = spapr_get_fw_dev_path;
1660 }
1661
1662 static const TypeInfo spapr_machine_info = {
1663     .name          = TYPE_SPAPR_MACHINE,
1664     .parent        = TYPE_MACHINE,
1665     .instance_size = sizeof(sPAPRMachineState),
1666     .instance_init = spapr_machine_initfn,
1667     .class_init    = spapr_machine_class_init,
1668     .interfaces = (InterfaceInfo[]) {
1669         { TYPE_FW_PATH_PROVIDER },
1670         { }
1671     },
1672 };
1673
1674 static void spapr_machine_register_types(void)
1675 {
1676     type_register_static(&spapr_machine_info);
1677 }
1678
1679 type_init(spapr_machine_register_types)