2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "sysemu/sysemu.h"
29 #include "hw/fw-path-provider.h"
32 #include "sysemu/blockdev.h"
33 #include "sysemu/cpus.h"
34 #include "sysemu/kvm.h"
36 #include "mmu-hash64.h"
38 #include "hw/boards.h"
39 #include "hw/ppc/ppc.h"
40 #include "hw/loader.h"
42 #include "hw/ppc/spapr.h"
43 #include "hw/ppc/spapr_vio.h"
44 #include "hw/pci-host/spapr.h"
45 #include "hw/ppc/xics.h"
46 #include "hw/pci/msi.h"
48 #include "hw/pci/pci.h"
49 #include "hw/scsi/scsi.h"
50 #include "hw/virtio/virtio-scsi.h"
52 #include "exec/address-spaces.h"
54 #include "qemu/config-file.h"
55 #include "qemu/error-report.h"
59 /* SLOF memory layout:
61 * SLOF raw image loaded at 0, copies its romfs right below the flat
62 * device-tree, then position SLOF itself 31M below that
64 * So we set FW_OVERHEAD to 40MB which should account for all of that
67 * We load our kernel at 4M, leaving space for SLOF initial image
69 #define FDT_MAX_SIZE 0x40000
70 #define RTAS_MAX_SIZE 0x10000
71 #define FW_MAX_SIZE 0x400000
72 #define FW_FILE_NAME "slof.bin"
73 #define FW_OVERHEAD 0x2800000
74 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
76 #define MIN_RMA_SLOF 128UL
78 #define TIMEBASE_FREQ 512000000ULL
81 #define XICS_IRQS 1024
83 #define PHANDLE_XICP 0x00001111
85 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
87 #define TYPE_SPAPR_MACHINE "spapr-machine"
89 sPAPREnvironment
*spapr
;
91 int spapr_allocate_irq(int hint
, bool lsi
)
97 if (hint
>= spapr
->next_irq
) {
98 spapr
->next_irq
= hint
+ 1;
100 /* FIXME: we should probably check for collisions somehow */
102 irq
= spapr
->next_irq
++;
105 /* Configure irq type */
106 if (!xics_get_qirq(spapr
->icp
, irq
)) {
110 xics_set_irq_type(spapr
->icp
, irq
, lsi
);
116 * Allocate block of consequtive IRQs, returns a number of the first.
117 * If msi==true, aligns the first IRQ number to num.
119 int spapr_allocate_irq_block(int num
, bool lsi
, bool msi
)
125 * MSIMesage::data is used for storing VIRQ so
126 * it has to be aligned to num to support multiple
127 * MSI vectors. MSI-X is not affected by this.
128 * The hint is used for the first IRQ, the rest should
129 * be allocated continuously.
132 assert((num
== 1) || (num
== 2) || (num
== 4) ||
133 (num
== 8) || (num
== 16) || (num
== 32));
134 hint
= (spapr
->next_irq
+ num
- 1) & ~(num
- 1);
137 for (i
= 0; i
< num
; ++i
) {
140 irq
= spapr_allocate_irq(hint
, lsi
);
150 /* If the above doesn't create a consecutive block then that's
152 assert(irq
== (first
+ i
));
158 static XICSState
*try_create_xics(const char *type
, int nr_servers
,
163 dev
= qdev_create(NULL
, type
);
164 qdev_prop_set_uint32(dev
, "nr_servers", nr_servers
);
165 qdev_prop_set_uint32(dev
, "nr_irqs", nr_irqs
);
166 if (qdev_init(dev
) < 0) {
170 return XICS_COMMON(dev
);
173 static XICSState
*xics_system_init(int nr_servers
, int nr_irqs
)
175 XICSState
*icp
= NULL
;
178 QemuOpts
*machine_opts
= qemu_get_machine_opts();
179 bool irqchip_allowed
= qemu_opt_get_bool(machine_opts
,
180 "kernel_irqchip", true);
181 bool irqchip_required
= qemu_opt_get_bool(machine_opts
,
182 "kernel_irqchip", false);
183 if (irqchip_allowed
) {
184 icp
= try_create_xics(TYPE_KVM_XICS
, nr_servers
, nr_irqs
);
187 if (irqchip_required
&& !icp
) {
188 perror("Failed to create in-kernel XICS\n");
194 icp
= try_create_xics(TYPE_XICS
, nr_servers
, nr_irqs
);
198 perror("Failed to create XICS\n");
205 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
209 uint32_t servers_prop
[smt_threads
];
210 uint32_t gservers_prop
[smt_threads
* 2];
211 int index
= ppc_get_vcpu_dt_id(cpu
);
213 if (cpu
->cpu_version
) {
214 ret
= fdt_setprop(fdt
, offset
, "cpu-version",
215 &cpu
->cpu_version
, sizeof(cpu
->cpu_version
));
221 /* Build interrupt servers and gservers properties */
222 for (i
= 0; i
< smt_threads
; i
++) {
223 servers_prop
[i
] = cpu_to_be32(index
+ i
);
224 /* Hack, direct the group queues back to cpu 0 */
225 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
226 gservers_prop
[i
*2 + 1] = 0;
228 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
229 servers_prop
, sizeof(servers_prop
));
233 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
234 gservers_prop
, sizeof(gservers_prop
));
239 static int spapr_fixup_cpu_dt(void *fdt
, sPAPREnvironment
*spapr
)
244 int smt
= kvmppc_smt_threads();
245 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
248 DeviceClass
*dc
= DEVICE_GET_CLASS(cpu
);
249 int index
= ppc_get_vcpu_dt_id(POWERPC_CPU(cpu
));
250 uint32_t associativity
[] = {cpu_to_be32(0x5),
254 cpu_to_be32(cpu
->numa_node
),
257 if ((index
% smt
) != 0) {
261 snprintf(cpu_model
, 32, "/cpus/%s@%x", dc
->fw_name
,
264 offset
= fdt_path_offset(fdt
, cpu_model
);
269 if (nb_numa_nodes
> 1) {
270 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
271 sizeof(associativity
));
277 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
278 pft_size_prop
, sizeof(pft_size_prop
));
283 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, POWERPC_CPU(cpu
),
293 static size_t create_page_sizes_prop(CPUPPCState
*env
, uint32_t *prop
,
296 size_t maxcells
= maxsize
/ sizeof(uint32_t);
300 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
301 struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
303 if (!sps
->page_shift
) {
306 for (count
= 0; count
< PPC_PAGE_SIZES_MAX_SZ
; count
++) {
307 if (sps
->enc
[count
].page_shift
== 0) {
311 if ((p
- prop
) >= (maxcells
- 3 - count
* 2)) {
314 *(p
++) = cpu_to_be32(sps
->page_shift
);
315 *(p
++) = cpu_to_be32(sps
->slb_enc
);
316 *(p
++) = cpu_to_be32(count
);
317 for (j
= 0; j
< count
; j
++) {
318 *(p
++) = cpu_to_be32(sps
->enc
[j
].page_shift
);
319 *(p
++) = cpu_to_be32(sps
->enc
[j
].pte_enc
);
323 return (p
- prop
) * sizeof(uint32_t);
330 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
331 #exp, fdt_strerror(ret)); \
337 static void *spapr_create_fdt_skel(hwaddr initrd_base
,
341 const char *boot_device
,
342 const char *kernel_cmdline
,
347 uint32_t start_prop
= cpu_to_be32(initrd_base
);
348 uint32_t end_prop
= cpu_to_be32(initrd_base
+ initrd_size
);
349 char hypertas_prop
[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
350 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode";
351 char qemu_hypertas_prop
[] = "hcall-memop1";
352 uint32_t refpoints
[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
353 uint32_t interrupt_server_ranges_prop
[] = {0, cpu_to_be32(smp_cpus
)};
354 int smt
= kvmppc_smt_threads();
355 unsigned char vec5
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
356 QemuOpts
*opts
= qemu_opts_find(qemu_find_opts("smp-opts"), NULL
);
357 unsigned sockets
= opts
? qemu_opt_get_number(opts
, "sockets", 0) : 0;
358 uint32_t cpus_per_socket
= sockets
? (smp_cpus
/ sockets
) : 1;
360 fdt
= g_malloc0(FDT_MAX_SIZE
);
361 _FDT((fdt_create(fdt
, FDT_MAX_SIZE
)));
364 _FDT((fdt_add_reservemap_entry(fdt
, KERNEL_LOAD_ADDR
, kernel_size
)));
367 _FDT((fdt_add_reservemap_entry(fdt
, initrd_base
, initrd_size
)));
369 _FDT((fdt_finish_reservemap(fdt
)));
372 _FDT((fdt_begin_node(fdt
, "")));
373 _FDT((fdt_property_string(fdt
, "device_type", "chrp")));
374 _FDT((fdt_property_string(fdt
, "model", "IBM pSeries (emulated by qemu)")));
375 _FDT((fdt_property_string(fdt
, "compatible", "qemu,pseries")));
377 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x2)));
378 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x2)));
381 _FDT((fdt_begin_node(fdt
, "chosen")));
383 /* Set Form1_affinity */
384 _FDT((fdt_property(fdt
, "ibm,architecture-vec-5", vec5
, sizeof(vec5
))));
386 _FDT((fdt_property_string(fdt
, "bootargs", kernel_cmdline
)));
387 _FDT((fdt_property(fdt
, "linux,initrd-start",
388 &start_prop
, sizeof(start_prop
))));
389 _FDT((fdt_property(fdt
, "linux,initrd-end",
390 &end_prop
, sizeof(end_prop
))));
392 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
393 cpu_to_be64(kernel_size
) };
395 _FDT((fdt_property(fdt
, "qemu,boot-kernel", &kprop
, sizeof(kprop
))));
397 _FDT((fdt_property(fdt
, "qemu,boot-kernel-le", NULL
, 0)));
401 _FDT((fdt_property_string(fdt
, "qemu,boot-device", boot_device
)));
403 _FDT((fdt_property_cell(fdt
, "qemu,graphic-width", graphic_width
)));
404 _FDT((fdt_property_cell(fdt
, "qemu,graphic-height", graphic_height
)));
405 _FDT((fdt_property_cell(fdt
, "qemu,graphic-depth", graphic_depth
)));
407 _FDT((fdt_end_node(fdt
)));
410 _FDT((fdt_begin_node(fdt
, "cpus")));
412 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
413 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
416 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
417 CPUPPCState
*env
= &cpu
->env
;
418 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
419 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
420 int index
= ppc_get_vcpu_dt_id(cpu
);
422 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
423 0xffffffff, 0xffffffff};
424 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ
;
425 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
426 uint32_t page_sizes_prop
[64];
427 size_t page_sizes_prop_size
;
429 if ((index
% smt
) != 0) {
433 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
435 _FDT((fdt_begin_node(fdt
, nodename
)));
439 _FDT((fdt_property_cell(fdt
, "reg", index
)));
440 _FDT((fdt_property_string(fdt
, "device_type", "cpu")));
442 _FDT((fdt_property_cell(fdt
, "cpu-version", env
->spr
[SPR_PVR
])));
443 _FDT((fdt_property_cell(fdt
, "d-cache-block-size",
444 env
->dcache_line_size
)));
445 _FDT((fdt_property_cell(fdt
, "d-cache-line-size",
446 env
->dcache_line_size
)));
447 _FDT((fdt_property_cell(fdt
, "i-cache-block-size",
448 env
->icache_line_size
)));
449 _FDT((fdt_property_cell(fdt
, "i-cache-line-size",
450 env
->icache_line_size
)));
452 if (pcc
->l1_dcache_size
) {
453 _FDT((fdt_property_cell(fdt
, "d-cache-size", pcc
->l1_dcache_size
)));
455 fprintf(stderr
, "Warning: Unknown L1 dcache size for cpu\n");
457 if (pcc
->l1_icache_size
) {
458 _FDT((fdt_property_cell(fdt
, "i-cache-size", pcc
->l1_icache_size
)));
460 fprintf(stderr
, "Warning: Unknown L1 icache size for cpu\n");
463 _FDT((fdt_property_cell(fdt
, "timebase-frequency", tbfreq
)));
464 _FDT((fdt_property_cell(fdt
, "clock-frequency", cpufreq
)));
465 _FDT((fdt_property_cell(fdt
, "ibm,slb-size", env
->slb_nr
)));
466 _FDT((fdt_property_string(fdt
, "status", "okay")));
467 _FDT((fdt_property(fdt
, "64-bit", NULL
, 0)));
469 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
470 _FDT((fdt_property(fdt
, "ibm,purr", NULL
, 0)));
473 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
474 _FDT((fdt_property(fdt
, "ibm,processor-segment-sizes",
475 segs
, sizeof(segs
))));
478 /* Advertise VMX/VSX (vector extensions) if available
479 * 0 / no property == no vector extensions
480 * 1 == VMX / Altivec available
481 * 2 == VSX available */
482 if (env
->insns_flags
& PPC_ALTIVEC
) {
483 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
485 _FDT((fdt_property_cell(fdt
, "ibm,vmx", vmx
)));
488 /* Advertise DFP (Decimal Floating Point) if available
489 * 0 / no property == no DFP
490 * 1 == DFP available */
491 if (env
->insns_flags2
& PPC2_DFP
) {
492 _FDT((fdt_property_cell(fdt
, "ibm,dfp", 1)));
495 page_sizes_prop_size
= create_page_sizes_prop(env
, page_sizes_prop
,
496 sizeof(page_sizes_prop
));
497 if (page_sizes_prop_size
) {
498 _FDT((fdt_property(fdt
, "ibm,segment-page-sizes",
499 page_sizes_prop
, page_sizes_prop_size
)));
502 _FDT((fdt_property_cell(fdt
, "ibm,chip-id",
503 cs
->cpu_index
/ cpus_per_socket
)));
505 _FDT((fdt_end_node(fdt
)));
508 _FDT((fdt_end_node(fdt
)));
511 _FDT((fdt_begin_node(fdt
, "rtas")));
513 _FDT((fdt_property(fdt
, "ibm,hypertas-functions", hypertas_prop
,
514 sizeof(hypertas_prop
))));
515 _FDT((fdt_property(fdt
, "qemu,hypertas-functions", qemu_hypertas_prop
,
516 sizeof(qemu_hypertas_prop
))));
518 _FDT((fdt_property(fdt
, "ibm,associativity-reference-points",
519 refpoints
, sizeof(refpoints
))));
521 _FDT((fdt_property_cell(fdt
, "rtas-error-log-max", RTAS_ERROR_LOG_MAX
)));
523 _FDT((fdt_end_node(fdt
)));
525 /* interrupt controller */
526 _FDT((fdt_begin_node(fdt
, "interrupt-controller")));
528 _FDT((fdt_property_string(fdt
, "device_type",
529 "PowerPC-External-Interrupt-Presentation")));
530 _FDT((fdt_property_string(fdt
, "compatible", "IBM,ppc-xicp")));
531 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
532 _FDT((fdt_property(fdt
, "ibm,interrupt-server-ranges",
533 interrupt_server_ranges_prop
,
534 sizeof(interrupt_server_ranges_prop
))));
535 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 2)));
536 _FDT((fdt_property_cell(fdt
, "linux,phandle", PHANDLE_XICP
)));
537 _FDT((fdt_property_cell(fdt
, "phandle", PHANDLE_XICP
)));
539 _FDT((fdt_end_node(fdt
)));
542 _FDT((fdt_begin_node(fdt
, "vdevice")));
544 _FDT((fdt_property_string(fdt
, "device_type", "vdevice")));
545 _FDT((fdt_property_string(fdt
, "compatible", "IBM,vdevice")));
546 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
547 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
548 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 0x2)));
549 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
551 _FDT((fdt_end_node(fdt
)));
554 spapr_events_fdt_skel(fdt
, epow_irq
);
556 _FDT((fdt_end_node(fdt
))); /* close root node */
557 _FDT((fdt_finish(fdt
)));
562 static int spapr_populate_memory(sPAPREnvironment
*spapr
, void *fdt
)
564 uint32_t associativity
[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
565 cpu_to_be32(0x0), cpu_to_be32(0x0),
568 hwaddr node0_size
, mem_start
, node_size
;
569 uint64_t mem_reg_property
[2];
573 if (nb_numa_nodes
> 1 && node_mem
[0] < ram_size
) {
574 node0_size
= node_mem
[0];
576 node0_size
= ram_size
;
580 mem_reg_property
[0] = 0;
581 mem_reg_property
[1] = cpu_to_be64(spapr
->rma_size
);
582 off
= fdt_add_subnode(fdt
, 0, "memory@0");
584 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
585 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
586 sizeof(mem_reg_property
))));
587 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
588 sizeof(associativity
))));
591 if (node0_size
> spapr
->rma_size
) {
592 mem_reg_property
[0] = cpu_to_be64(spapr
->rma_size
);
593 mem_reg_property
[1] = cpu_to_be64(node0_size
- spapr
->rma_size
);
595 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, spapr
->rma_size
);
596 off
= fdt_add_subnode(fdt
, 0, mem_name
);
598 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
599 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
600 sizeof(mem_reg_property
))));
601 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
602 sizeof(associativity
))));
605 /* RAM: Node 1 and beyond */
606 mem_start
= node0_size
;
607 for (i
= 1; i
< nb_numa_nodes
; i
++) {
608 mem_reg_property
[0] = cpu_to_be64(mem_start
);
609 if (mem_start
>= ram_size
) {
612 node_size
= node_mem
[i
];
613 if (node_size
> ram_size
- mem_start
) {
614 node_size
= ram_size
- mem_start
;
617 mem_reg_property
[1] = cpu_to_be64(node_size
);
618 associativity
[3] = associativity
[4] = cpu_to_be32(i
);
619 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, mem_start
);
620 off
= fdt_add_subnode(fdt
, 0, mem_name
);
622 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
623 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
624 sizeof(mem_reg_property
))));
625 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
626 sizeof(associativity
))));
627 mem_start
+= node_size
;
633 static void spapr_finalize_fdt(sPAPREnvironment
*spapr
,
644 fdt
= g_malloc(FDT_MAX_SIZE
);
646 /* open out the base tree into a temp buffer for the final tweaks */
647 _FDT((fdt_open_into(spapr
->fdt_skel
, fdt
, FDT_MAX_SIZE
)));
649 ret
= spapr_populate_memory(spapr
, fdt
);
651 fprintf(stderr
, "couldn't setup memory nodes in fdt\n");
655 ret
= spapr_populate_vdevice(spapr
->vio_bus
, fdt
);
657 fprintf(stderr
, "couldn't setup vio devices in fdt\n");
661 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
662 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
666 fprintf(stderr
, "couldn't setup PCI devices in fdt\n");
671 ret
= spapr_rtas_device_tree_setup(fdt
, rtas_addr
, rtas_size
);
673 fprintf(stderr
, "Couldn't set up RTAS device tree properties\n");
676 /* Advertise NUMA via ibm,associativity */
677 ret
= spapr_fixup_cpu_dt(fdt
, spapr
);
679 fprintf(stderr
, "Couldn't finalize CPU device tree properties\n");
682 bootlist
= get_boot_devices_list(&cb
, true);
683 if (cb
&& bootlist
) {
684 int offset
= fdt_path_offset(fdt
, "/chosen");
688 for (i
= 0; i
< cb
; i
++) {
689 if (bootlist
[i
] == '\n') {
694 ret
= fdt_setprop_string(fdt
, offset
, "qemu,boot-list", bootlist
);
697 if (!spapr
->has_graphics
) {
698 spapr_populate_chosen_stdout(fdt
, spapr
->vio_bus
);
701 _FDT((fdt_pack(fdt
)));
703 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
704 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
705 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
709 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
714 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
716 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
719 static void emulate_spapr_hypercall(PowerPCCPU
*cpu
)
721 CPUPPCState
*env
= &cpu
->env
;
724 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
725 env
->gpr
[3] = H_PRIVILEGE
;
727 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
731 static void spapr_reset_htab(sPAPREnvironment
*spapr
)
735 /* allocate hash page table. For now we always make this 16mb,
736 * later we should probably make it scale to the size of guest
739 shift
= kvmppc_reset_htab(spapr
->htab_shift
);
742 /* Kernel handles htab, we don't need to allocate one */
743 spapr
->htab_shift
= shift
;
744 kvmppc_kern_htab
= true;
747 /* Allocate an htab if we don't yet have one */
748 spapr
->htab
= qemu_memalign(HTAB_SIZE(spapr
), HTAB_SIZE(spapr
));
752 memset(spapr
->htab
, 0, HTAB_SIZE(spapr
));
755 /* Update the RMA size if necessary */
756 if (spapr
->vrma_adjust
) {
757 hwaddr node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
758 spapr
->rma_size
= kvmppc_rma_size(node0_size
, spapr
->htab_shift
);
762 static void ppc_spapr_reset(void)
764 PowerPCCPU
*first_ppc_cpu
;
766 /* Reset the hash table & recalc the RMA */
767 spapr_reset_htab(spapr
);
769 qemu_devices_reset();
772 spapr_finalize_fdt(spapr
, spapr
->fdt_addr
, spapr
->rtas_addr
,
775 /* Set up the entry state */
776 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
777 first_ppc_cpu
->env
.gpr
[3] = spapr
->fdt_addr
;
778 first_ppc_cpu
->env
.gpr
[5] = 0;
779 first_cpu
->halted
= 0;
780 first_ppc_cpu
->env
.nip
= spapr
->entry_point
;
784 static void spapr_cpu_reset(void *opaque
)
786 PowerPCCPU
*cpu
= opaque
;
787 CPUState
*cs
= CPU(cpu
);
788 CPUPPCState
*env
= &cpu
->env
;
792 /* All CPUs start halted. CPU0 is unhalted from the machine level
793 * reset code and the rest are explicitly started up by the guest
794 * using an RTAS call */
797 env
->spr
[SPR_HIOR
] = 0;
799 env
->external_htab
= (uint8_t *)spapr
->htab
;
800 if (kvm_enabled() && !env
->external_htab
) {
802 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
803 * functions do the right thing.
805 env
->external_htab
= (void *)1;
809 * htab_mask is the mask used to normalize hash value to PTEG index.
810 * htab_shift is log2 of hash table size.
811 * We have 8 hpte per group, and each hpte is 16 bytes.
812 * ie have 128 bytes per hpte entry.
814 env
->htab_mask
= (1ULL << ((spapr
)->htab_shift
- 7)) - 1;
815 env
->spr
[SPR_SDR1
] = (target_ulong
)(uintptr_t)spapr
->htab
|
816 (spapr
->htab_shift
- 18);
819 static void spapr_create_nvram(sPAPREnvironment
*spapr
)
821 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
822 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
825 qdev_prop_set_drive_nofail(dev
, "drive", dinfo
->bdrv
);
828 qdev_init_nofail(dev
);
830 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
833 /* Returns whether we want to use VGA or not */
834 static int spapr_vga_init(PCIBus
*pci_bus
)
836 switch (vga_interface_type
) {
842 return pci_vga_init(pci_bus
) != NULL
;
844 fprintf(stderr
, "This vga model is not supported,"
845 "currently it only supports -vga std\n");
850 static const VMStateDescription vmstate_spapr
= {
853 .minimum_version_id
= 1,
854 .fields
= (VMStateField
[]) {
855 VMSTATE_UINT32(next_irq
, sPAPREnvironment
),
858 VMSTATE_UINT64(rtc_offset
, sPAPREnvironment
),
859 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPREnvironment
, 2),
860 VMSTATE_END_OF_LIST()
864 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
865 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
866 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
867 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
869 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
871 sPAPREnvironment
*spapr
= opaque
;
873 /* "Iteration" header */
874 qemu_put_be32(f
, spapr
->htab_shift
);
877 spapr
->htab_save_index
= 0;
878 spapr
->htab_first_pass
= true;
880 assert(kvm_enabled());
882 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
883 if (spapr
->htab_fd
< 0) {
884 fprintf(stderr
, "Unable to open fd for reading hash table from KVM: %s\n",
894 static void htab_save_first_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
897 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
898 int index
= spapr
->htab_save_index
;
899 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
901 assert(spapr
->htab_first_pass
);
906 /* Consume invalid HPTEs */
907 while ((index
< htabslots
)
908 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
910 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
913 /* Consume valid HPTEs */
915 while ((index
< htabslots
)
916 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
918 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
921 if (index
> chunkstart
) {
922 int n_valid
= index
- chunkstart
;
924 qemu_put_be32(f
, chunkstart
);
925 qemu_put_be16(f
, n_valid
);
927 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
928 HASH_PTE_SIZE_64
* n_valid
);
930 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
934 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
936 if (index
>= htabslots
) {
937 assert(index
== htabslots
);
939 spapr
->htab_first_pass
= false;
941 spapr
->htab_save_index
= index
;
944 static int htab_save_later_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
947 bool final
= max_ns
< 0;
948 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
949 int examined
= 0, sent
= 0;
950 int index
= spapr
->htab_save_index
;
951 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
953 assert(!spapr
->htab_first_pass
);
956 int chunkstart
, invalidstart
;
958 /* Consume non-dirty HPTEs */
959 while ((index
< htabslots
)
960 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
966 /* Consume valid dirty HPTEs */
967 while ((index
< htabslots
)
968 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
969 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
970 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
975 invalidstart
= index
;
976 /* Consume invalid dirty HPTEs */
977 while ((index
< htabslots
)
978 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
979 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
980 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
985 if (index
> chunkstart
) {
986 int n_valid
= invalidstart
- chunkstart
;
987 int n_invalid
= index
- invalidstart
;
989 qemu_put_be32(f
, chunkstart
);
990 qemu_put_be16(f
, n_valid
);
991 qemu_put_be16(f
, n_invalid
);
992 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
993 HASH_PTE_SIZE_64
* n_valid
);
994 sent
+= index
- chunkstart
;
996 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1001 if (examined
>= htabslots
) {
1005 if (index
>= htabslots
) {
1006 assert(index
== htabslots
);
1009 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
1011 if (index
>= htabslots
) {
1012 assert(index
== htabslots
);
1016 spapr
->htab_save_index
= index
;
1018 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
1021 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1022 #define MAX_KVM_BUF_SIZE 2048
1024 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
1026 sPAPREnvironment
*spapr
= opaque
;
1029 /* Iteration header */
1030 qemu_put_be32(f
, 0);
1033 assert(kvm_enabled());
1035 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
,
1036 MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
1040 } else if (spapr
->htab_first_pass
) {
1041 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
1043 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
1047 qemu_put_be32(f
, 0);
1048 qemu_put_be16(f
, 0);
1049 qemu_put_be16(f
, 0);
1054 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
1056 sPAPREnvironment
*spapr
= opaque
;
1058 /* Iteration header */
1059 qemu_put_be32(f
, 0);
1064 assert(kvm_enabled());
1066 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
, MAX_KVM_BUF_SIZE
, -1);
1070 close(spapr
->htab_fd
);
1071 spapr
->htab_fd
= -1;
1073 htab_save_later_pass(f
, spapr
, -1);
1077 qemu_put_be32(f
, 0);
1078 qemu_put_be16(f
, 0);
1079 qemu_put_be16(f
, 0);
1084 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
1086 sPAPREnvironment
*spapr
= opaque
;
1087 uint32_t section_hdr
;
1090 if (version_id
< 1 || version_id
> 1) {
1091 fprintf(stderr
, "htab_load() bad version\n");
1095 section_hdr
= qemu_get_be32(f
);
1098 /* First section, just the hash shift */
1099 if (spapr
->htab_shift
!= section_hdr
) {
1106 assert(kvm_enabled());
1108 fd
= kvmppc_get_htab_fd(true);
1110 fprintf(stderr
, "Unable to open fd to restore KVM hash table: %s\n",
1117 uint16_t n_valid
, n_invalid
;
1119 index
= qemu_get_be32(f
);
1120 n_valid
= qemu_get_be16(f
);
1121 n_invalid
= qemu_get_be16(f
);
1123 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1128 if ((index
+ n_valid
+ n_invalid
) >
1129 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1130 /* Bad index in stream */
1131 fprintf(stderr
, "htab_load() bad index %d (%hd+%hd entries) "
1132 "in htab stream (htab_shift=%d)\n", index
, n_valid
, n_invalid
,
1139 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1140 HASH_PTE_SIZE_64
* n_valid
);
1143 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1144 HASH_PTE_SIZE_64
* n_invalid
);
1151 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1166 static SaveVMHandlers savevm_htab_handlers
= {
1167 .save_live_setup
= htab_save_setup
,
1168 .save_live_iterate
= htab_save_iterate
,
1169 .save_live_complete
= htab_save_complete
,
1170 .load_state
= htab_load
,
1173 /* pSeries LPAR / sPAPR hardware init */
1174 static void ppc_spapr_init(MachineState
*machine
)
1176 ram_addr_t ram_size
= machine
->ram_size
;
1177 const char *cpu_model
= machine
->cpu_model
;
1178 const char *kernel_filename
= machine
->kernel_filename
;
1179 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1180 const char *initrd_filename
= machine
->initrd_filename
;
1181 const char *boot_device
= machine
->boot_order
;
1186 MemoryRegion
*sysmem
= get_system_memory();
1187 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1188 hwaddr rma_alloc_size
;
1189 hwaddr node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
1190 uint32_t initrd_base
= 0;
1191 long kernel_size
= 0, initrd_size
= 0;
1192 long load_limit
, rtas_limit
, fw_size
;
1193 bool kernel_le
= false;
1196 msi_supported
= true;
1198 spapr
= g_malloc0(sizeof(*spapr
));
1199 QLIST_INIT(&spapr
->phbs
);
1201 cpu_ppc_hypercall
= emulate_spapr_hypercall
;
1203 /* Allocate RMA if necessary */
1204 rma_alloc_size
= kvmppc_alloc_rma("ppc_spapr.rma", sysmem
);
1206 if (rma_alloc_size
== -1) {
1207 hw_error("qemu: Unable to create RMA\n");
1211 if (rma_alloc_size
&& (rma_alloc_size
< node0_size
)) {
1212 spapr
->rma_size
= rma_alloc_size
;
1214 spapr
->rma_size
= node0_size
;
1216 /* With KVM, we don't actually know whether KVM supports an
1217 * unbounded RMA (PR KVM) or is limited by the hash table size
1218 * (HV KVM using VRMA), so we always assume the latter
1220 * In that case, we also limit the initial allocations for RTAS
1221 * etc... to 256M since we have no way to know what the VRMA size
1222 * is going to be as it depends on the size of the hash table
1223 * isn't determined yet.
1225 if (kvm_enabled()) {
1226 spapr
->vrma_adjust
= 1;
1227 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
1231 if (spapr
->rma_size
> node0_size
) {
1232 fprintf(stderr
, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")\n",
1237 /* We place the device tree and RTAS just below either the top of the RMA,
1238 * or just below 2GB, whichever is lowere, so that it can be
1239 * processed with 32-bit real mode code if necessary */
1240 rtas_limit
= MIN(spapr
->rma_size
, 0x80000000);
1241 spapr
->rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1242 spapr
->fdt_addr
= spapr
->rtas_addr
- FDT_MAX_SIZE
;
1243 load_limit
= spapr
->fdt_addr
- FW_OVERHEAD
;
1245 /* We aim for a hash table of size 1/128 the size of RAM. The
1246 * normal rule of thumb is 1/64 the size of RAM, but that's much
1247 * more than needed for the Linux guests we support. */
1248 spapr
->htab_shift
= 18; /* Minimum architected size */
1249 while (spapr
->htab_shift
<= 46) {
1250 if ((1ULL << (spapr
->htab_shift
+ 7)) >= ram_size
) {
1253 spapr
->htab_shift
++;
1256 /* Set up Interrupt Controller before we create the VCPUs */
1257 spapr
->icp
= xics_system_init(smp_cpus
* kvmppc_smt_threads() / smp_threads
,
1259 spapr
->next_irq
= XICS_IRQ_BASE
;
1262 if (cpu_model
== NULL
) {
1263 cpu_model
= kvm_enabled() ? "host" : "POWER7";
1265 for (i
= 0; i
< smp_cpus
; i
++) {
1266 cpu
= cpu_ppc_init(cpu_model
);
1268 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
1273 /* Set time-base frequency to 512 MHz */
1274 cpu_ppc_tb_init(env
, TIMEBASE_FREQ
);
1276 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1277 * MSR[IP] should never be set.
1279 env
->msr_mask
&= ~(1 << 6);
1281 /* Tell KVM that we're in PAPR mode */
1282 if (kvm_enabled()) {
1283 kvmppc_set_papr(cpu
);
1286 if (cpu
->max_compat
) {
1287 if (ppc_set_compat(cpu
, cpu
->max_compat
) < 0) {
1292 xics_cpu_setup(spapr
->icp
, cpu
);
1294 qemu_register_reset(spapr_cpu_reset
, cpu
);
1298 spapr
->ram_limit
= ram_size
;
1299 if (spapr
->ram_limit
> rma_alloc_size
) {
1300 ram_addr_t nonrma_base
= rma_alloc_size
;
1301 ram_addr_t nonrma_size
= spapr
->ram_limit
- rma_alloc_size
;
1303 memory_region_init_ram(ram
, NULL
, "ppc_spapr.ram", nonrma_size
);
1304 vmstate_register_ram_global(ram
);
1305 memory_region_add_subregion(sysmem
, nonrma_base
, ram
);
1308 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
1309 spapr
->rtas_size
= load_image_targphys(filename
, spapr
->rtas_addr
,
1310 rtas_limit
- spapr
->rtas_addr
);
1311 if (spapr
->rtas_size
< 0) {
1312 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1315 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
1316 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
1317 spapr
->rtas_size
, RTAS_MAX_SIZE
);
1322 /* Set up EPOW events infrastructure */
1323 spapr_events_init(spapr
);
1325 /* Set up VIO bus */
1326 spapr
->vio_bus
= spapr_vio_bus_init();
1328 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1329 if (serial_hds
[i
]) {
1330 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
1334 /* We always have at least the nvram device on VIO */
1335 spapr_create_nvram(spapr
);
1338 spapr_pci_msi_init(spapr
, SPAPR_PCI_MSI_WINDOW
);
1339 spapr_pci_rtas_init();
1341 phb
= spapr_create_phb(spapr
, 0);
1343 for (i
= 0; i
< nb_nics
; i
++) {
1344 NICInfo
*nd
= &nd_table
[i
];
1347 nd
->model
= g_strdup("ibmveth");
1350 if (strcmp(nd
->model
, "ibmveth") == 0) {
1351 spapr_vlan_create(spapr
->vio_bus
, nd
);
1353 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
1357 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
1358 spapr_vscsi_create(spapr
->vio_bus
);
1362 if (spapr_vga_init(phb
->bus
)) {
1363 spapr
->has_graphics
= true;
1366 if (usb_enabled(spapr
->has_graphics
)) {
1367 pci_create_simple(phb
->bus
, -1, "pci-ohci");
1368 if (spapr
->has_graphics
) {
1369 usbdevice_create("keyboard");
1370 usbdevice_create("mouse");
1374 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
1375 fprintf(stderr
, "qemu: pSeries SLOF firmware requires >= "
1376 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF
);
1380 if (kernel_filename
) {
1381 uint64_t lowaddr
= 0;
1383 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
1384 NULL
, &lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
1385 if (kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
1386 kernel_size
= load_elf(kernel_filename
,
1387 translate_kernel_address
, NULL
,
1388 NULL
, &lowaddr
, NULL
, 0, ELF_MACHINE
, 0);
1389 kernel_le
= kernel_size
> 0;
1391 if (kernel_size
< 0) {
1392 fprintf(stderr
, "qemu: error loading %s: %s\n",
1393 kernel_filename
, load_elf_strerror(kernel_size
));
1398 if (initrd_filename
) {
1399 /* Try to locate the initrd in the gap between the kernel
1400 * and the firmware. Add a bit of space just in case
1402 initrd_base
= (KERNEL_LOAD_ADDR
+ kernel_size
+ 0x1ffff) & ~0xffff;
1403 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
1404 load_limit
- initrd_base
);
1405 if (initrd_size
< 0) {
1406 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
1416 if (bios_name
== NULL
) {
1417 bios_name
= FW_FILE_NAME
;
1419 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1420 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
1422 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1427 spapr
->entry_point
= 0x100;
1429 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
1430 register_savevm_live(NULL
, "spapr/htab", -1, 1,
1431 &savevm_htab_handlers
, spapr
);
1433 /* Prepare the device tree */
1434 spapr
->fdt_skel
= spapr_create_fdt_skel(initrd_base
, initrd_size
,
1435 kernel_size
, kernel_le
,
1436 boot_device
, kernel_cmdline
,
1438 assert(spapr
->fdt_skel
!= NULL
);
1441 static int spapr_kvm_type(const char *vm_type
)
1447 if (!strcmp(vm_type
, "HV")) {
1451 if (!strcmp(vm_type
, "PR")) {
1455 error_report("Unknown kvm-type specified '%s'", vm_type
);
1460 * Implementation of an interface to adjust firmware patch
1461 * for the bootindex property handling.
1463 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
1466 #define CAST(type, obj, name) \
1467 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1468 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
1469 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1472 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
1473 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
1474 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
1478 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1479 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
1480 * in the top 16 bits of the 64-bit LUN
1482 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
1483 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1484 (uint64_t)id
<< 48);
1485 } else if (virtio
) {
1487 * We use SRP luns of the form 01000000 | (target << 8) | lun
1488 * in the top 32 bits of the 64-bit LUN
1489 * Note: the quote above is from SLOF and it is wrong,
1490 * the actual binding is:
1491 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
1493 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
1494 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1495 (uint64_t)id
<< 32);
1498 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
1499 * in the top 32 bits of the 64-bit LUN
1501 unsigned usb_port
= atoi(usb
->port
->path
);
1502 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
1503 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1504 (uint64_t)id
<< 32);
1509 /* Replace "pci" with "pci@800000020000000" */
1510 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
1516 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
1518 MachineClass
*mc
= MACHINE_CLASS(oc
);
1519 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
1521 mc
->name
= "pseries";
1522 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
1524 mc
->init
= ppc_spapr_init
;
1525 mc
->reset
= ppc_spapr_reset
;
1526 mc
->block_default_type
= IF_SCSI
;
1527 mc
->max_cpus
= MAX_CPUS
;
1528 mc
->no_parallel
= 1;
1529 mc
->default_boot_order
= NULL
;
1530 mc
->kvm_type
= spapr_kvm_type
;
1532 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
1535 static const TypeInfo spapr_machine_info
= {
1536 .name
= TYPE_SPAPR_MACHINE
,
1537 .parent
= TYPE_MACHINE
,
1538 .class_init
= spapr_machine_class_init
,
1539 .interfaces
= (InterfaceInfo
[]) {
1540 { TYPE_FW_PATH_PROVIDER
},
1545 static void spapr_machine_register_types(void)
1547 type_register_static(&spapr_machine_info
);
1550 type_init(spapr_machine_register_types
)