2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "sysemu/sysemu.h"
29 #include "hw/fw-path-provider.h"
32 #include "sysemu/blockdev.h"
33 #include "sysemu/cpus.h"
34 #include "sysemu/kvm.h"
36 #include "mmu-hash64.h"
38 #include "hw/boards.h"
39 #include "hw/ppc/ppc.h"
40 #include "hw/loader.h"
42 #include "hw/ppc/spapr.h"
43 #include "hw/ppc/spapr_vio.h"
44 #include "hw/pci-host/spapr.h"
45 #include "hw/ppc/xics.h"
46 #include "hw/pci/msi.h"
48 #include "hw/pci/pci.h"
49 #include "hw/scsi/scsi.h"
50 #include "hw/virtio/virtio-scsi.h"
52 #include "exec/address-spaces.h"
54 #include "qemu/config-file.h"
55 #include "qemu/error-report.h"
60 /* SLOF memory layout:
62 * SLOF raw image loaded at 0, copies its romfs right below the flat
63 * device-tree, then position SLOF itself 31M below that
65 * So we set FW_OVERHEAD to 40MB which should account for all of that
68 * We load our kernel at 4M, leaving space for SLOF initial image
70 #define FDT_MAX_SIZE 0x40000
71 #define RTAS_MAX_SIZE 0x10000
72 #define FW_MAX_SIZE 0x400000
73 #define FW_FILE_NAME "slof.bin"
74 #define FW_OVERHEAD 0x2800000
75 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
77 #define MIN_RMA_SLOF 128UL
79 #define TIMEBASE_FREQ 512000000ULL
82 #define XICS_IRQS 1024
84 #define PHANDLE_XICP 0x00001111
86 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
88 #define TYPE_SPAPR_MACHINE "spapr-machine"
90 sPAPREnvironment
*spapr
;
92 int spapr_allocate_irq(int hint
, bool lsi
)
98 if (hint
>= spapr
->next_irq
) {
99 spapr
->next_irq
= hint
+ 1;
101 /* FIXME: we should probably check for collisions somehow */
103 irq
= spapr
->next_irq
++;
106 /* Configure irq type */
107 if (!xics_get_qirq(spapr
->icp
, irq
)) {
111 xics_set_irq_type(spapr
->icp
, irq
, lsi
);
117 * Allocate block of consequtive IRQs, returns a number of the first.
118 * If msi==true, aligns the first IRQ number to num.
120 int spapr_allocate_irq_block(int num
, bool lsi
, bool msi
)
126 * MSIMesage::data is used for storing VIRQ so
127 * it has to be aligned to num to support multiple
128 * MSI vectors. MSI-X is not affected by this.
129 * The hint is used for the first IRQ, the rest should
130 * be allocated continuously.
133 assert((num
== 1) || (num
== 2) || (num
== 4) ||
134 (num
== 8) || (num
== 16) || (num
== 32));
135 hint
= (spapr
->next_irq
+ num
- 1) & ~(num
- 1);
138 for (i
= 0; i
< num
; ++i
) {
141 irq
= spapr_allocate_irq(hint
, lsi
);
151 /* If the above doesn't create a consecutive block then that's
153 assert(irq
== (first
+ i
));
159 static XICSState
*try_create_xics(const char *type
, int nr_servers
,
164 dev
= qdev_create(NULL
, type
);
165 qdev_prop_set_uint32(dev
, "nr_servers", nr_servers
);
166 qdev_prop_set_uint32(dev
, "nr_irqs", nr_irqs
);
167 if (qdev_init(dev
) < 0) {
171 return XICS_COMMON(dev
);
174 static XICSState
*xics_system_init(int nr_servers
, int nr_irqs
)
176 XICSState
*icp
= NULL
;
179 QemuOpts
*machine_opts
= qemu_get_machine_opts();
180 bool irqchip_allowed
= qemu_opt_get_bool(machine_opts
,
181 "kernel_irqchip", true);
182 bool irqchip_required
= qemu_opt_get_bool(machine_opts
,
183 "kernel_irqchip", false);
184 if (irqchip_allowed
) {
185 icp
= try_create_xics(TYPE_KVM_XICS
, nr_servers
, nr_irqs
);
188 if (irqchip_required
&& !icp
) {
189 perror("Failed to create in-kernel XICS\n");
195 icp
= try_create_xics(TYPE_XICS
, nr_servers
, nr_irqs
);
199 perror("Failed to create XICS\n");
206 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
210 uint32_t servers_prop
[smt_threads
];
211 uint32_t gservers_prop
[smt_threads
* 2];
212 int index
= ppc_get_vcpu_dt_id(cpu
);
214 if (cpu
->cpu_version
) {
215 ret
= fdt_setprop(fdt
, offset
, "cpu-version",
216 &cpu
->cpu_version
, sizeof(cpu
->cpu_version
));
222 /* Build interrupt servers and gservers properties */
223 for (i
= 0; i
< smt_threads
; i
++) {
224 servers_prop
[i
] = cpu_to_be32(index
+ i
);
225 /* Hack, direct the group queues back to cpu 0 */
226 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
227 gservers_prop
[i
*2 + 1] = 0;
229 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
230 servers_prop
, sizeof(servers_prop
));
234 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
235 gservers_prop
, sizeof(gservers_prop
));
240 static int spapr_fixup_cpu_dt(void *fdt
, sPAPREnvironment
*spapr
)
242 int ret
= 0, offset
, cpus_offset
;
245 int smt
= kvmppc_smt_threads();
246 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
249 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
250 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
251 int index
= ppc_get_vcpu_dt_id(cpu
);
252 uint32_t associativity
[] = {cpu_to_be32(0x5),
256 cpu_to_be32(cs
->numa_node
),
259 if ((index
% smt
) != 0) {
263 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
265 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
266 if (cpus_offset
< 0) {
267 cpus_offset
= fdt_add_subnode(fdt
, fdt_path_offset(fdt
, "/"),
269 if (cpus_offset
< 0) {
273 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
275 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
281 if (nb_numa_nodes
> 1) {
282 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
283 sizeof(associativity
));
289 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
290 pft_size_prop
, sizeof(pft_size_prop
));
295 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
,
305 static size_t create_page_sizes_prop(CPUPPCState
*env
, uint32_t *prop
,
308 size_t maxcells
= maxsize
/ sizeof(uint32_t);
312 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
313 struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
315 if (!sps
->page_shift
) {
318 for (count
= 0; count
< PPC_PAGE_SIZES_MAX_SZ
; count
++) {
319 if (sps
->enc
[count
].page_shift
== 0) {
323 if ((p
- prop
) >= (maxcells
- 3 - count
* 2)) {
326 *(p
++) = cpu_to_be32(sps
->page_shift
);
327 *(p
++) = cpu_to_be32(sps
->slb_enc
);
328 *(p
++) = cpu_to_be32(count
);
329 for (j
= 0; j
< count
; j
++) {
330 *(p
++) = cpu_to_be32(sps
->enc
[j
].page_shift
);
331 *(p
++) = cpu_to_be32(sps
->enc
[j
].pte_enc
);
335 return (p
- prop
) * sizeof(uint32_t);
342 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
343 #exp, fdt_strerror(ret)); \
349 static void *spapr_create_fdt_skel(hwaddr initrd_base
,
353 const char *boot_device
,
354 const char *kernel_cmdline
,
359 uint32_t start_prop
= cpu_to_be32(initrd_base
);
360 uint32_t end_prop
= cpu_to_be32(initrd_base
+ initrd_size
);
361 char hypertas_prop
[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
362 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode";
363 char qemu_hypertas_prop
[] = "hcall-memop1";
364 uint32_t refpoints
[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
365 uint32_t interrupt_server_ranges_prop
[] = {0, cpu_to_be32(smp_cpus
)};
366 int smt
= kvmppc_smt_threads();
367 unsigned char vec5
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
368 QemuOpts
*opts
= qemu_opts_find(qemu_find_opts("smp-opts"), NULL
);
369 unsigned sockets
= opts
? qemu_opt_get_number(opts
, "sockets", 0) : 0;
370 uint32_t cpus_per_socket
= sockets
? (smp_cpus
/ sockets
) : 1;
372 fdt
= g_malloc0(FDT_MAX_SIZE
);
373 _FDT((fdt_create(fdt
, FDT_MAX_SIZE
)));
376 _FDT((fdt_add_reservemap_entry(fdt
, KERNEL_LOAD_ADDR
, kernel_size
)));
379 _FDT((fdt_add_reservemap_entry(fdt
, initrd_base
, initrd_size
)));
381 _FDT((fdt_finish_reservemap(fdt
)));
384 _FDT((fdt_begin_node(fdt
, "")));
385 _FDT((fdt_property_string(fdt
, "device_type", "chrp")));
386 _FDT((fdt_property_string(fdt
, "model", "IBM pSeries (emulated by qemu)")));
387 _FDT((fdt_property_string(fdt
, "compatible", "qemu,pseries")));
389 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x2)));
390 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x2)));
393 _FDT((fdt_begin_node(fdt
, "chosen")));
395 /* Set Form1_affinity */
396 _FDT((fdt_property(fdt
, "ibm,architecture-vec-5", vec5
, sizeof(vec5
))));
398 _FDT((fdt_property_string(fdt
, "bootargs", kernel_cmdline
)));
399 _FDT((fdt_property(fdt
, "linux,initrd-start",
400 &start_prop
, sizeof(start_prop
))));
401 _FDT((fdt_property(fdt
, "linux,initrd-end",
402 &end_prop
, sizeof(end_prop
))));
404 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
405 cpu_to_be64(kernel_size
) };
407 _FDT((fdt_property(fdt
, "qemu,boot-kernel", &kprop
, sizeof(kprop
))));
409 _FDT((fdt_property(fdt
, "qemu,boot-kernel-le", NULL
, 0)));
413 _FDT((fdt_property_string(fdt
, "qemu,boot-device", boot_device
)));
415 _FDT((fdt_property_cell(fdt
, "qemu,graphic-width", graphic_width
)));
416 _FDT((fdt_property_cell(fdt
, "qemu,graphic-height", graphic_height
)));
417 _FDT((fdt_property_cell(fdt
, "qemu,graphic-depth", graphic_depth
)));
419 _FDT((fdt_end_node(fdt
)));
422 _FDT((fdt_begin_node(fdt
, "cpus")));
424 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
425 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
428 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
429 CPUPPCState
*env
= &cpu
->env
;
430 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
431 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
432 int index
= ppc_get_vcpu_dt_id(cpu
);
434 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
435 0xffffffff, 0xffffffff};
436 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ
;
437 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
438 uint32_t page_sizes_prop
[64];
439 size_t page_sizes_prop_size
;
441 if ((index
% smt
) != 0) {
445 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
447 _FDT((fdt_begin_node(fdt
, nodename
)));
451 _FDT((fdt_property_cell(fdt
, "reg", index
)));
452 _FDT((fdt_property_string(fdt
, "device_type", "cpu")));
454 _FDT((fdt_property_cell(fdt
, "cpu-version", env
->spr
[SPR_PVR
])));
455 _FDT((fdt_property_cell(fdt
, "d-cache-block-size",
456 env
->dcache_line_size
)));
457 _FDT((fdt_property_cell(fdt
, "d-cache-line-size",
458 env
->dcache_line_size
)));
459 _FDT((fdt_property_cell(fdt
, "i-cache-block-size",
460 env
->icache_line_size
)));
461 _FDT((fdt_property_cell(fdt
, "i-cache-line-size",
462 env
->icache_line_size
)));
464 if (pcc
->l1_dcache_size
) {
465 _FDT((fdt_property_cell(fdt
, "d-cache-size", pcc
->l1_dcache_size
)));
467 fprintf(stderr
, "Warning: Unknown L1 dcache size for cpu\n");
469 if (pcc
->l1_icache_size
) {
470 _FDT((fdt_property_cell(fdt
, "i-cache-size", pcc
->l1_icache_size
)));
472 fprintf(stderr
, "Warning: Unknown L1 icache size for cpu\n");
475 _FDT((fdt_property_cell(fdt
, "timebase-frequency", tbfreq
)));
476 _FDT((fdt_property_cell(fdt
, "clock-frequency", cpufreq
)));
477 _FDT((fdt_property_cell(fdt
, "ibm,slb-size", env
->slb_nr
)));
478 _FDT((fdt_property_string(fdt
, "status", "okay")));
479 _FDT((fdt_property(fdt
, "64-bit", NULL
, 0)));
481 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
482 _FDT((fdt_property(fdt
, "ibm,purr", NULL
, 0)));
485 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
486 _FDT((fdt_property(fdt
, "ibm,processor-segment-sizes",
487 segs
, sizeof(segs
))));
490 /* Advertise VMX/VSX (vector extensions) if available
491 * 0 / no property == no vector extensions
492 * 1 == VMX / Altivec available
493 * 2 == VSX available */
494 if (env
->insns_flags
& PPC_ALTIVEC
) {
495 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
497 _FDT((fdt_property_cell(fdt
, "ibm,vmx", vmx
)));
500 /* Advertise DFP (Decimal Floating Point) if available
501 * 0 / no property == no DFP
502 * 1 == DFP available */
503 if (env
->insns_flags2
& PPC2_DFP
) {
504 _FDT((fdt_property_cell(fdt
, "ibm,dfp", 1)));
507 page_sizes_prop_size
= create_page_sizes_prop(env
, page_sizes_prop
,
508 sizeof(page_sizes_prop
));
509 if (page_sizes_prop_size
) {
510 _FDT((fdt_property(fdt
, "ibm,segment-page-sizes",
511 page_sizes_prop
, page_sizes_prop_size
)));
514 _FDT((fdt_property_cell(fdt
, "ibm,chip-id",
515 cs
->cpu_index
/ cpus_per_socket
)));
517 _FDT((fdt_end_node(fdt
)));
520 _FDT((fdt_end_node(fdt
)));
523 _FDT((fdt_begin_node(fdt
, "rtas")));
525 _FDT((fdt_property(fdt
, "ibm,hypertas-functions", hypertas_prop
,
526 sizeof(hypertas_prop
))));
527 _FDT((fdt_property(fdt
, "qemu,hypertas-functions", qemu_hypertas_prop
,
528 sizeof(qemu_hypertas_prop
))));
530 _FDT((fdt_property(fdt
, "ibm,associativity-reference-points",
531 refpoints
, sizeof(refpoints
))));
533 _FDT((fdt_property_cell(fdt
, "rtas-error-log-max", RTAS_ERROR_LOG_MAX
)));
535 _FDT((fdt_end_node(fdt
)));
537 /* interrupt controller */
538 _FDT((fdt_begin_node(fdt
, "interrupt-controller")));
540 _FDT((fdt_property_string(fdt
, "device_type",
541 "PowerPC-External-Interrupt-Presentation")));
542 _FDT((fdt_property_string(fdt
, "compatible", "IBM,ppc-xicp")));
543 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
544 _FDT((fdt_property(fdt
, "ibm,interrupt-server-ranges",
545 interrupt_server_ranges_prop
,
546 sizeof(interrupt_server_ranges_prop
))));
547 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 2)));
548 _FDT((fdt_property_cell(fdt
, "linux,phandle", PHANDLE_XICP
)));
549 _FDT((fdt_property_cell(fdt
, "phandle", PHANDLE_XICP
)));
551 _FDT((fdt_end_node(fdt
)));
554 _FDT((fdt_begin_node(fdt
, "vdevice")));
556 _FDT((fdt_property_string(fdt
, "device_type", "vdevice")));
557 _FDT((fdt_property_string(fdt
, "compatible", "IBM,vdevice")));
558 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
559 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
560 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 0x2)));
561 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
563 _FDT((fdt_end_node(fdt
)));
566 spapr_events_fdt_skel(fdt
, epow_irq
);
568 _FDT((fdt_end_node(fdt
))); /* close root node */
569 _FDT((fdt_finish(fdt
)));
574 int spapr_h_cas_compose_response(target_ulong addr
, target_ulong size
)
576 void *fdt
, *fdt_skel
;
577 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
581 /* Create sceleton */
582 fdt_skel
= g_malloc0(size
);
583 _FDT((fdt_create(fdt_skel
, size
)));
584 _FDT((fdt_begin_node(fdt_skel
, "")));
585 _FDT((fdt_end_node(fdt_skel
)));
586 _FDT((fdt_finish(fdt_skel
)));
587 fdt
= g_malloc0(size
);
588 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
591 /* Place to make changes to the tree */
593 /* Pack resulting tree */
594 _FDT((fdt_pack(fdt
)));
596 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
597 trace_spapr_cas_failed(size
);
601 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
602 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
603 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
609 static int spapr_populate_memory(sPAPREnvironment
*spapr
, void *fdt
)
611 uint32_t associativity
[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
612 cpu_to_be32(0x0), cpu_to_be32(0x0),
615 hwaddr node0_size
, mem_start
, node_size
;
616 uint64_t mem_reg_property
[2];
620 if (nb_numa_nodes
> 1 && node_mem
[0] < ram_size
) {
621 node0_size
= node_mem
[0];
623 node0_size
= ram_size
;
627 mem_reg_property
[0] = 0;
628 mem_reg_property
[1] = cpu_to_be64(spapr
->rma_size
);
629 off
= fdt_add_subnode(fdt
, 0, "memory@0");
631 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
632 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
633 sizeof(mem_reg_property
))));
634 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
635 sizeof(associativity
))));
638 if (node0_size
> spapr
->rma_size
) {
639 mem_reg_property
[0] = cpu_to_be64(spapr
->rma_size
);
640 mem_reg_property
[1] = cpu_to_be64(node0_size
- spapr
->rma_size
);
642 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, spapr
->rma_size
);
643 off
= fdt_add_subnode(fdt
, 0, mem_name
);
645 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
646 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
647 sizeof(mem_reg_property
))));
648 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
649 sizeof(associativity
))));
652 /* RAM: Node 1 and beyond */
653 mem_start
= node0_size
;
654 for (i
= 1; i
< nb_numa_nodes
; i
++) {
655 mem_reg_property
[0] = cpu_to_be64(mem_start
);
656 if (mem_start
>= ram_size
) {
659 node_size
= node_mem
[i
];
660 if (node_size
> ram_size
- mem_start
) {
661 node_size
= ram_size
- mem_start
;
664 mem_reg_property
[1] = cpu_to_be64(node_size
);
665 associativity
[3] = associativity
[4] = cpu_to_be32(i
);
666 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, mem_start
);
667 off
= fdt_add_subnode(fdt
, 0, mem_name
);
669 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
670 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
671 sizeof(mem_reg_property
))));
672 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
673 sizeof(associativity
))));
674 mem_start
+= node_size
;
680 static void spapr_finalize_fdt(sPAPREnvironment
*spapr
,
691 fdt
= g_malloc(FDT_MAX_SIZE
);
693 /* open out the base tree into a temp buffer for the final tweaks */
694 _FDT((fdt_open_into(spapr
->fdt_skel
, fdt
, FDT_MAX_SIZE
)));
696 ret
= spapr_populate_memory(spapr
, fdt
);
698 fprintf(stderr
, "couldn't setup memory nodes in fdt\n");
702 ret
= spapr_populate_vdevice(spapr
->vio_bus
, fdt
);
704 fprintf(stderr
, "couldn't setup vio devices in fdt\n");
708 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
709 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
713 fprintf(stderr
, "couldn't setup PCI devices in fdt\n");
718 ret
= spapr_rtas_device_tree_setup(fdt
, rtas_addr
, rtas_size
);
720 fprintf(stderr
, "Couldn't set up RTAS device tree properties\n");
723 /* Advertise NUMA via ibm,associativity */
724 ret
= spapr_fixup_cpu_dt(fdt
, spapr
);
726 fprintf(stderr
, "Couldn't finalize CPU device tree properties\n");
729 bootlist
= get_boot_devices_list(&cb
, true);
730 if (cb
&& bootlist
) {
731 int offset
= fdt_path_offset(fdt
, "/chosen");
735 for (i
= 0; i
< cb
; i
++) {
736 if (bootlist
[i
] == '\n') {
741 ret
= fdt_setprop_string(fdt
, offset
, "qemu,boot-list", bootlist
);
744 if (!spapr
->has_graphics
) {
745 spapr_populate_chosen_stdout(fdt
, spapr
->vio_bus
);
748 _FDT((fdt_pack(fdt
)));
750 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
751 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
752 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
756 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
761 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
763 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
766 static void emulate_spapr_hypercall(PowerPCCPU
*cpu
)
768 CPUPPCState
*env
= &cpu
->env
;
771 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
772 env
->gpr
[3] = H_PRIVILEGE
;
774 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
778 static void spapr_reset_htab(sPAPREnvironment
*spapr
)
782 /* allocate hash page table. For now we always make this 16mb,
783 * later we should probably make it scale to the size of guest
786 shift
= kvmppc_reset_htab(spapr
->htab_shift
);
789 /* Kernel handles htab, we don't need to allocate one */
790 spapr
->htab_shift
= shift
;
791 kvmppc_kern_htab
= true;
794 /* Allocate an htab if we don't yet have one */
795 spapr
->htab
= qemu_memalign(HTAB_SIZE(spapr
), HTAB_SIZE(spapr
));
799 memset(spapr
->htab
, 0, HTAB_SIZE(spapr
));
802 /* Update the RMA size if necessary */
803 if (spapr
->vrma_adjust
) {
804 hwaddr node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
805 spapr
->rma_size
= kvmppc_rma_size(node0_size
, spapr
->htab_shift
);
809 static void ppc_spapr_reset(void)
811 PowerPCCPU
*first_ppc_cpu
;
813 /* Reset the hash table & recalc the RMA */
814 spapr_reset_htab(spapr
);
816 qemu_devices_reset();
819 spapr_finalize_fdt(spapr
, spapr
->fdt_addr
, spapr
->rtas_addr
,
822 /* Set up the entry state */
823 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
824 first_ppc_cpu
->env
.gpr
[3] = spapr
->fdt_addr
;
825 first_ppc_cpu
->env
.gpr
[5] = 0;
826 first_cpu
->halted
= 0;
827 first_ppc_cpu
->env
.nip
= spapr
->entry_point
;
831 static void spapr_cpu_reset(void *opaque
)
833 PowerPCCPU
*cpu
= opaque
;
834 CPUState
*cs
= CPU(cpu
);
835 CPUPPCState
*env
= &cpu
->env
;
839 /* All CPUs start halted. CPU0 is unhalted from the machine level
840 * reset code and the rest are explicitly started up by the guest
841 * using an RTAS call */
844 env
->spr
[SPR_HIOR
] = 0;
846 env
->external_htab
= (uint8_t *)spapr
->htab
;
847 if (kvm_enabled() && !env
->external_htab
) {
849 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
850 * functions do the right thing.
852 env
->external_htab
= (void *)1;
856 * htab_mask is the mask used to normalize hash value to PTEG index.
857 * htab_shift is log2 of hash table size.
858 * We have 8 hpte per group, and each hpte is 16 bytes.
859 * ie have 128 bytes per hpte entry.
861 env
->htab_mask
= (1ULL << ((spapr
)->htab_shift
- 7)) - 1;
862 env
->spr
[SPR_SDR1
] = (target_ulong
)(uintptr_t)spapr
->htab
|
863 (spapr
->htab_shift
- 18);
866 static void spapr_create_nvram(sPAPREnvironment
*spapr
)
868 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
869 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
872 qdev_prop_set_drive_nofail(dev
, "drive", dinfo
->bdrv
);
875 qdev_init_nofail(dev
);
877 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
880 /* Returns whether we want to use VGA or not */
881 static int spapr_vga_init(PCIBus
*pci_bus
)
883 switch (vga_interface_type
) {
889 return pci_vga_init(pci_bus
) != NULL
;
891 fprintf(stderr
, "This vga model is not supported,"
892 "currently it only supports -vga std\n");
897 static const VMStateDescription vmstate_spapr
= {
900 .minimum_version_id
= 1,
901 .fields
= (VMStateField
[]) {
902 VMSTATE_UINT32(next_irq
, sPAPREnvironment
),
905 VMSTATE_UINT64(rtc_offset
, sPAPREnvironment
),
906 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPREnvironment
, 2),
907 VMSTATE_END_OF_LIST()
911 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
912 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
913 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
914 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
916 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
918 sPAPREnvironment
*spapr
= opaque
;
920 /* "Iteration" header */
921 qemu_put_be32(f
, spapr
->htab_shift
);
924 spapr
->htab_save_index
= 0;
925 spapr
->htab_first_pass
= true;
927 assert(kvm_enabled());
929 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
930 if (spapr
->htab_fd
< 0) {
931 fprintf(stderr
, "Unable to open fd for reading hash table from KVM: %s\n",
941 static void htab_save_first_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
944 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
945 int index
= spapr
->htab_save_index
;
946 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
948 assert(spapr
->htab_first_pass
);
953 /* Consume invalid HPTEs */
954 while ((index
< htabslots
)
955 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
957 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
960 /* Consume valid HPTEs */
962 while ((index
< htabslots
)
963 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
965 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
968 if (index
> chunkstart
) {
969 int n_valid
= index
- chunkstart
;
971 qemu_put_be32(f
, chunkstart
);
972 qemu_put_be16(f
, n_valid
);
974 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
975 HASH_PTE_SIZE_64
* n_valid
);
977 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
981 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
983 if (index
>= htabslots
) {
984 assert(index
== htabslots
);
986 spapr
->htab_first_pass
= false;
988 spapr
->htab_save_index
= index
;
991 static int htab_save_later_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
994 bool final
= max_ns
< 0;
995 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
996 int examined
= 0, sent
= 0;
997 int index
= spapr
->htab_save_index
;
998 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1000 assert(!spapr
->htab_first_pass
);
1003 int chunkstart
, invalidstart
;
1005 /* Consume non-dirty HPTEs */
1006 while ((index
< htabslots
)
1007 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
1013 /* Consume valid dirty HPTEs */
1014 while ((index
< htabslots
)
1015 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1016 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1017 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1022 invalidstart
= index
;
1023 /* Consume invalid dirty HPTEs */
1024 while ((index
< htabslots
)
1025 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1026 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1027 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1032 if (index
> chunkstart
) {
1033 int n_valid
= invalidstart
- chunkstart
;
1034 int n_invalid
= index
- invalidstart
;
1036 qemu_put_be32(f
, chunkstart
);
1037 qemu_put_be16(f
, n_valid
);
1038 qemu_put_be16(f
, n_invalid
);
1039 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1040 HASH_PTE_SIZE_64
* n_valid
);
1041 sent
+= index
- chunkstart
;
1043 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1048 if (examined
>= htabslots
) {
1052 if (index
>= htabslots
) {
1053 assert(index
== htabslots
);
1056 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
1058 if (index
>= htabslots
) {
1059 assert(index
== htabslots
);
1063 spapr
->htab_save_index
= index
;
1065 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
1068 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1069 #define MAX_KVM_BUF_SIZE 2048
1071 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
1073 sPAPREnvironment
*spapr
= opaque
;
1076 /* Iteration header */
1077 qemu_put_be32(f
, 0);
1080 assert(kvm_enabled());
1082 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
,
1083 MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
1087 } else if (spapr
->htab_first_pass
) {
1088 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
1090 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
1094 qemu_put_be32(f
, 0);
1095 qemu_put_be16(f
, 0);
1096 qemu_put_be16(f
, 0);
1101 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
1103 sPAPREnvironment
*spapr
= opaque
;
1105 /* Iteration header */
1106 qemu_put_be32(f
, 0);
1111 assert(kvm_enabled());
1113 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
, MAX_KVM_BUF_SIZE
, -1);
1117 close(spapr
->htab_fd
);
1118 spapr
->htab_fd
= -1;
1120 htab_save_later_pass(f
, spapr
, -1);
1124 qemu_put_be32(f
, 0);
1125 qemu_put_be16(f
, 0);
1126 qemu_put_be16(f
, 0);
1131 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
1133 sPAPREnvironment
*spapr
= opaque
;
1134 uint32_t section_hdr
;
1137 if (version_id
< 1 || version_id
> 1) {
1138 fprintf(stderr
, "htab_load() bad version\n");
1142 section_hdr
= qemu_get_be32(f
);
1145 /* First section, just the hash shift */
1146 if (spapr
->htab_shift
!= section_hdr
) {
1153 assert(kvm_enabled());
1155 fd
= kvmppc_get_htab_fd(true);
1157 fprintf(stderr
, "Unable to open fd to restore KVM hash table: %s\n",
1164 uint16_t n_valid
, n_invalid
;
1166 index
= qemu_get_be32(f
);
1167 n_valid
= qemu_get_be16(f
);
1168 n_invalid
= qemu_get_be16(f
);
1170 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1175 if ((index
+ n_valid
+ n_invalid
) >
1176 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1177 /* Bad index in stream */
1178 fprintf(stderr
, "htab_load() bad index %d (%hd+%hd entries) "
1179 "in htab stream (htab_shift=%d)\n", index
, n_valid
, n_invalid
,
1186 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1187 HASH_PTE_SIZE_64
* n_valid
);
1190 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1191 HASH_PTE_SIZE_64
* n_invalid
);
1198 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1213 static SaveVMHandlers savevm_htab_handlers
= {
1214 .save_live_setup
= htab_save_setup
,
1215 .save_live_iterate
= htab_save_iterate
,
1216 .save_live_complete
= htab_save_complete
,
1217 .load_state
= htab_load
,
1220 /* pSeries LPAR / sPAPR hardware init */
1221 static void ppc_spapr_init(MachineState
*machine
)
1223 ram_addr_t ram_size
= machine
->ram_size
;
1224 const char *cpu_model
= machine
->cpu_model
;
1225 const char *kernel_filename
= machine
->kernel_filename
;
1226 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1227 const char *initrd_filename
= machine
->initrd_filename
;
1228 const char *boot_device
= machine
->boot_order
;
1233 MemoryRegion
*sysmem
= get_system_memory();
1234 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1235 hwaddr rma_alloc_size
;
1236 hwaddr node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
1237 uint32_t initrd_base
= 0;
1238 long kernel_size
= 0, initrd_size
= 0;
1239 long load_limit
, rtas_limit
, fw_size
;
1240 bool kernel_le
= false;
1243 msi_supported
= true;
1245 spapr
= g_malloc0(sizeof(*spapr
));
1246 QLIST_INIT(&spapr
->phbs
);
1248 cpu_ppc_hypercall
= emulate_spapr_hypercall
;
1250 /* Allocate RMA if necessary */
1251 rma_alloc_size
= kvmppc_alloc_rma("ppc_spapr.rma", sysmem
);
1253 if (rma_alloc_size
== -1) {
1254 hw_error("qemu: Unable to create RMA\n");
1258 if (rma_alloc_size
&& (rma_alloc_size
< node0_size
)) {
1259 spapr
->rma_size
= rma_alloc_size
;
1261 spapr
->rma_size
= node0_size
;
1263 /* With KVM, we don't actually know whether KVM supports an
1264 * unbounded RMA (PR KVM) or is limited by the hash table size
1265 * (HV KVM using VRMA), so we always assume the latter
1267 * In that case, we also limit the initial allocations for RTAS
1268 * etc... to 256M since we have no way to know what the VRMA size
1269 * is going to be as it depends on the size of the hash table
1270 * isn't determined yet.
1272 if (kvm_enabled()) {
1273 spapr
->vrma_adjust
= 1;
1274 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
1278 if (spapr
->rma_size
> node0_size
) {
1279 fprintf(stderr
, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")\n",
1284 /* We place the device tree and RTAS just below either the top of the RMA,
1285 * or just below 2GB, whichever is lowere, so that it can be
1286 * processed with 32-bit real mode code if necessary */
1287 rtas_limit
= MIN(spapr
->rma_size
, 0x80000000);
1288 spapr
->rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1289 spapr
->fdt_addr
= spapr
->rtas_addr
- FDT_MAX_SIZE
;
1290 load_limit
= spapr
->fdt_addr
- FW_OVERHEAD
;
1292 /* We aim for a hash table of size 1/128 the size of RAM. The
1293 * normal rule of thumb is 1/64 the size of RAM, but that's much
1294 * more than needed for the Linux guests we support. */
1295 spapr
->htab_shift
= 18; /* Minimum architected size */
1296 while (spapr
->htab_shift
<= 46) {
1297 if ((1ULL << (spapr
->htab_shift
+ 7)) >= ram_size
) {
1300 spapr
->htab_shift
++;
1303 /* Set up Interrupt Controller before we create the VCPUs */
1304 spapr
->icp
= xics_system_init(smp_cpus
* kvmppc_smt_threads() / smp_threads
,
1306 spapr
->next_irq
= XICS_IRQ_BASE
;
1309 if (cpu_model
== NULL
) {
1310 cpu_model
= kvm_enabled() ? "host" : "POWER7";
1312 for (i
= 0; i
< smp_cpus
; i
++) {
1313 cpu
= cpu_ppc_init(cpu_model
);
1315 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
1320 /* Set time-base frequency to 512 MHz */
1321 cpu_ppc_tb_init(env
, TIMEBASE_FREQ
);
1323 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1324 * MSR[IP] should never be set.
1326 env
->msr_mask
&= ~(1 << 6);
1328 /* Tell KVM that we're in PAPR mode */
1329 if (kvm_enabled()) {
1330 kvmppc_set_papr(cpu
);
1333 if (cpu
->max_compat
) {
1334 if (ppc_set_compat(cpu
, cpu
->max_compat
) < 0) {
1339 xics_cpu_setup(spapr
->icp
, cpu
);
1341 qemu_register_reset(spapr_cpu_reset
, cpu
);
1345 spapr
->ram_limit
= ram_size
;
1346 if (spapr
->ram_limit
> rma_alloc_size
) {
1347 ram_addr_t nonrma_base
= rma_alloc_size
;
1348 ram_addr_t nonrma_size
= spapr
->ram_limit
- rma_alloc_size
;
1350 memory_region_init_ram(ram
, NULL
, "ppc_spapr.ram", nonrma_size
);
1351 vmstate_register_ram_global(ram
);
1352 memory_region_add_subregion(sysmem
, nonrma_base
, ram
);
1355 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
1356 spapr
->rtas_size
= load_image_targphys(filename
, spapr
->rtas_addr
,
1357 rtas_limit
- spapr
->rtas_addr
);
1358 if (spapr
->rtas_size
< 0) {
1359 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1362 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
1363 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
1364 spapr
->rtas_size
, RTAS_MAX_SIZE
);
1369 /* Set up EPOW events infrastructure */
1370 spapr_events_init(spapr
);
1372 /* Set up VIO bus */
1373 spapr
->vio_bus
= spapr_vio_bus_init();
1375 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1376 if (serial_hds
[i
]) {
1377 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
1381 /* We always have at least the nvram device on VIO */
1382 spapr_create_nvram(spapr
);
1385 spapr_pci_msi_init(spapr
, SPAPR_PCI_MSI_WINDOW
);
1386 spapr_pci_rtas_init();
1388 phb
= spapr_create_phb(spapr
, 0);
1390 for (i
= 0; i
< nb_nics
; i
++) {
1391 NICInfo
*nd
= &nd_table
[i
];
1394 nd
->model
= g_strdup("ibmveth");
1397 if (strcmp(nd
->model
, "ibmveth") == 0) {
1398 spapr_vlan_create(spapr
->vio_bus
, nd
);
1400 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
1404 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
1405 spapr_vscsi_create(spapr
->vio_bus
);
1409 if (spapr_vga_init(phb
->bus
)) {
1410 spapr
->has_graphics
= true;
1413 if (usb_enabled(spapr
->has_graphics
)) {
1414 pci_create_simple(phb
->bus
, -1, "pci-ohci");
1415 if (spapr
->has_graphics
) {
1416 usbdevice_create("keyboard");
1417 usbdevice_create("mouse");
1421 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
1422 fprintf(stderr
, "qemu: pSeries SLOF firmware requires >= "
1423 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF
);
1427 if (kernel_filename
) {
1428 uint64_t lowaddr
= 0;
1430 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
1431 NULL
, &lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
1432 if (kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
1433 kernel_size
= load_elf(kernel_filename
,
1434 translate_kernel_address
, NULL
,
1435 NULL
, &lowaddr
, NULL
, 0, ELF_MACHINE
, 0);
1436 kernel_le
= kernel_size
> 0;
1438 if (kernel_size
< 0) {
1439 fprintf(stderr
, "qemu: error loading %s: %s\n",
1440 kernel_filename
, load_elf_strerror(kernel_size
));
1445 if (initrd_filename
) {
1446 /* Try to locate the initrd in the gap between the kernel
1447 * and the firmware. Add a bit of space just in case
1449 initrd_base
= (KERNEL_LOAD_ADDR
+ kernel_size
+ 0x1ffff) & ~0xffff;
1450 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
1451 load_limit
- initrd_base
);
1452 if (initrd_size
< 0) {
1453 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
1463 if (bios_name
== NULL
) {
1464 bios_name
= FW_FILE_NAME
;
1466 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1467 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
1469 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1474 spapr
->entry_point
= 0x100;
1476 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
1477 register_savevm_live(NULL
, "spapr/htab", -1, 1,
1478 &savevm_htab_handlers
, spapr
);
1480 /* Prepare the device tree */
1481 spapr
->fdt_skel
= spapr_create_fdt_skel(initrd_base
, initrd_size
,
1482 kernel_size
, kernel_le
,
1483 boot_device
, kernel_cmdline
,
1485 assert(spapr
->fdt_skel
!= NULL
);
1488 static int spapr_kvm_type(const char *vm_type
)
1494 if (!strcmp(vm_type
, "HV")) {
1498 if (!strcmp(vm_type
, "PR")) {
1502 error_report("Unknown kvm-type specified '%s'", vm_type
);
1507 * Implementation of an interface to adjust firmware patch
1508 * for the bootindex property handling.
1510 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
1513 #define CAST(type, obj, name) \
1514 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1515 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
1516 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1519 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
1520 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
1521 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
1525 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1526 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
1527 * in the top 16 bits of the 64-bit LUN
1529 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
1530 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1531 (uint64_t)id
<< 48);
1532 } else if (virtio
) {
1534 * We use SRP luns of the form 01000000 | (target << 8) | lun
1535 * in the top 32 bits of the 64-bit LUN
1536 * Note: the quote above is from SLOF and it is wrong,
1537 * the actual binding is:
1538 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
1540 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
1541 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1542 (uint64_t)id
<< 32);
1545 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
1546 * in the top 32 bits of the 64-bit LUN
1548 unsigned usb_port
= atoi(usb
->port
->path
);
1549 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
1550 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1551 (uint64_t)id
<< 32);
1556 /* Replace "pci" with "pci@800000020000000" */
1557 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
1563 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
1565 MachineClass
*mc
= MACHINE_CLASS(oc
);
1566 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
1568 mc
->name
= "pseries";
1569 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
1571 mc
->init
= ppc_spapr_init
;
1572 mc
->reset
= ppc_spapr_reset
;
1573 mc
->block_default_type
= IF_SCSI
;
1574 mc
->max_cpus
= MAX_CPUS
;
1575 mc
->no_parallel
= 1;
1576 mc
->default_boot_order
= NULL
;
1577 mc
->kvm_type
= spapr_kvm_type
;
1579 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
1582 static const TypeInfo spapr_machine_info
= {
1583 .name
= TYPE_SPAPR_MACHINE
,
1584 .parent
= TYPE_MACHINE
,
1585 .class_init
= spapr_machine_class_init
,
1586 .interfaces
= (InterfaceInfo
[]) {
1587 { TYPE_FW_PATH_PROVIDER
},
1592 static void spapr_machine_register_types(void)
1594 type_register_static(&spapr_machine_info
);
1597 type_init(spapr_machine_register_types
)