2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
34 #include "hw/fw-path-provider.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
41 #include "migration/misc.h"
42 #include "migration/global_state.h"
43 #include "migration/register.h"
44 #include "mmu-hash64.h"
45 #include "mmu-book3s-v3.h"
46 #include "cpu-models.h"
49 #include "hw/boards.h"
50 #include "hw/ppc/ppc.h"
51 #include "hw/loader.h"
53 #include "hw/ppc/fdt.h"
54 #include "hw/ppc/spapr.h"
55 #include "hw/ppc/spapr_vio.h"
56 #include "hw/pci-host/spapr.h"
57 #include "hw/pci/msi.h"
59 #include "hw/pci/pci.h"
60 #include "hw/scsi/scsi.h"
61 #include "hw/virtio/virtio-scsi.h"
62 #include "hw/virtio/vhost-scsi-common.h"
64 #include "exec/address-spaces.h"
65 #include "exec/ram_addr.h"
67 #include "qemu/config-file.h"
68 #include "qemu/error-report.h"
71 #include "hw/intc/intc.h"
73 #include "qemu/cutils.h"
74 #include "hw/ppc/spapr_cpu_core.h"
75 #include "hw/mem/memory-device.h"
79 /* SLOF memory layout:
81 * SLOF raw image loaded at 0, copies its romfs right below the flat
82 * device-tree, then position SLOF itself 31M below that
84 * So we set FW_OVERHEAD to 40MB which should account for all of that
87 * We load our kernel at 4M, leaving space for SLOF initial image
89 #define FDT_MAX_SIZE 0x100000
90 #define RTAS_MAX_SIZE 0x10000
91 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
92 #define FW_MAX_SIZE 0x400000
93 #define FW_FILE_NAME "slof.bin"
94 #define FW_OVERHEAD 0x2800000
95 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
97 #define MIN_RMA_SLOF 128UL
99 #define PHANDLE_INTC 0x00001111
101 /* These two functions implement the VCPU id numbering: one to compute them
102 * all and one to identify thread 0 of a VCORE. Any change to the first one
103 * is likely to have an impact on the second one, so let's keep them close.
105 static int spapr_vcpu_id(sPAPRMachineState
*spapr
, int cpu_index
)
109 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState
*spapr
,
115 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
118 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
120 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
121 * and newer QEMUs don't even have them. In both cases, we don't want
122 * to send anything on the wire.
127 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
128 .name
= "icp/server",
130 .minimum_version_id
= 1,
131 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
132 .fields
= (VMStateField
[]) {
133 VMSTATE_UNUSED(4), /* uint32_t xirr */
134 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
135 VMSTATE_UNUSED(1), /* uint8_t mfrr */
136 VMSTATE_END_OF_LIST()
140 static void pre_2_10_vmstate_register_dummy_icp(int i
)
142 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
143 (void *)(uintptr_t) i
);
146 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
148 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
149 (void *)(uintptr_t) i
);
152 int spapr_max_server_number(sPAPRMachineState
*spapr
)
155 return DIV_ROUND_UP(max_cpus
* spapr
->vsmt
, smp_threads
);
158 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
162 uint32_t servers_prop
[smt_threads
];
163 uint32_t gservers_prop
[smt_threads
* 2];
164 int index
= spapr_get_vcpu_id(cpu
);
166 if (cpu
->compat_pvr
) {
167 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
173 /* Build interrupt servers and gservers properties */
174 for (i
= 0; i
< smt_threads
; i
++) {
175 servers_prop
[i
] = cpu_to_be32(index
+ i
);
176 /* Hack, direct the group queues back to cpu 0 */
177 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
178 gservers_prop
[i
*2 + 1] = 0;
180 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
181 servers_prop
, sizeof(servers_prop
));
185 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
186 gservers_prop
, sizeof(gservers_prop
));
191 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
193 int index
= spapr_get_vcpu_id(cpu
);
194 uint32_t associativity
[] = {cpu_to_be32(0x5),
198 cpu_to_be32(cpu
->node_id
),
201 /* Advertise NUMA via ibm,associativity */
202 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
203 sizeof(associativity
));
206 /* Populate the "ibm,pa-features" property */
207 static void spapr_populate_pa_features(sPAPRMachineState
*spapr
,
209 void *fdt
, int offset
,
212 uint8_t pa_features_206
[] = { 6, 0,
213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
214 uint8_t pa_features_207
[] = { 24, 0,
215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
219 uint8_t pa_features_300
[] = { 66, 0,
220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
235 /* 42: PM, 44: PC RA, 46: SC vec'd */
236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
237 /* 48: SIMD, 50: QP BFP, 52: String */
238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
239 /* 54: DecFP, 56: DecI, 58: SHA */
240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
241 /* 60: NM atomic, 62: RNG */
242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
244 uint8_t *pa_features
= NULL
;
247 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
248 pa_features
= pa_features_206
;
249 pa_size
= sizeof(pa_features_206
);
251 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
252 pa_features
= pa_features_207
;
253 pa_size
= sizeof(pa_features_207
);
255 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
256 pa_features
= pa_features_300
;
257 pa_size
= sizeof(pa_features_300
);
263 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
265 * Note: we keep CI large pages off by default because a 64K capable
266 * guest provisioned with large pages might otherwise try to map a qemu
267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
268 * even if that qemu runs on a 4k host.
269 * We dd this bit back here if we are confident this is not an issue
271 pa_features
[3] |= 0x20;
273 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
274 pa_features
[24] |= 0x80; /* Transactional memory support */
276 if (legacy_guest
&& pa_size
> 40) {
277 /* Workaround for broken kernels that attempt (guest) radix
278 * mode when they can't handle it, if they see the radix bit set
279 * in pa-features. So hide it from them. */
280 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
283 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
286 static int spapr_fixup_cpu_dt(void *fdt
, sPAPRMachineState
*spapr
)
288 int ret
= 0, offset
, cpus_offset
;
291 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
294 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
295 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
296 int index
= spapr_get_vcpu_id(cpu
);
297 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
299 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
303 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
305 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
306 if (cpus_offset
< 0) {
307 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
308 if (cpus_offset
< 0) {
312 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
314 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
320 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
321 pft_size_prop
, sizeof(pft_size_prop
));
326 if (nb_numa_nodes
> 1) {
327 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
);
333 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
338 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
,
339 spapr
->cas_legacy_guest_workaround
);
344 static hwaddr
spapr_node0_size(MachineState
*machine
)
348 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
349 if (numa_info
[i
].node_mem
) {
350 return MIN(pow2floor(numa_info
[i
].node_mem
),
355 return machine
->ram_size
;
358 static void add_str(GString
*s
, const gchar
*s1
)
360 g_string_append_len(s
, s1
, strlen(s1
) + 1);
363 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
366 uint32_t associativity
[] = {
367 cpu_to_be32(0x4), /* length */
368 cpu_to_be32(0x0), cpu_to_be32(0x0),
369 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
372 uint64_t mem_reg_property
[2];
375 mem_reg_property
[0] = cpu_to_be64(start
);
376 mem_reg_property
[1] = cpu_to_be64(size
);
378 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
379 off
= fdt_add_subnode(fdt
, 0, mem_name
);
381 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
382 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
383 sizeof(mem_reg_property
))));
384 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
385 sizeof(associativity
))));
389 static int spapr_populate_memory(sPAPRMachineState
*spapr
, void *fdt
)
391 MachineState
*machine
= MACHINE(spapr
);
392 hwaddr mem_start
, node_size
;
393 int i
, nb_nodes
= nb_numa_nodes
;
394 NodeInfo
*nodes
= numa_info
;
397 /* No NUMA nodes, assume there is just one node with whole RAM */
398 if (!nb_numa_nodes
) {
400 ramnode
.node_mem
= machine
->ram_size
;
404 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
405 if (!nodes
[i
].node_mem
) {
408 if (mem_start
>= machine
->ram_size
) {
411 node_size
= nodes
[i
].node_mem
;
412 if (node_size
> machine
->ram_size
- mem_start
) {
413 node_size
= machine
->ram_size
- mem_start
;
417 /* spapr_machine_init() checks for rma_size <= node0_size
419 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
420 mem_start
+= spapr
->rma_size
;
421 node_size
-= spapr
->rma_size
;
423 for ( ; node_size
; ) {
424 hwaddr sizetmp
= pow2floor(node_size
);
426 /* mem_start != 0 here */
427 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
428 sizetmp
= 1ULL << ctzl(mem_start
);
431 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
432 node_size
-= sizetmp
;
433 mem_start
+= sizetmp
;
440 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
441 sPAPRMachineState
*spapr
)
443 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
444 CPUPPCState
*env
= &cpu
->env
;
445 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
446 int index
= spapr_get_vcpu_id(cpu
);
447 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
448 0xffffffff, 0xffffffff};
449 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
450 : SPAPR_TIMEBASE_FREQ
;
451 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
452 uint32_t page_sizes_prop
[64];
453 size_t page_sizes_prop_size
;
454 uint32_t vcpus_per_socket
= smp_threads
* smp_cores
;
455 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
456 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
457 sPAPRDRConnector
*drc
;
459 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
462 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
464 drc_index
= spapr_drc_index(drc
);
465 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
468 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
469 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
471 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
472 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
473 env
->dcache_line_size
)));
474 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
475 env
->dcache_line_size
)));
476 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
477 env
->icache_line_size
)));
478 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
479 env
->icache_line_size
)));
481 if (pcc
->l1_dcache_size
) {
482 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
483 pcc
->l1_dcache_size
)));
485 warn_report("Unknown L1 dcache size for cpu");
487 if (pcc
->l1_icache_size
) {
488 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
489 pcc
->l1_icache_size
)));
491 warn_report("Unknown L1 icache size for cpu");
494 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
495 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
496 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
497 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
498 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
499 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
501 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
502 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
505 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
506 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
507 segs
, sizeof(segs
))));
510 /* Advertise VSX (vector extensions) if available
511 * 1 == VMX / Altivec available
514 * Only CPUs for which we create core types in spapr_cpu_core.c
515 * are possible, and all of those have VMX */
516 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
517 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
519 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
522 /* Advertise DFP (Decimal Floating Point) if available
523 * 0 / no property == no DFP
524 * 1 == DFP available */
525 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
526 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
529 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
530 sizeof(page_sizes_prop
));
531 if (page_sizes_prop_size
) {
532 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
533 page_sizes_prop
, page_sizes_prop_size
)));
536 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
, false);
538 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
539 cs
->cpu_index
/ vcpus_per_socket
)));
541 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
542 pft_size_prop
, sizeof(pft_size_prop
))));
544 if (nb_numa_nodes
> 1) {
545 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
548 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
550 if (pcc
->radix_page_info
) {
551 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
552 radix_AP_encodings
[i
] =
553 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
555 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
557 pcc
->radix_page_info
->count
*
558 sizeof(radix_AP_encodings
[0]))));
562 static void spapr_populate_cpus_dt_node(void *fdt
, sPAPRMachineState
*spapr
)
571 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
573 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
574 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
577 * We walk the CPUs in reverse order to ensure that CPU DT nodes
578 * created by fdt_add_subnode() end up in the right order in FDT
579 * for the guest kernel the enumerate the CPUs correctly.
581 * The CPU list cannot be traversed in reverse order, so we need
587 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
591 for (i
= n_cpus
- 1; i
>= 0; i
--) {
592 CPUState
*cs
= rev
[i
];
593 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
594 int index
= spapr_get_vcpu_id(cpu
);
595 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
598 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
602 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
603 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
606 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
612 static int spapr_rng_populate_dt(void *fdt
)
617 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
621 ret
= fdt_setprop_string(fdt
, node
, "device_type",
622 "ibm,platform-facilities");
623 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
624 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
626 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
630 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
635 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
637 MemoryDeviceInfoList
*info
;
639 for (info
= list
; info
; info
= info
->next
) {
640 MemoryDeviceInfo
*value
= info
->value
;
642 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
643 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
645 if (addr
>= pcdimm_info
->addr
&&
646 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
647 return pcdimm_info
->node
;
655 struct sPAPRDrconfCellV2
{
663 typedef struct DrconfCellQueue
{
664 struct sPAPRDrconfCellV2 cell
;
665 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
668 static DrconfCellQueue
*
669 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
670 uint32_t drc_index
, uint32_t aa_index
,
673 DrconfCellQueue
*elem
;
675 elem
= g_malloc0(sizeof(*elem
));
676 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
677 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
678 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
679 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
680 elem
->cell
.flags
= cpu_to_be32(flags
);
685 /* ibm,dynamic-memory-v2 */
686 static int spapr_populate_drmem_v2(sPAPRMachineState
*spapr
, void *fdt
,
687 int offset
, MemoryDeviceInfoList
*dimms
)
689 MachineState
*machine
= MACHINE(spapr
);
690 uint8_t *int_buf
, *cur_index
;
692 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
693 uint64_t addr
, cur_addr
, size
;
694 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
695 uint64_t mem_end
= machine
->device_memory
->base
+
696 memory_region_size(&machine
->device_memory
->mr
);
697 uint32_t node
, buf_len
, nr_entries
= 0;
698 sPAPRDRConnector
*drc
;
699 DrconfCellQueue
*elem
, *next
;
700 MemoryDeviceInfoList
*info
;
701 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
702 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
704 /* Entry to cover RAM and the gap area */
705 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
706 SPAPR_LMB_FLAGS_RESERVED
|
707 SPAPR_LMB_FLAGS_DRC_INVALID
);
708 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
711 cur_addr
= machine
->device_memory
->base
;
712 for (info
= dimms
; info
; info
= info
->next
) {
713 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
719 /* Entry for hot-pluggable area */
720 if (cur_addr
< addr
) {
721 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
723 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
724 cur_addr
, spapr_drc_index(drc
), -1, 0);
725 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
730 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
732 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
733 spapr_drc_index(drc
), node
,
734 SPAPR_LMB_FLAGS_ASSIGNED
);
735 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
737 cur_addr
= addr
+ size
;
740 /* Entry for remaining hotpluggable area */
741 if (cur_addr
< mem_end
) {
742 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
744 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
745 cur_addr
, spapr_drc_index(drc
), -1, 0);
746 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
750 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
751 int_buf
= cur_index
= g_malloc0(buf_len
);
752 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
753 cur_index
+= sizeof(nr_entries
);
755 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
756 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
757 cur_index
+= sizeof(elem
->cell
);
758 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
762 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
770 /* ibm,dynamic-memory */
771 static int spapr_populate_drmem_v1(sPAPRMachineState
*spapr
, void *fdt
,
772 int offset
, MemoryDeviceInfoList
*dimms
)
774 MachineState
*machine
= MACHINE(spapr
);
776 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
777 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
778 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
779 memory_region_size(&machine
->device_memory
->mr
)) /
781 uint32_t *int_buf
, *cur_index
, buf_len
;
784 * Allocate enough buffer size to fit in ibm,dynamic-memory
786 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
787 cur_index
= int_buf
= g_malloc0(buf_len
);
788 int_buf
[0] = cpu_to_be32(nr_lmbs
);
790 for (i
= 0; i
< nr_lmbs
; i
++) {
791 uint64_t addr
= i
* lmb_size
;
792 uint32_t *dynamic_memory
= cur_index
;
794 if (i
>= device_lmb_start
) {
795 sPAPRDRConnector
*drc
;
797 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
800 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
801 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
802 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
803 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
804 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
805 if (memory_region_present(get_system_memory(), addr
)) {
806 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
808 dynamic_memory
[5] = cpu_to_be32(0);
812 * LMB information for RMA, boot time RAM and gap b/n RAM and
813 * device memory region -- all these are marked as reserved
814 * and as having no valid DRC.
816 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
817 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
818 dynamic_memory
[2] = cpu_to_be32(0);
819 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
820 dynamic_memory
[4] = cpu_to_be32(-1);
821 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
822 SPAPR_LMB_FLAGS_DRC_INVALID
);
825 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
827 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
836 * Adds ibm,dynamic-reconfiguration-memory node.
837 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
838 * of this device tree node.
840 static int spapr_populate_drconf_memory(sPAPRMachineState
*spapr
, void *fdt
)
842 MachineState
*machine
= MACHINE(spapr
);
844 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
845 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
846 uint32_t *int_buf
, *cur_index
, buf_len
;
847 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
848 MemoryDeviceInfoList
*dimms
= NULL
;
851 * Don't create the node if there is no device memory
853 if (machine
->ram_size
== machine
->maxram_size
) {
857 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
859 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
860 sizeof(prop_lmb_size
));
865 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
870 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
875 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
876 dimms
= qmp_memory_device_list();
877 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
878 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
880 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
882 qapi_free_MemoryDeviceInfoList(dimms
);
888 /* ibm,associativity-lookup-arrays */
889 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
890 cur_index
= int_buf
= g_malloc0(buf_len
);
891 int_buf
[0] = cpu_to_be32(nr_nodes
);
892 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
894 for (i
= 0; i
< nr_nodes
; i
++) {
895 uint32_t associativity
[] = {
901 memcpy(cur_index
, associativity
, sizeof(associativity
));
904 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
905 (cur_index
- int_buf
) * sizeof(uint32_t));
911 static int spapr_dt_cas_updates(sPAPRMachineState
*spapr
, void *fdt
,
912 sPAPROptionVector
*ov5_updates
)
914 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
917 /* Generate ibm,dynamic-reconfiguration-memory node if required */
918 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
919 g_assert(smc
->dr_lmb_enabled
);
920 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
926 offset
= fdt_path_offset(fdt
, "/chosen");
928 offset
= fdt_add_subnode(fdt
, 0, "chosen");
933 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
934 "ibm,architecture-vec-5");
940 static bool spapr_hotplugged_dev_before_cas(void)
942 Object
*drc_container
, *obj
;
943 ObjectProperty
*prop
;
944 ObjectPropertyIterator iter
;
946 drc_container
= container_get(object_get_root(), "/dr-connector");
947 object_property_iter_init(&iter
, drc_container
);
948 while ((prop
= object_property_iter_next(&iter
))) {
949 if (!strstart(prop
->type
, "link<", NULL
)) {
952 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
953 if (spapr_drc_needed(obj
)) {
960 int spapr_h_cas_compose_response(sPAPRMachineState
*spapr
,
961 target_ulong addr
, target_ulong size
,
962 sPAPROptionVector
*ov5_updates
)
964 void *fdt
, *fdt_skel
;
965 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
967 if (spapr_hotplugged_dev_before_cas()) {
971 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
972 error_report("SLOF provided an unexpected CAS buffer size "
973 TARGET_FMT_lu
" (min: %zu, max: %u)",
974 size
, sizeof(hdr
), FW_MAX_SIZE
);
980 /* Create skeleton */
981 fdt_skel
= g_malloc0(size
);
982 _FDT((fdt_create(fdt_skel
, size
)));
983 _FDT((fdt_finish_reservemap(fdt_skel
)));
984 _FDT((fdt_begin_node(fdt_skel
, "")));
985 _FDT((fdt_end_node(fdt_skel
)));
986 _FDT((fdt_finish(fdt_skel
)));
987 fdt
= g_malloc0(size
);
988 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
991 /* Fixup cpu nodes */
992 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
994 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
998 /* Pack resulting tree */
999 _FDT((fdt_pack(fdt
)));
1001 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
1002 trace_spapr_cas_failed(size
);
1006 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
1007 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
1008 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
1014 static void spapr_dt_rtas(sPAPRMachineState
*spapr
, void *fdt
)
1017 GString
*hypertas
= g_string_sized_new(256);
1018 GString
*qemu_hypertas
= g_string_sized_new(256);
1019 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1020 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
1021 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
1022 uint32_t lrdr_capacity
[] = {
1023 cpu_to_be32(max_device_addr
>> 32),
1024 cpu_to_be32(max_device_addr
& 0xffffffff),
1025 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
1026 cpu_to_be32(max_cpus
/ smp_threads
),
1028 uint32_t maxdomains
[] = {
1033 cpu_to_be32(nb_numa_nodes
? nb_numa_nodes
: 1),
1036 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
1039 add_str(hypertas
, "hcall-pft");
1040 add_str(hypertas
, "hcall-term");
1041 add_str(hypertas
, "hcall-dabr");
1042 add_str(hypertas
, "hcall-interrupt");
1043 add_str(hypertas
, "hcall-tce");
1044 add_str(hypertas
, "hcall-vio");
1045 add_str(hypertas
, "hcall-splpar");
1046 add_str(hypertas
, "hcall-bulk");
1047 add_str(hypertas
, "hcall-set-mode");
1048 add_str(hypertas
, "hcall-sprg0");
1049 add_str(hypertas
, "hcall-copy");
1050 add_str(hypertas
, "hcall-debug");
1051 add_str(hypertas
, "hcall-vphn");
1052 add_str(qemu_hypertas
, "hcall-memop1");
1054 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1055 add_str(hypertas
, "hcall-multi-tce");
1058 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1059 add_str(hypertas
, "hcall-hpt-resize");
1062 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1063 hypertas
->str
, hypertas
->len
));
1064 g_string_free(hypertas
, TRUE
);
1065 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1066 qemu_hypertas
->str
, qemu_hypertas
->len
));
1067 g_string_free(qemu_hypertas
, TRUE
);
1069 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1070 refpoints
, sizeof(refpoints
)));
1072 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1073 maxdomains
, sizeof(maxdomains
)));
1075 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1076 RTAS_ERROR_LOG_MAX
));
1077 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1078 RTAS_EVENT_SCAN_RATE
));
1080 g_assert(msi_nonbroken
);
1081 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1084 * According to PAPR, rtas ibm,os-term does not guarantee a return
1085 * back to the guest cpu.
1087 * While an additional ibm,extended-os-term property indicates
1088 * that rtas call return will always occur. Set this property.
1090 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1092 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1093 lrdr_capacity
, sizeof(lrdr_capacity
)));
1095 spapr_dt_rtas_tokens(fdt
, rtas
);
1099 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1100 * and the XIVE features that the guest may request and thus the valid
1101 * values for bytes 23..26 of option vector 5:
1103 static void spapr_dt_ov5_platform_support(sPAPRMachineState
*spapr
, void *fdt
,
1106 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1109 23, spapr
->irq
->ov5
, /* Xive mode. */
1110 24, 0x00, /* Hash/Radix, filled in below. */
1111 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1112 26, 0x40, /* Radix options: GTSE == yes. */
1115 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1116 first_ppc_cpu
->compat_pvr
)) {
1118 * If we're in a pre POWER9 compat mode then the guest should
1119 * do hash and use the legacy interrupt mode
1121 val
[1] = 0x00; /* XICS */
1122 val
[3] = 0x00; /* Hash */
1123 } else if (kvm_enabled()) {
1124 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1125 val
[3] = 0x80; /* OV5_MMU_BOTH */
1126 } else if (kvmppc_has_cap_mmu_radix()) {
1127 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1129 val
[3] = 0x00; /* Hash */
1132 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1135 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1139 static void spapr_dt_chosen(sPAPRMachineState
*spapr
, void *fdt
)
1141 MachineState
*machine
= MACHINE(spapr
);
1143 const char *boot_device
= machine
->boot_order
;
1144 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1146 char *bootlist
= get_boot_devices_list(&cb
);
1148 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1150 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs", machine
->kernel_cmdline
));
1151 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1152 spapr
->initrd_base
));
1153 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1154 spapr
->initrd_base
+ spapr
->initrd_size
));
1156 if (spapr
->kernel_size
) {
1157 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1158 cpu_to_be64(spapr
->kernel_size
) };
1160 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1161 &kprop
, sizeof(kprop
)));
1162 if (spapr
->kernel_le
) {
1163 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1167 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1169 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1170 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1171 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1173 if (cb
&& bootlist
) {
1176 for (i
= 0; i
< cb
; i
++) {
1177 if (bootlist
[i
] == '\n') {
1181 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1184 if (boot_device
&& strlen(boot_device
)) {
1185 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1188 if (!spapr
->has_graphics
&& stdout_path
) {
1190 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1191 * kernel. New platforms should only use the "stdout-path" property. Set
1192 * the new property and continue using older property to remain
1193 * compatible with the existing firmware.
1195 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1196 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1199 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1201 g_free(stdout_path
);
1205 static void spapr_dt_hypervisor(sPAPRMachineState
*spapr
, void *fdt
)
1207 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1208 * KVM to work under pHyp with some guest co-operation */
1210 uint8_t hypercall
[16];
1212 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1213 /* indicate KVM hypercall interface */
1214 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1215 if (kvmppc_has_cap_fixup_hcalls()) {
1217 * Older KVM versions with older guest kernels were broken
1218 * with the magic page, don't allow the guest to map it.
1220 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1221 sizeof(hypercall
))) {
1222 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1223 hypercall
, sizeof(hypercall
)));
1228 static void *spapr_build_fdt(sPAPRMachineState
*spapr
)
1230 MachineState
*machine
= MACHINE(spapr
);
1231 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1232 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1238 fdt
= g_malloc0(FDT_MAX_SIZE
);
1239 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1242 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1243 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1244 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1247 * Add info to guest to indentify which host is it being run on
1248 * and what is the uuid of the guest
1250 if (spapr
->host_model
&& !g_str_equal(spapr
->host_model
, "none")) {
1251 if (g_str_equal(spapr
->host_model
, "passthrough")) {
1252 /* -M host-model=passthrough */
1253 if (kvmppc_get_host_model(&buf
)) {
1254 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1258 /* -M host-model=<user-string> */
1259 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1263 if (spapr
->host_serial
&& !g_str_equal(spapr
->host_serial
, "none")) {
1264 if (g_str_equal(spapr
->host_serial
, "passthrough")) {
1265 /* -M host-serial=passthrough */
1266 if (kvmppc_get_host_serial(&buf
)) {
1267 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1271 /* -M host-serial=<user-string> */
1272 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1276 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1278 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1279 if (qemu_uuid_set
) {
1280 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1284 if (qemu_get_vm_name()) {
1285 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1286 qemu_get_vm_name()));
1289 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1290 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1292 /* /interrupt controller */
1293 spapr
->irq
->dt_populate(spapr
, spapr_max_server_number(spapr
), fdt
,
1296 ret
= spapr_populate_memory(spapr
, fdt
);
1298 error_report("couldn't setup memory nodes in fdt");
1303 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1305 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1306 ret
= spapr_rng_populate_dt(fdt
);
1308 error_report("could not set up rng device in the fdt");
1313 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1314 ret
= spapr_populate_pci_dt(phb
, PHANDLE_INTC
, fdt
,
1315 spapr
->irq
->nr_msis
);
1317 error_report("couldn't setup PCI devices in fdt");
1323 spapr_populate_cpus_dt_node(fdt
, spapr
);
1325 if (smc
->dr_lmb_enabled
) {
1326 _FDT(spapr_drc_populate_dt(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1329 if (mc
->has_hotpluggable_cpus
) {
1330 int offset
= fdt_path_offset(fdt
, "/cpus");
1331 ret
= spapr_drc_populate_dt(fdt
, offset
, NULL
,
1332 SPAPR_DR_CONNECTOR_TYPE_CPU
);
1334 error_report("Couldn't set up CPU DR device tree properties");
1339 /* /event-sources */
1340 spapr_dt_events(spapr
, fdt
);
1343 spapr_dt_rtas(spapr
, fdt
);
1346 spapr_dt_chosen(spapr
, fdt
);
1349 if (kvm_enabled()) {
1350 spapr_dt_hypervisor(spapr
, fdt
);
1353 /* Build memory reserve map */
1354 if (spapr
->kernel_size
) {
1355 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1357 if (spapr
->initrd_size
) {
1358 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1361 /* ibm,client-architecture-support updates */
1362 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1364 error_report("couldn't setup CAS properties fdt");
1371 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1373 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1376 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1379 CPUPPCState
*env
= &cpu
->env
;
1381 /* The TCG path should also be holding the BQL at this point */
1382 g_assert(qemu_mutex_iothread_locked());
1385 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1386 env
->gpr
[3] = H_PRIVILEGE
;
1388 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1392 struct LPCRSyncState
{
1397 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1399 struct LPCRSyncState
*s
= arg
.host_ptr
;
1400 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1401 CPUPPCState
*env
= &cpu
->env
;
1404 cpu_synchronize_state(cs
);
1405 lpcr
= env
->spr
[SPR_LPCR
];
1408 ppc_store_lpcr(cpu
, lpcr
);
1411 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1414 struct LPCRSyncState s
= {
1419 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1423 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1425 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1427 /* Copy PATE1:GR into PATE0:HR */
1428 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1429 entry
->dw1
= spapr
->patb_entry
;
1432 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1433 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1434 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1435 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1436 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1439 * Get the fd to access the kernel htab, re-opening it if necessary
1441 static int get_htab_fd(sPAPRMachineState
*spapr
)
1443 Error
*local_err
= NULL
;
1445 if (spapr
->htab_fd
>= 0) {
1446 return spapr
->htab_fd
;
1449 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1450 if (spapr
->htab_fd
< 0) {
1451 error_report_err(local_err
);
1454 return spapr
->htab_fd
;
1457 void close_htab_fd(sPAPRMachineState
*spapr
)
1459 if (spapr
->htab_fd
>= 0) {
1460 close(spapr
->htab_fd
);
1462 spapr
->htab_fd
= -1;
1465 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1467 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1469 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1472 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1474 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1476 assert(kvm_enabled());
1482 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1485 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1488 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1489 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1493 * HTAB is controlled by KVM. Fetch into temporary buffer
1495 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1496 kvmppc_read_hptes(hptes
, ptex
, n
);
1501 * HTAB is controlled by QEMU. Just point to the internally
1504 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1507 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1508 const ppc_hash_pte64_t
*hptes
,
1511 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1514 g_free((void *)hptes
);
1517 /* Nothing to do for qemu managed HPT */
1520 static void spapr_store_hpte(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1521 uint64_t pte0
, uint64_t pte1
)
1523 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1524 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1527 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1529 if (pte0
& HPTE64_V_VALID
) {
1530 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1532 * When setting valid, we write PTE1 first. This ensures
1533 * proper synchronization with the reading code in
1534 * ppc_hash64_pteg_search()
1537 stq_p(spapr
->htab
+ offset
, pte0
);
1539 stq_p(spapr
->htab
+ offset
, pte0
);
1541 * When clearing it we set PTE0 first. This ensures proper
1542 * synchronization with the reading code in
1543 * ppc_hash64_pteg_search()
1546 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1551 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1555 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1556 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1557 * that's much more than is needed for Linux guests */
1558 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1559 shift
= MAX(shift
, 18); /* Minimum architected size */
1560 shift
= MIN(shift
, 46); /* Maximum architected size */
1564 void spapr_free_hpt(sPAPRMachineState
*spapr
)
1566 g_free(spapr
->htab
);
1568 spapr
->htab_shift
= 0;
1569 close_htab_fd(spapr
);
1572 void spapr_reallocate_hpt(sPAPRMachineState
*spapr
, int shift
,
1577 /* Clean up any HPT info from a previous boot */
1578 spapr_free_hpt(spapr
);
1580 rc
= kvmppc_reset_htab(shift
);
1582 /* kernel-side HPT needed, but couldn't allocate one */
1583 error_setg_errno(errp
, errno
,
1584 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1586 /* This is almost certainly fatal, but if the caller really
1587 * wants to carry on with shift == 0, it's welcome to try */
1588 } else if (rc
> 0) {
1589 /* kernel-side HPT allocated */
1592 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1596 spapr
->htab_shift
= shift
;
1599 /* kernel-side HPT not needed, allocate in userspace instead */
1600 size_t size
= 1ULL << shift
;
1603 spapr
->htab
= qemu_memalign(size
, size
);
1605 error_setg_errno(errp
, errno
,
1606 "Could not allocate HPT of order %d", shift
);
1610 memset(spapr
->htab
, 0, size
);
1611 spapr
->htab_shift
= shift
;
1613 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1614 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1617 /* We're setting up a hash table, so that means we're not radix */
1618 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1621 void spapr_setup_hpt_and_vrma(sPAPRMachineState
*spapr
)
1625 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1626 || (spapr
->cas_reboot
1627 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1628 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1630 uint64_t current_ram_size
;
1632 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1633 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1635 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1637 if (spapr
->vrma_adjust
) {
1638 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1643 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1645 sPAPRDRConnector
*drc
=
1646 (sPAPRDRConnector
*) object_dynamic_cast(child
,
1647 TYPE_SPAPR_DR_CONNECTOR
);
1650 spapr_drc_reset(drc
);
1656 static void spapr_machine_reset(void)
1658 MachineState
*machine
= MACHINE(qdev_get_machine());
1659 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
1660 PowerPCCPU
*first_ppc_cpu
;
1661 uint32_t rtas_limit
;
1662 hwaddr rtas_addr
, fdt_addr
;
1666 spapr_caps_apply(spapr
);
1668 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1669 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1670 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1671 spapr
->max_compat_pvr
)) {
1673 * If using KVM with radix mode available, VCPUs can be started
1674 * without a HPT because KVM will start them in radix mode.
1675 * Set the GR bit in PATE so that we know there is no HPT.
1677 spapr
->patb_entry
= PATE1_GR
;
1678 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1680 spapr_setup_hpt_and_vrma(spapr
);
1684 * If this reset wasn't generated by CAS, we should reset our
1685 * negotiated options and start from scratch
1687 if (!spapr
->cas_reboot
) {
1688 spapr_ovec_cleanup(spapr
->ov5_cas
);
1689 spapr
->ov5_cas
= spapr_ovec_new();
1691 ppc_set_compat(first_ppc_cpu
, spapr
->max_compat_pvr
, &error_fatal
);
1694 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
1695 spapr_irq_msi_reset(spapr
);
1698 qemu_devices_reset();
1701 * This is fixing some of the default configuration of the XIVE
1702 * devices. To be called after the reset of the machine devices.
1704 spapr_irq_reset(spapr
, &error_fatal
);
1706 /* DRC reset may cause a device to be unplugged. This will cause troubles
1707 * if this device is used by another device (eg, a running vhost backend
1708 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1709 * situations, we reset DRCs after all devices have been reset.
1711 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1713 spapr_clear_pending_events(spapr
);
1716 * We place the device tree and RTAS just below either the top of the RMA,
1717 * or just below 2GB, whichever is lower, so that it can be
1718 * processed with 32-bit real mode code if necessary
1720 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1721 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1722 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1724 fdt
= spapr_build_fdt(spapr
);
1726 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1730 /* Should only fail if we've built a corrupted tree */
1733 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1734 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1735 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1740 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1741 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1742 g_free(spapr
->fdt_blob
);
1743 spapr
->fdt_size
= fdt_totalsize(fdt
);
1744 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1745 spapr
->fdt_blob
= fdt
;
1747 /* Set up the entry state */
1748 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1749 first_ppc_cpu
->env
.gpr
[5] = 0;
1751 spapr
->cas_reboot
= false;
1754 static void spapr_create_nvram(sPAPRMachineState
*spapr
)
1756 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1757 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1760 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1764 qdev_init_nofail(dev
);
1766 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
1769 static void spapr_rtc_create(sPAPRMachineState
*spapr
)
1771 object_initialize(&spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
);
1772 object_property_add_child(OBJECT(spapr
), "rtc", OBJECT(&spapr
->rtc
),
1774 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1776 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1777 "date", &error_fatal
);
1780 /* Returns whether we want to use VGA or not */
1781 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1783 switch (vga_interface_type
) {
1791 return pci_vga_init(pci_bus
) != NULL
;
1794 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1799 static int spapr_pre_load(void *opaque
)
1803 rc
= spapr_caps_pre_load(opaque
);
1811 static int spapr_post_load(void *opaque
, int version_id
)
1813 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1816 err
= spapr_caps_post_migration(spapr
);
1822 * In earlier versions, there was no separate qdev for the PAPR
1823 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1824 * So when migrating from those versions, poke the incoming offset
1825 * value into the RTC device
1827 if (version_id
< 3) {
1828 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1834 if (kvm_enabled() && spapr
->patb_entry
) {
1835 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1836 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1837 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1840 * Update LPCR:HR and UPRT as they may not be set properly in
1843 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1844 LPCR_HR
| LPCR_UPRT
);
1846 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1848 error_report("Process table config unsupported by the host");
1853 err
= spapr_irq_post_load(spapr
, version_id
);
1861 static int spapr_pre_save(void *opaque
)
1865 rc
= spapr_caps_pre_save(opaque
);
1873 static bool version_before_3(void *opaque
, int version_id
)
1875 return version_id
< 3;
1878 static bool spapr_pending_events_needed(void *opaque
)
1880 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1881 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1884 static const VMStateDescription vmstate_spapr_event_entry
= {
1885 .name
= "spapr_event_log_entry",
1887 .minimum_version_id
= 1,
1888 .fields
= (VMStateField
[]) {
1889 VMSTATE_UINT32(summary
, sPAPREventLogEntry
),
1890 VMSTATE_UINT32(extended_length
, sPAPREventLogEntry
),
1891 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, sPAPREventLogEntry
, 0,
1892 NULL
, extended_length
),
1893 VMSTATE_END_OF_LIST()
1897 static const VMStateDescription vmstate_spapr_pending_events
= {
1898 .name
= "spapr_pending_events",
1900 .minimum_version_id
= 1,
1901 .needed
= spapr_pending_events_needed
,
1902 .fields
= (VMStateField
[]) {
1903 VMSTATE_QTAILQ_V(pending_events
, sPAPRMachineState
, 1,
1904 vmstate_spapr_event_entry
, sPAPREventLogEntry
, next
),
1905 VMSTATE_END_OF_LIST()
1909 static bool spapr_ov5_cas_needed(void *opaque
)
1911 sPAPRMachineState
*spapr
= opaque
;
1912 sPAPROptionVector
*ov5_mask
= spapr_ovec_new();
1913 sPAPROptionVector
*ov5_legacy
= spapr_ovec_new();
1914 sPAPROptionVector
*ov5_removed
= spapr_ovec_new();
1917 /* Prior to the introduction of sPAPROptionVector, we had two option
1918 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1919 * Both of these options encode machine topology into the device-tree
1920 * in such a way that the now-booted OS should still be able to interact
1921 * appropriately with QEMU regardless of what options were actually
1922 * negotiatied on the source side.
1924 * As such, we can avoid migrating the CAS-negotiated options if these
1925 * are the only options available on the current machine/platform.
1926 * Since these are the only options available for pseries-2.7 and
1927 * earlier, this allows us to maintain old->new/new->old migration
1930 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1931 * via default pseries-2.8 machines and explicit command-line parameters.
1932 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1933 * of the actual CAS-negotiated values to continue working properly. For
1934 * example, availability of memory unplug depends on knowing whether
1935 * OV5_HP_EVT was negotiated via CAS.
1937 * Thus, for any cases where the set of available CAS-negotiatable
1938 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1939 * include the CAS-negotiated options in the migration stream, unless
1940 * if they affect boot time behaviour only.
1942 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1943 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1944 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1946 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1947 * the mask itself since in the future it's possible "legacy" bits may be
1948 * removed via machine options, which could generate a false positive
1949 * that breaks migration.
1951 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
1952 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
1954 spapr_ovec_cleanup(ov5_mask
);
1955 spapr_ovec_cleanup(ov5_legacy
);
1956 spapr_ovec_cleanup(ov5_removed
);
1961 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1962 .name
= "spapr_option_vector_ov5_cas",
1964 .minimum_version_id
= 1,
1965 .needed
= spapr_ov5_cas_needed
,
1966 .fields
= (VMStateField
[]) {
1967 VMSTATE_STRUCT_POINTER_V(ov5_cas
, sPAPRMachineState
, 1,
1968 vmstate_spapr_ovec
, sPAPROptionVector
),
1969 VMSTATE_END_OF_LIST()
1973 static bool spapr_patb_entry_needed(void *opaque
)
1975 sPAPRMachineState
*spapr
= opaque
;
1977 return !!spapr
->patb_entry
;
1980 static const VMStateDescription vmstate_spapr_patb_entry
= {
1981 .name
= "spapr_patb_entry",
1983 .minimum_version_id
= 1,
1984 .needed
= spapr_patb_entry_needed
,
1985 .fields
= (VMStateField
[]) {
1986 VMSTATE_UINT64(patb_entry
, sPAPRMachineState
),
1987 VMSTATE_END_OF_LIST()
1991 static bool spapr_irq_map_needed(void *opaque
)
1993 sPAPRMachineState
*spapr
= opaque
;
1995 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1998 static const VMStateDescription vmstate_spapr_irq_map
= {
1999 .name
= "spapr_irq_map",
2001 .minimum_version_id
= 1,
2002 .needed
= spapr_irq_map_needed
,
2003 .fields
= (VMStateField
[]) {
2004 VMSTATE_BITMAP(irq_map
, sPAPRMachineState
, 0, irq_map_nr
),
2005 VMSTATE_END_OF_LIST()
2009 static bool spapr_dtb_needed(void *opaque
)
2011 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
2013 return smc
->update_dt_enabled
;
2016 static int spapr_dtb_pre_load(void *opaque
)
2018 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
2020 g_free(spapr
->fdt_blob
);
2021 spapr
->fdt_blob
= NULL
;
2022 spapr
->fdt_size
= 0;
2027 static const VMStateDescription vmstate_spapr_dtb
= {
2028 .name
= "spapr_dtb",
2030 .minimum_version_id
= 1,
2031 .needed
= spapr_dtb_needed
,
2032 .pre_load
= spapr_dtb_pre_load
,
2033 .fields
= (VMStateField
[]) {
2034 VMSTATE_UINT32(fdt_initial_size
, sPAPRMachineState
),
2035 VMSTATE_UINT32(fdt_size
, sPAPRMachineState
),
2036 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, sPAPRMachineState
, 0, NULL
,
2038 VMSTATE_END_OF_LIST()
2042 static const VMStateDescription vmstate_spapr
= {
2045 .minimum_version_id
= 1,
2046 .pre_load
= spapr_pre_load
,
2047 .post_load
= spapr_post_load
,
2048 .pre_save
= spapr_pre_save
,
2049 .fields
= (VMStateField
[]) {
2050 /* used to be @next_irq */
2051 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2054 VMSTATE_UINT64_TEST(rtc_offset
, sPAPRMachineState
, version_before_3
),
2056 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPRMachineState
, 2),
2057 VMSTATE_END_OF_LIST()
2059 .subsections
= (const VMStateDescription
*[]) {
2060 &vmstate_spapr_ov5_cas
,
2061 &vmstate_spapr_patb_entry
,
2062 &vmstate_spapr_pending_events
,
2063 &vmstate_spapr_cap_htm
,
2064 &vmstate_spapr_cap_vsx
,
2065 &vmstate_spapr_cap_dfp
,
2066 &vmstate_spapr_cap_cfpc
,
2067 &vmstate_spapr_cap_sbbc
,
2068 &vmstate_spapr_cap_ibs
,
2069 &vmstate_spapr_irq_map
,
2070 &vmstate_spapr_cap_nested_kvm_hv
,
2076 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2078 sPAPRMachineState
*spapr
= opaque
;
2080 /* "Iteration" header */
2081 if (!spapr
->htab_shift
) {
2082 qemu_put_be32(f
, -1);
2084 qemu_put_be32(f
, spapr
->htab_shift
);
2088 spapr
->htab_save_index
= 0;
2089 spapr
->htab_first_pass
= true;
2091 if (spapr
->htab_shift
) {
2092 assert(kvm_enabled());
2100 static void htab_save_chunk(QEMUFile
*f
, sPAPRMachineState
*spapr
,
2101 int chunkstart
, int n_valid
, int n_invalid
)
2103 qemu_put_be32(f
, chunkstart
);
2104 qemu_put_be16(f
, n_valid
);
2105 qemu_put_be16(f
, n_invalid
);
2106 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2107 HASH_PTE_SIZE_64
* n_valid
);
2110 static void htab_save_end_marker(QEMUFile
*f
)
2112 qemu_put_be32(f
, 0);
2113 qemu_put_be16(f
, 0);
2114 qemu_put_be16(f
, 0);
2117 static void htab_save_first_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
2120 bool has_timeout
= max_ns
!= -1;
2121 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2122 int index
= spapr
->htab_save_index
;
2123 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2125 assert(spapr
->htab_first_pass
);
2130 /* Consume invalid HPTEs */
2131 while ((index
< htabslots
)
2132 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2133 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2137 /* Consume valid HPTEs */
2139 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2140 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2141 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2145 if (index
> chunkstart
) {
2146 int n_valid
= index
- chunkstart
;
2148 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2151 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2155 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2157 if (index
>= htabslots
) {
2158 assert(index
== htabslots
);
2160 spapr
->htab_first_pass
= false;
2162 spapr
->htab_save_index
= index
;
2165 static int htab_save_later_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
2168 bool final
= max_ns
< 0;
2169 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2170 int examined
= 0, sent
= 0;
2171 int index
= spapr
->htab_save_index
;
2172 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2174 assert(!spapr
->htab_first_pass
);
2177 int chunkstart
, invalidstart
;
2179 /* Consume non-dirty HPTEs */
2180 while ((index
< htabslots
)
2181 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2187 /* Consume valid dirty HPTEs */
2188 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2189 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2190 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2191 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2196 invalidstart
= index
;
2197 /* Consume invalid dirty HPTEs */
2198 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2199 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2200 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2201 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2206 if (index
> chunkstart
) {
2207 int n_valid
= invalidstart
- chunkstart
;
2208 int n_invalid
= index
- invalidstart
;
2210 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2211 sent
+= index
- chunkstart
;
2213 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2218 if (examined
>= htabslots
) {
2222 if (index
>= htabslots
) {
2223 assert(index
== htabslots
);
2226 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2228 if (index
>= htabslots
) {
2229 assert(index
== htabslots
);
2233 spapr
->htab_save_index
= index
;
2235 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2238 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2239 #define MAX_KVM_BUF_SIZE 2048
2241 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2243 sPAPRMachineState
*spapr
= opaque
;
2247 /* Iteration header */
2248 if (!spapr
->htab_shift
) {
2249 qemu_put_be32(f
, -1);
2252 qemu_put_be32(f
, 0);
2256 assert(kvm_enabled());
2258 fd
= get_htab_fd(spapr
);
2263 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2267 } else if (spapr
->htab_first_pass
) {
2268 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2270 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2273 htab_save_end_marker(f
);
2278 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2280 sPAPRMachineState
*spapr
= opaque
;
2283 /* Iteration header */
2284 if (!spapr
->htab_shift
) {
2285 qemu_put_be32(f
, -1);
2288 qemu_put_be32(f
, 0);
2294 assert(kvm_enabled());
2296 fd
= get_htab_fd(spapr
);
2301 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2306 if (spapr
->htab_first_pass
) {
2307 htab_save_first_pass(f
, spapr
, -1);
2309 htab_save_later_pass(f
, spapr
, -1);
2313 htab_save_end_marker(f
);
2318 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2320 sPAPRMachineState
*spapr
= opaque
;
2321 uint32_t section_hdr
;
2323 Error
*local_err
= NULL
;
2325 if (version_id
< 1 || version_id
> 1) {
2326 error_report("htab_load() bad version");
2330 section_hdr
= qemu_get_be32(f
);
2332 if (section_hdr
== -1) {
2333 spapr_free_hpt(spapr
);
2338 /* First section gives the htab size */
2339 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2341 error_report_err(local_err
);
2348 assert(kvm_enabled());
2350 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2352 error_report_err(local_err
);
2359 uint16_t n_valid
, n_invalid
;
2361 index
= qemu_get_be32(f
);
2362 n_valid
= qemu_get_be16(f
);
2363 n_invalid
= qemu_get_be16(f
);
2365 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2370 if ((index
+ n_valid
+ n_invalid
) >
2371 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2372 /* Bad index in stream */
2374 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2375 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2381 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2382 HASH_PTE_SIZE_64
* n_valid
);
2385 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2386 HASH_PTE_SIZE_64
* n_invalid
);
2393 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2408 static void htab_save_cleanup(void *opaque
)
2410 sPAPRMachineState
*spapr
= opaque
;
2412 close_htab_fd(spapr
);
2415 static SaveVMHandlers savevm_htab_handlers
= {
2416 .save_setup
= htab_save_setup
,
2417 .save_live_iterate
= htab_save_iterate
,
2418 .save_live_complete_precopy
= htab_save_complete
,
2419 .save_cleanup
= htab_save_cleanup
,
2420 .load_state
= htab_load
,
2423 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2426 MachineState
*machine
= MACHINE(opaque
);
2427 machine
->boot_order
= g_strdup(boot_device
);
2430 static void spapr_create_lmb_dr_connectors(sPAPRMachineState
*spapr
)
2432 MachineState
*machine
= MACHINE(spapr
);
2433 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2434 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2437 for (i
= 0; i
< nr_lmbs
; i
++) {
2440 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2441 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2447 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2448 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2449 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2451 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2455 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2456 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2457 " is not aligned to %" PRIu64
" MiB",
2459 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2463 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2464 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2465 " is not aligned to %" PRIu64
" MiB",
2467 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2471 for (i
= 0; i
< nb_numa_nodes
; i
++) {
2472 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2474 "Node %d memory size 0x%" PRIx64
2475 " is not aligned to %" PRIu64
" MiB",
2476 i
, numa_info
[i
].node_mem
,
2477 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2483 /* find cpu slot in machine->possible_cpus by core_id */
2484 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2486 int index
= id
/ smp_threads
;
2488 if (index
>= ms
->possible_cpus
->len
) {
2494 return &ms
->possible_cpus
->cpus
[index
];
2497 static void spapr_set_vsmt_mode(sPAPRMachineState
*spapr
, Error
**errp
)
2499 Error
*local_err
= NULL
;
2500 bool vsmt_user
= !!spapr
->vsmt
;
2501 int kvm_smt
= kvmppc_smt_threads();
2504 if (!kvm_enabled() && (smp_threads
> 1)) {
2505 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2506 "on a pseries machine");
2509 if (!is_power_of_2(smp_threads
)) {
2510 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2511 "machine because it must be a power of 2", smp_threads
);
2515 /* Detemine the VSMT mode to use: */
2517 if (spapr
->vsmt
< smp_threads
) {
2518 error_setg(&local_err
, "Cannot support VSMT mode %d"
2519 " because it must be >= threads/core (%d)",
2520 spapr
->vsmt
, smp_threads
);
2523 /* In this case, spapr->vsmt has been set by the command line */
2526 * Default VSMT value is tricky, because we need it to be as
2527 * consistent as possible (for migration), but this requires
2528 * changing it for at least some existing cases. We pick 8 as
2529 * the value that we'd get with KVM on POWER8, the
2530 * overwhelmingly common case in production systems.
2532 spapr
->vsmt
= MAX(8, smp_threads
);
2535 /* KVM: If necessary, set the SMT mode: */
2536 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2537 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2539 /* Looks like KVM isn't able to change VSMT mode */
2540 error_setg(&local_err
,
2541 "Failed to set KVM's VSMT mode to %d (errno %d)",
2543 /* We can live with that if the default one is big enough
2544 * for the number of threads, and a submultiple of the one
2545 * we want. In this case we'll waste some vcpu ids, but
2546 * behaviour will be correct */
2547 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2548 warn_report_err(local_err
);
2553 error_append_hint(&local_err
,
2554 "On PPC, a VM with %d threads/core"
2555 " on a host with %d threads/core"
2556 " requires the use of VSMT mode %d.\n",
2557 smp_threads
, kvm_smt
, spapr
->vsmt
);
2559 kvmppc_hint_smt_possible(&local_err
);
2564 /* else TCG: nothing to do currently */
2566 error_propagate(errp
, local_err
);
2569 static void spapr_init_cpus(sPAPRMachineState
*spapr
)
2571 MachineState
*machine
= MACHINE(spapr
);
2572 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2573 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2574 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2575 const CPUArchIdList
*possible_cpus
;
2576 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2579 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2580 if (mc
->has_hotpluggable_cpus
) {
2581 if (smp_cpus
% smp_threads
) {
2582 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2583 smp_cpus
, smp_threads
);
2586 if (max_cpus
% smp_threads
) {
2587 error_report("max_cpus (%u) must be multiple of threads (%u)",
2588 max_cpus
, smp_threads
);
2592 if (max_cpus
!= smp_cpus
) {
2593 error_report("This machine version does not support CPU hotplug");
2596 boot_cores_nr
= possible_cpus
->len
;
2599 if (smc
->pre_2_10_has_unused_icps
) {
2602 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2603 /* Dummy entries get deregistered when real ICPState objects
2604 * are registered during CPU core hotplug.
2606 pre_2_10_vmstate_register_dummy_icp(i
);
2610 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2611 int core_id
= i
* smp_threads
;
2613 if (mc
->has_hotpluggable_cpus
) {
2614 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2615 spapr_vcpu_id(spapr
, core_id
));
2618 if (i
< boot_cores_nr
) {
2619 Object
*core
= object_new(type
);
2620 int nr_threads
= smp_threads
;
2622 /* Handle the partially filled core for older machine types */
2623 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2624 nr_threads
= smp_cpus
- i
* smp_threads
;
2627 object_property_set_int(core
, nr_threads
, "nr-threads",
2629 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2631 object_property_set_bool(core
, true, "realized", &error_fatal
);
2638 static PCIHostState
*spapr_create_default_phb(void)
2642 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2643 qdev_prop_set_uint32(dev
, "index", 0);
2644 qdev_init_nofail(dev
);
2646 return PCI_HOST_BRIDGE(dev
);
2649 /* pSeries LPAR / sPAPR hardware init */
2650 static void spapr_machine_init(MachineState
*machine
)
2652 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
2653 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2654 const char *kernel_filename
= machine
->kernel_filename
;
2655 const char *initrd_filename
= machine
->initrd_filename
;
2658 MemoryRegion
*sysmem
= get_system_memory();
2659 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2660 hwaddr node0_size
= spapr_node0_size(machine
);
2661 long load_limit
, fw_size
;
2663 Error
*resize_hpt_err
= NULL
;
2665 msi_nonbroken
= true;
2667 QLIST_INIT(&spapr
->phbs
);
2668 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2670 /* Determine capabilities to run with */
2671 spapr_caps_init(spapr
);
2673 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2674 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2676 * If the user explicitly requested a mode we should either
2677 * supply it, or fail completely (which we do below). But if
2678 * it's not set explicitly, we reset our mode to something
2681 if (resize_hpt_err
) {
2682 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2683 error_free(resize_hpt_err
);
2684 resize_hpt_err
= NULL
;
2686 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2690 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2692 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2694 * User requested HPT resize, but this host can't supply it. Bail out
2696 error_report_err(resize_hpt_err
);
2700 spapr
->rma_size
= node0_size
;
2702 /* With KVM, we don't actually know whether KVM supports an
2703 * unbounded RMA (PR KVM) or is limited by the hash table size
2704 * (HV KVM using VRMA), so we always assume the latter
2706 * In that case, we also limit the initial allocations for RTAS
2707 * etc... to 256M since we have no way to know what the VRMA size
2708 * is going to be as it depends on the size of the hash table
2709 * which isn't determined yet.
2711 if (kvm_enabled()) {
2712 spapr
->vrma_adjust
= 1;
2713 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2716 /* Actually we don't support unbounded RMA anymore since we added
2717 * proper emulation of HV mode. The max we can get is 16G which
2718 * also happens to be what we configure for PAPR mode so make sure
2719 * we don't do anything bigger than that
2721 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2723 if (spapr
->rma_size
> node0_size
) {
2724 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2729 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2730 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2733 * VSMT must be set in order to be able to compute VCPU ids, ie to
2734 * call spapr_max_server_number() or spapr_vcpu_id().
2736 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2738 /* Set up Interrupt Controller before we create the VCPUs */
2739 spapr_irq_init(spapr
, &error_fatal
);
2741 /* Set up containers for ibm,client-architecture-support negotiated options
2743 spapr
->ov5
= spapr_ovec_new();
2744 spapr
->ov5_cas
= spapr_ovec_new();
2746 if (smc
->dr_lmb_enabled
) {
2747 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2748 spapr_validate_node_memory(machine
, &error_fatal
);
2751 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2753 /* advertise support for dedicated HP event source to guests */
2754 if (spapr
->use_hotplug_event_source
) {
2755 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2758 /* advertise support for HPT resizing */
2759 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2760 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2763 /* advertise support for ibm,dyamic-memory-v2 */
2764 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2766 /* advertise XIVE on POWER9 machines */
2767 if (spapr
->irq
->ov5
& (SPAPR_OV5_XIVE_EXPLOIT
| SPAPR_OV5_XIVE_BOTH
)) {
2768 if (ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
2769 0, spapr
->max_compat_pvr
)) {
2770 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2771 } else if (spapr
->irq
->ov5
& SPAPR_OV5_XIVE_EXPLOIT
) {
2772 error_report("XIVE-only machines require a POWER9 CPU");
2778 spapr_init_cpus(spapr
);
2780 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2781 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2782 spapr
->max_compat_pvr
)) {
2783 /* KVM and TCG always allow GTSE with radix... */
2784 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2786 /* ... but not with hash (currently). */
2788 if (kvm_enabled()) {
2789 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2790 kvmppc_enable_logical_ci_hcalls();
2791 kvmppc_enable_set_mode_hcall();
2793 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2794 kvmppc_enable_clear_ref_mod_hcalls();
2798 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2800 memory_region_add_subregion(sysmem
, 0, ram
);
2802 /* always allocate the device memory information */
2803 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2805 /* initialize hotplug memory address space */
2806 if (machine
->ram_size
< machine
->maxram_size
) {
2807 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2809 * Limit the number of hotpluggable memory slots to half the number
2810 * slots that KVM supports, leaving the other half for PCI and other
2811 * devices. However ensure that number of slots doesn't drop below 32.
2813 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2814 SPAPR_MAX_RAM_SLOTS
;
2816 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2817 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2819 if (machine
->ram_slots
> max_memslots
) {
2820 error_report("Specified number of memory slots %"
2821 PRIu64
" exceeds max supported %d",
2822 machine
->ram_slots
, max_memslots
);
2826 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2827 SPAPR_DEVICE_MEM_ALIGN
);
2828 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2829 "device-memory", device_mem_size
);
2830 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2831 &machine
->device_memory
->mr
);
2834 if (smc
->dr_lmb_enabled
) {
2835 spapr_create_lmb_dr_connectors(spapr
);
2838 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2840 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2843 spapr
->rtas_size
= get_image_size(filename
);
2844 if (spapr
->rtas_size
< 0) {
2845 error_report("Could not get size of LPAR rtas '%s'", filename
);
2848 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2849 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2850 error_report("Could not load LPAR rtas '%s'", filename
);
2853 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2854 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2855 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2860 /* Set up RTAS event infrastructure */
2861 spapr_events_init(spapr
);
2863 /* Set up the RTC RTAS interfaces */
2864 spapr_rtc_create(spapr
);
2866 /* Set up VIO bus */
2867 spapr
->vio_bus
= spapr_vio_bus_init();
2869 for (i
= 0; i
< serial_max_hds(); i
++) {
2871 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2875 /* We always have at least the nvram device on VIO */
2876 spapr_create_nvram(spapr
);
2879 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2880 * connectors (described in root DT node's "ibm,drc-types" property)
2881 * are pre-initialized here. additional child connectors (such as
2882 * connectors for a PHBs PCI slots) are added as needed during their
2883 * parent's realization.
2885 if (smc
->dr_phb_enabled
) {
2886 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2887 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2892 spapr_pci_rtas_init();
2894 phb
= spapr_create_default_phb();
2896 for (i
= 0; i
< nb_nics
; i
++) {
2897 NICInfo
*nd
= &nd_table
[i
];
2900 nd
->model
= g_strdup("spapr-vlan");
2903 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2904 g_str_equal(nd
->model
, "ibmveth")) {
2905 spapr_vlan_create(spapr
->vio_bus
, nd
);
2907 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2911 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2912 spapr_vscsi_create(spapr
->vio_bus
);
2916 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2917 spapr
->has_graphics
= true;
2918 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2922 if (smc
->use_ohci_by_default
) {
2923 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2925 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2928 if (spapr
->has_graphics
) {
2929 USBBus
*usb_bus
= usb_bus_find(-1);
2931 usb_create_simple(usb_bus
, "usb-kbd");
2932 usb_create_simple(usb_bus
, "usb-mouse");
2936 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
2938 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2943 if (kernel_filename
) {
2944 uint64_t lowaddr
= 0;
2946 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2947 translate_kernel_address
, NULL
,
2948 NULL
, &lowaddr
, NULL
, 1,
2949 PPC_ELF_MACHINE
, 0, 0);
2950 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2951 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2952 translate_kernel_address
, NULL
, NULL
,
2953 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
2955 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2957 if (spapr
->kernel_size
< 0) {
2958 error_report("error loading %s: %s", kernel_filename
,
2959 load_elf_strerror(spapr
->kernel_size
));
2964 if (initrd_filename
) {
2965 /* Try to locate the initrd in the gap between the kernel
2966 * and the firmware. Add a bit of space just in case
2968 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
2969 + 0x1ffff) & ~0xffff;
2970 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2973 - spapr
->initrd_base
);
2974 if (spapr
->initrd_size
< 0) {
2975 error_report("could not load initial ram disk '%s'",
2982 if (bios_name
== NULL
) {
2983 bios_name
= FW_FILE_NAME
;
2985 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2987 error_report("Could not find LPAR firmware '%s'", bios_name
);
2990 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2992 error_report("Could not load LPAR firmware '%s'", filename
);
2997 /* FIXME: Should register things through the MachineState's qdev
2998 * interface, this is a legacy from the sPAPREnvironment structure
2999 * which predated MachineState but had a similar function */
3000 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3001 register_savevm_live(NULL
, "spapr/htab", -1, 1,
3002 &savevm_htab_handlers
, spapr
);
3004 qemu_register_boot_set(spapr_boot_set
, spapr
);
3006 if (kvm_enabled()) {
3007 /* to stop and start vmclock */
3008 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3011 kvmppc_spapr_enable_inkernel_multitce();
3015 static int spapr_kvm_type(const char *vm_type
)
3021 if (!strcmp(vm_type
, "HV")) {
3025 if (!strcmp(vm_type
, "PR")) {
3029 error_report("Unknown kvm-type specified '%s'", vm_type
);
3034 * Implementation of an interface to adjust firmware path
3035 * for the bootindex property handling.
3037 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3040 #define CAST(type, obj, name) \
3041 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3042 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3043 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3044 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3047 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3048 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3049 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3053 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3054 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3055 * 0x8000 | (target << 8) | (bus << 5) | lun
3056 * (see the "Logical unit addressing format" table in SAM5)
3058 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3059 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3060 (uint64_t)id
<< 48);
3061 } else if (virtio
) {
3063 * We use SRP luns of the form 01000000 | (target << 8) | lun
3064 * in the top 32 bits of the 64-bit LUN
3065 * Note: the quote above is from SLOF and it is wrong,
3066 * the actual binding is:
3067 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3069 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3070 if (d
->lun
>= 256) {
3071 /* Use the LUN "flat space addressing method" */
3074 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3075 (uint64_t)id
<< 32);
3078 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3079 * in the top 32 bits of the 64-bit LUN
3081 unsigned usb_port
= atoi(usb
->port
->path
);
3082 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3083 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3084 (uint64_t)id
<< 32);
3089 * SLOF probes the USB devices, and if it recognizes that the device is a
3090 * storage device, it changes its name to "storage" instead of "usb-host",
3091 * and additionally adds a child node for the SCSI LUN, so the correct
3092 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3094 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3095 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3096 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3097 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3102 /* Replace "pci" with "pci@800000020000000" */
3103 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3107 /* Same logic as virtio above */
3108 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3109 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3112 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3113 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3114 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3115 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3121 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3123 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3125 return g_strdup(spapr
->kvm_type
);
3128 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3130 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3132 g_free(spapr
->kvm_type
);
3133 spapr
->kvm_type
= g_strdup(value
);
3136 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3138 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3140 return spapr
->use_hotplug_event_source
;
3143 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3146 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3148 spapr
->use_hotplug_event_source
= value
;
3151 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3156 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3158 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3160 switch (spapr
->resize_hpt
) {
3161 case SPAPR_RESIZE_HPT_DEFAULT
:
3162 return g_strdup("default");
3163 case SPAPR_RESIZE_HPT_DISABLED
:
3164 return g_strdup("disabled");
3165 case SPAPR_RESIZE_HPT_ENABLED
:
3166 return g_strdup("enabled");
3167 case SPAPR_RESIZE_HPT_REQUIRED
:
3168 return g_strdup("required");
3170 g_assert_not_reached();
3173 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3175 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3177 if (strcmp(value
, "default") == 0) {
3178 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3179 } else if (strcmp(value
, "disabled") == 0) {
3180 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3181 } else if (strcmp(value
, "enabled") == 0) {
3182 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3183 } else if (strcmp(value
, "required") == 0) {
3184 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3186 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3190 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3191 void *opaque
, Error
**errp
)
3193 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3196 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3197 void *opaque
, Error
**errp
)
3199 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3202 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3204 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3206 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3207 return g_strdup("legacy");
3208 } else if (spapr
->irq
== &spapr_irq_xics
) {
3209 return g_strdup("xics");
3210 } else if (spapr
->irq
== &spapr_irq_xive
) {
3211 return g_strdup("xive");
3212 } else if (spapr
->irq
== &spapr_irq_dual
) {
3213 return g_strdup("dual");
3215 g_assert_not_reached();
3218 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3220 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3222 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3223 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3227 /* The legacy IRQ backend can not be set */
3228 if (strcmp(value
, "xics") == 0) {
3229 spapr
->irq
= &spapr_irq_xics
;
3230 } else if (strcmp(value
, "xive") == 0) {
3231 spapr
->irq
= &spapr_irq_xive
;
3232 } else if (strcmp(value
, "dual") == 0) {
3233 spapr
->irq
= &spapr_irq_dual
;
3235 error_setg(errp
, "Bad value for \"ic-mode\" property");
3239 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3241 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3243 return g_strdup(spapr
->host_model
);
3246 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3248 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3250 g_free(spapr
->host_model
);
3251 spapr
->host_model
= g_strdup(value
);
3254 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3256 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3258 return g_strdup(spapr
->host_serial
);
3261 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3263 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3265 g_free(spapr
->host_serial
);
3266 spapr
->host_serial
= g_strdup(value
);
3269 static void spapr_instance_init(Object
*obj
)
3271 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3272 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3274 spapr
->htab_fd
= -1;
3275 spapr
->use_hotplug_event_source
= true;
3276 object_property_add_str(obj
, "kvm-type",
3277 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3278 object_property_set_description(obj
, "kvm-type",
3279 "Specifies the KVM virtualization mode (HV, PR)",
3281 object_property_add_bool(obj
, "modern-hotplug-events",
3282 spapr_get_modern_hotplug_events
,
3283 spapr_set_modern_hotplug_events
,
3285 object_property_set_description(obj
, "modern-hotplug-events",
3286 "Use dedicated hotplug event mechanism in"
3287 " place of standard EPOW events when possible"
3288 " (required for memory hot-unplug support)",
3290 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3291 "Maximum permitted CPU compatibility mode",
3294 object_property_add_str(obj
, "resize-hpt",
3295 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3296 object_property_set_description(obj
, "resize-hpt",
3297 "Resizing of the Hash Page Table (enabled, disabled, required)",
3299 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3300 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3301 object_property_set_description(obj
, "vsmt",
3302 "Virtual SMT: KVM behaves as if this were"
3303 " the host's SMT mode", &error_abort
);
3304 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3305 spapr_get_msix_emulation
, NULL
, NULL
);
3307 /* The machine class defines the default interrupt controller mode */
3308 spapr
->irq
= smc
->irq
;
3309 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3310 spapr_set_ic_mode
, NULL
);
3311 object_property_set_description(obj
, "ic-mode",
3312 "Specifies the interrupt controller mode (xics, xive, dual)",
3315 object_property_add_str(obj
, "host-model",
3316 spapr_get_host_model
, spapr_set_host_model
,
3318 object_property_set_description(obj
, "host-model",
3319 "Set host's model-id to use - none|passthrough|string", &error_abort
);
3320 object_property_add_str(obj
, "host-serial",
3321 spapr_get_host_serial
, spapr_set_host_serial
,
3323 object_property_set_description(obj
, "host-serial",
3324 "Set host's system-id to use - none|passthrough|string", &error_abort
);
3327 static void spapr_machine_finalizefn(Object
*obj
)
3329 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3331 g_free(spapr
->kvm_type
);
3334 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3336 cpu_synchronize_state(cs
);
3337 ppc_cpu_do_system_reset(cs
);
3340 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3345 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3349 int spapr_lmb_dt_populate(sPAPRDRConnector
*drc
, sPAPRMachineState
*spapr
,
3350 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3355 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3356 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3358 *fdt_start_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3359 SPAPR_MEMORY_BLOCK_SIZE
);
3363 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3364 bool dedicated_hp_event_source
, Error
**errp
)
3366 sPAPRDRConnector
*drc
;
3367 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3369 uint64_t addr
= addr_start
;
3370 bool hotplugged
= spapr_drc_hotplugged(dev
);
3371 Error
*local_err
= NULL
;
3373 for (i
= 0; i
< nr_lmbs
; i
++) {
3374 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3375 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3378 spapr_drc_attach(drc
, dev
, &local_err
);
3380 while (addr
> addr_start
) {
3381 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3382 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3383 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3384 spapr_drc_detach(drc
);
3386 error_propagate(errp
, local_err
);
3390 spapr_drc_reset(drc
);
3392 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3394 /* send hotplug notification to the
3395 * guest only in case of hotplugged memory
3398 if (dedicated_hp_event_source
) {
3399 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3400 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3401 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3403 spapr_drc_index(drc
));
3405 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3411 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3414 Error
*local_err
= NULL
;
3415 sPAPRMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3416 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3417 uint64_t size
, addr
;
3419 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3421 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3426 addr
= object_property_get_uint(OBJECT(dimm
),
3427 PC_DIMM_ADDR_PROP
, &local_err
);
3432 spapr_add_lmbs(dev
, addr
, size
, spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3441 pc_dimm_unplug(dimm
, MACHINE(ms
));
3443 error_propagate(errp
, local_err
);
3446 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3449 const sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3450 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3451 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3452 Error
*local_err
= NULL
;
3457 if (!smc
->dr_lmb_enabled
) {
3458 error_setg(errp
, "Memory hotplug not supported for this machine");
3462 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3464 error_propagate(errp
, local_err
);
3468 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3469 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3470 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3474 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3476 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3477 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3479 error_propagate(errp
, local_err
);
3483 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3486 struct sPAPRDIMMState
{
3489 QTAILQ_ENTRY(sPAPRDIMMState
) next
;
3492 static sPAPRDIMMState
*spapr_pending_dimm_unplugs_find(sPAPRMachineState
*s
,
3495 sPAPRDIMMState
*dimm_state
= NULL
;
3497 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3498 if (dimm_state
->dimm
== dimm
) {
3505 static sPAPRDIMMState
*spapr_pending_dimm_unplugs_add(sPAPRMachineState
*spapr
,
3509 sPAPRDIMMState
*ds
= NULL
;
3512 * If this request is for a DIMM whose removal had failed earlier
3513 * (due to guest's refusal to remove the LMBs), we would have this
3514 * dimm already in the pending_dimm_unplugs list. In that
3515 * case don't add again.
3517 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3519 ds
= g_malloc0(sizeof(sPAPRDIMMState
));
3520 ds
->nr_lmbs
= nr_lmbs
;
3522 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3527 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState
*spapr
,
3528 sPAPRDIMMState
*dimm_state
)
3530 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3534 static sPAPRDIMMState
*spapr_recover_pending_dimm_state(sPAPRMachineState
*ms
,
3537 sPAPRDRConnector
*drc
;
3538 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3540 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3541 uint32_t avail_lmbs
= 0;
3542 uint64_t addr_start
, addr
;
3545 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3549 for (i
= 0; i
< nr_lmbs
; i
++) {
3550 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3551 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3556 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3559 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3562 /* Callback to be called during DRC release. */
3563 void spapr_lmb_release(DeviceState
*dev
)
3565 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3566 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3567 sPAPRDIMMState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3569 /* This information will get lost if a migration occurs
3570 * during the unplug process. In this case recover it. */
3572 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3574 /* The DRC being examined by the caller at least must be counted */
3575 g_assert(ds
->nr_lmbs
);
3578 if (--ds
->nr_lmbs
) {
3583 * Now that all the LMBs have been removed by the guest, call the
3584 * unplug handler chain. This can never fail.
3586 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3589 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3591 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3592 sPAPRDIMMState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3594 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3595 object_unparent(OBJECT(dev
));
3596 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3599 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3600 DeviceState
*dev
, Error
**errp
)
3602 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3603 Error
*local_err
= NULL
;
3604 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3606 uint64_t size
, addr_start
, addr
;
3608 sPAPRDRConnector
*drc
;
3610 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3611 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3613 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3620 * An existing pending dimm state for this DIMM means that there is an
3621 * unplug operation in progress, waiting for the spapr_lmb_release
3622 * callback to complete the job (BQL can't cover that far). In this case,
3623 * bail out to avoid detaching DRCs that were already released.
3625 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3626 error_setg(&local_err
,
3627 "Memory unplug already in progress for device %s",
3632 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3635 for (i
= 0; i
< nr_lmbs
; i
++) {
3636 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3637 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3640 spapr_drc_detach(drc
);
3641 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3644 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3645 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3646 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3647 nr_lmbs
, spapr_drc_index(drc
));
3649 error_propagate(errp
, local_err
);
3652 /* Callback to be called during DRC release. */
3653 void spapr_core_release(DeviceState
*dev
)
3655 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3657 /* Call the unplug handler chain. This can never fail. */
3658 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3661 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3663 MachineState
*ms
= MACHINE(hotplug_dev
);
3664 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3665 CPUCore
*cc
= CPU_CORE(dev
);
3666 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3668 if (smc
->pre_2_10_has_unused_icps
) {
3669 sPAPRCPUCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3672 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3673 CPUState
*cs
= CPU(sc
->threads
[i
]);
3675 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3680 core_slot
->cpu
= NULL
;
3681 object_unparent(OBJECT(dev
));
3685 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3688 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3690 sPAPRDRConnector
*drc
;
3691 CPUCore
*cc
= CPU_CORE(dev
);
3693 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3694 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3699 error_setg(errp
, "Boot CPU core may not be unplugged");
3703 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3704 spapr_vcpu_id(spapr
, cc
->core_id
));
3707 spapr_drc_detach(drc
);
3709 spapr_hotplug_req_remove_by_index(drc
);
3712 int spapr_core_dt_populate(sPAPRDRConnector
*drc
, sPAPRMachineState
*spapr
,
3713 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3715 sPAPRCPUCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3716 CPUState
*cs
= CPU(core
->threads
[0]);
3717 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3718 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3719 int id
= spapr_get_vcpu_id(cpu
);
3723 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3724 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3727 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3729 *fdt_start_offset
= offset
;
3733 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3736 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3737 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3738 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3739 sPAPRCPUCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3740 CPUCore
*cc
= CPU_CORE(dev
);
3742 sPAPRDRConnector
*drc
;
3743 Error
*local_err
= NULL
;
3744 CPUArchId
*core_slot
;
3746 bool hotplugged
= spapr_drc_hotplugged(dev
);
3748 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3750 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3754 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3755 spapr_vcpu_id(spapr
, cc
->core_id
));
3757 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3760 spapr_drc_attach(drc
, dev
, &local_err
);
3762 error_propagate(errp
, local_err
);
3768 * Send hotplug notification interrupt to the guest only
3769 * in case of hotplugged CPUs.
3771 spapr_hotplug_req_add_by_index(drc
);
3773 spapr_drc_reset(drc
);
3777 core_slot
->cpu
= OBJECT(dev
);
3779 if (smc
->pre_2_10_has_unused_icps
) {
3782 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3783 cs
= CPU(core
->threads
[i
]);
3784 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3789 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3792 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3793 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3794 Error
*local_err
= NULL
;
3795 CPUCore
*cc
= CPU_CORE(dev
);
3796 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3797 const char *type
= object_get_typename(OBJECT(dev
));
3798 CPUArchId
*core_slot
;
3801 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3802 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3806 if (strcmp(base_core_type
, type
)) {
3807 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3811 if (cc
->core_id
% smp_threads
) {
3812 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3817 * In general we should have homogeneous threads-per-core, but old
3818 * (pre hotplug support) machine types allow the last core to have
3819 * reduced threads as a compatibility hack for when we allowed
3820 * total vcpus not a multiple of threads-per-core.
3822 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3823 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3824 cc
->nr_threads
, smp_threads
);
3828 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3830 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3834 if (core_slot
->cpu
) {
3835 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3839 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3842 error_propagate(errp
, local_err
);
3845 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
3846 DeviceState
*dev
, Error
**errp
)
3848 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3849 spapr_memory_plug(hotplug_dev
, dev
, errp
);
3850 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3851 spapr_core_plug(hotplug_dev
, dev
, errp
);
3855 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
3856 DeviceState
*dev
, Error
**errp
)
3858 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3859 spapr_memory_unplug(hotplug_dev
, dev
);
3860 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3861 spapr_core_unplug(hotplug_dev
, dev
);
3865 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
3866 DeviceState
*dev
, Error
**errp
)
3868 sPAPRMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3869 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
3871 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3872 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
3873 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
3875 /* NOTE: this means there is a window after guest reset, prior to
3876 * CAS negotiation, where unplug requests will fail due to the
3877 * capability not being detected yet. This is a bit different than
3878 * the case with PCI unplug, where the events will be queued and
3879 * eventually handled by the guest after boot
3881 error_setg(errp
, "Memory hot unplug not supported for this guest");
3883 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3884 if (!mc
->has_hotpluggable_cpus
) {
3885 error_setg(errp
, "CPU hot unplug not supported on this machine");
3888 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
3892 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
3893 DeviceState
*dev
, Error
**errp
)
3895 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3896 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
3897 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3898 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
3902 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
3905 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
3906 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3907 return HOTPLUG_HANDLER(machine
);
3912 static CpuInstanceProperties
3913 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
3915 CPUArchId
*core_slot
;
3916 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3918 /* make sure possible_cpu are intialized */
3919 mc
->possible_cpu_arch_ids(machine
);
3920 /* get CPU core slot containing thread that matches cpu_index */
3921 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
3923 return core_slot
->props
;
3926 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
3928 return idx
/ smp_cores
% nb_numa_nodes
;
3931 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
3934 const char *core_type
;
3935 int spapr_max_cores
= max_cpus
/ smp_threads
;
3936 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3938 if (!mc
->has_hotpluggable_cpus
) {
3939 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
3941 if (machine
->possible_cpus
) {
3942 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
3943 return machine
->possible_cpus
;
3946 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3948 error_report("Unable to find sPAPR CPU Core definition");
3952 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
3953 sizeof(CPUArchId
) * spapr_max_cores
);
3954 machine
->possible_cpus
->len
= spapr_max_cores
;
3955 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
3956 int core_id
= i
* smp_threads
;
3958 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
3959 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
3960 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
3961 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
3962 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
3964 return machine
->possible_cpus
;
3967 static void spapr_phb_placement(sPAPRMachineState
*spapr
, uint32_t index
,
3968 uint64_t *buid
, hwaddr
*pio
,
3969 hwaddr
*mmio32
, hwaddr
*mmio64
,
3970 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
3973 * New-style PHB window placement.
3975 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3976 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3979 * Some guest kernels can't work with MMIO windows above 1<<46
3980 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3982 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3983 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3984 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3985 * 1TiB 64-bit MMIO windows for each PHB.
3987 const uint64_t base_buid
= 0x800000020000000ULL
;
3990 /* Sanity check natural alignments */
3991 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3992 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3993 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
3994 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
3995 /* Sanity check bounds */
3996 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
3997 SPAPR_PCI_MEM32_WIN_SIZE
);
3998 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
3999 SPAPR_PCI_MEM64_WIN_SIZE
);
4001 if (index
>= SPAPR_MAX_PHBS
) {
4002 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4003 SPAPR_MAX_PHBS
- 1);
4007 *buid
= base_buid
+ index
;
4008 for (i
= 0; i
< n_dma
; ++i
) {
4009 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4012 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4013 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4014 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4017 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4019 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
4021 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4024 static void spapr_ics_resend(XICSFabric
*dev
)
4026 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
4028 ics_resend(spapr
->ics
);
4031 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4033 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4035 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4038 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4041 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
4043 spapr
->irq
->print_info(spapr
, mon
);
4046 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4048 return cpu
->vcpu_id
;
4051 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4053 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4056 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4058 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4059 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4060 error_append_hint(errp
, "Adjust the number of cpus to %d "
4061 "or try to raise the number of threads per core\n",
4062 vcpu_id
* smp_threads
/ spapr
->vsmt
);
4066 cpu
->vcpu_id
= vcpu_id
;
4069 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4074 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4076 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4084 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4086 MachineClass
*mc
= MACHINE_CLASS(oc
);
4087 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4088 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4089 NMIClass
*nc
= NMI_CLASS(oc
);
4090 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4091 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4092 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4093 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4095 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4096 mc
->ignore_boot_device_suffixes
= true;
4099 * We set up the default / latest behaviour here. The class_init
4100 * functions for the specific versioned machine types can override
4101 * these details for backwards compatibility
4103 mc
->init
= spapr_machine_init
;
4104 mc
->reset
= spapr_machine_reset
;
4105 mc
->block_default_type
= IF_SCSI
;
4106 mc
->max_cpus
= 1024;
4107 mc
->no_parallel
= 1;
4108 mc
->default_boot_order
= "";
4109 mc
->default_ram_size
= 512 * MiB
;
4110 mc
->default_display
= "std";
4111 mc
->kvm_type
= spapr_kvm_type
;
4112 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4113 mc
->pci_allow_0_address
= true;
4114 assert(!mc
->get_hotplug_handler
);
4115 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4116 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4117 hc
->plug
= spapr_machine_device_plug
;
4118 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4119 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4120 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4121 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4122 hc
->unplug
= spapr_machine_device_unplug
;
4124 smc
->dr_lmb_enabled
= true;
4125 smc
->update_dt_enabled
= true;
4126 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4127 mc
->has_hotpluggable_cpus
= true;
4128 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4129 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4130 nc
->nmi_monitor_handler
= spapr_nmi
;
4131 smc
->phb_placement
= spapr_phb_placement
;
4132 vhc
->hypercall
= emulate_spapr_hypercall
;
4133 vhc
->hpt_mask
= spapr_hpt_mask
;
4134 vhc
->map_hptes
= spapr_map_hptes
;
4135 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4136 vhc
->store_hpte
= spapr_store_hpte
;
4137 vhc
->get_pate
= spapr_get_pate
;
4138 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4139 xic
->ics_get
= spapr_ics_get
;
4140 xic
->ics_resend
= spapr_ics_resend
;
4141 xic
->icp_get
= spapr_icp_get
;
4142 ispc
->print_info
= spapr_pic_print_info
;
4143 /* Force NUMA node memory size to be a multiple of
4144 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4145 * in which LMBs are represented and hot-added
4147 mc
->numa_mem_align_shift
= 28;
4149 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4150 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4151 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4152 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4153 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4154 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4155 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4156 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4157 spapr_caps_add_properties(smc
, &error_abort
);
4158 smc
->irq
= &spapr_irq_xics
;
4161 static const TypeInfo spapr_machine_info
= {
4162 .name
= TYPE_SPAPR_MACHINE
,
4163 .parent
= TYPE_MACHINE
,
4165 .instance_size
= sizeof(sPAPRMachineState
),
4166 .instance_init
= spapr_instance_init
,
4167 .instance_finalize
= spapr_machine_finalizefn
,
4168 .class_size
= sizeof(sPAPRMachineClass
),
4169 .class_init
= spapr_machine_class_init
,
4170 .interfaces
= (InterfaceInfo
[]) {
4171 { TYPE_FW_PATH_PROVIDER
},
4173 { TYPE_HOTPLUG_HANDLER
},
4174 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4175 { TYPE_XICS_FABRIC
},
4176 { TYPE_INTERRUPT_STATS_PROVIDER
},
4181 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4182 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4185 MachineClass *mc = MACHINE_CLASS(oc); \
4186 spapr_machine_##suffix##_class_options(mc); \
4188 mc->alias = "pseries"; \
4189 mc->is_default = 1; \
4192 static const TypeInfo spapr_machine_##suffix##_info = { \
4193 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4194 .parent = TYPE_SPAPR_MACHINE, \
4195 .class_init = spapr_machine_##suffix##_class_init, \
4197 static void spapr_machine_register_##suffix(void) \
4199 type_register(&spapr_machine_##suffix##_info); \
4201 type_init(spapr_machine_register_##suffix)
4206 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4208 /* Defaults for the latest behaviour inherited from the base class */
4211 DEFINE_SPAPR_MACHINE(4_0
, "4.0", true);
4216 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4218 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4219 static GlobalProperty compat
[] = {
4220 { TYPE_SPAPR_MACHINE
, "host-model", "passthrough" },
4221 { TYPE_SPAPR_MACHINE
, "host-serial", "passthrough" },
4224 spapr_machine_4_0_class_options(mc
);
4225 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4226 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4228 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4229 smc
->update_dt_enabled
= false;
4232 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4238 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4240 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4242 spapr_machine_3_1_class_options(mc
);
4243 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4245 smc
->legacy_irq_allocation
= true;
4246 smc
->irq
= &spapr_irq_xics_legacy
;
4249 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4254 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4256 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4257 static GlobalProperty compat
[] = {
4258 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4259 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4262 spapr_machine_3_0_class_options(mc
);
4263 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4264 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4266 /* We depend on kvm_enabled() to choose a default value for the
4267 * hpt-max-page-size capability. Of course we can't do it here
4268 * because this is too early and the HW accelerator isn't initialzed
4269 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4271 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4274 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4276 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4278 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4280 spapr_machine_2_12_class_options(mc
);
4281 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4282 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4283 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4286 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4292 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4294 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4296 spapr_machine_2_12_class_options(mc
);
4297 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4298 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4301 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4307 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4309 spapr_machine_2_11_class_options(mc
);
4310 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4313 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4319 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4321 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4322 static GlobalProperty compat
[] = {
4323 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4326 spapr_machine_2_10_class_options(mc
);
4327 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4328 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4329 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4330 smc
->pre_2_10_has_unused_icps
= true;
4331 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4334 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4340 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4342 static GlobalProperty compat
[] = {
4343 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4346 spapr_machine_2_9_class_options(mc
);
4347 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4348 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4349 mc
->numa_mem_align_shift
= 23;
4352 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4358 static void phb_placement_2_7(sPAPRMachineState
*spapr
, uint32_t index
,
4359 uint64_t *buid
, hwaddr
*pio
,
4360 hwaddr
*mmio32
, hwaddr
*mmio64
,
4361 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
4363 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4364 const uint64_t base_buid
= 0x800000020000000ULL
;
4365 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4366 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4367 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4368 const uint32_t max_index
= 255;
4369 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4371 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4372 hwaddr phb0_base
, phb_base
;
4375 /* Do we have device memory? */
4376 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4377 /* Can't just use maxram_size, because there may be an
4378 * alignment gap between normal and device memory regions
4380 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4381 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4384 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4386 if (index
> max_index
) {
4387 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4392 *buid
= base_buid
+ index
;
4393 for (i
= 0; i
< n_dma
; ++i
) {
4394 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4397 phb_base
= phb0_base
+ index
* phb_spacing
;
4398 *pio
= phb_base
+ pio_offset
;
4399 *mmio32
= phb_base
+ mmio_offset
;
4401 * We don't set the 64-bit MMIO window, relying on the PHB's
4402 * fallback behaviour of automatically splitting a large "32-bit"
4403 * window into contiguous 32-bit and 64-bit windows
4407 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4409 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4410 static GlobalProperty compat
[] = {
4411 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4412 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4413 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4414 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4417 spapr_machine_2_8_class_options(mc
);
4418 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4419 mc
->default_machine_opts
= "modern-hotplug-events=off";
4420 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4421 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4422 smc
->phb_placement
= phb_placement_2_7
;
4425 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4431 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4433 static GlobalProperty compat
[] = {
4434 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4437 spapr_machine_2_7_class_options(mc
);
4438 mc
->has_hotpluggable_cpus
= false;
4439 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4440 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4443 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4449 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4451 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4452 static GlobalProperty compat
[] = {
4453 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4456 spapr_machine_2_6_class_options(mc
);
4457 smc
->use_ohci_by_default
= true;
4458 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4459 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4462 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4468 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4470 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4472 spapr_machine_2_5_class_options(mc
);
4473 smc
->dr_lmb_enabled
= false;
4474 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4477 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4483 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4485 static GlobalProperty compat
[] = {
4486 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4488 spapr_machine_2_4_class_options(mc
);
4489 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4490 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4492 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4498 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4500 static GlobalProperty compat
[] = {
4501 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4504 spapr_machine_2_3_class_options(mc
);
4505 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4506 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4507 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4509 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4515 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4517 spapr_machine_2_2_class_options(mc
);
4518 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4520 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4522 static void spapr_machine_register_types(void)
4524 type_register_static(&spapr_machine_info
);
4527 type_init(spapr_machine_register_types
)