2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "sysemu/sysemu.h"
29 #include "hw/fw-path-provider.h"
32 #include "sysemu/blockdev.h"
33 #include "sysemu/cpus.h"
34 #include "sysemu/kvm.h"
36 #include "mmu-hash64.h"
39 #include "hw/boards.h"
40 #include "hw/ppc/ppc.h"
41 #include "hw/loader.h"
43 #include "hw/ppc/spapr.h"
44 #include "hw/ppc/spapr_vio.h"
45 #include "hw/pci-host/spapr.h"
46 #include "hw/ppc/xics.h"
47 #include "hw/pci/msi.h"
49 #include "hw/pci/pci.h"
50 #include "hw/scsi/scsi.h"
51 #include "hw/virtio/virtio-scsi.h"
53 #include "exec/address-spaces.h"
55 #include "qemu/config-file.h"
56 #include "qemu/error-report.h"
61 /* SLOF memory layout:
63 * SLOF raw image loaded at 0, copies its romfs right below the flat
64 * device-tree, then position SLOF itself 31M below that
66 * So we set FW_OVERHEAD to 40MB which should account for all of that
69 * We load our kernel at 4M, leaving space for SLOF initial image
71 #define FDT_MAX_SIZE 0x40000
72 #define RTAS_MAX_SIZE 0x10000
73 #define FW_MAX_SIZE 0x400000
74 #define FW_FILE_NAME "slof.bin"
75 #define FW_OVERHEAD 0x2800000
76 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
78 #define MIN_RMA_SLOF 128UL
80 #define TIMEBASE_FREQ 512000000ULL
83 #define XICS_IRQS 1024
85 #define PHANDLE_XICP 0x00001111
87 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
89 #define TYPE_SPAPR_MACHINE "spapr-machine"
91 sPAPREnvironment
*spapr
;
93 int spapr_allocate_irq(int hint
, bool lsi
)
99 if (hint
>= spapr
->next_irq
) {
100 spapr
->next_irq
= hint
+ 1;
102 /* FIXME: we should probably check for collisions somehow */
104 irq
= spapr
->next_irq
++;
107 /* Configure irq type */
108 if (!xics_get_qirq(spapr
->icp
, irq
)) {
112 xics_set_irq_type(spapr
->icp
, irq
, lsi
);
118 * Allocate block of consequtive IRQs, returns a number of the first.
119 * If msi==true, aligns the first IRQ number to num.
121 int spapr_allocate_irq_block(int num
, bool lsi
, bool msi
)
127 * MSIMesage::data is used for storing VIRQ so
128 * it has to be aligned to num to support multiple
129 * MSI vectors. MSI-X is not affected by this.
130 * The hint is used for the first IRQ, the rest should
131 * be allocated continuously.
134 assert((num
== 1) || (num
== 2) || (num
== 4) ||
135 (num
== 8) || (num
== 16) || (num
== 32));
136 hint
= (spapr
->next_irq
+ num
- 1) & ~(num
- 1);
139 for (i
= 0; i
< num
; ++i
) {
142 irq
= spapr_allocate_irq(hint
, lsi
);
152 /* If the above doesn't create a consecutive block then that's
154 assert(irq
== (first
+ i
));
160 static XICSState
*try_create_xics(const char *type
, int nr_servers
,
165 dev
= qdev_create(NULL
, type
);
166 qdev_prop_set_uint32(dev
, "nr_servers", nr_servers
);
167 qdev_prop_set_uint32(dev
, "nr_irqs", nr_irqs
);
168 if (qdev_init(dev
) < 0) {
172 return XICS_COMMON(dev
);
175 static XICSState
*xics_system_init(int nr_servers
, int nr_irqs
)
177 XICSState
*icp
= NULL
;
180 QemuOpts
*machine_opts
= qemu_get_machine_opts();
181 bool irqchip_allowed
= qemu_opt_get_bool(machine_opts
,
182 "kernel_irqchip", true);
183 bool irqchip_required
= qemu_opt_get_bool(machine_opts
,
184 "kernel_irqchip", false);
185 if (irqchip_allowed
) {
186 icp
= try_create_xics(TYPE_KVM_XICS
, nr_servers
, nr_irqs
);
189 if (irqchip_required
&& !icp
) {
190 perror("Failed to create in-kernel XICS\n");
196 icp
= try_create_xics(TYPE_XICS
, nr_servers
, nr_irqs
);
200 perror("Failed to create XICS\n");
207 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
211 uint32_t servers_prop
[smt_threads
];
212 uint32_t gservers_prop
[smt_threads
* 2];
213 int index
= ppc_get_vcpu_dt_id(cpu
);
215 if (cpu
->cpu_version
) {
216 ret
= fdt_setprop(fdt
, offset
, "cpu-version",
217 &cpu
->cpu_version
, sizeof(cpu
->cpu_version
));
223 /* Build interrupt servers and gservers properties */
224 for (i
= 0; i
< smt_threads
; i
++) {
225 servers_prop
[i
] = cpu_to_be32(index
+ i
);
226 /* Hack, direct the group queues back to cpu 0 */
227 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
228 gservers_prop
[i
*2 + 1] = 0;
230 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
231 servers_prop
, sizeof(servers_prop
));
235 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
236 gservers_prop
, sizeof(gservers_prop
));
241 static int spapr_fixup_cpu_dt(void *fdt
, sPAPREnvironment
*spapr
)
243 int ret
= 0, offset
, cpus_offset
;
246 int smt
= kvmppc_smt_threads();
247 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
250 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
251 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
252 int index
= ppc_get_vcpu_dt_id(cpu
);
253 uint32_t associativity
[] = {cpu_to_be32(0x5),
257 cpu_to_be32(cs
->numa_node
),
260 if ((index
% smt
) != 0) {
264 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
266 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
267 if (cpus_offset
< 0) {
268 cpus_offset
= fdt_add_subnode(fdt
, fdt_path_offset(fdt
, "/"),
270 if (cpus_offset
< 0) {
274 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
276 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
282 if (nb_numa_nodes
> 1) {
283 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
284 sizeof(associativity
));
290 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
291 pft_size_prop
, sizeof(pft_size_prop
));
296 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
,
297 ppc_get_compat_smt_threads(cpu
));
306 static size_t create_page_sizes_prop(CPUPPCState
*env
, uint32_t *prop
,
309 size_t maxcells
= maxsize
/ sizeof(uint32_t);
313 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
314 struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
316 if (!sps
->page_shift
) {
319 for (count
= 0; count
< PPC_PAGE_SIZES_MAX_SZ
; count
++) {
320 if (sps
->enc
[count
].page_shift
== 0) {
324 if ((p
- prop
) >= (maxcells
- 3 - count
* 2)) {
327 *(p
++) = cpu_to_be32(sps
->page_shift
);
328 *(p
++) = cpu_to_be32(sps
->slb_enc
);
329 *(p
++) = cpu_to_be32(count
);
330 for (j
= 0; j
< count
; j
++) {
331 *(p
++) = cpu_to_be32(sps
->enc
[j
].page_shift
);
332 *(p
++) = cpu_to_be32(sps
->enc
[j
].pte_enc
);
336 return (p
- prop
) * sizeof(uint32_t);
343 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
344 #exp, fdt_strerror(ret)); \
349 static void add_str(GString
*s
, const gchar
*s1
)
351 g_string_append_len(s
, s1
, strlen(s1
) + 1);
354 static void *spapr_create_fdt_skel(hwaddr initrd_base
,
358 const char *boot_device
,
359 const char *kernel_cmdline
,
364 uint32_t start_prop
= cpu_to_be32(initrd_base
);
365 uint32_t end_prop
= cpu_to_be32(initrd_base
+ initrd_size
);
366 GString
*hypertas
= g_string_sized_new(256);
367 GString
*qemu_hypertas
= g_string_sized_new(256);
368 uint32_t refpoints
[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
369 uint32_t interrupt_server_ranges_prop
[] = {0, cpu_to_be32(smp_cpus
)};
370 int smt
= kvmppc_smt_threads();
371 unsigned char vec5
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
372 QemuOpts
*opts
= qemu_opts_find(qemu_find_opts("smp-opts"), NULL
);
373 unsigned sockets
= opts
? qemu_opt_get_number(opts
, "sockets", 0) : 0;
374 uint32_t cpus_per_socket
= sockets
? (smp_cpus
/ sockets
) : 1;
376 add_str(hypertas
, "hcall-pft");
377 add_str(hypertas
, "hcall-term");
378 add_str(hypertas
, "hcall-dabr");
379 add_str(hypertas
, "hcall-interrupt");
380 add_str(hypertas
, "hcall-tce");
381 add_str(hypertas
, "hcall-vio");
382 add_str(hypertas
, "hcall-splpar");
383 add_str(hypertas
, "hcall-bulk");
384 add_str(hypertas
, "hcall-set-mode");
385 add_str(qemu_hypertas
, "hcall-memop1");
387 fdt
= g_malloc0(FDT_MAX_SIZE
);
388 _FDT((fdt_create(fdt
, FDT_MAX_SIZE
)));
391 _FDT((fdt_add_reservemap_entry(fdt
, KERNEL_LOAD_ADDR
, kernel_size
)));
394 _FDT((fdt_add_reservemap_entry(fdt
, initrd_base
, initrd_size
)));
396 _FDT((fdt_finish_reservemap(fdt
)));
399 _FDT((fdt_begin_node(fdt
, "")));
400 _FDT((fdt_property_string(fdt
, "device_type", "chrp")));
401 _FDT((fdt_property_string(fdt
, "model", "IBM pSeries (emulated by qemu)")));
402 _FDT((fdt_property_string(fdt
, "compatible", "qemu,pseries")));
404 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x2)));
405 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x2)));
408 _FDT((fdt_begin_node(fdt
, "chosen")));
410 /* Set Form1_affinity */
411 _FDT((fdt_property(fdt
, "ibm,architecture-vec-5", vec5
, sizeof(vec5
))));
413 _FDT((fdt_property_string(fdt
, "bootargs", kernel_cmdline
)));
414 _FDT((fdt_property(fdt
, "linux,initrd-start",
415 &start_prop
, sizeof(start_prop
))));
416 _FDT((fdt_property(fdt
, "linux,initrd-end",
417 &end_prop
, sizeof(end_prop
))));
419 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
420 cpu_to_be64(kernel_size
) };
422 _FDT((fdt_property(fdt
, "qemu,boot-kernel", &kprop
, sizeof(kprop
))));
424 _FDT((fdt_property(fdt
, "qemu,boot-kernel-le", NULL
, 0)));
428 _FDT((fdt_property_string(fdt
, "qemu,boot-device", boot_device
)));
430 _FDT((fdt_property_cell(fdt
, "qemu,graphic-width", graphic_width
)));
431 _FDT((fdt_property_cell(fdt
, "qemu,graphic-height", graphic_height
)));
432 _FDT((fdt_property_cell(fdt
, "qemu,graphic-depth", graphic_depth
)));
434 _FDT((fdt_end_node(fdt
)));
437 _FDT((fdt_begin_node(fdt
, "cpus")));
439 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
440 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
443 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
444 CPUPPCState
*env
= &cpu
->env
;
445 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
446 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
447 int index
= ppc_get_vcpu_dt_id(cpu
);
449 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
450 0xffffffff, 0xffffffff};
451 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ
;
452 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
453 uint32_t page_sizes_prop
[64];
454 size_t page_sizes_prop_size
;
456 if ((index
% smt
) != 0) {
460 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
462 _FDT((fdt_begin_node(fdt
, nodename
)));
466 _FDT((fdt_property_cell(fdt
, "reg", index
)));
467 _FDT((fdt_property_string(fdt
, "device_type", "cpu")));
469 _FDT((fdt_property_cell(fdt
, "cpu-version", env
->spr
[SPR_PVR
])));
470 _FDT((fdt_property_cell(fdt
, "d-cache-block-size",
471 env
->dcache_line_size
)));
472 _FDT((fdt_property_cell(fdt
, "d-cache-line-size",
473 env
->dcache_line_size
)));
474 _FDT((fdt_property_cell(fdt
, "i-cache-block-size",
475 env
->icache_line_size
)));
476 _FDT((fdt_property_cell(fdt
, "i-cache-line-size",
477 env
->icache_line_size
)));
479 if (pcc
->l1_dcache_size
) {
480 _FDT((fdt_property_cell(fdt
, "d-cache-size", pcc
->l1_dcache_size
)));
482 fprintf(stderr
, "Warning: Unknown L1 dcache size for cpu\n");
484 if (pcc
->l1_icache_size
) {
485 _FDT((fdt_property_cell(fdt
, "i-cache-size", pcc
->l1_icache_size
)));
487 fprintf(stderr
, "Warning: Unknown L1 icache size for cpu\n");
490 _FDT((fdt_property_cell(fdt
, "timebase-frequency", tbfreq
)));
491 _FDT((fdt_property_cell(fdt
, "clock-frequency", cpufreq
)));
492 _FDT((fdt_property_cell(fdt
, "ibm,slb-size", env
->slb_nr
)));
493 _FDT((fdt_property_string(fdt
, "status", "okay")));
494 _FDT((fdt_property(fdt
, "64-bit", NULL
, 0)));
496 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
497 _FDT((fdt_property(fdt
, "ibm,purr", NULL
, 0)));
500 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
501 _FDT((fdt_property(fdt
, "ibm,processor-segment-sizes",
502 segs
, sizeof(segs
))));
505 /* Advertise VMX/VSX (vector extensions) if available
506 * 0 / no property == no vector extensions
507 * 1 == VMX / Altivec available
508 * 2 == VSX available */
509 if (env
->insns_flags
& PPC_ALTIVEC
) {
510 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
512 _FDT((fdt_property_cell(fdt
, "ibm,vmx", vmx
)));
515 /* Advertise DFP (Decimal Floating Point) if available
516 * 0 / no property == no DFP
517 * 1 == DFP available */
518 if (env
->insns_flags2
& PPC2_DFP
) {
519 _FDT((fdt_property_cell(fdt
, "ibm,dfp", 1)));
522 page_sizes_prop_size
= create_page_sizes_prop(env
, page_sizes_prop
,
523 sizeof(page_sizes_prop
));
524 if (page_sizes_prop_size
) {
525 _FDT((fdt_property(fdt
, "ibm,segment-page-sizes",
526 page_sizes_prop
, page_sizes_prop_size
)));
529 _FDT((fdt_property_cell(fdt
, "ibm,chip-id",
530 cs
->cpu_index
/ cpus_per_socket
)));
532 _FDT((fdt_end_node(fdt
)));
535 _FDT((fdt_end_node(fdt
)));
538 _FDT((fdt_begin_node(fdt
, "rtas")));
540 _FDT((fdt_property(fdt
, "ibm,hypertas-functions", hypertas
->str
,
542 g_string_free(hypertas
, TRUE
);
543 _FDT((fdt_property(fdt
, "qemu,hypertas-functions", qemu_hypertas
->str
,
544 qemu_hypertas
->len
)));
545 g_string_free(qemu_hypertas
, TRUE
);
547 _FDT((fdt_property(fdt
, "ibm,associativity-reference-points",
548 refpoints
, sizeof(refpoints
))));
550 _FDT((fdt_property_cell(fdt
, "rtas-error-log-max", RTAS_ERROR_LOG_MAX
)));
552 _FDT((fdt_end_node(fdt
)));
554 /* interrupt controller */
555 _FDT((fdt_begin_node(fdt
, "interrupt-controller")));
557 _FDT((fdt_property_string(fdt
, "device_type",
558 "PowerPC-External-Interrupt-Presentation")));
559 _FDT((fdt_property_string(fdt
, "compatible", "IBM,ppc-xicp")));
560 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
561 _FDT((fdt_property(fdt
, "ibm,interrupt-server-ranges",
562 interrupt_server_ranges_prop
,
563 sizeof(interrupt_server_ranges_prop
))));
564 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 2)));
565 _FDT((fdt_property_cell(fdt
, "linux,phandle", PHANDLE_XICP
)));
566 _FDT((fdt_property_cell(fdt
, "phandle", PHANDLE_XICP
)));
568 _FDT((fdt_end_node(fdt
)));
571 _FDT((fdt_begin_node(fdt
, "vdevice")));
573 _FDT((fdt_property_string(fdt
, "device_type", "vdevice")));
574 _FDT((fdt_property_string(fdt
, "compatible", "IBM,vdevice")));
575 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
576 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
577 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 0x2)));
578 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
580 _FDT((fdt_end_node(fdt
)));
583 spapr_events_fdt_skel(fdt
, epow_irq
);
585 _FDT((fdt_end_node(fdt
))); /* close root node */
586 _FDT((fdt_finish(fdt
)));
591 int spapr_h_cas_compose_response(target_ulong addr
, target_ulong size
)
593 void *fdt
, *fdt_skel
;
594 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
598 /* Create sceleton */
599 fdt_skel
= g_malloc0(size
);
600 _FDT((fdt_create(fdt_skel
, size
)));
601 _FDT((fdt_begin_node(fdt_skel
, "")));
602 _FDT((fdt_end_node(fdt_skel
)));
603 _FDT((fdt_finish(fdt_skel
)));
604 fdt
= g_malloc0(size
);
605 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
608 /* Fix skeleton up */
609 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
611 /* Pack resulting tree */
612 _FDT((fdt_pack(fdt
)));
614 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
615 trace_spapr_cas_failed(size
);
619 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
620 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
621 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
627 static int spapr_populate_memory(sPAPREnvironment
*spapr
, void *fdt
)
629 uint32_t associativity
[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
630 cpu_to_be32(0x0), cpu_to_be32(0x0),
633 hwaddr node0_size
, mem_start
, node_size
;
634 uint64_t mem_reg_property
[2];
638 if (nb_numa_nodes
> 1 && node_mem
[0] < ram_size
) {
639 node0_size
= node_mem
[0];
641 node0_size
= ram_size
;
645 mem_reg_property
[0] = 0;
646 mem_reg_property
[1] = cpu_to_be64(spapr
->rma_size
);
647 off
= fdt_add_subnode(fdt
, 0, "memory@0");
649 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
650 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
651 sizeof(mem_reg_property
))));
652 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
653 sizeof(associativity
))));
656 if (node0_size
> spapr
->rma_size
) {
657 mem_reg_property
[0] = cpu_to_be64(spapr
->rma_size
);
658 mem_reg_property
[1] = cpu_to_be64(node0_size
- spapr
->rma_size
);
660 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, spapr
->rma_size
);
661 off
= fdt_add_subnode(fdt
, 0, mem_name
);
663 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
664 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
665 sizeof(mem_reg_property
))));
666 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
667 sizeof(associativity
))));
670 /* RAM: Node 1 and beyond */
671 mem_start
= node0_size
;
672 for (i
= 1; i
< nb_numa_nodes
; i
++) {
673 mem_reg_property
[0] = cpu_to_be64(mem_start
);
674 if (mem_start
>= ram_size
) {
677 node_size
= node_mem
[i
];
678 if (node_size
> ram_size
- mem_start
) {
679 node_size
= ram_size
- mem_start
;
682 mem_reg_property
[1] = cpu_to_be64(node_size
);
683 associativity
[3] = associativity
[4] = cpu_to_be32(i
);
684 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, mem_start
);
685 off
= fdt_add_subnode(fdt
, 0, mem_name
);
687 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
688 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
689 sizeof(mem_reg_property
))));
690 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
691 sizeof(associativity
))));
692 mem_start
+= node_size
;
698 static void spapr_finalize_fdt(sPAPREnvironment
*spapr
,
709 fdt
= g_malloc(FDT_MAX_SIZE
);
711 /* open out the base tree into a temp buffer for the final tweaks */
712 _FDT((fdt_open_into(spapr
->fdt_skel
, fdt
, FDT_MAX_SIZE
)));
714 ret
= spapr_populate_memory(spapr
, fdt
);
716 fprintf(stderr
, "couldn't setup memory nodes in fdt\n");
720 ret
= spapr_populate_vdevice(spapr
->vio_bus
, fdt
);
722 fprintf(stderr
, "couldn't setup vio devices in fdt\n");
726 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
727 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
731 fprintf(stderr
, "couldn't setup PCI devices in fdt\n");
736 ret
= spapr_rtas_device_tree_setup(fdt
, rtas_addr
, rtas_size
);
738 fprintf(stderr
, "Couldn't set up RTAS device tree properties\n");
741 /* Advertise NUMA via ibm,associativity */
742 ret
= spapr_fixup_cpu_dt(fdt
, spapr
);
744 fprintf(stderr
, "Couldn't finalize CPU device tree properties\n");
747 bootlist
= get_boot_devices_list(&cb
, true);
748 if (cb
&& bootlist
) {
749 int offset
= fdt_path_offset(fdt
, "/chosen");
753 for (i
= 0; i
< cb
; i
++) {
754 if (bootlist
[i
] == '\n') {
759 ret
= fdt_setprop_string(fdt
, offset
, "qemu,boot-list", bootlist
);
762 if (!spapr
->has_graphics
) {
763 spapr_populate_chosen_stdout(fdt
, spapr
->vio_bus
);
766 _FDT((fdt_pack(fdt
)));
768 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
769 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
770 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
774 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
779 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
781 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
784 static void emulate_spapr_hypercall(PowerPCCPU
*cpu
)
786 CPUPPCState
*env
= &cpu
->env
;
789 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
790 env
->gpr
[3] = H_PRIVILEGE
;
792 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
796 static void spapr_reset_htab(sPAPREnvironment
*spapr
)
800 /* allocate hash page table. For now we always make this 16mb,
801 * later we should probably make it scale to the size of guest
804 shift
= kvmppc_reset_htab(spapr
->htab_shift
);
807 /* Kernel handles htab, we don't need to allocate one */
808 spapr
->htab_shift
= shift
;
809 kvmppc_kern_htab
= true;
812 /* Allocate an htab if we don't yet have one */
813 spapr
->htab
= qemu_memalign(HTAB_SIZE(spapr
), HTAB_SIZE(spapr
));
817 memset(spapr
->htab
, 0, HTAB_SIZE(spapr
));
820 /* Update the RMA size if necessary */
821 if (spapr
->vrma_adjust
) {
822 hwaddr node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
823 spapr
->rma_size
= kvmppc_rma_size(node0_size
, spapr
->htab_shift
);
827 static void ppc_spapr_reset(void)
829 PowerPCCPU
*first_ppc_cpu
;
831 /* Reset the hash table & recalc the RMA */
832 spapr_reset_htab(spapr
);
834 qemu_devices_reset();
837 spapr_finalize_fdt(spapr
, spapr
->fdt_addr
, spapr
->rtas_addr
,
840 /* Set up the entry state */
841 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
842 first_ppc_cpu
->env
.gpr
[3] = spapr
->fdt_addr
;
843 first_ppc_cpu
->env
.gpr
[5] = 0;
844 first_cpu
->halted
= 0;
845 first_ppc_cpu
->env
.nip
= spapr
->entry_point
;
849 static void spapr_cpu_reset(void *opaque
)
851 PowerPCCPU
*cpu
= opaque
;
852 CPUState
*cs
= CPU(cpu
);
853 CPUPPCState
*env
= &cpu
->env
;
857 /* All CPUs start halted. CPU0 is unhalted from the machine level
858 * reset code and the rest are explicitly started up by the guest
859 * using an RTAS call */
862 env
->spr
[SPR_HIOR
] = 0;
864 env
->external_htab
= (uint8_t *)spapr
->htab
;
865 if (kvm_enabled() && !env
->external_htab
) {
867 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
868 * functions do the right thing.
870 env
->external_htab
= (void *)1;
874 * htab_mask is the mask used to normalize hash value to PTEG index.
875 * htab_shift is log2 of hash table size.
876 * We have 8 hpte per group, and each hpte is 16 bytes.
877 * ie have 128 bytes per hpte entry.
879 env
->htab_mask
= (1ULL << ((spapr
)->htab_shift
- 7)) - 1;
880 env
->spr
[SPR_SDR1
] = (target_ulong
)(uintptr_t)spapr
->htab
|
881 (spapr
->htab_shift
- 18);
884 static void spapr_create_nvram(sPAPREnvironment
*spapr
)
886 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
887 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
890 qdev_prop_set_drive_nofail(dev
, "drive", dinfo
->bdrv
);
893 qdev_init_nofail(dev
);
895 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
898 /* Returns whether we want to use VGA or not */
899 static int spapr_vga_init(PCIBus
*pci_bus
)
901 switch (vga_interface_type
) {
907 return pci_vga_init(pci_bus
) != NULL
;
909 fprintf(stderr
, "This vga model is not supported,"
910 "currently it only supports -vga std\n");
915 static const VMStateDescription vmstate_spapr
= {
918 .minimum_version_id
= 1,
919 .fields
= (VMStateField
[]) {
920 VMSTATE_UINT32(next_irq
, sPAPREnvironment
),
923 VMSTATE_UINT64(rtc_offset
, sPAPREnvironment
),
924 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPREnvironment
, 2),
925 VMSTATE_END_OF_LIST()
929 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
930 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
931 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
932 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
934 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
936 sPAPREnvironment
*spapr
= opaque
;
938 /* "Iteration" header */
939 qemu_put_be32(f
, spapr
->htab_shift
);
942 spapr
->htab_save_index
= 0;
943 spapr
->htab_first_pass
= true;
945 assert(kvm_enabled());
947 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
948 if (spapr
->htab_fd
< 0) {
949 fprintf(stderr
, "Unable to open fd for reading hash table from KVM: %s\n",
959 static void htab_save_first_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
962 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
963 int index
= spapr
->htab_save_index
;
964 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
966 assert(spapr
->htab_first_pass
);
971 /* Consume invalid HPTEs */
972 while ((index
< htabslots
)
973 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
975 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
978 /* Consume valid HPTEs */
980 while ((index
< htabslots
)
981 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
983 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
986 if (index
> chunkstart
) {
987 int n_valid
= index
- chunkstart
;
989 qemu_put_be32(f
, chunkstart
);
990 qemu_put_be16(f
, n_valid
);
992 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
993 HASH_PTE_SIZE_64
* n_valid
);
995 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
999 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
1001 if (index
>= htabslots
) {
1002 assert(index
== htabslots
);
1004 spapr
->htab_first_pass
= false;
1006 spapr
->htab_save_index
= index
;
1009 static int htab_save_later_pass(QEMUFile
*f
, sPAPREnvironment
*spapr
,
1012 bool final
= max_ns
< 0;
1013 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1014 int examined
= 0, sent
= 0;
1015 int index
= spapr
->htab_save_index
;
1016 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1018 assert(!spapr
->htab_first_pass
);
1021 int chunkstart
, invalidstart
;
1023 /* Consume non-dirty HPTEs */
1024 while ((index
< htabslots
)
1025 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
1031 /* Consume valid dirty HPTEs */
1032 while ((index
< htabslots
)
1033 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1034 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1035 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1040 invalidstart
= index
;
1041 /* Consume invalid dirty HPTEs */
1042 while ((index
< htabslots
)
1043 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1044 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1045 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1050 if (index
> chunkstart
) {
1051 int n_valid
= invalidstart
- chunkstart
;
1052 int n_invalid
= index
- invalidstart
;
1054 qemu_put_be32(f
, chunkstart
);
1055 qemu_put_be16(f
, n_valid
);
1056 qemu_put_be16(f
, n_invalid
);
1057 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1058 HASH_PTE_SIZE_64
* n_valid
);
1059 sent
+= index
- chunkstart
;
1061 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1066 if (examined
>= htabslots
) {
1070 if (index
>= htabslots
) {
1071 assert(index
== htabslots
);
1074 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
1076 if (index
>= htabslots
) {
1077 assert(index
== htabslots
);
1081 spapr
->htab_save_index
= index
;
1083 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
1086 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1087 #define MAX_KVM_BUF_SIZE 2048
1089 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
1091 sPAPREnvironment
*spapr
= opaque
;
1094 /* Iteration header */
1095 qemu_put_be32(f
, 0);
1098 assert(kvm_enabled());
1100 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
,
1101 MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
1105 } else if (spapr
->htab_first_pass
) {
1106 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
1108 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
1112 qemu_put_be32(f
, 0);
1113 qemu_put_be16(f
, 0);
1114 qemu_put_be16(f
, 0);
1119 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
1121 sPAPREnvironment
*spapr
= opaque
;
1123 /* Iteration header */
1124 qemu_put_be32(f
, 0);
1129 assert(kvm_enabled());
1131 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
, MAX_KVM_BUF_SIZE
, -1);
1135 close(spapr
->htab_fd
);
1136 spapr
->htab_fd
= -1;
1138 htab_save_later_pass(f
, spapr
, -1);
1142 qemu_put_be32(f
, 0);
1143 qemu_put_be16(f
, 0);
1144 qemu_put_be16(f
, 0);
1149 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
1151 sPAPREnvironment
*spapr
= opaque
;
1152 uint32_t section_hdr
;
1155 if (version_id
< 1 || version_id
> 1) {
1156 fprintf(stderr
, "htab_load() bad version\n");
1160 section_hdr
= qemu_get_be32(f
);
1163 /* First section, just the hash shift */
1164 if (spapr
->htab_shift
!= section_hdr
) {
1171 assert(kvm_enabled());
1173 fd
= kvmppc_get_htab_fd(true);
1175 fprintf(stderr
, "Unable to open fd to restore KVM hash table: %s\n",
1182 uint16_t n_valid
, n_invalid
;
1184 index
= qemu_get_be32(f
);
1185 n_valid
= qemu_get_be16(f
);
1186 n_invalid
= qemu_get_be16(f
);
1188 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1193 if ((index
+ n_valid
+ n_invalid
) >
1194 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1195 /* Bad index in stream */
1196 fprintf(stderr
, "htab_load() bad index %d (%hd+%hd entries) "
1197 "in htab stream (htab_shift=%d)\n", index
, n_valid
, n_invalid
,
1204 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1205 HASH_PTE_SIZE_64
* n_valid
);
1208 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1209 HASH_PTE_SIZE_64
* n_invalid
);
1216 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1231 static SaveVMHandlers savevm_htab_handlers
= {
1232 .save_live_setup
= htab_save_setup
,
1233 .save_live_iterate
= htab_save_iterate
,
1234 .save_live_complete
= htab_save_complete
,
1235 .load_state
= htab_load
,
1238 /* pSeries LPAR / sPAPR hardware init */
1239 static void ppc_spapr_init(MachineState
*machine
)
1241 ram_addr_t ram_size
= machine
->ram_size
;
1242 const char *cpu_model
= machine
->cpu_model
;
1243 const char *kernel_filename
= machine
->kernel_filename
;
1244 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1245 const char *initrd_filename
= machine
->initrd_filename
;
1246 const char *boot_device
= machine
->boot_order
;
1251 MemoryRegion
*sysmem
= get_system_memory();
1252 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1253 hwaddr rma_alloc_size
;
1254 hwaddr node0_size
= (nb_numa_nodes
> 1) ? node_mem
[0] : ram_size
;
1255 uint32_t initrd_base
= 0;
1256 long kernel_size
= 0, initrd_size
= 0;
1257 long load_limit
, rtas_limit
, fw_size
;
1258 bool kernel_le
= false;
1261 msi_supported
= true;
1263 spapr
= g_malloc0(sizeof(*spapr
));
1264 QLIST_INIT(&spapr
->phbs
);
1266 cpu_ppc_hypercall
= emulate_spapr_hypercall
;
1268 /* Allocate RMA if necessary */
1269 rma_alloc_size
= kvmppc_alloc_rma("ppc_spapr.rma", sysmem
);
1271 if (rma_alloc_size
== -1) {
1272 hw_error("qemu: Unable to create RMA\n");
1276 if (rma_alloc_size
&& (rma_alloc_size
< node0_size
)) {
1277 spapr
->rma_size
= rma_alloc_size
;
1279 spapr
->rma_size
= node0_size
;
1281 /* With KVM, we don't actually know whether KVM supports an
1282 * unbounded RMA (PR KVM) or is limited by the hash table size
1283 * (HV KVM using VRMA), so we always assume the latter
1285 * In that case, we also limit the initial allocations for RTAS
1286 * etc... to 256M since we have no way to know what the VRMA size
1287 * is going to be as it depends on the size of the hash table
1288 * isn't determined yet.
1290 if (kvm_enabled()) {
1291 spapr
->vrma_adjust
= 1;
1292 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
1296 if (spapr
->rma_size
> node0_size
) {
1297 fprintf(stderr
, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")\n",
1302 /* We place the device tree and RTAS just below either the top of the RMA,
1303 * or just below 2GB, whichever is lowere, so that it can be
1304 * processed with 32-bit real mode code if necessary */
1305 rtas_limit
= MIN(spapr
->rma_size
, 0x80000000);
1306 spapr
->rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1307 spapr
->fdt_addr
= spapr
->rtas_addr
- FDT_MAX_SIZE
;
1308 load_limit
= spapr
->fdt_addr
- FW_OVERHEAD
;
1310 /* We aim for a hash table of size 1/128 the size of RAM. The
1311 * normal rule of thumb is 1/64 the size of RAM, but that's much
1312 * more than needed for the Linux guests we support. */
1313 spapr
->htab_shift
= 18; /* Minimum architected size */
1314 while (spapr
->htab_shift
<= 46) {
1315 if ((1ULL << (spapr
->htab_shift
+ 7)) >= ram_size
) {
1318 spapr
->htab_shift
++;
1321 /* Set up Interrupt Controller before we create the VCPUs */
1322 spapr
->icp
= xics_system_init(smp_cpus
* kvmppc_smt_threads() / smp_threads
,
1324 spapr
->next_irq
= XICS_IRQ_BASE
;
1327 if (cpu_model
== NULL
) {
1328 cpu_model
= kvm_enabled() ? "host" : "POWER7";
1330 for (i
= 0; i
< smp_cpus
; i
++) {
1331 cpu
= cpu_ppc_init(cpu_model
);
1333 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
1338 /* Set time-base frequency to 512 MHz */
1339 cpu_ppc_tb_init(env
, TIMEBASE_FREQ
);
1341 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1342 * MSR[IP] should never be set.
1344 env
->msr_mask
&= ~(1 << 6);
1346 /* Tell KVM that we're in PAPR mode */
1347 if (kvm_enabled()) {
1348 kvmppc_set_papr(cpu
);
1351 if (cpu
->max_compat
) {
1352 if (ppc_set_compat(cpu
, cpu
->max_compat
) < 0) {
1357 xics_cpu_setup(spapr
->icp
, cpu
);
1359 qemu_register_reset(spapr_cpu_reset
, cpu
);
1363 spapr
->ram_limit
= ram_size
;
1364 if (spapr
->ram_limit
> rma_alloc_size
) {
1365 ram_addr_t nonrma_base
= rma_alloc_size
;
1366 ram_addr_t nonrma_size
= spapr
->ram_limit
- rma_alloc_size
;
1368 memory_region_init_ram(ram
, NULL
, "ppc_spapr.ram", nonrma_size
);
1369 vmstate_register_ram_global(ram
);
1370 memory_region_add_subregion(sysmem
, nonrma_base
, ram
);
1373 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
1374 spapr
->rtas_size
= load_image_targphys(filename
, spapr
->rtas_addr
,
1375 rtas_limit
- spapr
->rtas_addr
);
1376 if (spapr
->rtas_size
< 0) {
1377 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1380 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
1381 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
1382 spapr
->rtas_size
, RTAS_MAX_SIZE
);
1387 /* Set up EPOW events infrastructure */
1388 spapr_events_init(spapr
);
1390 /* Set up VIO bus */
1391 spapr
->vio_bus
= spapr_vio_bus_init();
1393 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1394 if (serial_hds
[i
]) {
1395 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
1399 /* We always have at least the nvram device on VIO */
1400 spapr_create_nvram(spapr
);
1403 spapr_pci_msi_init(spapr
, SPAPR_PCI_MSI_WINDOW
);
1404 spapr_pci_rtas_init();
1406 phb
= spapr_create_phb(spapr
, 0);
1408 for (i
= 0; i
< nb_nics
; i
++) {
1409 NICInfo
*nd
= &nd_table
[i
];
1412 nd
->model
= g_strdup("ibmveth");
1415 if (strcmp(nd
->model
, "ibmveth") == 0) {
1416 spapr_vlan_create(spapr
->vio_bus
, nd
);
1418 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
1422 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
1423 spapr_vscsi_create(spapr
->vio_bus
);
1427 if (spapr_vga_init(phb
->bus
)) {
1428 spapr
->has_graphics
= true;
1431 if (usb_enabled(spapr
->has_graphics
)) {
1432 pci_create_simple(phb
->bus
, -1, "pci-ohci");
1433 if (spapr
->has_graphics
) {
1434 usbdevice_create("keyboard");
1435 usbdevice_create("mouse");
1439 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
1440 fprintf(stderr
, "qemu: pSeries SLOF firmware requires >= "
1441 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF
);
1445 if (kernel_filename
) {
1446 uint64_t lowaddr
= 0;
1448 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
1449 NULL
, &lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
1450 if (kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
1451 kernel_size
= load_elf(kernel_filename
,
1452 translate_kernel_address
, NULL
,
1453 NULL
, &lowaddr
, NULL
, 0, ELF_MACHINE
, 0);
1454 kernel_le
= kernel_size
> 0;
1456 if (kernel_size
< 0) {
1457 fprintf(stderr
, "qemu: error loading %s: %s\n",
1458 kernel_filename
, load_elf_strerror(kernel_size
));
1463 if (initrd_filename
) {
1464 /* Try to locate the initrd in the gap between the kernel
1465 * and the firmware. Add a bit of space just in case
1467 initrd_base
= (KERNEL_LOAD_ADDR
+ kernel_size
+ 0x1ffff) & ~0xffff;
1468 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
1469 load_limit
- initrd_base
);
1470 if (initrd_size
< 0) {
1471 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
1481 if (bios_name
== NULL
) {
1482 bios_name
= FW_FILE_NAME
;
1484 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1485 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
1487 hw_error("qemu: could not load LPAR rtas '%s'\n", filename
);
1492 spapr
->entry_point
= 0x100;
1494 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
1495 register_savevm_live(NULL
, "spapr/htab", -1, 1,
1496 &savevm_htab_handlers
, spapr
);
1498 /* Prepare the device tree */
1499 spapr
->fdt_skel
= spapr_create_fdt_skel(initrd_base
, initrd_size
,
1500 kernel_size
, kernel_le
,
1501 boot_device
, kernel_cmdline
,
1503 assert(spapr
->fdt_skel
!= NULL
);
1506 static int spapr_kvm_type(const char *vm_type
)
1512 if (!strcmp(vm_type
, "HV")) {
1516 if (!strcmp(vm_type
, "PR")) {
1520 error_report("Unknown kvm-type specified '%s'", vm_type
);
1525 * Implementation of an interface to adjust firmware patch
1526 * for the bootindex property handling.
1528 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
1531 #define CAST(type, obj, name) \
1532 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1533 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
1534 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1537 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
1538 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
1539 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
1543 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1544 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
1545 * in the top 16 bits of the 64-bit LUN
1547 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
1548 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1549 (uint64_t)id
<< 48);
1550 } else if (virtio
) {
1552 * We use SRP luns of the form 01000000 | (target << 8) | lun
1553 * in the top 32 bits of the 64-bit LUN
1554 * Note: the quote above is from SLOF and it is wrong,
1555 * the actual binding is:
1556 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
1558 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
1559 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1560 (uint64_t)id
<< 32);
1563 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
1564 * in the top 32 bits of the 64-bit LUN
1566 unsigned usb_port
= atoi(usb
->port
->path
);
1567 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
1568 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1569 (uint64_t)id
<< 32);
1574 /* Replace "pci" with "pci@800000020000000" */
1575 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
1581 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
1583 MachineClass
*mc
= MACHINE_CLASS(oc
);
1584 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
1586 mc
->name
= "pseries";
1587 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
1589 mc
->init
= ppc_spapr_init
;
1590 mc
->reset
= ppc_spapr_reset
;
1591 mc
->block_default_type
= IF_SCSI
;
1592 mc
->max_cpus
= MAX_CPUS
;
1593 mc
->no_parallel
= 1;
1594 mc
->default_boot_order
= NULL
;
1595 mc
->kvm_type
= spapr_kvm_type
;
1597 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
1600 static const TypeInfo spapr_machine_info
= {
1601 .name
= TYPE_SPAPR_MACHINE
,
1602 .parent
= TYPE_MACHINE
,
1603 .class_init
= spapr_machine_class_init
,
1604 .interfaces
= (InterfaceInfo
[]) {
1605 { TYPE_FW_PATH_PROVIDER
},
1610 static void spapr_machine_register_types(void)
1612 type_register_static(&spapr_machine_info
);
1615 type_init(spapr_machine_register_types
)